[thirdparty/binutils-gdb.git] / opcodes / riscv-dis.c

/* RISC-V disassembler
   Copyright (C) 2011-2021 Free Software Foundation, Inc.

   Contributed by Andrew Waterman (andrew@sifive.com).
   Based on MIPS target.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; see the file COPYING3. If not,
   see <http://www.gnu.org/licenses/>.  */

#include "sysdep.h"
#include "disassemble.h"
#include "libiberty.h"
#include "opcode/riscv.h"
#include "opintl.h"
#include "elf-bfd.h"
#include "elf/riscv.h"
#include "elfxx-riscv.h"

#include "bfd_stdint.h"
#include <ctype.h>

static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;

struct riscv_private_data
{
  bfd_vma gp;
  bfd_vma print_addr;
  bfd_vma hi_addr[OP_MASK_RD + 1];
};

static const char * const *riscv_gpr_names;
static const char * const *riscv_fpr_names;

/* Other options.  */
static int no_aliases;	/* If set disassemble as most general inst.  */

static void
set_default_riscv_dis_options (void)
{
  riscv_gpr_names = riscv_gpr_names_abi;
  riscv_fpr_names = riscv_fpr_names_abi;
  no_aliases = 0;
}

static bfd_boolean
parse_riscv_dis_option_without_args (const char *option)
{
  if (strcmp (option, "no-aliases") == 0)
    no_aliases = 1;
  else if (strcmp (option, "numeric") == 0)
    {
      riscv_gpr_names = riscv_gpr_names_numeric;
      riscv_fpr_names = riscv_fpr_names_numeric;
    }
  else
    return FALSE;
  return TRUE;
}

static void
parse_riscv_dis_option (const char *option)
{
  char *equal, *value;

  if (parse_riscv_dis_option_without_args (option))
    return;

  equal = strchr (option, '=');
  if (equal == NULL)
    {
      /* The option without '=' should be defined above.  */
      opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
      return;
    }
  if (equal == option
      || *(equal + 1) == '\0')
    {
      /* Invalid options with '=', no option name before '=',
       and no value after '='.  */
      opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
                            option);
      return;
    }

  *equal = '\0';
  value = equal + 1;
  if (strcmp (option, "priv-spec") == 0)
    {
      enum riscv_priv_spec_class priv_spec = PRIV_SPEC_CLASS_NONE;
      if (!riscv_get_priv_spec_class (value, &priv_spec))
	opcodes_error_handler (_("unknown privilege spec set by %s=%s"),
			       option, value);
      else if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
	default_priv_spec = priv_spec;
      else if (default_priv_spec != priv_spec)
	opcodes_error_handler (_("mis-matched privilege spec set by %s=%s, "
				 "the elf privilege attribute is %s"),
			       option, value,
			       riscv_get_priv_spec_name (default_priv_spec));
    }
  else
    {
      /* xgettext:c-format */
      opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
    }
}

static void
parse_riscv_dis_options (const char *opts_in)
{
  char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;

  set_default_riscv_dis_options ();

  for ( ; opt_end != NULL; opt = opt_end + 1)
    {
      if ((opt_end = strchr (opt, ',')) != NULL)
	*opt_end = 0;
      parse_riscv_dis_option (opt);
    }

  free (opts);
}

/* Print one argument from an array.  */

static void
arg_print (struct disassemble_info *info, unsigned long val,
	   const char* const* array, size_t size)
{
  const char *s = val >= size || array[val] == NULL ? "unknown" : array[val];
  (*info->fprintf_func) (info->stream, "%s", s);
}

static void
maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
{
  if (pd->hi_addr[base_reg] != (bfd_vma)-1)
    {
      pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
      pd->hi_addr[base_reg] = -1;
    }
  else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
    pd->print_addr = pd->gp + offset;
  else if (base_reg == X_TP || base_reg == 0)
    pd->print_addr = offset;
}

/* Print insn arguments for 32/64-bit code.  */

static void
print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
{
  struct riscv_private_data *pd = info->private_data;
  int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
  int rd = (l >> OP_SH_RD) & OP_MASK_RD;
  fprintf_ftype print = info->fprintf_func;

  if (*d != '\0')
    print (info->stream, "\t");

  for (; *d != '\0'; d++)
    {
      switch (*d)
	{
	case 'C': /* RVC */
	  switch (*++d)
	    {
	    case 's': /* RS1 x8-x15 */
	    case 'w': /* RS1 x8-x15 */
	      print (info->stream, "%s",
		     riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
	      break;
	    case 't': /* RS2 x8-x15 */
	    case 'x': /* RS2 x8-x15 */
	      print (info->stream, "%s",
		     riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
	      break;
	    case 'U': /* RS1, constrained to equal RD */
	      print (info->stream, "%s", riscv_gpr_names[rd]);
	      break;
	    case 'c': /* RS1, constrained to equal sp */
	      print (info->stream, "%s", riscv_gpr_names[X_SP]);
	      break;
	    case 'V': /* RS2 */
	      print (info->stream, "%s",
		     riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
	      break;
	    case 'i':
	      print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
	      break;
	    case 'o':
	    case 'j':
	      print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
	      break;
	    case 'k':
	      print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l));
	      break;
	    case 'l':
	      print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l));
	      break;
	    case 'm':
	      print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l));
	      break;
	    case 'n':
	      print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l));
	      break;
	    case 'K':
	      print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l));
	      break;
	    case 'L':
	      print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l));
	      break;
	    case 'M':
	      print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l));
	      break;
	    case 'N':
	      print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l));
	      break;
	    case 'p':
	      info->target = EXTRACT_RVC_B_IMM (l) + pc;
	      (*info->print_address_func) (info->target, info);
	      break;
	    case 'a':
	      info->target = EXTRACT_RVC_J_IMM (l) + pc;
	      (*info->print_address_func) (info->target, info);
	      break;
	    case 'u':
	      print (info->stream, "0x%x",
		     (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
	      break;
	    case '>':
	      print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
	      break;
	    case '<':
	      print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
	      break;
	    case 'T': /* floating-point RS2 */
	      print (info->stream, "%s",
		     riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
	      break;
	    case 'D': /* floating-point RS2 x8-x15 */
	      print (info->stream, "%s",
		     riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
	      break;
	    }
	  break;

	case ',':
	case '(':
	case ')':
	case '[':
	case ']':
	  print (info->stream, "%c", *d);
	  break;

	case '0':
	  /* Only print constant 0 if it is the last argument */
	  if (!d[1])
	    print (info->stream, "0");
	  break;

	case 'b':
	case 's':
	  if ((l & MASK_JALR) == MATCH_JALR)
	    maybe_print_address (pd, rs1, 0);
	  print (info->stream, "%s", riscv_gpr_names[rs1]);
	  break;

	case 't':
	  print (info->stream, "%s",
		 riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
	  break;

	case 'u':
	  print (info->stream, "0x%x",
		 (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
	  break;

	case 'm':
	  arg_print (info, EXTRACT_OPERAND (RM, l),
		     riscv_rm, ARRAY_SIZE (riscv_rm));
	  break;

	case 'P':
	  arg_print (info, EXTRACT_OPERAND (PRED, l),
		     riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
	  break;

	case 'Q':
	  arg_print (info, EXTRACT_OPERAND (SUCC, l),
		     riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
	  break;

	case 'o':
	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
	  /* Fall through.  */
	case 'j':
	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
	      || (l & MASK_JALR) == MATCH_JALR)
	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
	  print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l));
	  break;

	case 'q':
	  maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l));
	  print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
	  break;

	case 'a':
	  info->target = EXTRACT_UJTYPE_IMM (l) + pc;
	  (*info->print_address_func) (info->target, info);
	  break;

	case 'p':
	  info->target = EXTRACT_SBTYPE_IMM (l) + pc;
	  (*info->print_address_func) (info->target, info);
	  break;

	case 'd':
	  if ((l & MASK_AUIPC) == MATCH_AUIPC)
	    pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l);
	  else if ((l & MASK_LUI) == MATCH_LUI)
	    pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
	  else if ((l & MASK_C_LUI) == MATCH_C_LUI)
	    pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l);
	  print (info->stream, "%s", riscv_gpr_names[rd]);
	  break;

	case 'z':
	  print (info->stream, "%s", riscv_gpr_names[0]);
	  break;

	case '>':
	  print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
	  break;

	case '<':
	  print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
	  break;

	case 'S':
	case 'U':
	  print (info->stream, "%s", riscv_fpr_names[rs1]);
	  break;

	case 'T':
	  print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]);
	  break;

	case 'D':
	  print (info->stream, "%s", riscv_fpr_names[rd]);
	  break;

	case 'R':
	  print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
	  break;

	case 'E':
	  {
	    static const char *riscv_csr_hash[4096];    /* Total 2^12 CSR.  */
	    static bfd_boolean init_csr = FALSE;
	    unsigned int csr = EXTRACT_OPERAND (CSR, l);

	    if (!init_csr)
	      {
		unsigned int i;
		for (i = 0; i < 4096; i++)
		  riscv_csr_hash[i] = NULL;

		/* Set to the newest privilege version.  */
		if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
		  default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;

#define DECLARE_CSR(name, num, class, define_version, abort_version)	\
		if (riscv_csr_hash[num] == NULL 			\
		    && ((define_version == PRIV_SPEC_CLASS_NONE 	\
			 && abort_version == PRIV_SPEC_CLASS_NONE)	\
			|| (default_priv_spec >= define_version 	\
			    && default_priv_spec < abort_version)))	\
		  riscv_csr_hash[num] = #name;
#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
		DECLARE_CSR (name, num, class, define_version, abort_version)
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
	      }

	    if (riscv_csr_hash[csr] != NULL)
	      print (info->stream, "%s", riscv_csr_hash[csr]);
	    else
	      print (info->stream, "0x%x", csr);
	    break;
	  }

	case 'Z':
	  print (info->stream, "%d", rs1);
	  break;

	default:
	  /* xgettext:c-format */
	  print (info->stream, _("# internal error, undefined modifier (%c)"),
		 *d);
	  return;
	}
    }
}

/* Print the RISC-V instruction at address MEMADDR in debugged memory,
   on using INFO.  Returns length of the instruction, in bytes.
   BIGENDIAN must be 1 if this is big-endian code, 0 if
   this is little-endian code.  */

static int
riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
{
  const struct riscv_opcode *op;
  static bfd_boolean init = 0;
  static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
  struct riscv_private_data *pd;
  int insnlen;

#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))

  /* Build a hash table to shorten the search time.  */
  if (! init)
    {
      for (op = riscv_opcodes; op->name; op++)
	if (!riscv_hash[OP_HASH_IDX (op->match)])
	  riscv_hash[OP_HASH_IDX (op->match)] = op;

      init = 1;
    }

  if (info->private_data == NULL)
    {
      int i;

      pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
      pd->gp = -1;
      pd->print_addr = -1;
      for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
	pd->hi_addr[i] = -1;

      for (i = 0; i < info->symtab_size; i++)
	if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
	  pd->gp = bfd_asymbol_value (info->symtab[i]);
    }
  else
    pd = info->private_data;

  insnlen = riscv_insn_length (word);

  /* RISC-V instructions are always little-endian.  */
  info->endian_code = BFD_ENDIAN_LITTLE;

  info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
  info->bytes_per_line = 8;
  /* We don't support constant pools, so this must be code.  */
  info->display_endian = info->endian_code;
  info->insn_info_valid = 1;
  info->branch_delay_insns = 0;
  info->data_size = 0;
  info->insn_type = dis_nonbranch;
  info->target = 0;
  info->target2 = 0;

  op = riscv_hash[OP_HASH_IDX (word)];
  if (op != NULL)
    {
      unsigned xlen = 0;

      /* If XLEN is not known, get its value from the ELF class.  */
      if (info->mach == bfd_mach_riscv64)
	xlen = 64;
      else if (info->mach == bfd_mach_riscv32)
	xlen = 32;
      else if (info->section != NULL)
	{
	  Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
	  xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
	}

      for (; op->name; op++)
	{
	  /* Does the opcode match?  */
	  if (! (op->match_func) (op, word))
	    continue;
	  /* Is this a pseudo-instruction and may we print it as such?  */
	  if (no_aliases && (op->pinfo & INSN_ALIAS))
	    continue;
	  /* Is this instruction restricted to a certain value of XLEN?  */
	  if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
	    continue;

	  /* It's a match.  */
	  (*info->fprintf_func) (info->stream, "%s", op->name);
	  print_insn_args (op->args, word, memaddr, info);

	  /* Try to disassemble multi-instruction addressing sequences.  */
	  if (pd->print_addr != (bfd_vma)-1)
	    {
	      info->target = pd->print_addr;
	      (*info->fprintf_func) (info->stream, " # ");
	      (*info->print_address_func) (info->target, info);
	      pd->print_addr = -1;
	    }

	  /* Finish filling out insn_info fields.  */
	  switch (op->pinfo & INSN_TYPE)
	    {
	    case INSN_BRANCH:
	      info->insn_type = dis_branch;
	      break;
	    case INSN_CONDBRANCH:
	      info->insn_type = dis_condbranch;
	      break;
	    case INSN_JSR:
	      info->insn_type = dis_jsr;
	      break;
	    case INSN_DREF:
	      info->insn_type = dis_dref;
	      break;
	    default:
	      break;
	    }

	  if (op->pinfo & INSN_DATA_SIZE)
	    {
	      int size = ((op->pinfo & INSN_DATA_SIZE)
			  >> INSN_DATA_SIZE_SHIFT);
	      info->data_size = 1 << (size - 1);
	    }

	  return insnlen;
	}
    }

  /* We did not find a match, so just print the instruction bits.  */
  info->insn_type = dis_noninsn;
  (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word);
  return insnlen;
}

int
print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
{
  bfd_byte packet[2];
  insn_t insn = 0;
  bfd_vma n;
  int status;

  if (info->disassembler_options != NULL)
    {
      parse_riscv_dis_options (info->disassembler_options);
      /* Avoid repeatedly parsing the options.  */
      info->disassembler_options = NULL;
    }
  else if (riscv_gpr_names == NULL)
    set_default_riscv_dis_options ();

  /* Instructions are a sequence of 2-byte packets in little-endian order.  */
  for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2)
    {
      status = (*info->read_memory_func) (memaddr + n, packet, 2, info);
      if (status != 0)
	{
	  /* Don't fail just because we fell off the end.  */
	  if (n > 0)
	    break;
	  (*info->memory_error_func) (status, memaddr, info);
	  return status;
	}

      insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n);
    }

  return riscv_disassemble_insn (memaddr, insn, info);
}

disassembler_ftype
riscv_get_disassembler (bfd *abfd)
{
  /* If -Mpriv-spec= isn't set, then try to set it by checking the elf
     privileged attributes.  */
  if (abfd)
    {
      const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section;
      if (bfd_get_section_by_name (abfd, sec_name) != NULL)
        {
	  obj_attribute *attr = elf_known_obj_attributes_proc (abfd);
	  unsigned int Tag_a = Tag_RISCV_priv_spec;
	  unsigned int Tag_b = Tag_RISCV_priv_spec_minor;
	  unsigned int Tag_c = Tag_RISCV_priv_spec_revision;
	  riscv_get_priv_spec_class_from_numbers (attr[Tag_a].i,
						  attr[Tag_b].i,
						  attr[Tag_c].i,
						  &default_priv_spec);
        }
    }
   return print_insn_riscv;
}

/* Prevent use of the fake labels that are generated as part of the DWARF
   and for relaxable relocations in the assembler.  */

bfd_boolean
riscv_symbol_is_valid (asymbol * sym,
                       struct disassemble_info * info ATTRIBUTE_UNUSED)
{
  const char * name;

  if (sym == NULL)
    return FALSE;

  name = bfd_asymbol_name (sym);

  return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0);
}

void
print_riscv_disassembler_options (FILE *stream)
{
  fprintf (stream, _("\n\
The following RISC-V-specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));

  fprintf (stream, _("\n\
  numeric         Print numeric register names, rather than ABI names.\n"));

  fprintf (stream, _("\n\
  no-aliases      Disassemble only into canonical instructions, rather\n\
                  than into pseudoinstructions.\n"));

  fprintf (stream, _("\n\
  priv-spec=PRIV  Print the CSR according to the chosen privilege spec\n\
                  (1.9, 1.9.1, 1.10, 1.11).\n"));

  fprintf (stream, _("\n"));
}
Commit	Line	Data
e23eba97	1	/* RISC-V disassembler
250d07de	2	Copyright (C) 2011-2021 Free Software Foundation, Inc.
e23eba97 NC	3
	4	Contributed by Andrew Waterman (andrew@sifive.com).
	5	Based on MIPS target.
	6
	7	This file is part of the GNU opcodes library.
	8
	9	This library is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 3, or (at your option)
	12	any later version.
	13
	14	It is distributed in the hope that it will be useful, but WITHOUT
	15	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	16	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	17	License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with this program; see the file COPYING3. If not,
	21	see <http://www.gnu.org/licenses/>. */
	22
	23	#include "sysdep.h"
88c1242d	24	#include "disassemble.h"
e23eba97 NC	25	#include "libiberty.h"
	26	#include "opcode/riscv.h"
	27	#include "opintl.h"
	28	#include "elf-bfd.h"
	29	#include "elf/riscv.h"
39ff0b81	30	#include "elfxx-riscv.h"
e23eba97	31
2d5d5a8f	32	#include "bfd_stdint.h"
e23eba97 NC	33	#include <ctype.h>
e23eba97 NC	34
8f595e9b NC	35	static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
8f595e9b NC	36
e23eba97 NC	37	struct riscv_private_data
	38	{
	39	bfd_vma gp;
	40	bfd_vma print_addr;
	41	bfd_vma hi_addr[OP_MASK_RD + 1];
	42	};
	43
	44	static const char * const *riscv_gpr_names;
	45	static const char * const *riscv_fpr_names;
	46
	47	/* Other options. */
	48	static int no_aliases; /* If set disassemble as most general inst. */
	49
	50	static void
	51	set_default_riscv_dis_options (void)
	52	{
	53	riscv_gpr_names = riscv_gpr_names_abi;
	54	riscv_fpr_names = riscv_fpr_names_abi;
	55	no_aliases = 0;
	56	}
	57
8f595e9b NC	58	static bfd_boolean
8f595e9b NC	59	parse_riscv_dis_option_without_args (const char *option)
e23eba97 NC	60	{
	61	if (strcmp (option, "no-aliases") == 0)
	62	no_aliases = 1;
	63	else if (strcmp (option, "numeric") == 0)
	64	{
	65	riscv_gpr_names = riscv_gpr_names_numeric;
	66	riscv_fpr_names = riscv_fpr_names_numeric;
	67	}
8f595e9b NC	68	else
	69	return FALSE;
	70	return TRUE;
	71	}
	72
	73	static void
	74	parse_riscv_dis_option (const char *option)
	75	{
	76	char equal, value;
	77
	78	if (parse_riscv_dis_option_without_args (option))
	79	return;
	80
	81	equal = strchr (option, '=');
	82	if (equal == NULL)
	83	{
	84	/* The option without '=' should be defined above. */
	85	opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
	86	return;
	87	}
	88	if (equal == option
	89	\|\| *(equal + 1) == '\0')
	90	{
	91	/* Invalid options with '=', no option name before '=',
	92	and no value after '='. */
	93	opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
	94	option);
	95	return;
	96	}
	97
	98	*equal = '\0';
	99	value = equal + 1;
	100	if (strcmp (option, "priv-spec") == 0)
	101	{
8152e040 NC	102	enum riscv_priv_spec_class priv_spec = PRIV_SPEC_CLASS_NONE;
	103	if (!riscv_get_priv_spec_class (value, &priv_spec))
	104	opcodes_error_handler (_("unknown privilege spec set by %s=%s"),
	105	option, value);
	106	else if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
	107	default_priv_spec = priv_spec;
	108	else if (default_priv_spec != priv_spec)
	109	opcodes_error_handler (_("mis-matched privilege spec set by %s=%s, "
	110	"the elf privilege attribute is %s"),
	111	option, value,
	112	riscv_get_priv_spec_name (default_priv_spec));
8f595e9b	113	}
e23eba97 NC	114	else
e23eba97 NC	115	{
a6743a54 AM	116	/* xgettext:c-format */
a6743a54 AM	117	opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
e23eba97 NC	118	}
	119	}
	120
	121	static void
	122	parse_riscv_dis_options (const char *opts_in)
	123	{
	124	char opts = xstrdup (opts_in), opt = opts, *opt_end = opts;
	125
	126	set_default_riscv_dis_options ();
	127
	128	for ( ; opt_end != NULL; opt = opt_end + 1)
	129	{
	130	if ((opt_end = strchr (opt, ',')) != NULL)
	131	*opt_end = 0;
	132	parse_riscv_dis_option (opt);
	133	}
	134
	135	free (opts);
	136	}
	137
	138	/* Print one argument from an array. */
	139
	140	static void
	141	arg_print (struct disassemble_info *info, unsigned long val,
	142	const char* const* array, size_t size)
	143	{
	144	const char *s = val >= size \|\| array[val] == NULL ? "unknown" : array[val];
	145	(*info->fprintf_func) (info->stream, "%s", s);
	146	}
	147
	148	static void
	149	maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
	150	{
	151	if (pd->hi_addr[base_reg] != (bfd_vma)-1)
	152	{
35fd2b2b	153	pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
e23eba97 NC	154	pd->hi_addr[base_reg] = -1;
	155	}
	156	else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
	157	pd->print_addr = pd->gp + offset;
	158	else if (base_reg == X_TP \|\| base_reg == 0)
	159	pd->print_addr = offset;
	160	}
	161
	162	/* Print insn arguments for 32/64-bit code. */
	163
	164	static void
	165	print_insn_args (const char d, insn_t l, bfd_vma pc, disassemble_info info)
	166	{
	167	struct riscv_private_data *pd = info->private_data;
	168	int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
	169	int rd = (l >> OP_SH_RD) & OP_MASK_RD;
	170	fprintf_ftype print = info->fprintf_func;
	171
	172	if (*d != '\0')
	173	print (info->stream, "\t");
	174
	175	for (; *d != '\0'; d++)
	176	{
	177	switch (*d)
	178	{
	179	case 'C': /* RVC */
	180	switch (*++d)
	181	{
	182	case 's': /* RS1 x8-x15 */
	183	case 'w': /* RS1 x8-x15 */
	184	print (info->stream, "%s",
	185	riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
	186	break;
	187	case 't': /* RS2 x8-x15 */
	188	case 'x': /* RS2 x8-x15 */
	189	print (info->stream, "%s",
	190	riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
	191	break;
	192	case 'U': /* RS1, constrained to equal RD */
	193	print (info->stream, "%s", riscv_gpr_names[rd]);
	194	break;
	195	case 'c': /* RS1, constrained to equal sp */
	196	print (info->stream, "%s", riscv_gpr_names[X_SP]);
	197	break;
	198	case 'V': /* RS2 */
	199	print (info->stream, "%s",
	200	riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
	201	break;
	202	case 'i':
	203	print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
	204	break;
f91d48de	205	case 'o':
e23eba97 NC	206	case 'j':
	207	print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
	208	break;
	209	case 'k':
	210	print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l));
	211	break;
	212	case 'l':
	213	print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l));
	214	break;
	215	case 'm':
	216	print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l));
	217	break;
	218	case 'n':
	219	print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l));
	220	break;
	221	case 'K':
	222	print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l));
	223	break;
	224	case 'L':
	225	print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l));
	226	break;
	227	case 'M':
	228	print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l));
	229	break;
	230	case 'N':
	231	print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l));
	232	break;
	233	case 'p':
	234	info->target = EXTRACT_RVC_B_IMM (l) + pc;
	235	(*info->print_address_func) (info->target, info);
	236	break;
	237	case 'a':
	238	info->target = EXTRACT_RVC_J_IMM (l) + pc;
	239	(*info->print_address_func) (info->target, info);
	240	break;
	241	case 'u':
	242	print (info->stream, "0x%x",
	243	(int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
	244	break;
	245	case '>':
	246	print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
	247	break;
	248	case '<':
	249	print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
	250	break;
	251	case 'T': /* floating-point RS2 */
	252	print (info->stream, "%s",
	253	riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
	254	break;
	255	case 'D': /* floating-point RS2 x8-x15 */
	256	print (info->stream, "%s",
	257	riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
	258	break;
	259	}
	260	break;
	261
	262	case ',':
	263	case '(':
	264	case ')':
	265	case '[':
	266	case ']':
	267	print (info->stream, "%c", *d);
	268	break;
	269
270	case '0':
271	/* Only print constant 0 if it is the last argument */
272	if (!d[1])
273	print (info->stream, "0");
274	break;
275
276	case 'b':
277	case 's':
35eeb78f JW	278	if ((l & MASK_JALR) == MATCH_JALR)
35eeb78f JW	279	maybe_print_address (pd, rs1, 0);
e23eba97 NC	280	print (info->stream, "%s", riscv_gpr_names[rs1]);
	281	break;
	282
	283	case 't':
	284	print (info->stream, "%s",
	285	riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
	286	break;
	287
	288	case 'u':
	289	print (info->stream, "0x%x",
	290	(unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
	291	break;
	292
	293	case 'm':
	294	arg_print (info, EXTRACT_OPERAND (RM, l),
	295	riscv_rm, ARRAY_SIZE (riscv_rm));
	296	break;
	297
	298	case 'P':
	299	arg_print (info, EXTRACT_OPERAND (PRED, l),
	300	riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
	301	break;
	302
	303	case 'Q':
	304	arg_print (info, EXTRACT_OPERAND (SUCC, l),
	305	riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
	306	break;
	307
	308	case 'o':
	309	maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
b52d3cfc	310	/* Fall through. */
e23eba97 NC	311	case 'j':
	312	if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
	313	\|\| (l & MASK_JALR) == MATCH_JALR)
	314	maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
	315	print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l));
	316	break;
	317
	318	case 'q':
	319	maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l));
	320	print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
	321	break;
	322
	323	case 'a':
	324	info->target = EXTRACT_UJTYPE_IMM (l) + pc;
	325	(*info->print_address_func) (info->target, info);
	326	break;
	327
	328	case 'p':
	329	info->target = EXTRACT_SBTYPE_IMM (l) + pc;
	330	(*info->print_address_func) (info->target, info);
	331	break;
	332
	333	case 'd':
	334	if ((l & MASK_AUIPC) == MATCH_AUIPC)
	335	pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l);
	336	else if ((l & MASK_LUI) == MATCH_LUI)
	337	pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
	338	else if ((l & MASK_C_LUI) == MATCH_C_LUI)
	339	pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l);
	340	print (info->stream, "%s", riscv_gpr_names[rd]);
	341	break;
	342
	343	case 'z':
	344	print (info->stream, "%s", riscv_gpr_names[0]);
	345	break;
	346
	347	case '>':
	348	print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
	349	break;
	350
	351	case '<':
	352	print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
	353	break;
	354
	355	case 'S':
	356	case 'U':
	357	print (info->stream, "%s", riscv_fpr_names[rs1]);
	358	break;
	359
	360	case 'T':
	361	print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]);
	362	break;
	363
	364	case 'D':
	365	print (info->stream, "%s", riscv_fpr_names[rd]);
	366	break;
	367
	368	case 'R':
	369	print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
	370	break;
	371
	372	case 'E':
	373	{
8f595e9b NC	374	static const char riscv_csr_hash[4096]; / Total 2^12 CSR. */
8f595e9b NC	375	static bfd_boolean init_csr = FALSE;
e23eba97	376	unsigned int csr = EXTRACT_OPERAND (CSR, l);
8f595e9b NC	377
8f595e9b NC	378	if (!init_csr)
e23eba97	379	{
8f595e9b NC	380	unsigned int i;
	381	for (i = 0; i < 4096; i++)
	382	riscv_csr_hash[i] = NULL;
	383
	384	/* Set to the newest privilege version. */
	385	if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
	386	default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
	387
08ccfccf NC	388	#define DECLARE_CSR(name, num, class, define_version, abort_version) \
	389	if (riscv_csr_hash[num] == NULL \
	390	&& ((define_version == PRIV_SPEC_CLASS_NONE \
	391	&& abort_version == PRIV_SPEC_CLASS_NONE) \
	392	\|\| (default_priv_spec >= define_version \
	393	&& default_priv_spec < abort_version))) \
8f595e9b NC	394	riscv_csr_hash[num] = #name;
	395	#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
	396	DECLARE_CSR (name, num, class, define_version, abort_version)
e23eba97 NC	397	#include "opcode/riscv-opc.h"
	398	#undef DECLARE_CSR
	399	}
8f595e9b NC	400
	401	if (riscv_csr_hash[csr] != NULL)
	402	print (info->stream, "%s", riscv_csr_hash[csr]);
e23eba97 NC	403	else
	404	print (info->stream, "0x%x", csr);
	405	break;
	406	}
	407
	408	case 'Z':
	409	print (info->stream, "%d", rs1);
	410	break;
	411
	412	default:
	413	/* xgettext:c-format */
	414	print (info->stream, _("# internal error, undefined modifier (%c)"),
	415	*d);
	416	return;
	417	}
	418	}
	419	}
	420
	421	/* Print the RISC-V instruction at address MEMADDR in debugged memory,
	422	on using INFO. Returns length of the instruction, in bytes.
	423	BIGENDIAN must be 1 if this is big-endian code, 0 if
	424	this is little-endian code. */
	425
	426	static int
	427	riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
	428	{
	429	const struct riscv_opcode *op;
	430	static bfd_boolean init = 0;
	431	static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
	432	struct riscv_private_data *pd;
	433	int insnlen;
	434
	435	#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
	436
	437	/* Build a hash table to shorten the search time. */
	438	if (! init)
	439	{
	440	for (op = riscv_opcodes; op->name; op++)
	441	if (!riscv_hash[OP_HASH_IDX (op->match)])
	442	riscv_hash[OP_HASH_IDX (op->match)] = op;
	443
	444	init = 1;
	445	}
	446
	447	if (info->private_data == NULL)
	448	{
	449	int i;
	450
	451	pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
	452	pd->gp = -1;
	453	pd->print_addr = -1;
	454	for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
	455	pd->hi_addr[i] = -1;
	456
	457	for (i = 0; i < info->symtab_size; i++)
b5292032	458	if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
e23eba97 NC	459	pd->gp = bfd_asymbol_value (info->symtab[i]);
	460	}
	461	else
	462	pd = info->private_data;
	463
	464	insnlen = riscv_insn_length (word);
	465
d7560e2d JW	466	/* RISC-V instructions are always little-endian. */
	467	info->endian_code = BFD_ENDIAN_LITTLE;
	468
e23eba97 NC	469	info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
e23eba97 NC	470	info->bytes_per_line = 8;
d7560e2d JW	471	/* We don't support constant pools, so this must be code. */
d7560e2d JW	472	info->display_endian = info->endian_code;
e23eba97 NC	473	info->insn_info_valid = 1;
	474	info->branch_delay_insns = 0;
	475	info->data_size = 0;
	476	info->insn_type = dis_nonbranch;
	477	info->target = 0;
	478	info->target2 = 0;
	479
	480	op = riscv_hash[OP_HASH_IDX (word)];
	481	if (op != NULL)
	482	{
1080bf78	483	unsigned xlen = 0;
e23eba97	484
2922d21d AW	485	/* If XLEN is not known, get its value from the ELF class. */
	486	if (info->mach == bfd_mach_riscv64)
	487	xlen = 64;
	488	else if (info->mach == bfd_mach_riscv32)
	489	xlen = 32;
	490	else if (info->section != NULL)
e23eba97 NC	491	{
	492	Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
	493	xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
	494	}
	495
	496	for (; op->name; op++)
	497	{
	498	/* Does the opcode match? */
	499	if (! (op->match_func) (op, word))
	500	continue;
	501	/* Is this a pseudo-instruction and may we print it as such? */
	502	if (no_aliases && (op->pinfo & INSN_ALIAS))
	503	continue;
	504	/* Is this instruction restricted to a certain value of XLEN? */
43135d3b	505	if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
e23eba97 NC	506	continue;
	507
	508	/* It's a match. */
	509	(*info->fprintf_func) (info->stream, "%s", op->name);
	510	print_insn_args (op->args, word, memaddr, info);
	511
	512	/* Try to disassemble multi-instruction addressing sequences. */
	513	if (pd->print_addr != (bfd_vma)-1)
	514	{
	515	info->target = pd->print_addr;
	516	(*info->fprintf_func) (info->stream, " # ");
	517	(*info->print_address_func) (info->target, info);
	518	pd->print_addr = -1;
	519	}
	520
eb41b248 JW	521	/* Finish filling out insn_info fields. */
	522	switch (op->pinfo & INSN_TYPE)
	523	{
	524	case INSN_BRANCH:
	525	info->insn_type = dis_branch;
	526	break;
	527	case INSN_CONDBRANCH:
	528	info->insn_type = dis_condbranch;
	529	break;
	530	case INSN_JSR:
	531	info->insn_type = dis_jsr;
	532	break;
	533	case INSN_DREF:
	534	info->insn_type = dis_dref;
	535	break;
	536	default:
	537	break;
	538	}
	539
	540	if (op->pinfo & INSN_DATA_SIZE)
	541	{
	542	int size = ((op->pinfo & INSN_DATA_SIZE)
	543	>> INSN_DATA_SIZE_SHIFT);
	544	info->data_size = 1 << (size - 1);
	545	}
	546
e23eba97 NC	547	return insnlen;
	548	}
	549	}
	550
	551	/* We did not find a match, so just print the instruction bits. */
	552	info->insn_type = dis_noninsn;
	553	(*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word);
	554	return insnlen;
	555	}
	556
	557	int
	558	print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
	559	{
	560	bfd_byte packet[2];
	561	insn_t insn = 0;
	562	bfd_vma n;
	563	int status;
	564
	565	if (info->disassembler_options != NULL)
	566	{
	567	parse_riscv_dis_options (info->disassembler_options);
	568	/* Avoid repeatedly parsing the options. */
	569	info->disassembler_options = NULL;
	570	}
	571	else if (riscv_gpr_names == NULL)
	572	set_default_riscv_dis_options ();
	573
	574	/* Instructions are a sequence of 2-byte packets in little-endian order. */
	575	for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2)
	576	{
	577	status = (*info->read_memory_func) (memaddr + n, packet, 2, info);
	578	if (status != 0)
	579	{
	580	/* Don't fail just because we fell off the end. */
	581	if (n > 0)
	582	break;
	583	(*info->memory_error_func) (status, memaddr, info);
	584	return status;
	585	}
	586
	587	insn \|= ((insn_t) bfd_getl16 (packet)) << (8 * n);
	588	}
	589
	590	return riscv_disassemble_insn (memaddr, insn, info);
	591	}
	592
8152e040 NC	593	disassembler_ftype
	594	riscv_get_disassembler (bfd *abfd)
	595	{
	596	/* If -Mpriv-spec= isn't set, then try to set it by checking the elf
	597	privileged attributes. */
	598	if (abfd)
	599	{
	600	const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section;
	601	if (bfd_get_section_by_name (abfd, sec_name) != NULL)
	602	{
	603	obj_attribute *attr = elf_known_obj_attributes_proc (abfd);
	604	unsigned int Tag_a = Tag_RISCV_priv_spec;
	605	unsigned int Tag_b = Tag_RISCV_priv_spec_minor;
	606	unsigned int Tag_c = Tag_RISCV_priv_spec_revision;
	607	riscv_get_priv_spec_class_from_numbers (attr[Tag_a].i,
	608	attr[Tag_b].i,
	609	attr[Tag_c].i,
	610	&default_priv_spec);
	611	}
	612	}
	613	return print_insn_riscv;
	614	}
	615
884b49e3 AB	616	/* Prevent use of the fake labels that are generated as part of the DWARF
	617	and for relaxable relocations in the assembler. */
	618
	619	bfd_boolean
	620	riscv_symbol_is_valid (asymbol * sym,
	621	struct disassemble_info * info ATTRIBUTE_UNUSED)
	622	{
	623	const char * name;
	624
	625	if (sym == NULL)
	626	return FALSE;
	627
	628	name = bfd_asymbol_name (sym);
	629
	630	return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0);
	631	}
	632
e23eba97 NC	633	void
	634	print_riscv_disassembler_options (FILE *stream)
	635	{
	636	fprintf (stream, _("\n\
	637	The following RISC-V-specific disassembler options are supported for use\n\
	638	with the -M switch (multiple options should be separated by commas):\n"));
	639
	640	fprintf (stream, _("\n\
8f595e9b NC	641	numeric Print numeric register names, rather than ABI names.\n"));
	642
	643	fprintf (stream, _("\n\
	644	no-aliases Disassemble only into canonical instructions, rather\n\
	645	than into pseudoinstructions.\n"));
e23eba97 NC	646
e23eba97 NC	647	fprintf (stream, _("\n\
8f595e9b NC	648	priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
8f595e9b NC	649	(1.9, 1.9.1, 1.10, 1.11).\n"));
e23eba97 NC	650
	651	fprintf (stream, _("\n"));
	652	}