[thirdparty/binutils-gdb.git] / opcodes / riscv-dis.c

/* RISC-V disassembler
   Copyright (C) 2011-2021 Free Software Foundation, Inc.

   Contributed by Andrew Waterman (andrew@sifive.com).
   Based on MIPS target.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; see the file COPYING3. If not,
   see <http://www.gnu.org/licenses/>.  */

#include "sysdep.h"
#include "disassemble.h"
#include "libiberty.h"
#include "opcode/riscv.h"
#include "opintl.h"
#include "elf-bfd.h"
#include "elf/riscv.h"
#include "cpu-riscv.h"

#include "bfd_stdint.h"
#include <ctype.h>

static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;

struct riscv_private_data
{
  bfd_vma gp;
  bfd_vma print_addr;
  bfd_vma hi_addr[OP_MASK_RD + 1];
};

static const char * const *riscv_gpr_names;
static const char * const *riscv_fpr_names;

/* If set, disassemble as most general instruction.  */
static int no_aliases;

static void
set_default_riscv_dis_options (void)
{
  riscv_gpr_names = riscv_gpr_names_abi;
  riscv_fpr_names = riscv_fpr_names_abi;
  no_aliases = 0;
}

static bfd_boolean
parse_riscv_dis_option_without_args (const char *option)
{
  if (strcmp (option, "no-aliases") == 0)
    no_aliases = 1;
  else if (strcmp (option, "numeric") == 0)
    {
      riscv_gpr_names = riscv_gpr_names_numeric;
      riscv_fpr_names = riscv_fpr_names_numeric;
    }
  else
    return FALSE;
  return TRUE;
}

static void
parse_riscv_dis_option (const char *option)
{
  char *equal, *value;

  if (parse_riscv_dis_option_without_args (option))
    return;

  equal = strchr (option, '=');
  if (equal == NULL)
    {
      /* The option without '=' should be defined above.  */
      opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
      return;
    }
  if (equal == option
      || *(equal + 1) == '\0')
    {
      /* Invalid options with '=', no option name before '=',
       and no value after '='.  */
      opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
                            option);
      return;
    }

  *equal = '\0';
  value = equal + 1;
  if (strcmp (option, "priv-spec") == 0)
    {
      enum riscv_spec_class priv_spec = PRIV_SPEC_CLASS_NONE;
      const char *name = NULL;

      RISCV_GET_PRIV_SPEC_CLASS (value, priv_spec);
      if (priv_spec == PRIV_SPEC_CLASS_NONE)
	opcodes_error_handler (_("unknown privileged spec set by %s=%s"),
			       option, value);
      else if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
	default_priv_spec = priv_spec;
      else if (default_priv_spec != priv_spec)
	{
	  RISCV_GET_PRIV_SPEC_NAME (name, default_priv_spec);
	  opcodes_error_handler (_("mis-matched privilege spec set by %s=%s, "
				   "the elf privilege attribute is %s"),
				 option, value, name);
	}
    }
  else
    {
      /* xgettext:c-format */
      opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
    }
}

static void
parse_riscv_dis_options (const char *opts_in)
{
  char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;

  set_default_riscv_dis_options ();

  for ( ; opt_end != NULL; opt = opt_end + 1)
    {
      if ((opt_end = strchr (opt, ',')) != NULL)
	*opt_end = 0;
      parse_riscv_dis_option (opt);
    }

  free (opts);
}

/* Print one argument from an array.  */

static void
arg_print (struct disassemble_info *info, unsigned long val,
	   const char* const* array, size_t size)
{
  const char *s = val >= size || array[val] == NULL ? "unknown" : array[val];
  (*info->fprintf_func) (info->stream, "%s", s);
}

static void
maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
{
  if (pd->hi_addr[base_reg] != (bfd_vma)-1)
    {
      pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
      pd->hi_addr[base_reg] = -1;
    }
  else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
    pd->print_addr = pd->gp + offset;
  else if (base_reg == X_TP || base_reg == 0)
    pd->print_addr = offset;
}

/* Print insn arguments for 32/64-bit code.  */

static void
print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
{
  struct riscv_private_data *pd = info->private_data;
  int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
  int rd = (l >> OP_SH_RD) & OP_MASK_RD;
  fprintf_ftype print = info->fprintf_func;

  if (*d != '\0')
    print (info->stream, "\t");

  for (; *d != '\0'; d++)
    {
      switch (*d)
	{
	case 'C': /* RVC */
	  switch (*++d)
	    {
	    case 's': /* RS1 x8-x15.  */
	    case 'w': /* RS1 x8-x15.  */
	      print (info->stream, "%s",
		     riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
	      break;
	    case 't': /* RS2 x8-x15.  */
	    case 'x': /* RS2 x8-x15.  */
	      print (info->stream, "%s",
		     riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
	      break;
	    case 'U': /* RS1, constrained to equal RD.  */
	      print (info->stream, "%s", riscv_gpr_names[rd]);
	      break;
	    case 'c': /* RS1, constrained to equal sp.  */
	      print (info->stream, "%s", riscv_gpr_names[X_SP]);
	      break;
	    case 'V': /* RS2 */
	      print (info->stream, "%s",
		     riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
	      break;
	    case 'o':
	    case 'j':
	      print (info->stream, "%d", (int)EXTRACT_CITYPE_IMM (l));
	      break;
	    case 'k':
	      print (info->stream, "%d", (int)EXTRACT_CLTYPE_LW_IMM (l));
	      break;
	    case 'l':
	      print (info->stream, "%d", (int)EXTRACT_CLTYPE_LD_IMM (l));
	      break;
	    case 'm':
	      print (info->stream, "%d", (int)EXTRACT_CITYPE_LWSP_IMM (l));
	      break;
	    case 'n':
	      print (info->stream, "%d", (int)EXTRACT_CITYPE_LDSP_IMM (l));
	      break;
	    case 'K':
	      print (info->stream, "%d", (int)EXTRACT_CIWTYPE_ADDI4SPN_IMM (l));
	      break;
	    case 'L':
	      print (info->stream, "%d", (int)EXTRACT_CITYPE_ADDI16SP_IMM (l));
	      break;
	    case 'M':
	      print (info->stream, "%d", (int)EXTRACT_CSSTYPE_SWSP_IMM (l));
	      break;
	    case 'N':
	      print (info->stream, "%d", (int)EXTRACT_CSSTYPE_SDSP_IMM (l));
	      break;
	    case 'p':
	      info->target = EXTRACT_CBTYPE_IMM (l) + pc;
	      (*info->print_address_func) (info->target, info);
	      break;
	    case 'a':
	      info->target = EXTRACT_CJTYPE_IMM (l) + pc;
	      (*info->print_address_func) (info->target, info);
	      break;
	    case 'u':
	      print (info->stream, "0x%x",
		     (int)(EXTRACT_CITYPE_IMM (l) & (RISCV_BIGIMM_REACH-1)));
	      break;
	    case '>':
	      print (info->stream, "0x%x", (int)EXTRACT_CITYPE_IMM (l) & 0x3f);
	      break;
	    case '<':
	      print (info->stream, "0x%x", (int)EXTRACT_CITYPE_IMM (l) & 0x1f);
	      break;
	    case 'T': /* Floating-point RS2.  */
	      print (info->stream, "%s",
		     riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
	      break;
	    case 'D': /* Floating-point RS2 x8-x15.  */
	      print (info->stream, "%s",
		     riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
	      break;
	    }
	  break;

	case ',':
	case '(':
	case ')':
	case '[':
	case ']':
	  print (info->stream, "%c", *d);
	  break;

	case '0':
	  /* Only print constant 0 if it is the last argument.  */
	  if (!d[1])
	    print (info->stream, "0");
	  break;

	case 'b':
	case 's':
	  if ((l & MASK_JALR) == MATCH_JALR)
	    maybe_print_address (pd, rs1, 0);
	  print (info->stream, "%s", riscv_gpr_names[rs1]);
	  break;

	case 't':
	  print (info->stream, "%s",
		 riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
	  break;

	case 'u':
	  print (info->stream, "0x%x",
		 (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
	  break;

	case 'm':
	  arg_print (info, EXTRACT_OPERAND (RM, l),
		     riscv_rm, ARRAY_SIZE (riscv_rm));
	  break;

	case 'P':
	  arg_print (info, EXTRACT_OPERAND (PRED, l),
		     riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
	  break;

	case 'Q':
	  arg_print (info, EXTRACT_OPERAND (SUCC, l),
		     riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
	  break;

	case 'o':
	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
	  /* Fall through.  */
	case 'j':
	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
	      || (l & MASK_JALR) == MATCH_JALR)
	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
	  print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l));
	  break;

	case 'q':
	  maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l));
	  print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
	  break;

	case 'a':
	  info->target = EXTRACT_JTYPE_IMM (l) + pc;
	  (*info->print_address_func) (info->target, info);
	  break;

	case 'p':
	  info->target = EXTRACT_BTYPE_IMM (l) + pc;
	  (*info->print_address_func) (info->target, info);
	  break;

	case 'd':
	  if ((l & MASK_AUIPC) == MATCH_AUIPC)
	    pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l);
	  else if ((l & MASK_LUI) == MATCH_LUI)
	    pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
	  else if ((l & MASK_C_LUI) == MATCH_C_LUI)
	    pd->hi_addr[rd] = EXTRACT_CITYPE_LUI_IMM (l);
	  print (info->stream, "%s", riscv_gpr_names[rd]);
	  break;

	case 'z':
	  print (info->stream, "%s", riscv_gpr_names[0]);
	  break;

	case '>':
	  print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
	  break;

	case '<':
	  print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
	  break;

	case 'S':
	case 'U':
	  print (info->stream, "%s", riscv_fpr_names[rs1]);
	  break;

	case 'T':
	  print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]);
	  break;

	case 'D':
	  print (info->stream, "%s", riscv_fpr_names[rd]);
	  break;

	case 'R':
	  print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
	  break;

	case 'E':
	  {
	    static const char *riscv_csr_hash[4096]; /* Total 2^12 CSRs.  */
	    static bfd_boolean init_csr = FALSE;
	    unsigned int csr = EXTRACT_OPERAND (CSR, l);

	    if (!init_csr)
	      {
		unsigned int i;
		for (i = 0; i < 4096; i++)
		  riscv_csr_hash[i] = NULL;

		/* Set to the newest privileged version.  */
		if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
		  default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;

#define DECLARE_CSR(name, num, class, define_version, abort_version)	\
		if (riscv_csr_hash[num] == NULL 			\
		    && ((define_version == PRIV_SPEC_CLASS_NONE 	\
			 && abort_version == PRIV_SPEC_CLASS_NONE)	\
			|| (default_priv_spec >= define_version 	\
			    && default_priv_spec < abort_version)))	\
		  riscv_csr_hash[num] = #name;
#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
		DECLARE_CSR (name, num, class, define_version, abort_version)
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
	      }

	    if (riscv_csr_hash[csr] != NULL)
	      print (info->stream, "%s", riscv_csr_hash[csr]);
	    else
	      print (info->stream, "0x%x", csr);
	    break;
	  }

	case 'Z':
	  print (info->stream, "%d", rs1);
	  break;

	default:
	  /* xgettext:c-format */
	  print (info->stream, _("# internal error, undefined modifier (%c)"),
		 *d);
	  return;
	}
    }
}

/* Print the RISC-V instruction at address MEMADDR in debugged memory,
   on using INFO.  Returns length of the instruction, in bytes.
   BIGENDIAN must be 1 if this is big-endian code, 0 if
   this is little-endian code.  */

static int
riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
{
  const struct riscv_opcode *op;
  static bfd_boolean init = 0;
  static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
  struct riscv_private_data *pd;
  int insnlen;

#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))

  /* Build a hash table to shorten the search time.  */
  if (! init)
    {
      for (op = riscv_opcodes; op->name; op++)
	if (!riscv_hash[OP_HASH_IDX (op->match)])
	  riscv_hash[OP_HASH_IDX (op->match)] = op;

      init = 1;
    }

  if (info->private_data == NULL)
    {
      int i;

      pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
      pd->gp = -1;
      pd->print_addr = -1;
      for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
	pd->hi_addr[i] = -1;

      for (i = 0; i < info->symtab_size; i++)
	if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
	  pd->gp = bfd_asymbol_value (info->symtab[i]);
    }
  else
    pd = info->private_data;

  insnlen = riscv_insn_length (word);

  /* RISC-V instructions are always little-endian.  */
  info->endian_code = BFD_ENDIAN_LITTLE;

  info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
  info->bytes_per_line = 8;
  /* We don't support constant pools, so this must be code.  */
  info->display_endian = info->endian_code;
  info->insn_info_valid = 1;
  info->branch_delay_insns = 0;
  info->data_size = 0;
  info->insn_type = dis_nonbranch;
  info->target = 0;
  info->target2 = 0;

  op = riscv_hash[OP_HASH_IDX (word)];
  if (op != NULL)
    {
      unsigned xlen = 0;

      /* If XLEN is not known, get its value from the ELF class.  */
      if (info->mach == bfd_mach_riscv64)
	xlen = 64;
      else if (info->mach == bfd_mach_riscv32)
	xlen = 32;
      else if (info->section != NULL)
	{
	  Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
	  xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
	}

      for (; op->name; op++)
	{
	  /* Does the opcode match?  */
	  if (! (op->match_func) (op, word))
	    continue;
	  /* Is this a pseudo-instruction and may we print it as such?  */
	  if (no_aliases && (op->pinfo & INSN_ALIAS))
	    continue;
	  /* Is this instruction restricted to a certain value of XLEN?  */
	  if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
	    continue;

	  /* It's a match.  */
	  (*info->fprintf_func) (info->stream, "%s", op->name);
	  print_insn_args (op->args, word, memaddr, info);

	  /* Try to disassemble multi-instruction addressing sequences.  */
	  if (pd->print_addr != (bfd_vma)-1)
	    {
	      info->target = pd->print_addr;
	      (*info->fprintf_func) (info->stream, " # ");
	      (*info->print_address_func) (info->target, info);
	      pd->print_addr = -1;
	    }

	  /* Finish filling out insn_info fields.  */
	  switch (op->pinfo & INSN_TYPE)
	    {
	    case INSN_BRANCH:
	      info->insn_type = dis_branch;
	      break;
	    case INSN_CONDBRANCH:
	      info->insn_type = dis_condbranch;
	      break;
	    case INSN_JSR:
	      info->insn_type = dis_jsr;
	      break;
	    case INSN_DREF:
	      info->insn_type = dis_dref;
	      break;
	    default:
	      break;
	    }

	  if (op->pinfo & INSN_DATA_SIZE)
	    {
	      int size = ((op->pinfo & INSN_DATA_SIZE)
			  >> INSN_DATA_SIZE_SHIFT);
	      info->data_size = 1 << (size - 1);
	    }

	  return insnlen;
	}
    }

  /* We did not find a match, so just print the instruction bits.  */
  info->insn_type = dis_noninsn;
  (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word);
  return insnlen;
}

int
print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
{
  bfd_byte packet[2];
  insn_t insn = 0;
  bfd_vma n;
  int status;

  if (info->disassembler_options != NULL)
    {
      parse_riscv_dis_options (info->disassembler_options);
      /* Avoid repeatedly parsing the options.  */
      info->disassembler_options = NULL;
    }
  else if (riscv_gpr_names == NULL)
    set_default_riscv_dis_options ();

  /* Instructions are a sequence of 2-byte packets in little-endian order.  */
  for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2)
    {
      status = (*info->read_memory_func) (memaddr + n, packet, 2, info);
      if (status != 0)
	{
	  /* Don't fail just because we fell off the end.  */
	  if (n > 0)
	    break;
	  (*info->memory_error_func) (status, memaddr, info);
	  return status;
	}

      insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n);
    }

  return riscv_disassemble_insn (memaddr, insn, info);
}

disassembler_ftype
riscv_get_disassembler (bfd *abfd)
{
  if (abfd)
    {
      const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section;
      if (bfd_get_section_by_name (abfd, sec_name) != NULL)
        {
	  obj_attribute *attr = elf_known_obj_attributes_proc (abfd);
	  unsigned int Tag_a = Tag_RISCV_priv_spec;
	  unsigned int Tag_b = Tag_RISCV_priv_spec_minor;
	  unsigned int Tag_c = Tag_RISCV_priv_spec_revision;
	  riscv_get_priv_spec_class_from_numbers (attr[Tag_a].i,
						  attr[Tag_b].i,
						  attr[Tag_c].i,
						  &default_priv_spec);
        }
    }
   return print_insn_riscv;
}

/* Prevent use of the fake labels that are generated as part of the DWARF
   and for relaxable relocations in the assembler.  */

bfd_boolean
riscv_symbol_is_valid (asymbol * sym,
                       struct disassemble_info * info ATTRIBUTE_UNUSED)
{
  const char * name;

  if (sym == NULL)
    return FALSE;

  name = bfd_asymbol_name (sym);

  return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0);
}

void
print_riscv_disassembler_options (FILE *stream)
{
  fprintf (stream, _("\n\
The following RISC-V-specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));

  fprintf (stream, _("\n\
  numeric         Print numeric register names, rather than ABI names.\n"));

  fprintf (stream, _("\n\
  no-aliases      Disassemble only into canonical instructions, rather\n\
                  than into pseudoinstructions.\n"));

  fprintf (stream, _("\n\
  priv-spec=PRIV  Print the CSR according to the chosen privilege spec\n\
                  (1.9, 1.9.1, 1.10, 1.11).\n"));

  fprintf (stream, _("\n"));
}
Commit	Line	Data
e23eba97	1	/* RISC-V disassembler
250d07de	2	Copyright (C) 2011-2021 Free Software Foundation, Inc.
e23eba97 NC	3
	4	Contributed by Andrew Waterman (andrew@sifive.com).
	5	Based on MIPS target.
	6
	7	This file is part of the GNU opcodes library.
	8
	9	This library is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 3, or (at your option)
	12	any later version.
	13
	14	It is distributed in the hope that it will be useful, but WITHOUT
	15	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	16	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	17	License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with this program; see the file COPYING3. If not,
	21	see <http://www.gnu.org/licenses/>. */
	22
	23	#include "sysdep.h"
88c1242d	24	#include "disassemble.h"
e23eba97 NC	25	#include "libiberty.h"
	26	#include "opcode/riscv.h"
	27	#include "opintl.h"
	28	#include "elf-bfd.h"
	29	#include "elf/riscv.h"
3d73d29e	30	#include "cpu-riscv.h"
e23eba97	31
2d5d5a8f	32	#include "bfd_stdint.h"
e23eba97 NC	33	#include <ctype.h>
e23eba97 NC	34
3d73d29e	35	static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
8f595e9b	36
e23eba97 NC	37	struct riscv_private_data
	38	{
	39	bfd_vma gp;
	40	bfd_vma print_addr;
	41	bfd_vma hi_addr[OP_MASK_RD + 1];
	42	};
	43
	44	static const char * const *riscv_gpr_names;
	45	static const char * const *riscv_fpr_names;
	46
dcd709e0 NC	47	/* If set, disassemble as most general instruction. */
dcd709e0 NC	48	static int no_aliases;
e23eba97 NC	49
	50	static void
	51	set_default_riscv_dis_options (void)
	52	{
	53	riscv_gpr_names = riscv_gpr_names_abi;
	54	riscv_fpr_names = riscv_fpr_names_abi;
	55	no_aliases = 0;
	56	}
	57
8f595e9b NC	58	static bfd_boolean
8f595e9b NC	59	parse_riscv_dis_option_without_args (const char *option)
e23eba97 NC	60	{
	61	if (strcmp (option, "no-aliases") == 0)
	62	no_aliases = 1;
	63	else if (strcmp (option, "numeric") == 0)
	64	{
	65	riscv_gpr_names = riscv_gpr_names_numeric;
	66	riscv_fpr_names = riscv_fpr_names_numeric;
	67	}
8f595e9b NC	68	else
	69	return FALSE;
	70	return TRUE;
	71	}
	72
	73	static void
	74	parse_riscv_dis_option (const char *option)
	75	{
	76	char equal, value;
	77
	78	if (parse_riscv_dis_option_without_args (option))
	79	return;
	80
	81	equal = strchr (option, '=');
	82	if (equal == NULL)
	83	{
	84	/* The option without '=' should be defined above. */
	85	opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
	86	return;
	87	}
	88	if (equal == option
	89	\|\| *(equal + 1) == '\0')
	90	{
	91	/* Invalid options with '=', no option name before '=',
	92	and no value after '='. */
	93	opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
	94	option);
	95	return;
	96	}
	97
	98	*equal = '\0';
	99	value = equal + 1;
	100	if (strcmp (option, "priv-spec") == 0)
	101	{
3d73d29e NC	102	enum riscv_spec_class priv_spec = PRIV_SPEC_CLASS_NONE;
	103	const char *name = NULL;
	104
	105	RISCV_GET_PRIV_SPEC_CLASS (value, priv_spec);
	106	if (priv_spec == PRIV_SPEC_CLASS_NONE)
b800637e	107	opcodes_error_handler (_("unknown privileged spec set by %s=%s"),
8152e040 NC	108	option, value);
	109	else if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
	110	default_priv_spec = priv_spec;
	111	else if (default_priv_spec != priv_spec)
3d73d29e NC	112	{
	113	RISCV_GET_PRIV_SPEC_NAME (name, default_priv_spec);
	114	opcodes_error_handler (_("mis-matched privilege spec set by %s=%s, "
	115	"the elf privilege attribute is %s"),
	116	option, value, name);
	117	}
8f595e9b	118	}
e23eba97 NC	119	else
e23eba97 NC	120	{
a6743a54 AM	121	/* xgettext:c-format */
a6743a54 AM	122	opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
e23eba97 NC	123	}
	124	}
	125
	126	static void
	127	parse_riscv_dis_options (const char *opts_in)
	128	{
	129	char opts = xstrdup (opts_in), opt = opts, *opt_end = opts;
	130
	131	set_default_riscv_dis_options ();
	132
	133	for ( ; opt_end != NULL; opt = opt_end + 1)
	134	{
	135	if ((opt_end = strchr (opt, ',')) != NULL)
	136	*opt_end = 0;
	137	parse_riscv_dis_option (opt);
	138	}
	139
	140	free (opts);
	141	}
	142
	143	/* Print one argument from an array. */
	144
	145	static void
	146	arg_print (struct disassemble_info *info, unsigned long val,
	147	const char* const* array, size_t size)
	148	{
	149	const char *s = val >= size \|\| array[val] == NULL ? "unknown" : array[val];
	150	(*info->fprintf_func) (info->stream, "%s", s);
	151	}
	152
	153	static void
	154	maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
	155	{
	156	if (pd->hi_addr[base_reg] != (bfd_vma)-1)
	157	{
35fd2b2b	158	pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
e23eba97 NC	159	pd->hi_addr[base_reg] = -1;
	160	}
	161	else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
	162	pd->print_addr = pd->gp + offset;
	163	else if (base_reg == X_TP \|\| base_reg == 0)
	164	pd->print_addr = offset;
	165	}
	166
	167	/* Print insn arguments for 32/64-bit code. */
	168
	169	static void
	170	print_insn_args (const char d, insn_t l, bfd_vma pc, disassemble_info info)
	171	{
	172	struct riscv_private_data *pd = info->private_data;
	173	int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
	174	int rd = (l >> OP_SH_RD) & OP_MASK_RD;
	175	fprintf_ftype print = info->fprintf_func;
	176
	177	if (*d != '\0')
	178	print (info->stream, "\t");
	179
	180	for (; *d != '\0'; d++)
	181	{
	182	switch (*d)
	183	{
	184	case 'C': /* RVC */
	185	switch (*++d)
	186	{
dcd709e0 NC	187	case 's': /* RS1 x8-x15. */
dcd709e0 NC	188	case 'w': /* RS1 x8-x15. */
e23eba97 NC	189	print (info->stream, "%s",
	190	riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
	191	break;
dcd709e0 NC	192	case 't': /* RS2 x8-x15. */
dcd709e0 NC	193	case 'x': /* RS2 x8-x15. */
e23eba97 NC	194	print (info->stream, "%s",
	195	riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
	196	break;
dcd709e0	197	case 'U': /* RS1, constrained to equal RD. */
e23eba97 NC	198	print (info->stream, "%s", riscv_gpr_names[rd]);
e23eba97 NC	199	break;
dcd709e0	200	case 'c': /* RS1, constrained to equal sp. */
e23eba97 NC	201	print (info->stream, "%s", riscv_gpr_names[X_SP]);
	202	break;
	203	case 'V': /* RS2 */
	204	print (info->stream, "%s",
	205	riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
	206	break;
f91d48de	207	case 'o':
e23eba97	208	case 'j':
5a9f5403	209	print (info->stream, "%d", (int)EXTRACT_CITYPE_IMM (l));
e23eba97 NC	210	break;
e23eba97 NC	211	case 'k':
5a9f5403	212	print (info->stream, "%d", (int)EXTRACT_CLTYPE_LW_IMM (l));
e23eba97 NC	213	break;
e23eba97 NC	214	case 'l':
5a9f5403	215	print (info->stream, "%d", (int)EXTRACT_CLTYPE_LD_IMM (l));
e23eba97 NC	216	break;
e23eba97 NC	217	case 'm':
5a9f5403	218	print (info->stream, "%d", (int)EXTRACT_CITYPE_LWSP_IMM (l));
e23eba97 NC	219	break;
e23eba97 NC	220	case 'n':
5a9f5403	221	print (info->stream, "%d", (int)EXTRACT_CITYPE_LDSP_IMM (l));
e23eba97 NC	222	break;
e23eba97 NC	223	case 'K':
5a9f5403	224	print (info->stream, "%d", (int)EXTRACT_CIWTYPE_ADDI4SPN_IMM (l));
e23eba97 NC	225	break;
e23eba97 NC	226	case 'L':
5a9f5403	227	print (info->stream, "%d", (int)EXTRACT_CITYPE_ADDI16SP_IMM (l));
e23eba97 NC	228	break;
e23eba97 NC	229	case 'M':
5a9f5403	230	print (info->stream, "%d", (int)EXTRACT_CSSTYPE_SWSP_IMM (l));
e23eba97 NC	231	break;
e23eba97 NC	232	case 'N':
5a9f5403	233	print (info->stream, "%d", (int)EXTRACT_CSSTYPE_SDSP_IMM (l));
e23eba97 NC	234	break;
e23eba97 NC	235	case 'p':
5a9f5403	236	info->target = EXTRACT_CBTYPE_IMM (l) + pc;
e23eba97 NC	237	(*info->print_address_func) (info->target, info);
	238	break;
	239	case 'a':
5a9f5403	240	info->target = EXTRACT_CJTYPE_IMM (l) + pc;
e23eba97 NC	241	(*info->print_address_func) (info->target, info);
	242	break;
	243	case 'u':
	244	print (info->stream, "0x%x",
5a9f5403	245	(int)(EXTRACT_CITYPE_IMM (l) & (RISCV_BIGIMM_REACH-1)));
e23eba97 NC	246	break;
e23eba97 NC	247	case '>':
5a9f5403	248	print (info->stream, "0x%x", (int)EXTRACT_CITYPE_IMM (l) & 0x3f);
e23eba97 NC	249	break;
e23eba97 NC	250	case '<':
5a9f5403	251	print (info->stream, "0x%x", (int)EXTRACT_CITYPE_IMM (l) & 0x1f);
e23eba97	252	break;
dcd709e0	253	case 'T': /* Floating-point RS2. */
e23eba97 NC	254	print (info->stream, "%s",
	255	riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
	256	break;
dcd709e0	257	case 'D': /* Floating-point RS2 x8-x15. */
e23eba97 NC	258	print (info->stream, "%s",
	259	riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
	260	break;
	261	}
	262	break;
	263
	264	case ',':
	265	case '(':
	266	case ')':
	267	case '[':
	268	case ']':
	269	print (info->stream, "%c", *d);
	270	break;
	271
	272	case '0':
dcd709e0	273	/* Only print constant 0 if it is the last argument. */
e23eba97 NC	274	if (!d[1])
	275	print (info->stream, "0");
	276	break;
	277
	278	case 'b':
	279	case 's':
35eeb78f JW	280	if ((l & MASK_JALR) == MATCH_JALR)
35eeb78f JW	281	maybe_print_address (pd, rs1, 0);
e23eba97 NC	282	print (info->stream, "%s", riscv_gpr_names[rs1]);
	283	break;
	284
	285	case 't':
	286	print (info->stream, "%s",
	287	riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
	288	break;
	289
	290	case 'u':
	291	print (info->stream, "0x%x",
	292	(unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
	293	break;
	294
	295	case 'm':
	296	arg_print (info, EXTRACT_OPERAND (RM, l),
	297	riscv_rm, ARRAY_SIZE (riscv_rm));
	298	break;
	299
	300	case 'P':
	301	arg_print (info, EXTRACT_OPERAND (PRED, l),
	302	riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
	303	break;
	304
	305	case 'Q':
	306	arg_print (info, EXTRACT_OPERAND (SUCC, l),
	307	riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
	308	break;
	309
	310	case 'o':
	311	maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
b52d3cfc	312	/* Fall through. */
e23eba97 NC	313	case 'j':
	314	if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
	315	\|\| (l & MASK_JALR) == MATCH_JALR)
	316	maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
	317	print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l));
	318	break;
	319
	320	case 'q':
	321	maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l));
	322	print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
	323	break;
	324
	325	case 'a':
5a9f5403	326	info->target = EXTRACT_JTYPE_IMM (l) + pc;
e23eba97 NC	327	(*info->print_address_func) (info->target, info);
	328	break;
	329
	330	case 'p':
5a9f5403	331	info->target = EXTRACT_BTYPE_IMM (l) + pc;
e23eba97 NC	332	(*info->print_address_func) (info->target, info);
	333	break;
	334
	335	case 'd':
	336	if ((l & MASK_AUIPC) == MATCH_AUIPC)
	337	pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l);
	338	else if ((l & MASK_LUI) == MATCH_LUI)
	339	pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
	340	else if ((l & MASK_C_LUI) == MATCH_C_LUI)
5a9f5403	341	pd->hi_addr[rd] = EXTRACT_CITYPE_LUI_IMM (l);
e23eba97 NC	342	print (info->stream, "%s", riscv_gpr_names[rd]);
	343	break;
	344
	345	case 'z':
	346	print (info->stream, "%s", riscv_gpr_names[0]);
	347	break;
	348
	349	case '>':
	350	print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
	351	break;
	352
	353	case '<':
	354	print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
	355	break;
	356
	357	case 'S':
	358	case 'U':
	359	print (info->stream, "%s", riscv_fpr_names[rs1]);
	360	break;
	361
	362	case 'T':
	363	print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]);
	364	break;
	365
	366	case 'D':
	367	print (info->stream, "%s", riscv_fpr_names[rd]);
	368	break;
	369
	370	case 'R':
	371	print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
	372	break;
	373
	374	case 'E':
	375	{
dcd709e0	376	static const char riscv_csr_hash[4096]; / Total 2^12 CSRs. */
8f595e9b	377	static bfd_boolean init_csr = FALSE;
e23eba97	378	unsigned int csr = EXTRACT_OPERAND (CSR, l);
8f595e9b NC	379
8f595e9b NC	380	if (!init_csr)
e23eba97	381	{
8f595e9b NC	382	unsigned int i;
	383	for (i = 0; i < 4096; i++)
	384	riscv_csr_hash[i] = NULL;
	385
dcd709e0	386	/* Set to the newest privileged version. */
8f595e9b NC	387	if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
	388	default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
	389
08ccfccf NC	390	#define DECLARE_CSR(name, num, class, define_version, abort_version) \
	391	if (riscv_csr_hash[num] == NULL \
	392	&& ((define_version == PRIV_SPEC_CLASS_NONE \
	393	&& abort_version == PRIV_SPEC_CLASS_NONE) \
	394	\|\| (default_priv_spec >= define_version \
	395	&& default_priv_spec < abort_version))) \
8f595e9b NC	396	riscv_csr_hash[num] = #name;
	397	#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
	398	DECLARE_CSR (name, num, class, define_version, abort_version)
e23eba97 NC	399	#include "opcode/riscv-opc.h"
	400	#undef DECLARE_CSR
	401	}
8f595e9b NC	402
	403	if (riscv_csr_hash[csr] != NULL)
	404	print (info->stream, "%s", riscv_csr_hash[csr]);
e23eba97 NC	405	else
	406	print (info->stream, "0x%x", csr);
	407	break;
	408	}
	409
	410	case 'Z':
	411	print (info->stream, "%d", rs1);
	412	break;
	413
	414	default:
	415	/* xgettext:c-format */
	416	print (info->stream, _("# internal error, undefined modifier (%c)"),
	417	*d);
	418	return;
	419	}
	420	}
	421	}
	422
	423	/* Print the RISC-V instruction at address MEMADDR in debugged memory,
	424	on using INFO. Returns length of the instruction, in bytes.
	425	BIGENDIAN must be 1 if this is big-endian code, 0 if
	426	this is little-endian code. */
	427
	428	static int
	429	riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
	430	{
	431	const struct riscv_opcode *op;
	432	static bfd_boolean init = 0;
	433	static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
	434	struct riscv_private_data *pd;
	435	int insnlen;
	436
	437	#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
	438
	439	/* Build a hash table to shorten the search time. */
	440	if (! init)
	441	{
	442	for (op = riscv_opcodes; op->name; op++)
	443	if (!riscv_hash[OP_HASH_IDX (op->match)])
	444	riscv_hash[OP_HASH_IDX (op->match)] = op;
	445
	446	init = 1;
	447	}
	448
	449	if (info->private_data == NULL)
	450	{
	451	int i;
	452
	453	pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
	454	pd->gp = -1;
	455	pd->print_addr = -1;
	456	for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
	457	pd->hi_addr[i] = -1;
	458
	459	for (i = 0; i < info->symtab_size; i++)
b5292032	460	if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
e23eba97 NC	461	pd->gp = bfd_asymbol_value (info->symtab[i]);
	462	}
	463	else
	464	pd = info->private_data;
	465
	466	insnlen = riscv_insn_length (word);
	467
d7560e2d JW	468	/* RISC-V instructions are always little-endian. */
	469	info->endian_code = BFD_ENDIAN_LITTLE;
	470
e23eba97 NC	471	info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
e23eba97 NC	472	info->bytes_per_line = 8;
d7560e2d JW	473	/* We don't support constant pools, so this must be code. */
d7560e2d JW	474	info->display_endian = info->endian_code;
e23eba97 NC	475	info->insn_info_valid = 1;
	476	info->branch_delay_insns = 0;
	477	info->data_size = 0;
	478	info->insn_type = dis_nonbranch;
	479	info->target = 0;
	480	info->target2 = 0;
	481
	482	op = riscv_hash[OP_HASH_IDX (word)];
	483	if (op != NULL)
	484	{
1080bf78	485	unsigned xlen = 0;
e23eba97	486
2922d21d AW	487	/* If XLEN is not known, get its value from the ELF class. */
	488	if (info->mach == bfd_mach_riscv64)
	489	xlen = 64;
	490	else if (info->mach == bfd_mach_riscv32)
	491	xlen = 32;
	492	else if (info->section != NULL)
e23eba97 NC	493	{
	494	Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
	495	xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
	496	}
	497
	498	for (; op->name; op++)
	499	{
	500	/* Does the opcode match? */
	501	if (! (op->match_func) (op, word))
	502	continue;
	503	/* Is this a pseudo-instruction and may we print it as such? */
	504	if (no_aliases && (op->pinfo & INSN_ALIAS))
	505	continue;
	506	/* Is this instruction restricted to a certain value of XLEN? */
43135d3b	507	if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
e23eba97 NC	508	continue;
	509
	510	/* It's a match. */
	511	(*info->fprintf_func) (info->stream, "%s", op->name);
	512	print_insn_args (op->args, word, memaddr, info);
	513
	514	/* Try to disassemble multi-instruction addressing sequences. */
	515	if (pd->print_addr != (bfd_vma)-1)
	516	{
	517	info->target = pd->print_addr;
	518	(*info->fprintf_func) (info->stream, " # ");
	519	(*info->print_address_func) (info->target, info);
	520	pd->print_addr = -1;
	521	}
	522
eb41b248 JW	523	/* Finish filling out insn_info fields. */
	524	switch (op->pinfo & INSN_TYPE)
	525	{
	526	case INSN_BRANCH:
	527	info->insn_type = dis_branch;
	528	break;
	529	case INSN_CONDBRANCH:
	530	info->insn_type = dis_condbranch;
	531	break;
	532	case INSN_JSR:
	533	info->insn_type = dis_jsr;
	534	break;
	535	case INSN_DREF:
	536	info->insn_type = dis_dref;
	537	break;
	538	default:
	539	break;
	540	}
	541
	542	if (op->pinfo & INSN_DATA_SIZE)
	543	{
	544	int size = ((op->pinfo & INSN_DATA_SIZE)
	545	>> INSN_DATA_SIZE_SHIFT);
	546	info->data_size = 1 << (size - 1);
	547	}
	548
e23eba97 NC	549	return insnlen;
	550	}
	551	}
	552
	553	/* We did not find a match, so just print the instruction bits. */
	554	info->insn_type = dis_noninsn;
	555	(*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word);
	556	return insnlen;
	557	}
	558
	559	int
	560	print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
	561	{
	562	bfd_byte packet[2];
	563	insn_t insn = 0;
	564	bfd_vma n;
	565	int status;
	566
	567	if (info->disassembler_options != NULL)
	568	{
	569	parse_riscv_dis_options (info->disassembler_options);
	570	/* Avoid repeatedly parsing the options. */
	571	info->disassembler_options = NULL;
	572	}
	573	else if (riscv_gpr_names == NULL)
	574	set_default_riscv_dis_options ();
	575
	576	/* Instructions are a sequence of 2-byte packets in little-endian order. */
	577	for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2)
	578	{
	579	status = (*info->read_memory_func) (memaddr + n, packet, 2, info);
	580	if (status != 0)
	581	{
	582	/* Don't fail just because we fell off the end. */
	583	if (n > 0)
	584	break;
	585	(*info->memory_error_func) (status, memaddr, info);
	586	return status;
	587	}
	588
	589	insn \|= ((insn_t) bfd_getl16 (packet)) << (8 * n);
	590	}
	591
	592	return riscv_disassemble_insn (memaddr, insn, info);
	593	}
	594
8152e040 NC	595	disassembler_ftype
	596	riscv_get_disassembler (bfd *abfd)
	597	{
8152e040 NC	598	if (abfd)
	599	{
	600	const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section;
	601	if (bfd_get_section_by_name (abfd, sec_name) != NULL)
	602	{
	603	obj_attribute *attr = elf_known_obj_attributes_proc (abfd);
	604	unsigned int Tag_a = Tag_RISCV_priv_spec;
	605	unsigned int Tag_b = Tag_RISCV_priv_spec_minor;
	606	unsigned int Tag_c = Tag_RISCV_priv_spec_revision;
	607	riscv_get_priv_spec_class_from_numbers (attr[Tag_a].i,
	608	attr[Tag_b].i,
	609	attr[Tag_c].i,
	610	&default_priv_spec);
	611	}
	612	}
	613	return print_insn_riscv;
	614	}
	615
884b49e3 AB	616	/* Prevent use of the fake labels that are generated as part of the DWARF
	617	and for relaxable relocations in the assembler. */
	618
	619	bfd_boolean
	620	riscv_symbol_is_valid (asymbol * sym,
	621	struct disassemble_info * info ATTRIBUTE_UNUSED)
	622	{
	623	const char * name;
	624
	625	if (sym == NULL)
	626	return FALSE;
	627
	628	name = bfd_asymbol_name (sym);
	629
	630	return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0);
	631	}
	632
e23eba97 NC	633	void
	634	print_riscv_disassembler_options (FILE *stream)
	635	{
	636	fprintf (stream, _("\n\
	637	The following RISC-V-specific disassembler options are supported for use\n\
	638	with the -M switch (multiple options should be separated by commas):\n"));
	639
	640	fprintf (stream, _("\n\
8f595e9b NC	641	numeric Print numeric register names, rather than ABI names.\n"));
	642
	643	fprintf (stream, _("\n\
	644	no-aliases Disassemble only into canonical instructions, rather\n\
	645	than into pseudoinstructions.\n"));
e23eba97 NC	646
e23eba97 NC	647	fprintf (stream, _("\n\
8f595e9b NC	648	priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
8f595e9b NC	649	(1.9, 1.9.1, 1.10, 1.11).\n"));
e23eba97 NC	650
	651	fprintf (stream, _("\n"));
	652	}