projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 252b5132 | 1 | /* Assemble V850 instructions. |
| 250d07de | 2 | Copyright (C) 1996-2021 Free Software Foundation, Inc. |
| 252b5132 | 3 | |
| 9b201bb5 NC |
4 | This file is part of the GNU opcodes library. |
| 5 | ||
| 6 | This library is free software; you can redistribute it and/or modify | |
| 8ad30312 | 7 | it under the terms of the GNU General Public License as published by |
| 9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
| 9 | any later version. | |
| 252b5132 | 10 | |
| 9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
| 12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 14 | License for more details. | |
| 252b5132 | 15 | |
| 8ad30312 NC |
16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program; if not, write to the Free Software | |
| 47b0e7ad NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
| 19 | MA 02110-1301, USA. */ | |
| 252b5132 | 20 | |
| 0d8dfecf | 21 | #include "sysdep.h" |
| df7b86aa | 22 | #include <stdio.h> |
| 252b5132 | 23 | #include "opcode/v850.h" |
| 1cd986c5 | 24 | #include "bfd.h" |
| 252b5132 RH |
25 | #include "opintl.h" |
| 26 | ||
| 8ad30312 | 27 | /* Regular opcodes. */ |
| 252b5132 RH |
28 | #define OP(x) ((x & 0x3f) << 5) |
| 29 | #define OP_MASK OP (0x3f) | |
| 30 | ||
| 1cd986c5 NC |
31 | /* Conditional branch opcodes (Format III). */ |
| 32 | #define BOP(x) ((0x58 << 4) | (x & 0x0f)) | |
| 33 | #define BOP_MASK ((0x78 << 4) | 0x0f) | |
| 34 | ||
| 35 | /* Conditional branch opcodes (Format VII). */ | |
| 36 | #define BOP7(x) (0x107e0 | (x & 0xf)) | |
| 37 | #define BOP7_MASK (0x1ffe0 | 0xf) | |
| 252b5132 | 38 | |
| 8ad30312 | 39 | /* One-word opcodes. */ |
| 252b5132 RH |
40 | #define one(x) ((unsigned int) (x)) |
| 41 | ||
| 8ad30312 | 42 | /* Two-word opcodes. */ |
| 252b5132 | 43 | #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) |
| 1cd986c5 | 44 | |
| 252b5132 RH |
45 | \f |
| 46 | /* The functions used to insert and extract complicated operands. */ | |
| 47 | ||
| 48 | /* Note: There is a conspiracy between these functions and | |
| 49 | v850_insert_operand() in gas/config/tc-v850.c. Error messages | |
| 50 | containing the string 'out of range' will be ignored unless a | |
| 51 | specific command line option is given to GAS. */ | |
| 52 | ||
| 53 | static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); | |
| 54 | static const char * out_of_range = N_ ("displacement value is out of range"); | |
| 55 | static const char * not_aligned = N_ ("displacement value is not aligned"); | |
| 56 | ||
| 57 | static const char * immediate_out_of_range = N_ ("immediate value is out of range"); | |
| 1cd986c5 NC |
58 | static const char * branch_out_of_range = N_ ("branch value out of range"); |
| 59 | static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset"); | |
| 60 | static const char * branch_to_odd_offset = N_ ("branch to odd offset"); | |
| 78c8d46c NC |
61 | static const char * pos_out_of_range = N_ ("position value is out of range"); |
| 62 | static const char * width_out_of_range = N_ ("width value is out of range"); | |
| 63 | static const char * selid_out_of_range = N_ ("SelID is out of range"); | |
| 64 | static const char * vector8_out_of_range = N_ ("vector8 is out of range"); | |
| 65 | static const char * vector5_out_of_range = N_ ("vector5 is out of range"); | |
| 66 | static const char * imm10_out_of_range = N_ ("imm10 is out of range"); | |
| 67 | static const char * sr_selid_out_of_range = N_ ("SR/SelID is out of range"); | |
| 1cd986c5 NC |
68 | |
| 69 | int | |
| 70 | v850_msg_is_out_of_range (const char* msg) | |
| 71 | { | |
| 72 | return msg == out_of_range | |
| 73 | || msg == immediate_out_of_range | |
| 74 | || msg == branch_out_of_range; | |
| 75 | } | |
| 252b5132 RH |
76 | |
| 77 | static unsigned long | |
| 7c80dd4c | 78 | insert_i5div1 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 | 79 | { |
| 1cd986c5 | 80 | if (value > 30 || value < 2) |
| 252b5132 | 81 | { |
| 1cd986c5 NC |
82 | if (value & 1) |
| 83 | * errmsg = _(not_valid); | |
| 252b5132 | 84 | else |
| 1cd986c5 | 85 | * errmsg = _(out_of_range); |
| 252b5132 | 86 | } |
| 1cd986c5 NC |
87 | else if (value & 1) |
| 88 | * errmsg = _(not_aligned); | |
| 252b5132 | 89 | |
| 1cd986c5 NC |
90 | value = (32 - value)/2; |
| 91 | ||
| 92 | return (insn | ((value << (2+16)) & 0x3c0000)); | |
| 252b5132 RH |
93 | } |
| 94 | ||
| 95 | static unsigned long | |
| 1cd986c5 | 96 | extract_i5div1 (unsigned long insn, int * invalid) |
| 252b5132 | 97 | { |
| 1cd986c5 NC |
98 | unsigned long ret = (insn & 0x003c0000) >> (16+2); |
| 99 | ret = 32 - (ret * 2); | |
| 252b5132 | 100 | |
| 1cd986c5 NC |
101 | if (invalid != 0) |
| 102 | *invalid = (ret > 30 || ret < 2) ? 1 : 0; | |
| 252b5132 RH |
103 | return ret; |
| 104 | } | |
| 105 | ||
| 106 | static unsigned long | |
| 7c80dd4c | 107 | insert_i5div2 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 | 108 | { |
| 1cd986c5 | 109 | if (value > 30 || value < 4) |
| 252b5132 | 110 | { |
| 1cd986c5 NC |
111 | if (value & 1) |
| 112 | * errmsg = _(not_valid); | |
| 252b5132 | 113 | else |
| 1cd986c5 | 114 | * errmsg = _(out_of_range); |
| 252b5132 | 115 | } |
| 1cd986c5 NC |
116 | else if (value & 1) |
| 117 | * errmsg = _(not_aligned); | |
| 252b5132 | 118 | |
| 1cd986c5 NC |
119 | value = (32 - value)/2; |
| 120 | ||
| 78c8d46c | 121 | return insn | ((value << (2 + 16)) & 0x3c0000); |
| 252b5132 RH |
122 | } |
| 123 | ||
| 124 | static unsigned long | |
| 1cd986c5 | 125 | extract_i5div2 (unsigned long insn, int * invalid) |
| 252b5132 | 126 | { |
| 1cd986c5 NC |
127 | unsigned long ret = (insn & 0x003c0000) >> (16+2); |
| 128 | ret = 32 - (ret * 2); | |
| 252b5132 | 129 | |
| 1cd986c5 NC |
130 | if (invalid != 0) |
| 131 | *invalid = (ret > 30 || ret < 4) ? 1 : 0; | |
| 132 | return ret; | |
| 252b5132 RH |
133 | } |
| 134 | ||
| 135 | static unsigned long | |
| 7c80dd4c | 136 | insert_i5div3 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 | 137 | { |
| 1cd986c5 | 138 | if (value > 32 || value < 2) |
| 252b5132 | 139 | { |
| 1cd986c5 | 140 | if (value & 1) |
| 252b5132 RH |
141 | * errmsg = _(not_valid); |
| 142 | else | |
| 143 | * errmsg = _(out_of_range); | |
| 144 | } | |
| 1cd986c5 | 145 | else if (value & 1) |
| 252b5132 RH |
146 | * errmsg = _(not_aligned); |
| 147 | ||
| 1cd986c5 NC |
148 | value = (32 - value)/2; |
| 149 | ||
| 78c8d46c | 150 | return insn | ((value << (2+16)) & 0x3c0000); |
| 252b5132 RH |
151 | } |
| 152 | ||
| 153 | static unsigned long | |
| 1cd986c5 | 154 | extract_i5div3 (unsigned long insn, int * invalid) |
| 252b5132 | 155 | { |
| 1cd986c5 NC |
156 | unsigned long ret = (insn & 0x003c0000) >> (16+2); |
| 157 | ret = 32 - (ret * 2); | |
| 252b5132 | 158 | |
| 1cd986c5 NC |
159 | if (invalid != 0) |
| 160 | *invalid = (ret > 32 || ret < 2) ? 1 : 0; | |
| 161 | return ret; | |
| 252b5132 RH |
162 | } |
| 163 | ||
| 164 | static unsigned long | |
| 7c80dd4c | 165 | insert_d5_4 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 | 166 | { |
| 7c80dd4c | 167 | if (value > 0x1f) |
| 252b5132 | 168 | { |
| 1cd986c5 | 169 | if (value & 1) |
| 252b5132 RH |
170 | * errmsg = _(not_valid); |
| 171 | else | |
| 172 | * errmsg = _(out_of_range); | |
| 173 | } | |
| 1cd986c5 | 174 | else if (value & 1) |
| 252b5132 RH |
175 | * errmsg = _(not_aligned); |
| 176 | ||
| 177 | value >>= 1; | |
| 178 | ||
| 1cd986c5 | 179 | return insn | (value & 0x0f); |
| 252b5132 RH |
180 | } |
| 181 | ||
| 182 | static unsigned long | |
| 1cd986c5 | 183 | extract_d5_4 (unsigned long insn, int * invalid) |
| 252b5132 | 184 | { |
| 1cd986c5 NC |
185 | unsigned long ret = (insn & 0x0f); |
| 186 | ||
| 187 | ret <<= 1; | |
| 252b5132 | 188 | |
| 1cd986c5 NC |
189 | if (invalid != 0) |
| 190 | *invalid = 0; | |
| 191 | return ret; | |
| 252b5132 RH |
192 | } |
| 193 | ||
| 194 | static unsigned long | |
| 7c80dd4c | 195 | insert_d8_6 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 | 196 | { |
| 7c80dd4c | 197 | if (value > 0xff) |
| 252b5132 RH |
198 | { |
| 199 | if ((value % 4) != 0) | |
| 1cd986c5 | 200 | * errmsg = _(not_valid); |
| 252b5132 RH |
201 | else |
| 202 | * errmsg = _(out_of_range); | |
| 203 | } | |
| 204 | else if ((value % 4) != 0) | |
| 205 | * errmsg = _(not_aligned); | |
| 206 | ||
| 207 | value >>= 1; | |
| 208 | ||
| 47b0e7ad | 209 | return insn | (value & 0x7e); |
| 252b5132 RH |
210 | } |
| 211 | ||
| 212 | static unsigned long | |
| 1cd986c5 | 213 | extract_d8_6 (unsigned long insn, int * invalid) |
| 252b5132 RH |
214 | { |
| 215 | unsigned long ret = (insn & 0x7e); | |
| 216 | ||
| 1cd986c5 NC |
217 | ret <<= 1; |
| 218 | ||
| 219 | if (invalid != 0) | |
| 220 | *invalid = 0; | |
| 221 | return ret; | |
| 252b5132 RH |
222 | } |
| 223 | ||
| 224 | static unsigned long | |
| 7c80dd4c | 225 | insert_d8_7 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 | 226 | { |
| 7c80dd4c | 227 | if (value > 0xff) |
| 252b5132 | 228 | { |
| 1cd986c5 | 229 | if ((value % 2) != 0) |
| 252b5132 RH |
230 | * errmsg = _(not_valid); |
| 231 | else | |
| 1cd986c5 | 232 | * errmsg = _(out_of_range); |
| 252b5132 | 233 | } |
| 1cd986c5 | 234 | else if ((value % 2) != 0) |
| 252b5132 RH |
235 | * errmsg = _(not_aligned); |
| 236 | ||
| 237 | value >>= 1; | |
| 238 | ||
| 1cd986c5 | 239 | return insn | (value & 0x7f); |
| 252b5132 RH |
240 | } |
| 241 | ||
| 242 | static unsigned long | |
| 1cd986c5 | 243 | extract_d8_7 (unsigned long insn, int * invalid) |
| 252b5132 | 244 | { |
| 1cd986c5 NC |
245 | unsigned long ret = (insn & 0x7f); |
| 246 | ||
| 247 | ret <<= 1; | |
| 248 | ||
| 249 | if (invalid != 0) | |
| 250 | *invalid = 0; | |
| 251 | return ret; | |
| 252 | } | |
| 253 | ||
| 254 | static unsigned long | |
| 7c80dd4c | 255 | insert_v8 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 1cd986c5 | 256 | { |
| 7c80dd4c | 257 | if (value > 0xff) |
| 1cd986c5 NC |
258 | * errmsg = _(immediate_out_of_range); |
| 259 | ||
| 260 | return insn | (value & 0x1f) | ((value & 0xe0) << (27-5)); | |
| 261 | } | |
| 262 | ||
| 263 | static unsigned long | |
| 264 | extract_v8 (unsigned long insn, int * invalid) | |
| 265 | { | |
| 3f26eb3a | 266 | unsigned long ret = (insn & 0x1f) | ((insn >> (27-5)) & 0xe0); |
| 1cd986c5 NC |
267 | |
| 268 | if (invalid != 0) | |
| 269 | *invalid = 0; | |
| 270 | return ret; | |
| 271 | } | |
| 272 | ||
| 273 | static unsigned long | |
| 7c80dd4c | 274 | insert_d9 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 1cd986c5 | 275 | { |
| 7c80dd4c | 276 | if (value + 0x100 > 0x1ff) |
| 1cd986c5 NC |
277 | { |
| 278 | if ((value % 2) != 0) | |
| 279 | * errmsg = branch_out_of_range_and_odd_offset; | |
| 280 | else | |
| 281 | * errmsg = branch_out_of_range; | |
| 282 | } | |
| 283 | else if ((value % 2) != 0) | |
| 284 | * errmsg = branch_to_odd_offset; | |
| 285 | ||
| 286 | return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3); | |
| 287 | } | |
| 288 | ||
| 289 | static unsigned long | |
| 290 | extract_d9 (unsigned long insn, int * invalid) | |
| 291 | { | |
| 7c80dd4c | 292 | unsigned long ret = ((insn >> 7) & 0x1f0) | ((insn >> 3) & 0x0e); |
| 1cd986c5 | 293 | |
| 3f26eb3a | 294 | ret = (ret ^ 0x100) - 0x100; |
| 1cd986c5 NC |
295 | |
| 296 | if (invalid != 0) | |
| 297 | *invalid = 0; | |
| 298 | return ret; | |
| 299 | } | |
| 300 | ||
| 301 | static unsigned long | |
| 7c80dd4c | 302 | insert_u16_loop (unsigned long insn, unsigned long value, const char ** errmsg) |
| 1cd986c5 | 303 | { |
| 41702d50 NC |
304 | /* Loop displacement is encoded as a positive value, |
| 305 | even though the instruction branches backwards. */ | |
| 7c80dd4c | 306 | if (value > 0xffff) |
| 1cd986c5 NC |
307 | { |
| 308 | if ((value % 2) != 0) | |
| 309 | * errmsg = branch_out_of_range_and_odd_offset; | |
| 310 | else | |
| 311 | * errmsg = branch_out_of_range; | |
| 312 | } | |
| 313 | else if ((value % 2) != 0) | |
| 314 | * errmsg = branch_to_odd_offset; | |
| 315 | ||
| 41702d50 | 316 | return insn | ((value & 0xfffe) << 16); |
| 1cd986c5 NC |
317 | } |
| 318 | ||
| 319 | static unsigned long | |
| 320 | extract_u16_loop (unsigned long insn, int * invalid) | |
| 321 | { | |
| 322 | long ret = (insn >> 16) & 0xfffe; | |
| 1cd986c5 NC |
323 | |
| 324 | if (invalid != 0) | |
| 325 | *invalid = 0; | |
| 326 | return ret; | |
| 327 | } | |
| 328 | ||
| 329 | static unsigned long | |
| 7c80dd4c | 330 | insert_d16_15 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 1cd986c5 | 331 | { |
| 7c80dd4c | 332 | if (value + 0x8000 > 0xffff) |
| 1cd986c5 NC |
333 | { |
| 334 | if ((value % 2) != 0) | |
| 335 | * errmsg = _(not_valid); | |
| 336 | else | |
| 337 | * errmsg = _(out_of_range); | |
| 338 | } | |
| 339 | else if ((value % 2) != 0) | |
| 340 | * errmsg = _(not_aligned); | |
| 341 | ||
| 342 | return insn | ((value & 0xfffe) << 16); | |
| 343 | } | |
| 344 | ||
| 345 | static unsigned long | |
| 346 | extract_d16_15 (unsigned long insn, int * invalid) | |
| 347 | { | |
| 7c80dd4c | 348 | unsigned long ret = (insn >> 16) & 0xfffe; |
| 3f26eb3a AM |
349 | |
| 350 | ret = (ret ^ 0x8000) - 0x8000; | |
| 252b5132 | 351 | |
| 1cd986c5 NC |
352 | if (invalid != 0) |
| 353 | *invalid = 0; | |
| 354 | return ret; | |
| 252b5132 RH |
355 | } |
| 356 | ||
| 357 | static unsigned long | |
| 7c80dd4c | 358 | insert_d16_16 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 | 359 | { |
| 7c80dd4c | 360 | if (value + 0x8000 > 0xffff) |
| 252b5132 RH |
361 | * errmsg = _(out_of_range); |
| 362 | ||
| 47b0e7ad | 363 | return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5); |
| 252b5132 RH |
364 | } |
| 365 | ||
| 366 | static unsigned long | |
| 1cd986c5 | 367 | extract_d16_16 (unsigned long insn, int * invalid) |
| 252b5132 | 368 | { |
| 7c80dd4c | 369 | unsigned long ret = ((insn >> 16) & 0xfffe) | ((insn >> 5) & 1); |
| 3f26eb3a AM |
370 | |
| 371 | ret = (ret ^ 0x8000) - 0x8000; | |
| 47b0e7ad | 372 | |
| 1cd986c5 NC |
373 | if (invalid != 0) |
| 374 | *invalid = 0; | |
| 252b5132 RH |
375 | return ret; |
| 376 | } | |
| 377 | ||
| 1cd986c5 | 378 | static unsigned long |
| 7c80dd4c | 379 | insert_d17_16 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 1cd986c5 | 380 | { |
| 7c80dd4c | 381 | if (value + 0x10000 > 0x1ffff) |
| 1cd986c5 NC |
382 | * errmsg = _(out_of_range); |
| 383 | ||
| 384 | return insn | ((value & 0xfffe) << 16) | ((value & 0x10000) >> (16 - 4)); | |
| 385 | } | |
| 386 | ||
| 387 | static unsigned long | |
| 388 | extract_d17_16 (unsigned long insn, int * invalid) | |
| 389 | { | |
| 7c80dd4c | 390 | unsigned long ret = ((insn >> 16) & 0xfffe) | ((insn << (16 - 4)) & 0x10000); |
| 3f26eb3a AM |
391 | |
| 392 | ret = (ret ^ 0x10000) - 0x10000; | |
| 1cd986c5 NC |
393 | |
| 394 | if (invalid != 0) | |
| 395 | *invalid = 0; | |
| 7c80dd4c | 396 | return ret; |
| 1cd986c5 NC |
397 | } |
| 398 | ||
| 399 | static unsigned long | |
| 7c80dd4c | 400 | insert_d22 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 1cd986c5 | 401 | { |
| 7c80dd4c | 402 | if (value + 0x200000 > 0x3fffff) |
| 1cd986c5 NC |
403 | { |
| 404 | if ((value % 2) != 0) | |
| 405 | * errmsg = branch_out_of_range_and_odd_offset; | |
| 406 | else | |
| 407 | * errmsg = branch_out_of_range; | |
| 408 | } | |
| 409 | else if ((value % 2) != 0) | |
| 410 | * errmsg = branch_to_odd_offset; | |
| 411 | ||
| 412 | return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16); | |
| 413 | } | |
| 414 | ||
| 415 | static unsigned long | |
| 416 | extract_d22 (unsigned long insn, int * invalid) | |
| 417 | { | |
| 7c80dd4c | 418 | unsigned long ret = ((insn >> 16) & 0xfffe) | ((insn << 16) & 0x3f0000); |
| 1cd986c5 | 419 | |
| 3f26eb3a | 420 | ret = (ret ^ 0x200000) - 0x200000; |
| 1cd986c5 NC |
421 | |
| 422 | if (invalid != 0) | |
| 423 | *invalid = 0; | |
| 7c80dd4c | 424 | return ret; |
| 1cd986c5 NC |
425 | } |
| 426 | ||
| 427 | static unsigned long | |
| 7c80dd4c | 428 | insert_d23 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 1cd986c5 | 429 | { |
| 7c80dd4c | 430 | if (value + 0x400000 > 0x7fffff) |
| 3f26eb3a | 431 | * errmsg = out_of_range; |
| 1cd986c5 NC |
432 | |
| 433 | return insn | ((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)); | |
| 434 | } | |
| 435 | ||
| 78c8d46c | 436 | static unsigned long |
| 7c80dd4c | 437 | insert_d23_align1 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 78c8d46c | 438 | { |
| 7c80dd4c | 439 | if (value + 0x400000 > 0x7fffff) |
| 78c8d46c NC |
440 | { |
| 441 | if (value & 0x1) | |
| 442 | * errmsg = _(not_valid); | |
| 443 | else | |
| 444 | * errmsg = _(out_of_range); | |
| 445 | } | |
| 446 | else if (value & 0x1) | |
| 447 | * errmsg = _(not_aligned); | |
| 448 | ||
| 449 | return insn | ((value & 0x7e) << 4) | ((value & 0x7fff80) << (16 - 7)); | |
| 450 | } | |
| 451 | ||
| 1cd986c5 NC |
452 | static unsigned long |
| 453 | extract_d23 (unsigned long insn, int * invalid) | |
| 454 | { | |
| 7c80dd4c | 455 | unsigned long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fff80); |
| 1cd986c5 | 456 | |
| 3f26eb3a | 457 | ret = (ret ^ 0x400000) - 0x400000; |
| 1cd986c5 NC |
458 | |
| 459 | if (invalid != 0) | |
| 460 | *invalid = 0; | |
| 7c80dd4c | 461 | return ret; |
| 1cd986c5 NC |
462 | } |
| 463 | ||
| 252b5132 | 464 | static unsigned long |
| 7c80dd4c | 465 | insert_i9 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 | 466 | { |
| 7c80dd4c | 467 | if (value + 0x100 > 0x1ff) |
| 252b5132 RH |
468 | * errmsg = _(immediate_out_of_range); |
| 469 | ||
| 470 | return insn | ((value & 0x1e0) << 13) | (value & 0x1f); | |
| 471 | } | |
| 472 | ||
| 473 | static unsigned long | |
| 1cd986c5 | 474 | extract_i9 (unsigned long insn, int * invalid) |
| 252b5132 | 475 | { |
| 7c80dd4c | 476 | unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f); |
| 252b5132 | 477 | |
| 3f26eb3a | 478 | ret = (ret ^ 0x100) - 0x100; |
| 47b0e7ad | 479 | |
| 1cd986c5 NC |
480 | if (invalid != 0) |
| 481 | *invalid = 0; | |
| 252b5132 RH |
482 | return ret; |
| 483 | } | |
| 484 | ||
| 485 | static unsigned long | |
| 7c80dd4c | 486 | insert_u9 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 RH |
487 | { |
| 488 | if (value > 0x1ff) | |
| 489 | * errmsg = _(immediate_out_of_range); | |
| 490 | ||
| 491 | return insn | ((value & 0x1e0) << 13) | (value & 0x1f); | |
| 492 | } | |
| 493 | ||
| 494 | static unsigned long | |
| 1cd986c5 | 495 | extract_u9 (unsigned long insn, int * invalid) |
| 252b5132 | 496 | { |
| 3f26eb3a | 497 | unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f); |
| 47b0e7ad | 498 | |
| 1cd986c5 NC |
499 | if (invalid != 0) |
| 500 | *invalid = 0; | |
| 252b5132 RH |
501 | return ret; |
| 502 | } | |
| 503 | ||
| 504 | static unsigned long | |
| 7c80dd4c | 505 | insert_spe (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 RH |
506 | { |
| 507 | if (value != 3) | |
| 508 | * errmsg = _("invalid register for stack adjustment"); | |
| 509 | ||
| 3f26eb3a | 510 | return insn & ~0x180000; |
| 252b5132 RH |
511 | } |
| 512 | ||
| 513 | static unsigned long | |
| 1cd986c5 | 514 | extract_spe (unsigned long insn ATTRIBUTE_UNUSED, int * invalid) |
| 252b5132 | 515 | { |
| 1cd986c5 NC |
516 | if (invalid != 0) |
| 517 | *invalid = 0; | |
| 518 | ||
| 252b5132 RH |
519 | return 3; |
| 520 | } | |
| 521 | ||
| 522 | static unsigned long | |
| 7c80dd4c | 523 | insert_r4 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 252b5132 | 524 | { |
| 1cd986c5 | 525 | if (value >= 32) |
| 78c8d46c | 526 | * errmsg = _("invalid register name"); |
| 47b0e7ad | 527 | |
| 78c8d46c | 528 | return insn | ((value & 0x01) << 23) | ((value & 0x1e) << 16); |
| 252b5132 RH |
529 | } |
| 530 | ||
| 531 | static unsigned long | |
| 1cd986c5 | 532 | extract_r4 (unsigned long insn, int * invalid) |
| 252b5132 | 533 | { |
| 78c8d46c NC |
534 | unsigned long r4; |
| 535 | unsigned long insn2; | |
| 536 | ||
| 537 | insn2 = insn >> 16; | |
| 538 | r4 = (((insn2 & 0x0080) >> 7) | (insn2 & 0x001e)); | |
| 539 | ||
| 540 | if (invalid != 0) | |
| 541 | *invalid = 0; | |
| 542 | ||
| 543 | return r4; | |
| 544 | } | |
| 545 | ||
| 546 | static unsigned long G_pos; | |
| 547 | ||
| 548 | static unsigned long | |
| 7c80dd4c | 549 | insert_POS (unsigned long insn, unsigned long pos, const char ** errmsg) |
| 78c8d46c | 550 | { |
| 7c80dd4c | 551 | if (pos > 0x1f) |
| 78c8d46c NC |
552 | * errmsg = _(pos_out_of_range); |
| 553 | ||
| 7c80dd4c | 554 | G_pos = pos; |
| 78c8d46c NC |
555 | |
| 556 | return insn; /* Not an oparaton until WIDTH. */ | |
| 557 | } | |
| 558 | ||
| 559 | static unsigned long | |
| 560 | extract_POS_U (unsigned long insn, int * invalid) | |
| 561 | { | |
| 562 | unsigned long pos,lsb; | |
| 563 | unsigned long insn2; | |
| 564 | insn2 = insn >> 16; | |
| 565 | ||
| 566 | lsb = ((insn2 & 0x0800) >> 8) | |
| 567 | | ((insn2 & 0x000e) >> 1); | |
| 568 | lsb += 16; | |
| 569 | pos = lsb; | |
| 570 | ||
| 571 | if (invalid != 0) | |
| 572 | *invalid = 0; | |
| 573 | ||
| 574 | return pos; | |
| 575 | } | |
| 576 | ||
| 577 | static unsigned long | |
| 578 | extract_POS_L (unsigned long insn, int * invalid) | |
| 579 | { | |
| 580 | unsigned long pos,lsb; | |
| 581 | unsigned long insn2; | |
| 582 | insn2 = insn >> 16; | |
| 583 | ||
| 584 | lsb = ((insn2 & 0x0800) >> 8) | |
| 585 | | ((insn2 & 0x000e) >> 1); | |
| 586 | pos = lsb; | |
| 587 | ||
| 588 | if (invalid != 0) | |
| 589 | *invalid = 0; | |
| 590 | ||
| 591 | return pos; | |
| 592 | } | |
| 593 | ||
| 594 | static unsigned long | |
| 7c80dd4c | 595 | insert_WIDTH (unsigned long insn, unsigned long width, const char ** errmsg) |
| 78c8d46c NC |
596 | { |
| 597 | unsigned long msb, lsb, opc, ret; | |
| 598 | unsigned long msb_expand, lsb_expand; | |
| 599 | ||
| 7c80dd4c | 600 | msb = width + G_pos - 1; |
| 78c8d46c NC |
601 | lsb = G_pos; |
| 602 | opc = 0; | |
| 603 | G_pos = 0; | |
| 604 | ||
| 7c80dd4c | 605 | if (width > 0x20) |
| 78c8d46c NC |
606 | * errmsg = _(width_out_of_range); |
| 607 | ||
| 608 | if ((msb >= 16) && (lsb >= 16)) | |
| 609 | opc = 0x0090; | |
| 610 | else if ((msb >= 16) && (lsb < 16)) | |
| 611 | opc = 0x00b0; | |
| 612 | else if ((msb < 16) && (lsb < 16)) | |
| 613 | opc = 0x00d0; | |
| 614 | else | |
| 615 | * errmsg = _(width_out_of_range); | |
| 616 | ||
| 617 | msb &= 0x0f; | |
| 618 | msb_expand = msb << 12; | |
| 619 | lsb &= 0x0f; | |
| 620 | lsb_expand = ((lsb & 0x8) << 8)|((lsb & 0x7) << 1); | |
| 621 | ||
| 622 | ret = (insn & 0x0000ffff) | ((opc | msb_expand | lsb_expand) << 16); | |
| 623 | ||
| 624 | return ret; | |
| 625 | } | |
| 626 | ||
| 627 | static unsigned long | |
| 628 | extract_WIDTH_U (unsigned long insn, int * invalid) | |
| 629 | { | |
| 630 | unsigned long width, msb, lsb; | |
| 631 | unsigned long insn2; | |
| 632 | insn2 = insn >> 16; | |
| 633 | ||
| 634 | msb = ((insn2 & 0xf000) >> 12); | |
| 635 | msb += 16; | |
| 636 | lsb = ((insn2 & 0x0800) >> 8) | |
| 637 | | ((insn2 & 0x000e) >> 1); | |
| 638 | lsb += 16; | |
| 639 | ||
| 640 | if (invalid != 0) | |
| 641 | *invalid = 0; | |
| 642 | ||
| 643 | width = msb - lsb + 1; | |
| 644 | ||
| 645 | return width; | |
| 646 | } | |
| 647 | ||
| 648 | static unsigned long | |
| 649 | extract_WIDTH_M (unsigned long insn, int * invalid) | |
| 650 | { | |
| 651 | unsigned long width, msb, lsb; | |
| 652 | unsigned long insn2; | |
| 653 | insn2 = insn >> 16; | |
| 654 | ||
| 655 | msb = ((insn2 & 0xf000) >> 12) ; | |
| 656 | msb += 16; | |
| 657 | lsb = ((insn2 & 0x0800) >> 8) | |
| 658 | | ((insn2 & 0x000e) >> 1); | |
| 659 | ||
| 660 | if (invalid != 0) | |
| 661 | *invalid = 0; | |
| 662 | ||
| 663 | width = msb - lsb + 1; | |
| 664 | ||
| 665 | return width; | |
| 666 | } | |
| 667 | ||
| 668 | static unsigned long | |
| 669 | extract_WIDTH_L (unsigned long insn, int * invalid) | |
| 670 | { | |
| 671 | unsigned long width, msb, lsb; | |
| 672 | unsigned long insn2; | |
| 673 | insn2 = insn >> 16; | |
| 674 | ||
| 675 | msb = ((insn2 & 0xf000) >> 12) ; | |
| 676 | lsb = ((insn2 & 0x0800) >> 8) | |
| 677 | | ((insn2 & 0x000e) >> 1); | |
| 678 | ||
| 679 | if (invalid != 0) | |
| 680 | *invalid = 0; | |
| 681 | ||
| 682 | width = msb - lsb + 1; | |
| 683 | ||
| 684 | return width; | |
| 685 | } | |
| 686 | ||
| 687 | static unsigned long | |
| 7c80dd4c | 688 | insert_SELID (unsigned long insn, unsigned long selid, const char ** errmsg) |
| 78c8d46c | 689 | { |
| 7c80dd4c | 690 | if (selid > 0x1f) |
| 78c8d46c NC |
691 | * errmsg = _(selid_out_of_range); |
| 692 | ||
| 2480b6fa | 693 | return insn | ((selid & 0x1fUL) << 27); |
| 78c8d46c NC |
694 | } |
| 695 | ||
| 696 | static unsigned long | |
| 697 | extract_SELID (unsigned long insn, int * invalid) | |
| 698 | { | |
| 699 | unsigned long selid; | |
| 700 | unsigned long insn2; | |
| 701 | ||
| 702 | insn2 = insn >> 16; | |
| 703 | ||
| 704 | selid = ((insn2 & 0xf800) >> 11); | |
| 705 | ||
| 706 | if (invalid != 0) | |
| 707 | *invalid = 0; | |
| 708 | ||
| 709 | return selid; | |
| 710 | } | |
| 711 | ||
| 712 | static unsigned long | |
| 7c80dd4c | 713 | insert_VECTOR8 (unsigned long insn, unsigned long vector8, const char ** errmsg) |
| 78c8d46c NC |
714 | { |
| 715 | unsigned long ret; | |
| 7c80dd4c | 716 | unsigned long VVV, vvvvv; |
| 78c8d46c | 717 | |
| 7c80dd4c | 718 | if (vector8 > 0xff) |
| 78c8d46c NC |
719 | * errmsg = _(vector8_out_of_range); |
| 720 | ||
| 721 | VVV = (vector8 & 0xe0) >> 5; | |
| 722 | vvvvv = (vector8 & 0x1f); | |
| 723 | ||
| 724 | ret = (insn | (VVV << 27) | vvvvv); | |
| 725 | ||
| 726 | return ret; | |
| 727 | } | |
| 728 | ||
| 729 | static unsigned long | |
| 730 | extract_VECTOR8 (unsigned long insn, int * invalid) | |
| 731 | { | |
| 732 | unsigned long vector8; | |
| 733 | unsigned long VVV,vvvvv; | |
| 734 | unsigned long insn2; | |
| 735 | ||
| 736 | insn2 = insn >> 16; | |
| 737 | VVV = ((insn2 & 0x3800) >> 11); | |
| 738 | vvvvv = (insn & 0x001f); | |
| 739 | vector8 = VVV << 5 | vvvvv; | |
| 740 | ||
| 741 | if (invalid != 0) | |
| 742 | *invalid = 0; | |
| 743 | ||
| 744 | return vector8; | |
| 745 | } | |
| 746 | ||
| 747 | static unsigned long | |
| 7c80dd4c | 748 | insert_VECTOR5 (unsigned long insn, unsigned long vector5, const char ** errmsg) |
| 78c8d46c NC |
749 | { |
| 750 | unsigned long ret; | |
| 751 | unsigned long vvvvv; | |
| 752 | ||
| 7c80dd4c | 753 | if (vector5 > 0x1f) |
| 78c8d46c NC |
754 | * errmsg = _(vector5_out_of_range); |
| 755 | ||
| 756 | vvvvv = (vector5 & 0x1f); | |
| 757 | ||
| 758 | ret = (insn | vvvvv); | |
| 759 | ||
| 760 | return ret; | |
| 761 | } | |
| 762 | ||
| 763 | static unsigned long | |
| 764 | extract_VECTOR5 (unsigned long insn, int * invalid) | |
| 765 | { | |
| 766 | unsigned long vector5; | |
| 767 | ||
| 768 | vector5 = (insn & 0x001f); | |
| 769 | ||
| 770 | if (invalid != 0) | |
| 771 | *invalid = 0; | |
| 772 | ||
| 773 | return vector5; | |
| 774 | } | |
| 775 | ||
| 776 | static unsigned long | |
| 7c80dd4c | 777 | insert_CACHEOP (unsigned long insn, unsigned long cacheop, const char ** errmsg ATTRIBUTE_UNUSED) |
| 78c8d46c NC |
778 | { |
| 779 | unsigned long ret; | |
| 7c80dd4c | 780 | unsigned long pp, PPPPP; |
| 78c8d46c NC |
781 | |
| 782 | pp = (cacheop & 0x60) >> 5; | |
| 783 | PPPPP = (cacheop & 0x1f); | |
| 784 | ||
| 785 | ret = insn | (pp << 11) | (PPPPP << 27); | |
| 786 | ||
| 787 | return ret; | |
| 788 | } | |
| 789 | ||
| 790 | static unsigned long | |
| 791 | extract_CACHEOP (unsigned long insn, int * invalid) | |
| 792 | { | |
| 793 | unsigned long ret; | |
| 7c80dd4c | 794 | unsigned long pp, PPPPP; |
| 78c8d46c NC |
795 | unsigned long insn2; |
| 796 | ||
| 797 | insn2 = insn >> 16; | |
| 798 | ||
| 799 | PPPPP = ((insn2 & 0xf800) >> 11); | |
| 800 | pp = ((insn & 0x1800) >> 11); | |
| 801 | ||
| 802 | ret = (pp << 5) | PPPPP; | |
| 803 | ||
| 804 | if (invalid != 0) | |
| 805 | *invalid = 0; | |
| 806 | ||
| 807 | return ret; | |
| 808 | } | |
| 809 | ||
| 810 | static unsigned long | |
| 7c80dd4c | 811 | insert_PREFOP (unsigned long insn, unsigned long prefop, const char ** errmsg ATTRIBUTE_UNUSED) |
| 78c8d46c NC |
812 | { |
| 813 | unsigned long ret; | |
| 814 | unsigned long PPPPP; | |
| 815 | ||
| 816 | PPPPP = (prefop & 0x1f); | |
| 817 | ||
| 818 | ret = insn | (PPPPP << 27); | |
| 819 | ||
| 820 | return ret; | |
| 821 | } | |
| 822 | ||
| 823 | static unsigned long | |
| 824 | extract_PREFOP (unsigned long insn, int * invalid) | |
| 825 | { | |
| 826 | unsigned long ret; | |
| 827 | unsigned long PPPPP; | |
| 828 | unsigned long insn2; | |
| 829 | ||
| 830 | insn2 = insn >> 16; | |
| 831 | ||
| 832 | PPPPP = (insn2 & 0xf800) >> 11; | |
| 833 | ||
| 834 | ret = PPPPP; | |
| 835 | ||
| 836 | if (invalid != 0) | |
| 837 | *invalid = 0; | |
| 838 | ||
| 839 | return ret; | |
| 840 | } | |
| 841 | ||
| 842 | static unsigned long | |
| 7c80dd4c | 843 | insert_IMM10U (unsigned long insn, unsigned long value, const char ** errmsg) |
| 78c8d46c NC |
844 | { |
| 845 | unsigned long imm10, ret; | |
| 846 | unsigned long iiiii,IIIII; | |
| 847 | ||
| 7c80dd4c | 848 | if (value > 0x3ff) |
| 78c8d46c NC |
849 | * errmsg = _(imm10_out_of_range); |
| 850 | ||
| 7c80dd4c | 851 | imm10 = value & 0x3ff; |
| 78c8d46c NC |
852 | IIIII = (imm10 >> 5) & 0x1f; |
| 853 | iiiii = imm10 & 0x1f; | |
| 854 | ||
| 855 | ret = insn | IIIII << 27 | iiiii; | |
| 856 | ||
| 857 | return ret; | |
| 858 | } | |
| 859 | ||
| 860 | static unsigned long | |
| 861 | extract_IMM10U (unsigned long insn, int * invalid) | |
| 862 | { | |
| 863 | unsigned long ret; | |
| 864 | unsigned long iiiii,IIIII; | |
| 865 | unsigned long insn2; | |
| 866 | insn2 = insn >> 16; | |
| 867 | ||
| 868 | IIIII = ((insn2 & 0xf800) >> 11); | |
| 869 | iiiii = (insn & 0x001f); | |
| 870 | ||
| 871 | ret = (IIIII << 5) | iiiii; | |
| 872 | ||
| 873 | if (invalid != 0) | |
| 874 | *invalid = 0; | |
| 875 | ||
| 876 | return ret; | |
| 877 | } | |
| 878 | ||
| 879 | static unsigned long | |
| 7c80dd4c | 880 | insert_SRSEL1 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 78c8d46c NC |
881 | { |
| 882 | unsigned long imm10, ret; | |
| 883 | unsigned long sr,selid; | |
| 884 | ||
| 7c80dd4c | 885 | if (value > 0x3ff) |
| 78c8d46c NC |
886 | * errmsg = _(sr_selid_out_of_range); |
| 887 | ||
| 7c80dd4c | 888 | imm10 = value; |
| 78c8d46c NC |
889 | selid = (imm10 & 0x3e0) >> 5; |
| 890 | sr = imm10 & 0x1f; | |
| 891 | ||
| 892 | ret = insn | selid << 27 | sr; | |
| 893 | ||
| 894 | return ret; | |
| 895 | } | |
| 896 | ||
| 897 | static unsigned long | |
| 898 | extract_SRSEL1 (unsigned long insn, int * invalid) | |
| 899 | { | |
| 900 | unsigned long ret; | |
| 901 | unsigned long sr, selid; | |
| 902 | unsigned long insn2; | |
| 903 | ||
| 904 | insn2 = insn >> 16; | |
| 905 | ||
| 906 | selid = ((insn2 & 0xf800) >> 11); | |
| 907 | sr = (insn & 0x001f); | |
| 908 | ||
| 909 | ret = (selid << 5) | sr; | |
| 910 | ||
| 911 | if (invalid != 0) | |
| 912 | *invalid = 0; | |
| 913 | ||
| 914 | return ret; | |
| 915 | } | |
| 916 | ||
| 917 | static unsigned long | |
| 7c80dd4c | 918 | insert_SRSEL2 (unsigned long insn, unsigned long value, const char ** errmsg) |
| 78c8d46c NC |
919 | { |
| 920 | unsigned long imm10, ret; | |
| 921 | unsigned long sr, selid; | |
| 922 | ||
| 7c80dd4c | 923 | if (value > 0x3ff) |
| 78c8d46c NC |
924 | * errmsg = _(sr_selid_out_of_range); |
| 925 | ||
| 7c80dd4c | 926 | imm10 = value; |
| 78c8d46c NC |
927 | selid = (imm10 & 0x3e0) >> 5; |
| 928 | sr = imm10 & 0x1f; | |
| 929 | ||
| 930 | ret = insn | selid << 27 | sr << 11; | |
| 931 | ||
| 932 | return ret; | |
| 933 | } | |
| 934 | ||
| 935 | static unsigned long | |
| 936 | extract_SRSEL2 (unsigned long insn, int * invalid) | |
| 937 | { | |
| 938 | unsigned long ret; | |
| 939 | unsigned long sr, selid; | |
| 940 | unsigned long insn2; | |
| 941 | ||
| 942 | insn2 = insn >> 16; | |
| 943 | ||
| 944 | selid = ((insn2 & 0xf800) >> 11); | |
| 945 | sr = ((insn & 0xf800) >> 11); | |
| 946 | ||
| 947 | ret = (selid << 5) | sr; | |
| 47b0e7ad | 948 | |
| 1cd986c5 NC |
949 | if (invalid != 0) |
| 950 | *invalid = 0; | |
| 78c8d46c | 951 | |
| 252b5132 RH |
952 | return ret; |
| 953 | } | |
| 252b5132 RH |
954 | \f |
| 955 | /* Warning: code in gas/config/tc-v850.c examines the contents of this array. | |
| 956 | If you change any of the values here, be sure to look for side effects in | |
| fc05c67f | 957 | that code. */ |
| 252b5132 RH |
958 | const struct v850_operand v850_operands[] = |
| 959 | { | |
| 960 | #define UNUSED 0 | |
| 1cd986c5 | 961 | { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE }, |
| 252b5132 | 962 | |
| 1cd986c5 | 963 | /* The R1 field in a format 1, 6, 7, 9, C insn. */ |
| 252b5132 | 964 | #define R1 (UNUSED + 1) |
| 1cd986c5 | 965 | { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, |
| 252b5132 RH |
966 | |
| 967 | /* As above, but register 0 is not allowed. */ | |
| 968 | #define R1_NOTR0 (R1 + 1) | |
| 1cd986c5 NC |
969 | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, |
| 970 | ||
| 971 | /* Even register is allowed. */ | |
| 972 | #define R1_EVEN (R1_NOTR0 + 1) | |
| 973 | { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, | |
| 974 | ||
| 975 | /* Bang (bit reverse). */ | |
| 976 | #define R1_BANG (R1_EVEN + 1) | |
| 977 | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE }, | |
| 978 | ||
| 979 | /* Percent (modulo). */ | |
| 980 | #define R1_PERCENT (R1_BANG + 1) | |
| 981 | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE }, | |
| 252b5132 | 982 | |
| 1cd986c5 NC |
983 | /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn. */ |
| 984 | #define R2 (R1_PERCENT + 1) | |
| 985 | { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, | |
| 252b5132 RH |
986 | |
| 987 | /* As above, but register 0 is not allowed. */ | |
| 988 | #define R2_NOTR0 (R2 + 1) | |
| 1cd986c5 | 989 | { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, |
| 252b5132 | 990 | |
| 1cd986c5 NC |
991 | /* Even register is allowed. */ |
| 992 | #define R2_EVEN (R2_NOTR0 + 1) | |
| 993 | { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, | |
| 252b5132 | 994 | |
| 1cd986c5 NC |
995 | /* Reg2 in dispose instruction. */ |
| 996 | #define R2_DISPOSE (R2_EVEN + 1) | |
| 997 | { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, | |
| 252b5132 | 998 | |
| 1cd986c5 NC |
999 | /* The R3 field in a format 11, 12, C insn. */ |
| 1000 | #define R3 (R2_DISPOSE + 1) | |
| 1001 | { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, | |
| 252b5132 | 1002 | |
| 1cd986c5 NC |
1003 | /* As above, but register 0 is not allowed. */ |
| 1004 | #define R3_NOTR0 (R3 + 1) | |
| 1005 | { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, | |
| 252b5132 | 1006 | |
| 1cd986c5 NC |
1007 | /* As above, but odd number registers are not allowed. */ |
| 1008 | #define R3_EVEN (R3_NOTR0 + 1) | |
| 1009 | { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, | |
| 252b5132 | 1010 | |
| 1cd986c5 NC |
1011 | /* As above, but register 0 is not allowed. */ |
| 1012 | #define R3_EVEN_NOTR0 (R3_EVEN + 1) | |
| 1013 | { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE }, | |
| 252b5132 | 1014 | |
| 1cd986c5 NC |
1015 | /* Forth register in FPU Instruction. */ |
| 1016 | #define R4 (R3_EVEN_NOTR0 + 1) | |
| 1017 | { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE }, | |
| 252b5132 | 1018 | |
| 1cd986c5 NC |
1019 | /* As above, but odd number registers are not allowed. */ |
| 1020 | #define R4_EVEN (R4 + 1) | |
| 1021 | { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, | |
| 252b5132 | 1022 | |
| 1cd986c5 NC |
1023 | /* Stack pointer in prepare instruction. */ |
| 1024 | #define SP (R4_EVEN + 1) | |
| 1025 | { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE }, | |
| 252b5132 RH |
1026 | |
| 1027 | /* EP Register. */ | |
| 1cd986c5 NC |
1028 | #define EP (SP + 1) |
| 1029 | { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE }, | |
| 1030 | ||
| 1031 | /* A list of registers in a prepare/dispose instruction. */ | |
| 1032 | #define LIST12 (EP + 1) | |
| 1033 | { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE }, | |
| 252b5132 | 1034 | |
| 1cd986c5 | 1035 | /* System register operands. */ |
| 78c8d46c | 1036 | #define OLDSR1 (LIST12 + 1) |
| 1cd986c5 | 1037 | { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, |
| 252b5132 | 1038 | |
| 78c8d46c NC |
1039 | #define SR1 (OLDSR1 + 1) |
| 1040 | { 0, 0, insert_SRSEL1, extract_SRSEL1, V850_OPERAND_SRG, BFD_RELOC_NONE }, | |
| 1041 | ||
| 252b5132 | 1042 | /* The R2 field as a system register. */ |
| 78c8d46c | 1043 | #define OLDSR2 (SR1 + 1) |
| 1cd986c5 | 1044 | { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, |
| 252b5132 | 1045 | |
| 78c8d46c NC |
1046 | #define SR2 (OLDSR2 + 1) |
| 1047 | { 0, 0, insert_SRSEL2, extract_SRSEL2, V850_OPERAND_SRG, BFD_RELOC_NONE }, | |
| 1048 | ||
| 1cd986c5 NC |
1049 | /* FPU CC bit position. */ |
| 1050 | #define FFF (SR2 + 1) | |
| 1051 | { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1052 | |
| 1cd986c5 NC |
1053 | /* The 4 bit condition code in a setf instruction. */ |
| 1054 | #define CCCC (FFF + 1) | |
| 1055 | { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, | |
| 252b5132 | 1056 | |
| 1cd986c5 NC |
1057 | /* Condition code in adf,sdf. */ |
| 1058 | #define CCCC_NOTSA (CCCC + 1) | |
| 1059 | { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE }, | |
| 252b5132 | 1060 | |
| 1cd986c5 NC |
1061 | /* Condition code in conditional moves. */ |
| 1062 | #define MOVCC (CCCC_NOTSA + 1) | |
| 1063 | { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, | |
| 252b5132 | 1064 | |
| 1cd986c5 NC |
1065 | /* Condition code in FPU. */ |
| 1066 | #define FLOAT_CCCC (MOVCC + 1) | |
| 1067 | { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE }, | |
| 252b5132 | 1068 | |
| 1cd986c5 NC |
1069 | /* The 1 bit immediate field in format C insn. */ |
| 1070 | #define VI1 (FLOAT_CCCC + 1) | |
| 1071 | { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1072 | |
| 1cd986c5 NC |
1073 | /* The 1 bit immediate field in format C insn. */ |
| 1074 | #define VC1 (VI1 + 1) | |
| 1075 | { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1076 | |
| 1cd986c5 NC |
1077 | /* The 2 bit immediate field in format C insn. */ |
| 1078 | #define DI2 (VC1 + 1) | |
| 1079 | { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1080 | |
| 1cd986c5 NC |
1081 | /* The 2 bit immediate field in format C insn. */ |
| 1082 | #define VI2 (DI2 + 1) | |
| 1083 | { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1084 | |
| 1cd986c5 NC |
1085 | /* The 2 bit immediate field in format C - DUP insn. */ |
| 1086 | #define VI2DUP (VI2 + 1) | |
| 1087 | { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1088 | |
| 1cd986c5 NC |
1089 | /* The 3 bit immediate field in format 8 insn. */ |
| 1090 | #define B3 (VI2DUP + 1) | |
| 1091 | { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1092 | |
| 1cd986c5 NC |
1093 | /* The 3 bit immediate field in format C insn. */ |
| 1094 | #define DI3 (B3 + 1) | |
| 1095 | { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1096 | |
| 1cd986c5 NC |
1097 | /* The 3 bit immediate field in format C insn. */ |
| 1098 | #define I3U (DI3 + 1) | |
| 1099 | { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1100 | |
| 1cd986c5 NC |
1101 | /* The 4 bit immediate field in format C insn. */ |
| 1102 | #define I4U (I3U + 1) | |
| 1103 | { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1104 | |
| 1cd986c5 NC |
1105 | /* The 4 bit immediate field in fetrap. */ |
| 1106 | #define I4U_NOTIMM0 (I4U + 1) | |
| 1107 | { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE }, | |
| 252b5132 | 1108 | |
| 1cd986c5 NC |
1109 | /* The unsigned disp4 field in a sld.bu. */ |
| 1110 | #define D4U (I4U_NOTIMM0 + 1) | |
| 1111 | { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET }, | |
| 252b5132 | 1112 | |
| 1cd986c5 NC |
1113 | /* The imm5 field in a format 2 insn. */ |
| 1114 | #define I5 (D4U + 1) | |
| 1115 | { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, | |
| 252b5132 | 1116 | |
| 1cd986c5 NC |
1117 | /* The imm5 field in a format 11 insn. */ |
| 1118 | #define I5DIV1 (I5 + 1) | |
| 1119 | { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1120 | |
| 1cd986c5 NC |
1121 | #define I5DIV2 (I5DIV1 + 1) |
| 1122 | { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1123 | |
| 1cd986c5 NC |
1124 | #define I5DIV3 (I5DIV2 + 1) |
| 1125 | { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1126 | |
| 1cd986c5 NC |
1127 | /* The unsigned imm5 field in a format 2 insn. */ |
| 1128 | #define I5U (I5DIV3 + 1) | |
| 1129 | { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1130 | |
| 1cd986c5 NC |
1131 | /* The imm5 field in a prepare/dispose instruction. */ |
| 1132 | #define IMM5 (I5U + 1) | |
| 1133 | { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 252b5132 | 1134 | |
| 1cd986c5 NC |
1135 | /* The unsigned disp5 field in a sld.hu. */ |
| 1136 | #define D5_4U (IMM5 + 1) | |
| 1137 | { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET }, | |
| 1138 | ||
| 1139 | /* The IMM6 field in a callt instruction. */ | |
| 1140 | #define IMM6 (D5_4U + 1) | |
| 1141 | { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET }, | |
| 1142 | ||
| 1143 | /* The signed disp7 field in a format 4 insn. */ | |
| 1144 | #define D7U (IMM6 + 1) | |
| 1145 | { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET }, | |
| 1146 | ||
| 1147 | /* The unsigned DISP8 field in a format 4 insn. */ | |
| 1148 | #define D8_7U (D7U + 1) | |
| 1149 | { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET }, | |
| 1150 | ||
| 1151 | /* The unsigned DISP8 field in a format 4 insn. */ | |
| 1152 | #define D8_6U (D8_7U + 1) | |
| 1153 | { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET }, | |
| 1154 | ||
| 1155 | /* The unsigned DISP8 field in a format 4 insn. */ | |
| 1156 | #define V8 (D8_6U + 1) | |
| 1157 | { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE }, | |
| 1158 | ||
| 1159 | /* The imm9 field in a multiply word. */ | |
| 1160 | #define I9 (V8 + 1) | |
| 1161 | { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, | |
| 1162 | ||
| 1163 | /* The unsigned imm9 field in a multiply word. */ | |
| 1164 | #define U9 (I9 + 1) | |
| 1165 | { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE }, | |
| 1166 | ||
| 1167 | /* The DISP9 field in a format 3 insn. */ | |
| 1168 | #define D9 (U9 + 1) | |
| 1169 | { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, | |
| 1170 | ||
| 1171 | /* The DISP9 field in a format 3 insn, relaxable. */ | |
| 1172 | #define D9_RELAX (D9 + 1) | |
| 1173 | { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, | |
| 1174 | ||
| 1175 | /* The imm16 field in a format 6 insn. */ | |
| 1176 | #define I16 (D9_RELAX + 1) | |
| 1177 | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 }, | |
| 1178 | ||
| dd42f060 | 1179 | /* The signed 16 bit immediate following a prepare instruction. */ |
| 78c8d46c | 1180 | #define IMM16LO (I16 + 1) |
| dd42f060 | 1181 | { 16, 32, NULL, NULL, V850E_IMMEDIATE16 | V850_OPERAND_SIGNED, BFD_RELOC_LO16 }, |
| 1cd986c5 NC |
1182 | |
| 1183 | /* The hi 16 bit immediate following a 32 bit instruction. */ | |
| 1184 | #define IMM16HI (IMM16LO + 1) | |
| 1185 | { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 }, | |
| 1186 | ||
| 1187 | /* The unsigned imm16 in a format 6 insn. */ | |
| 1188 | #define I16U (IMM16HI + 1) | |
| 1189 | { 16, 16, NULL, NULL, 0, BFD_RELOC_16 }, | |
| 1190 | ||
| 1191 | /* The disp16 field in a format 8 insn. */ | |
| 1192 | #define D16 (I16U + 1) | |
| 1193 | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_16 }, | |
| 1194 | ||
| 1195 | /* The disp16 field in an format 7 unsigned byte load insn. */ | |
| 1196 | #define D16_16 (D16 + 1) | |
| 1197 | { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET }, | |
| 1198 | ||
| 1199 | /* The disp16 field in a format 6 insn. */ | |
| 1200 | #define D16_15 (D16_16 + 1) | |
| 1201 | { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 }, | |
| 1202 | ||
| 1203 | /* The unsigned DISP16 field in a format 7 insn. */ | |
| 1204 | #define D16_LOOP (D16_15 + 1) | |
| 41702d50 | 1205 | { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL | V850_INVERSE_PCREL, BFD_RELOC_V850_16_PCREL }, |
| 1cd986c5 NC |
1206 | |
| 1207 | /* The DISP17 field in a format 7 insn. */ | |
| 1208 | #define D17_16 (D16_LOOP + 1) | |
| 1209 | { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL }, | |
| 1210 | ||
| 1211 | /* The DISP22 field in a format 4 insn, relaxable. | |
| 1212 | This _must_ follow D9_RELAX; the assembler assumes that the longer | |
| 1213 | version immediately follows the shorter version for relaxing. */ | |
| 1214 | #define D22 (D17_16 + 1) | |
| 1215 | { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL }, | |
| 1216 | ||
| 1217 | #define D23 (D22 + 1) | |
| 1218 | { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 }, | |
| 1219 | ||
| 78c8d46c NC |
1220 | #define D23_ALIGN1 (D23 + 1) |
| 1221 | { 23, 0, insert_d23_align1, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 }, | |
| 1222 | ||
| 1cd986c5 | 1223 | /* The 32 bit immediate following a 32 bit instruction. */ |
| 78c8d46c | 1224 | #define IMM32 (D23_ALIGN1 + 1) |
| 1cd986c5 NC |
1225 | { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 }, |
| 1226 | ||
| 1227 | #define D32_31 (IMM32 + 1) | |
| 1228 | { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS }, | |
| 1229 | ||
| 1230 | #define D32_31_PCREL (D32_31 + 1) | |
| 1231 | { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL }, | |
| 1232 | ||
| 78c8d46c NC |
1233 | #define POS_U (D32_31_PCREL + 1) |
| 1234 | { 0, 0, insert_POS, extract_POS_U, 0, BFD_RELOC_NONE }, | |
| 1235 | ||
| 1236 | #define POS_M (POS_U + 1) | |
| 1237 | { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE }, | |
| 1238 | ||
| 1239 | #define POS_L (POS_M + 1) | |
| 1240 | { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE }, | |
| 1241 | ||
| 1242 | #define WIDTH_U (POS_L + 1) | |
| 1243 | { 0, 0, insert_WIDTH, extract_WIDTH_U, 0, BFD_RELOC_NONE }, | |
| 1244 | ||
| 1245 | #define WIDTH_M (WIDTH_U + 1) | |
| 1246 | { 0, 0, insert_WIDTH, extract_WIDTH_M, 0, BFD_RELOC_NONE }, | |
| 1247 | ||
| 1248 | #define WIDTH_L (WIDTH_M + 1) | |
| 1249 | { 0, 0, insert_WIDTH, extract_WIDTH_L, 0, BFD_RELOC_NONE }, | |
| 1250 | ||
| 1251 | #define SELID (WIDTH_L + 1) | |
| 1252 | { 5, 27, insert_SELID, extract_SELID, 0, BFD_RELOC_NONE }, | |
| 1253 | ||
| 1254 | #define RIE_IMM5 (SELID + 1) | |
| 1255 | { 5, 11, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 1256 | ||
| 1257 | #define RIE_IMM4 (RIE_IMM5 + 1) | |
| 1258 | { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
| 1259 | ||
| 1260 | #define VECTOR8 (RIE_IMM4 + 1) | |
| 1261 | { 0, 0, insert_VECTOR8, extract_VECTOR8, 0, BFD_RELOC_NONE }, | |
| 1262 | ||
| 1263 | #define VECTOR5 (VECTOR8 + 1) | |
| 1264 | { 0, 0, insert_VECTOR5, extract_VECTOR5, 0, BFD_RELOC_NONE }, | |
| 1265 | ||
| 1266 | #define VR1 (VECTOR5 + 1) | |
| 1267 | { 5, 0, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE }, | |
| 1268 | ||
| 1269 | #define VR2 (VR1 + 1) | |
| 1270 | { 5, 11, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE }, | |
| 1271 | ||
| 1272 | #define CACHEOP (VR2 + 1) | |
| 1273 | { 0, 0, insert_CACHEOP, extract_CACHEOP, V850_OPERAND_CACHEOP, BFD_RELOC_NONE }, | |
| 1274 | ||
| 1275 | #define PREFOP (CACHEOP + 1) | |
| 1276 | { 0, 0, insert_PREFOP, extract_PREFOP, V850_OPERAND_PREFOP, BFD_RELOC_NONE }, | |
| 1277 | ||
| 1278 | #define IMM10U (PREFOP + 1) | |
| 1279 | { 0, 0, insert_IMM10U, extract_IMM10U, 0, BFD_RELOC_NONE }, | |
| 1cd986c5 NC |
1280 | }; |
| 1281 | ||
| 1282 | \f | |
| 1283 | /* Reg - Reg instruction format (Format I). */ | |
| 1284 | #define IF1 {R1, R2} | |
| 1285 | ||
| 1286 | /* Imm - Reg instruction format (Format II). */ | |
| 1287 | #define IF2 {I5, R2} | |
| 1288 | ||
| 1289 | /* Conditional branch instruction format (Format III). */ | |
| 1290 | #define IF3 {D9_RELAX} | |
| 252b5132 | 1291 | |
| 8ad30312 | 1292 | /* 3 operand instruction (Format VI). */ |
| 252b5132 RH |
1293 | #define IF6 {I16, R1, R2} |
| 1294 | ||
| 8ad30312 | 1295 | /* 3 operand instruction (Format VI). */ |
| 252b5132 RH |
1296 | #define IF6U {I16U, R1, R2} |
| 1297 | ||
| 1cd986c5 NC |
1298 | /* Conditional branch instruction format (Format VII). */ |
| 1299 | #define IF7 {D17_16} | |
| 252b5132 RH |
1300 | |
| 1301 | \f | |
| 1302 | /* The opcode table. | |
| 1303 | ||
| 1304 | The format of the opcode table is: | |
| 1305 | ||
| 1306 | NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR | |
| 1307 | ||
| 1308 | NAME is the name of the instruction. | |
| 1309 | OPCODE is the instruction opcode. | |
| 1310 | MASK is the opcode mask; this is used to tell the disassembler | |
| 1311 | which bits in the actual opcode must match OPCODE. | |
| 1312 | OPERANDS is the list of operands. | |
| 1313 | MEMOP specifies which operand (if any) is a memory operand. | |
| 1314 | PROCESSORS specifies which CPU(s) support the opcode. | |
| 47b0e7ad | 1315 | |
| 252b5132 RH |
1316 | The disassembler reads the table in order and prints the first |
| 1317 | instruction which matches, so this table is sorted to put more | |
| 1318 | specific instructions before more general instructions. It is also | |
| 1319 | sorted by major opcode. | |
| 1320 | ||
| 1321 | The table is also sorted by name. This is used by the assembler. | |
| 1322 | When parsing an instruction the assembler finds the first occurance | |
| 1323 | of the name of the instruciton in this table and then attempts to | |
| 1324 | match the instruction's arguments with description of the operands | |
| 1325 | associated with the entry it has just found in this table. If the | |
| 1326 | match fails the assembler looks at the next entry in this table. | |
| 1327 | If that entry has the same name as the previous entry, then it | |
| 1328 | tries to match the instruction against that entry and so on. This | |
| 1329 | is how the assembler copes with multiple, different formats of the | |
| 1330 | same instruction. */ | |
| 1331 | ||
| 1332 | const struct v850_opcode v850_opcodes[] = | |
| 1333 | { | |
| 1cd986c5 | 1334 | /* Standard instructions. */ |
| 252b5132 RH |
1335 | { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 1336 | { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, | |
| 1cd986c5 | 1337 | |
| 252b5132 | 1338 | { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, |
| 47b0e7ad | 1339 | |
| 78c8d46c | 1340 | { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 252b5132 | 1341 | |
| 252b5132 | 1342 | { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 1cd986c5 | 1343 | |
| 252b5132 | 1344 | { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, |
| 252b5132 | 1345 | |
| 8ad30312 | 1346 | /* Signed integer. */ |
| 252b5132 | 1347 | { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1cd986c5 | 1348 | { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 252b5132 | 1349 | { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1cd986c5 | 1350 | { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 8ad30312 | 1351 | /* Unsigned integer. */ |
| 252b5132 | 1352 | { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 252b5132 | 1353 | { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1cd986c5 | 1354 | { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 252b5132 | 1355 | { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 8ad30312 | 1356 | /* Common. */ |
| 252b5132 RH |
1357 | { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1358 | { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 8ad30312 | 1359 | /* Others. */ |
| 252b5132 | 1360 | { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1cd986c5 NC |
1361 | { "bf", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1362 | { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 252b5132 | 1363 | { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1cd986c5 | 1364 | { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 252b5132 | 1365 | { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1cd986c5 | 1366 | { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 252b5132 RH |
1367 | { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1368 | { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1cd986c5 NC |
1369 | { "bt", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1370 | { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1371 | { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 252b5132 | 1372 | |
| 78c8d46c NC |
1373 | /* Signed integer. */ |
| 1374 | { "bge", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1375 | { "bgt", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1376 | { "ble", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1377 | { "blt", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 43e65147 | 1378 | /* Unsigned integer. */ |
| 78c8d46c NC |
1379 | { "bh", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
| 1380 | { "bl", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1381 | { "bnh", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1382 | { "bnl", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 43e65147 | 1383 | /* Common. */ |
| 78c8d46c NC |
1384 | { "be", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
| 1385 | { "bne", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 43e65147 | 1386 | /* Others. */ |
| 78c8d46c NC |
1387 | { "bc", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
| 1388 | { "bf", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1389 | { "bn", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1390 | { "bnc", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1391 | { "bnv", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1392 | { "bnz", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1393 | { "bp", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1394 | { "br", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1395 | { "bsa", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1396 | { "bt", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1397 | { "bv", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1398 | { "bz", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
| 1399 | /* Bcond disp17 Gas local alias(not defined in spec). */ | |
| 1400 | ||
| 1401 | /* Signed integer. */ | |
| 1402 | { "bge17", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1403 | { "bgt17", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1404 | { "ble17", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1405 | { "blt17", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1406 | /* Unsigned integer. */ | |
| 1407 | { "bh17", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1408 | { "bl17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1409 | { "bnh17", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1410 | { "bnl17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1411 | /* Common. */ | |
| 1412 | { "be17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1413 | { "bne17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1414 | /* Others. */ | |
| 1415 | { "bc17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1416 | { "bf17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1417 | { "bn17", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1418 | { "bnc17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1419 | { "bnv17", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1420 | { "bnz17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1421 | { "bp17", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1422 | { "br17", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1423 | { "bsa17", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1424 | { "bt17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1425 | { "bv17", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1426 | { "bz17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1427 | ||
| 1cd986c5 | 1428 | { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 252b5132 | 1429 | |
| 1cd986c5 | 1430 | { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 252b5132 | 1431 | |
| 78c8d46c NC |
1432 | /* v850e3v5 bitfield instructions. */ |
| 1433 | { "bins", two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1434 | { "bins", two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1435 | { "bins", two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1436 | /* Gas local alias(not defined in spec). */ | |
| 1437 | { "binsu",two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1438 | { "binsm",two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1439 | { "binsl",two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1440 | ||
| 1441 | { "cache", two (0xe7e0, 0x0160), two (0xe7e0, 0x07ff), {CACHEOP, R1}, 2, PROCESSOR_V850E3V5_UP }, | |
| 1442 | ||
| 1cd986c5 NC |
1443 | { "callt", one (0x0200), one (0xffc0), {IMM6}, 0, PROCESSOR_NOT_V850 }, |
| 1444 | ||
| 78c8d46c | 1445 | { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1446 | |
| 1447 | { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, | |
| 1448 | { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, | |
| 1449 | ||
| 1450 | { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1451 | { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1452 | ||
| 1453 | { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 1454 | { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, | |
| 1455 | ||
| 1456 | { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, | |
| 1457 | ||
| 78c8d46c NC |
1458 | { "dbcp", one (0xe840), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
| 1459 | ||
| 1460 | { "dbhvtrap", one (0xe040), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1461 | ||
| 1462 | { "dbpush", two (0x5fe0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1463 | ||
| 1cd986c5 NC |
1464 | { "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, |
| 1465 | ||
| 78c8d46c NC |
1466 | { "dbtag", two (0xcfe0, 0x0160), two (0xffe0, 0x07ff), {IMM10U}, 0, PROCESSOR_V850E3V5_UP }, |
| 1467 | ||
| 1cd986c5 NC |
1468 | { "dbtrap", one (0xf840), one (0xffff), {0}, 0, PROCESSOR_NOT_V850 }, |
| 1469 | ||
| 1470 | { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, | |
| 1471 | ||
| 1472 | { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 }, | |
| 1473 | { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, | |
| 1474 | ||
| 1475 | { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1476 | ||
| 1477 | { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1478 | { "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1479 | ||
| 1480 | { "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
| 1481 | ||
| 1482 | { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1483 | ||
| 1484 | { "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
| 1485 | { "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
| 1486 | ||
| 78c8d46c | 1487 | { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 | 1488 | |
| 78c8d46c | 1489 | { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1490 | |
| 1491 | { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1492 | ||
| 1493 | { "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
| 1494 | ||
| 78c8d46c NC |
1495 | { "dst", two (0x07e0, 0x0134), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
| 1496 | ||
| 1cd986c5 NC |
1497 | { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
| 1498 | ||
| 78c8d46c NC |
1499 | { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP }, |
| 1500 | ||
| 1501 | { "est", two (0x07e0, 0x0132), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1cd986c5 | 1502 | |
| 78c8d46c | 1503 | { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 | 1504 | |
| 78c8d46c | 1505 | { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1506 | |
| 1507 | { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, | |
| 1508 | ||
| 78c8d46c | 1509 | { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1510 | |
| 1511 | { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1512 | ||
| 78c8d46c NC |
1513 | { "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, PROCESSOR_V850E3V5_UP }, |
| 1514 | { "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, PROCESSOR_V850E3V5_UP }, | |
| 43e65147 | 1515 | |
| 78c8d46c | 1516 | { "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP}, |
| 1cd986c5 | 1517 | { "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL}, |
| 78c8d46c NC |
1518 | { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP }, |
| 1519 | /* Gas local alias (not defined in spec). */ | |
| 1520 | { "jarlr", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS}, | |
| 1521 | /* Gas local alias of jarl imm22 (not defined in spec). */ | |
| 1cd986c5 | 1522 | { "jarl22", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS}, |
| 78c8d46c NC |
1523 | /* Gas local alias of jarl imm32 (not defined in spec). */ |
| 1524 | { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1525 | { "jarlw", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1cd986c5 | 1526 | |
| 78c8d46c NC |
1527 | { "jmp", two (0x06e0, 0x0000), two (0xffe0, 0x0001), {D32_31, R1}, 2, PROCESSOR_V850E3V5_UP }, |
| 1528 | { "jmp", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2 | PROCESSOR_V850E2V3 }, | |
| 1cd986c5 NC |
1529 | { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, |
| 1530 | /* Gas local alias of jmp disp22(not defined in spec). */ | |
| 1531 | { "jmp22", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, | |
| 1532 | /* Gas local alias of jmp disp32(not defined in spec). */ | |
| 78c8d46c NC |
1533 | { "jmp32", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
| 1534 | { "jmpw", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1cd986c5 NC |
1535 | |
| 1536 | { "jr", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, | |
| 78c8d46c | 1537 | { "jr", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1538 | /* Gas local alias of mov imm22(not defined in spec). */ |
| 1539 | { "jr22", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, | |
| 1540 | /* Gas local alias of mov imm32(not defined in spec). */ | |
| 78c8d46c | 1541 | { "jr32", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
| 1cd986c5 NC |
1542 | |
| 1543 | /* Alias of bcond (same as CA850). */ | |
| 252b5132 RH |
1544 | { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1545 | { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1546 | { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1547 | { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 8ad30312 | 1548 | /* Unsigned integer. */ |
| 252b5132 RH |
1549 | { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1550 | { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1551 | { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1552 | { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 8ad30312 | 1553 | /* Common. */ |
| 252b5132 RH |
1554 | { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1555 | { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 8ad30312 | 1556 | /* Others. */ |
| 252b5132 RH |
1557 | { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 1558 | { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1559 | { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1560 | { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1561 | { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1562 | { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1563 | { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 1564 | { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 252b5132 | 1565 | { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 47b0e7ad | 1566 | |
| 252b5132 | 1567 | |
| 78c8d46c | 1568 | { "ldacc", two (0x07e0, 0x0bc4), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, |
| 1cd986c5 NC |
1569 | |
| 1570 | { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL }, | |
| accc0180 | 1571 | { "ld.b", two (0x0780, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
| 78c8d46c | 1572 | { "ld.b23", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
| 1cd986c5 NC |
1573 | |
| 1574 | { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, | |
| accc0180 | 1575 | { "ld.bu", two (0x07a0, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
| 78c8d46c NC |
1576 | { "ld.bu23", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
| 1577 | ||
| 1578 | { "ld.dw", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP }, | |
| 1579 | { "ld.dw23", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1cd986c5 NC |
1580 | |
| 1581 | { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, | |
| 78c8d46c NC |
1582 | { "ld.h", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
| 1583 | { "ld.h23", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1cd986c5 NC |
1584 | |
| 1585 | { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, | |
| 78c8d46c NC |
1586 | { "ld.hu", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
| 1587 | { "ld.hu23", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1cd986c5 NC |
1588 | |
| 1589 | { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, | |
| 78c8d46c NC |
1590 | { "ld.w", two (0x0780, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
| 1591 | { "ld.w23", two (0x0780, 0x0009), two (0x07e0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
| 252b5132 | 1592 | |
| 78c8d46c | 1593 | { "ldl.w", two (0x07e0, 0x0378), two (0xffe0, 0x07ff), {R1, R3}, 1, PROCESSOR_V850E3V5_UP }, |
| 1cd986c5 | 1594 | |
| 78c8d46c NC |
1595 | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
| 1596 | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1597 | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, OLDSR2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) }, | |
| 1cd986c5 | 1598 | |
| 78c8d46c NC |
1599 | { "ldtc.gr", two (0x07e0, 0x0032), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP }, |
| 1600 | { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1601 | { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1cd986c5 | 1602 | |
| 78c8d46c NC |
1603 | { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP }, |
| 1604 | { "ldtc.pc", two (0x07e0, 0xf832), two (0x07e0, 0xffff), {R1}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1cd986c5 | 1605 | |
| 78c8d46c NC |
1606 | { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
| 1607 | { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1608 | ||
| 1609 | { "loop", two (0x06e0, 0x0001), two (0xffe0, 0x0001), {R1, D16_LOOP}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1610 | ||
| 1611 | { "macacc", two (0x07e0, 0x0bc0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1612 | ||
| 1613 | { "mac", two (0x07e0, 0x03c0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP }, | |
| 1614 | ||
| 1615 | { "macu", two (0x07e0, 0x03e0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP }, | |
| 1616 | ||
| 1617 | { "macuacc", two (0x07e0, 0x0bc2), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1cd986c5 NC |
1618 | |
| 1619 | { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1620 | { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1621 | { "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 }, | |
| 1622 | /* Gas local alias of mov imm32(not defined in spec). */ | |
| 1623 | { "movl", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_ALIAS }, | |
| 1624 | ||
| 1625 | { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1626 | ||
| 1627 | { "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1628 | ||
| 1629 | { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1630 | { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1631 | ||
| 1632 | { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1633 | { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1634 | ||
| 1635 | { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1636 | ||
| 1637 | { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1638 | { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 1639 | ||
| 1640 | { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, | |
| 1641 | ||
| 1642 | { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 1643 | ||
| 1644 | { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, | |
| 1645 | { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, | |
| 1646 | ||
| 1647 | { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 1648 | ||
| 1649 | { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, | |
| 1650 | ||
| 78c8d46c NC |
1651 | { "popsp", two (0x67e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, |
| 1652 | ||
| 1653 | { "pref", two (0xdfe0, 0x0160), two (0xffe0, 0x07ff), {PREFOP, R1}, 2, PROCESSOR_V850E3V5_UP }, | |
| 1654 | ||
| 1cd986c5 NC |
1655 | { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, |
| 1656 | { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 }, | |
| 1657 | { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 }, | |
| 1658 | { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, | |
| 1659 | { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, | |
| 1660 | ||
| 78c8d46c NC |
1661 | { "pushsp", two (0x47e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, |
| 1662 | ||
| 1663 | { "rotl", two (0x07e0, 0x00c6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1664 | { "rotl", two (0x07e0, 0x00c4), two (0x07e0, 0x07ff), {I5U, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1665 | ||
| 1cd986c5 NC |
1666 | { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
| 1667 | ||
| 78c8d46c | 1668 | { "sar", two (0x07e0, 0x00a2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1669 | { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
| 1670 | { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, | |
| 1671 | ||
| 1672 | { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, | |
| 1673 | ||
| 78c8d46c | 1674 | { "satadd", two (0x07e0, 0x03ba), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1675 | { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 1676 | { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1677 | ||
| 78c8d46c | 1678 | { "satsub", two (0x07e0, 0x039a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1679 | { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 1680 | ||
| 1681 | { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1682 | ||
| 1683 | { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 1684 | ||
| 78c8d46c | 1685 | { "sbf", two (0x07e0, 0x0380), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 | 1686 | |
| 78c8d46c | 1687 | { "sch0l", two (0x07e0, 0x0364), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 | 1688 | |
| 78c8d46c | 1689 | { "sch0r", two (0x07e0, 0x0360), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 | 1690 | |
| 78c8d46c | 1691 | { "sch1l", two (0x07e0, 0x0366), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 | 1692 | |
| 78c8d46c | 1693 | { "sch1r", two (0x07e0, 0x0362), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1694 | |
| 1695 | { "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
| 1696 | { "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
| 1697 | { "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
| 1698 | { "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
| 1699 | ||
| 1700 | { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, | |
| 1701 | { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, | |
| 1702 | ||
| 1703 | { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, | |
| 1704 | ||
| 78c8d46c | 1705 | { "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1706 | { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
| 1707 | { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, | |
| 1708 | ||
| 78c8d46c | 1709 | { "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
| 1cd986c5 NC |
1710 | { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
| 1711 | { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, | |
| 1712 | ||
| 1713 | { "sld.b", one (0x0300), one (0x0780), {D7U, EP, R2}, 2, PROCESSOR_ALL }, | |
| 1714 | ||
| 1715 | { "sld.bu", one (0x0060), one (0x07f0), {D4U, EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, | |
| 1716 | ||
| 1717 | { "sld.h", one (0x0400), one (0x0780), {D8_7U,EP, R2}, 2, PROCESSOR_ALL }, | |
| 1718 | ||
| 1719 | { "sld.hu", one (0x0070), one (0x07f0), {D5_4U,EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, | |
| 1720 | ||
| 1721 | { "sld.w", one (0x0500), one (0x0781), {D8_6U,EP, R2}, 2, PROCESSOR_ALL }, | |
| 1722 | ||
| 78c8d46c NC |
1723 | { "snooze", two (0x0fe0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
| 1724 | ||
| 1cd986c5 NC |
1725 | { "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, PROCESSOR_ALL }, |
| 1726 | ||
| 1727 | { "sst.h", one (0x0480), one (0x0780), {R2, D8_7U,EP}, 3, PROCESSOR_ALL }, | |
| 1728 | ||
| 1729 | { "sst.w", one (0x0501), one (0x0781), {R2, D8_6U,EP}, 3, PROCESSOR_ALL }, | |
| 1730 | ||
| 78c8d46c NC |
1731 | { "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, |
| 1732 | { "staccl", two (0x07e0, 0x0bc8), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1cd986c5 NC |
1733 | |
| 1734 | { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL }, | |
| 78c8d46c NC |
1735 | { "st.b", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP }, |
| 1736 | { "st.b23", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1737 | ||
| 1738 | { "st.dw", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP }, | |
| 1739 | { "st.dw23", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1cd986c5 NC |
1740 | |
| 1741 | { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, | |
| 78c8d46c NC |
1742 | { "st.h", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP }, |
| 1743 | { "st.h23", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1cd986c5 NC |
1744 | |
| 1745 | { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, | |
| 78c8d46c NC |
1746 | { "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP }, |
| 1747 | { "st.w23", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1748 | ||
| 1749 | { "stc.w", two (0x07e0, 0x037a), two (0xffe0, 0x07ff), {R3, R1}, 2, PROCESSOR_V850E3V5_UP }, | |
| 1750 | ||
| 1751 | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1752 | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1753 | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {OLDSR1, R2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) }, | |
| 1754 | ||
| 1755 | { "sttc.gr", two (0x07e0, 0x0052), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1756 | { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1757 | { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1758 | { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1759 | { "sttc.pc", two (0x07e0, 0xf852), two (0x07e0, 0xffff), {R2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1cd986c5 | 1760 | |
| 78c8d46c NC |
1761 | { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
| 1762 | { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
| 252b5132 | 1763 | |
| 1cd986c5 NC |
1764 | { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 1765 | ||
| 1766 | { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 1767 | ||
| 1768 | { "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, | |
| 1769 | ||
| 1770 | { "sxb", one (0x00a0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, | |
| 1771 | ||
| 1772 | { "sxh", one (0x00e0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, | |
| 1773 | ||
| 78c8d46c NC |
1774 | { "tlbai", two (0x87e0, 0x8960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
| 1775 | { "tlbr", two (0x87e0, 0xe960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1776 | { "tlbs", two (0x87e0, 0xc160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1777 | { "tlbvi", two (0x87e0, 0x8160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1778 | { "tlbw", two (0x87e0, 0xe160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1779 | ||
| 1cd986c5 NC |
1780 | { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, |
| 1781 | ||
| 1782 | { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 1783 | ||
| 1784 | { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, | |
| 1785 | { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, | |
| 1786 | ||
| 1787 | { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 1788 | ||
| 1789 | { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, | |
| 1790 | ||
| 1791 | { "zxb", one (0x0080), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, | |
| 1792 | ||
| 1793 | { "zxh", one (0x00c0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, | |
| 1794 | ||
| 1795 | /* Floating point operation. */ | |
| 78c8d46c NC |
1796 | { "absf.d", two (0x07e0, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
| 1797 | { "absf.s", two (0x07e0, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1798 | { "addf.d", two (0x07e0, 0x0470), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1799 | { "addf.s", two (0x07e0, 0x0460), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1800 | { "ceilf.dl", two (0x07e2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1801 | { "ceilf.dul", two (0x07f2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1802 | { "ceilf.duw", two (0x07f2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1803 | { "ceilf.dw", two (0x07e2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1804 | { "ceilf.sl", two (0x07e2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1805 | { "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1806 | { "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1807 | { "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 78c8d46c | 1808 | { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, |
| 1cd986c5 | 1809 | /* Default value for FFF is 0(not defined in spec). */ |
| 78c8d46c NC |
1810 | { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, |
| 1811 | { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07f1), {FFF, R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1cd986c5 | 1812 | /* Default value for FFF is 0(not defined in spec). */ |
| 78c8d46c NC |
1813 | { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07ff), {R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, |
| 1814 | { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87f1), {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1815 | { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87ff), {FLOAT_CCCC, R2_EVEN, R1_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1816 | { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87f1), {FLOAT_CCCC, R2, R1, FFF}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1817 | { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87ff), {FLOAT_CCCC, R2, R1}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1818 | { "cvtf.dl", two (0x07e4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1819 | { "cvtf.ds", two (0x07e3, 0x0452), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1820 | { "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1821 | { "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1822 | { "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 41702d50 | 1823 | { "cvtf.hs", two (0x07e2, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP }, |
| 78c8d46c NC |
1824 | { "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
| 1825 | { "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1826 | { "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1827 | { "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 41702d50 | 1828 | { "cvtf.sh", two (0x07e3, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP }, |
| 78c8d46c NC |
1829 | { "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
| 1830 | { "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1831 | { "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1832 | { "cvtf.uld", two (0x07f1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1833 | { "cvtf.uls", two (0x07f1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1834 | { "cvtf.uwd", two (0x07f0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1835 | { "cvtf.uws", two (0x07f0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1836 | { "cvtf.wd", two (0x07e0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1837 | { "cvtf.ws", two (0x07e0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1838 | { "divf.d", two (0x07e0, 0x047e), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1839 | { "divf.s", two (0x07e0, 0x046e), two (0x07e0, 0x07ff), {R1_NOTR0, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1840 | { "floorf.dl", two (0x07e3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1841 | { "floorf.dul", two (0x07f3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1842 | { "floorf.duw", two (0x07f3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1843 | { "floorf.dw", two (0x07e3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1844 | { "floorf.sl", two (0x07e3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1845 | { "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1846 | { "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1847 | { "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 41702d50 NC |
1848 | { "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, |
| 1849 | { "fmaf.s", two (0x07e0, 0x04e0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, | |
| 78c8d46c NC |
1850 | { "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
| 1851 | { "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1852 | { "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1853 | { "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 41702d50 NC |
1854 | { "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, |
| 1855 | { "fmsf.s", two (0x07e0, 0x04e2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, | |
| 78c8d46c NC |
1856 | { "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
| 1857 | { "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1858 | { "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1859 | { "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 41702d50 NC |
1860 | { "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, |
| 1861 | { "fnmaf.s", two (0x07e0, 0x04e4), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, | |
| 1862 | { "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, | |
| 1863 | { "fnmsf.s", two (0x07e0, 0x04e6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, | |
| 78c8d46c NC |
1864 | { "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
| 1865 | { "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1866 | ||
| 1867 | { "roundf.dl", two (0x07e0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1868 | { "roundf.dul", two (0x07f0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1869 | { "roundf.duw", two (0x07f0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1870 | { "roundf.dw", two (0x07e0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1871 | { "roundf.sl", two (0x07e0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1872 | { "roundf.sul", two (0x07f0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1873 | { "roundf.suw", two (0x07f0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1874 | { "roundf.sw", two (0x07e0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
| 1875 | ||
| 1876 | { "rsqrtf.d", two (0x07e2, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1877 | { "rsqrtf.s", two (0x07e2, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1878 | { "sqrtf.d", two (0x07e0, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1879 | { "sqrtf.s", two (0x07e0, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1880 | { "subf.d", two (0x07e0, 0x0472), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1881 | { "subf.s", two (0x07e0, 0x0462), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1882 | { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xfff1), {FFF}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1883 | { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1884 | { "trncf.dl", two (0x07e1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1885 | { "trncf.dul", two (0x07f1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1886 | { "trncf.duw", two (0x07f1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1887 | { "trncf.dw", two (0x07e1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1888 | { "trncf.sl", two (0x07e1, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1889 | { "trncf.sul", two (0x07f1, 0x0444), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1890 | { "trncf.suw", two (0x07f1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1891 | { "trncf.sw", two (0x07e1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1cd986c5 NC |
1892 | |
| 1893 | /* Special instruction (from gdb) mov 1, r0. */ | |
| 1894 | { "breakpoint", one (0x0001), one (0xffff), {UNUSED}, 0, PROCESSOR_ALL }, | |
| 1895 | ||
| 78c8d46c | 1896 | { "synci", one (0x001c), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
| 1cd986c5 | 1897 | |
| 78c8d46c NC |
1898 | { "synce", one (0x001d), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, |
| 1899 | { "syncm", one (0x001e), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1900 | { "syncp", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1901 | { "syscall", two (0xd7e0, 0x0160), two (0xffe0, 0xc7ff), {V8}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1902 | /* Alias of syncp. */ | |
| 1903 | { "sync", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_ALIAS }, | |
| 1904 | { "rmtrap", one (0xf040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1905 | { "rie", one (0x0040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1906 | { "rie", two (0x07f0, 0x0000), two (0x07f0, 0xffff), {RIE_IMM5,RIE_IMM4}, 0, PROCESSOR_V850E2V3_UP }, | |
| 1cd986c5 NC |
1907 | |
| 1908 | { 0, 0, 0, {0}, 0, 0 }, | |
| 252b5132 RH |
1909 | } ; |
| 1910 | ||
| 1911 | const int v850_num_opcodes = | |
| 1912 | sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); |