[thirdparty/binutils-gdb.git] / sim / Makefile.in

# Makefile.in generated by automake 1.15.1 from Makefile.am.
# @configure_input@

# Copyright (C) 1994-2017 Free Software Foundation, Inc.

# This Makefile.in is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.

# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
# PARTICULAR PURPOSE.

@SET_MAKE@

#   Copyright (C) 1993-2023 Free Software Foundation, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program.  If not, see <http://www.gnu.org/licenses/>.


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@ENABLE_SIM_TRUE@am__append_1 = \
@ENABLE_SIM_TRUE@	$(srcroot)/include/sim/callback.h \
@ENABLE_SIM_TRUE@	$(srcroot)/include/sim/sim.h

@SIM_ENABLE_HW_TRUE@am__append_2 = \
@SIM_ENABLE_HW_TRUE@	$(SIM_COMMON_HW_OBJS) \
@SIM_ENABLE_HW_TRUE@	$(SIM_HW_SOCKSER)

@SIM_ENABLE_HW_TRUE@am__append_3 = SIM_HW_DEVICES_="$(SIM_HW_DEVICES)"
@SIM_ENABLE_IGEN_TRUE@am__append_4 = $(IGEN)
@SIM_ENABLE_IGEN_TRUE@am__append_5 = igen/libigen.a
@SIM_ENABLE_IGEN_TRUE@am__append_6 = $(igen_IGEN_TOOLS)
@SIM_ENABLE_IGEN_TRUE@am__append_7 = $(igen_IGEN_TOOLS)
TESTS = testsuite/common/bits32m0$(EXEEXT) \
	testsuite/common/bits32m31$(EXEEXT) \
	testsuite/common/bits64m0$(EXEEXT) \
	testsuite/common/bits64m63$(EXEEXT) \
	testsuite/common/alu-tst$(EXEEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_8 = aarch64/libsim.a
@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_9 = aarch64/run
@SIM_ENABLE_ARCH_arm_TRUE@am__append_10 = arm/libsim.a
@SIM_ENABLE_ARCH_arm_TRUE@am__append_11 = arm/run
@SIM_ENABLE_ARCH_avr_TRUE@am__append_12 = avr/libsim.a
@SIM_ENABLE_ARCH_avr_TRUE@am__append_13 = avr/run
@SIM_ENABLE_ARCH_bfin_TRUE@am__append_14 = bfin/libsim.a
@SIM_ENABLE_ARCH_bfin_TRUE@am__append_15 = bfin/run
@SIM_ENABLE_ARCH_bfin_TRUE@am__append_16 = bfin_SIM_EXTRA_HW_DEVICES="$(bfin_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_bpf_TRUE@am__append_17 = bpf/libsim.a
@SIM_ENABLE_ARCH_bpf_TRUE@am__append_18 = bpf/run
@SIM_ENABLE_ARCH_bpf_TRUE@am__append_19 = \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/eng-le.h \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/eng-be.h

@SIM_ENABLE_ARCH_bpf_TRUE@am__append_20 = $(bpf_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_bpf_TRUE@am__append_21 = $(bpf_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_22 = cr16/libsim.a
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_23 = cr16/run
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_24 = cr16/simops.h
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_25 = $(cr16_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_26 = cr16/gencode
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_27 = $(cr16_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cris_TRUE@am__append_28 = cris/libsim.a
@SIM_ENABLE_ARCH_cris_TRUE@am__append_29 = cris/run
@SIM_ENABLE_ARCH_cris_TRUE@am__append_30 = cris_SIM_EXTRA_HW_DEVICES="$(cris_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_cris_TRUE@am__append_31 = cris/rvdummy
@SIM_ENABLE_ARCH_cris_TRUE@am__append_32 = \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/engv10.h \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/engv32.h

@SIM_ENABLE_ARCH_cris_TRUE@am__append_33 = $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cris_TRUE@am__append_34 = $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_35 = d10v/libsim.a
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_36 = d10v/run
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_37 = d10v/simops.h
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_38 = $(d10v_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_39 = d10v/gencode
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_40 = $(d10v_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_41 = erc32/libsim.a
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_42 = erc32/run erc32/sis
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_43 = sim-%D-install-exec-local
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_44 = sim-erc32-uninstall-local
@SIM_ENABLE_ARCH_examples_TRUE@am__append_45 = example-synacor/libsim.a
@SIM_ENABLE_ARCH_examples_TRUE@am__append_46 = example-synacor/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_47 = frv/libsim.a
@SIM_ENABLE_ARCH_frv_TRUE@am__append_48 = frv/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_49 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_50 = $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_frv_TRUE@am__append_51 = $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_52 = ft32/libsim.a
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_53 = ft32/run
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_54 = h8300/libsim.a
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_55 = h8300/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_56 = iq2000/libsim.a
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_57 = iq2000/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_58 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_59 = $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_60 = $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_61 = lm32/libsim.a
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_62 = lm32/run
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_63 = lm32_SIM_EXTRA_HW_DEVICES="$(lm32_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_64 = lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_65 = $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_66 = $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_67 = m32c/libsim.a
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_68 = m32c/run
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_69 = $(m32c_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_70 = m32c/opc2c
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_71 = \
@SIM_ENABLE_ARCH_m32c_TRUE@	$(m32c_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/m32c.c.log \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/r8c.c.log

@SIM_ENABLE_ARCH_m32r_TRUE@am__append_72 = m32r/libsim.a
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_73 = m32r/run
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_74 = m32r_SIM_EXTRA_HW_DEVICES="$(m32r_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_75 = \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/eng.h \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/engx.h \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/eng2.h

@SIM_ENABLE_ARCH_m32r_TRUE@am__append_76 = $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_77 = $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_78 = m68hc11/libsim.a
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_79 = m68hc11/run
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_80 = m68hc11_SIM_EXTRA_HW_DEVICES="$(m68hc11_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_81 = $(m68hc11_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_82 = m68hc11/gencode
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_83 = $(m68hc11_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_84 = mcore/libsim.a
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_85 = mcore/run
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_86 = microblaze/libsim.a
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_87 = microblaze/run
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_88 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/idecode.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/icache.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/engine.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/irun.o

@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_89 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_idecode.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_icache.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	\
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m32_support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m32_semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m32_idecode.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m32_icache.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	\
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16run.o

@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_90 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	$(SIM_MIPS_MULTI_OBJ) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/multi-run.o

@SIM_ENABLE_ARCH_mips_TRUE@am__append_91 = mips/libsim.a
@SIM_ENABLE_ARCH_mips_TRUE@am__append_92 = mips/run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_93 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_mips_TRUE@am__append_94 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@	$(SIM_MIPS_MULTI_SRC)
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_95 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	$(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/stamp-gen-mode-single

@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_96 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/stamp-gen-mode-m16-m16 \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/stamp-gen-mode-m16-m32

@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_97 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	$(SIM_MIPS_MULTI_SRC) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/stamp-gen-mode-multi-igen \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/stamp-gen-mode-multi-run

@SIM_ENABLE_ARCH_mips_TRUE@am__append_98 = $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@am__append_99 = $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@am__append_100 = mips/multi-include.h mips/multi-run.c
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_101 = mn10300/run
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_102 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_103 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/model.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/support.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/engine.h

@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_104 = $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_105 = $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_106 = moxie/run
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_107 = msp430/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_108 = or1k/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_109 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_110 = $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_111 = $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_112 = ppc/run ppc/psim
@SIM_ENABLE_ARCH_pru_TRUE@am__append_113 = pru/run
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_114 = riscv/run
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_115 = rl78/run
@SIM_ENABLE_ARCH_rx_TRUE@am__append_116 = rx/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_117 = sh/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_118 = \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/ppi.c

@SIM_ENABLE_ARCH_sh_TRUE@am__append_119 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_sh_TRUE@am__append_120 = sh/gencode
@SIM_ENABLE_ARCH_sh_TRUE@am__append_121 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_122 = v850/run
@SIM_ENABLE_ARCH_v850_TRUE@am__append_123 = \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/model.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/support.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/engine.h

@SIM_ENABLE_ARCH_v850_TRUE@am__append_124 = $(v850_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_125 = $(v850_BUILD_OUTPUTS)
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
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	$(top_srcdir)/../config/override.m4 \
	$(top_srcdir)/../config/pkg.m4 $(top_srcdir)/../libtool.m4 \
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	$(top_srcdir)/m4/sim_ac_option_debug.m4 \
	$(top_srcdir)/m4/sim_ac_option_endian.m4 \
	$(top_srcdir)/m4/sim_ac_option_environment.m4 \
	$(top_srcdir)/m4/sim_ac_option_hardware.m4 \
	$(top_srcdir)/m4/sim_ac_option_inline.m4 \
	$(top_srcdir)/m4/sim_ac_option_profile.m4 \
	$(top_srcdir)/m4/sim_ac_option_reserved_bits.m4 \
	$(top_srcdir)/m4/sim_ac_option_scache.m4 \
	$(top_srcdir)/m4/sim_ac_option_smp.m4 \
	$(top_srcdir)/m4/sim_ac_option_stdio.m4 \
	$(top_srcdir)/m4/sim_ac_option_trace.m4 \
	$(top_srcdir)/m4/sim_ac_option_warnings.m4 \
	$(top_srcdir)/m4/sim_ac_platform.m4 \
	$(top_srcdir)/m4/sim_ac_toolchain.m4 \
	$(top_srcdir)/frv/acinclude.m4 $(top_srcdir)/mips/acinclude.m4 \
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	$(top_srcdir)/configure.ac
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
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DIST_COMMON = $(srcdir)/Makefile.am $(top_srcdir)/configure \
	$(am__configure_deps) $(am__pkginclude_HEADERS_DIST)
am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
 configure.lineno config.status.lineno
mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs
CONFIG_HEADER = config.h
CONFIG_CLEAN_FILES = Make-common.sim aarch64/Makefile.sim \
	aarch64/.gdbinit arm/Makefile.sim arm/.gdbinit \
	avr/Makefile.sim avr/.gdbinit bfin/Makefile.sim bfin/.gdbinit \
	bpf/Makefile.sim bpf/.gdbinit cr16/Makefile.sim cr16/.gdbinit \
	cris/Makefile.sim cris/.gdbinit d10v/Makefile.sim \
	d10v/.gdbinit frv/Makefile.sim frv/.gdbinit ft32/Makefile.sim \
	ft32/.gdbinit h8300/Makefile.sim h8300/.gdbinit \
	iq2000/Makefile.sim iq2000/.gdbinit lm32/Makefile.sim \
	lm32/.gdbinit m32c/Makefile.sim m32c/.gdbinit \
	m32r/Makefile.sim m32r/.gdbinit m68hc11/Makefile.sim \
	m68hc11/.gdbinit mcore/Makefile.sim mcore/.gdbinit \
	microblaze/Makefile.sim microblaze/.gdbinit mips/Makefile.sim \
	mips/.gdbinit mn10300/Makefile.sim mn10300/.gdbinit \
	moxie/Makefile.sim moxie/.gdbinit msp430/Makefile.sim \
	msp430/.gdbinit or1k/Makefile.sim or1k/.gdbinit ppc/.gdbinit \
	pru/Makefile.sim pru/.gdbinit riscv/Makefile.sim \
	riscv/.gdbinit rl78/Makefile.sim rl78/.gdbinit rx/Makefile.sim \
	rx/.gdbinit sh/Makefile.sim sh/.gdbinit erc32/Makefile.sim \
	erc32/.gdbinit v850/Makefile.sim v850/.gdbinit \
	example-synacor/Makefile.sim example-synacor/.gdbinit \
	arch-subdir.mk .gdbinit
CONFIG_CLEAN_VPATH_FILES =
LIBRARIES = $(noinst_LIBRARIES)
ARFLAGS = cru
AM_V_AR = $(am__v_AR_@AM_V@)
am__v_AR_ = $(am__v_AR_@AM_DEFAULT_V@)
am__v_AR_0 = @echo "  AR      " $@;
am__v_AR_1 = 
aarch64_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_aarch64_TRUE@	%,aarch64/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_aarch64_TRUE@	%,aarch64/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/cpustate.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/interp.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/memory.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/modules.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/sim-resume.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/simulator.o
am_aarch64_libsim_a_OBJECTS =
aarch64_libsim_a_OBJECTS = $(am_aarch64_libsim_a_OBJECTS)
am__dirstamp = $(am__leading_dot)dirstamp
arm_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_DEPENDENCIES = arm/wrapper.o \
@SIM_ENABLE_ARCH_arm_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_arm_TRUE@	%,arm/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_arm_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_arm_TRUE@	%,arm/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armemu.o arm/armemu32.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/arminit.o arm/armos.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armsupp.o arm/armvirt.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/thumbemu.o arm/armcopro.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/maverick.o arm/iwmmxt.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/modules.o
am_arm_libsim_a_OBJECTS =
arm_libsim_a_OBJECTS = $(am_arm_libsim_a_OBJECTS)
avr_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_DEPENDENCIES = avr/interp.o \
@SIM_ENABLE_ARCH_avr_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_avr_TRUE@	%,avr/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_avr_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_avr_TRUE@	%,avr/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/modules.o avr/sim-resume.o
am_avr_libsim_a_OBJECTS =
avr_libsim_a_OBJECTS = $(am_avr_libsim_a_OBJECTS)
bfin_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_bfin_TRUE@	%,bfin/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_bfin_TRUE@	%,bfin/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_bfin_TRUE@	%,bfin/dv-%.o,$(bfin_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/bfin-sim.o bfin/devices.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/gui.o bfin/interp.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/machs.o bfin/modules.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/sim-resume.o
am_bfin_libsim_a_OBJECTS =
bfin_libsim_a_OBJECTS = $(am_bfin_libsim_a_OBJECTS)
bpf_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_bpf_TRUE@	%,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_bpf_TRUE@	%,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/modules.o bpf/cgen-run.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/cgen-scache.o bpf/cgen-trace.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/cgen-utils.o bpf/arch.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/cpu.o bpf/decode-le.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/decode-be.o bpf/sem-le.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/sem-be.o bpf/mloop-le.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/mloop-be.o bpf/bpf.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/bpf-helpers.o bpf/sim-if.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/traps.o
am_bpf_libsim_a_OBJECTS =
bpf_libsim_a_OBJECTS = $(am_bpf_libsim_a_OBJECTS)
common_libcommon_a_AR = $(AR) $(ARFLAGS)
common_libcommon_a_LIBADD =
am_common_libcommon_a_OBJECTS = common/callback.$(OBJEXT) \
	common/portability.$(OBJEXT) common/sim-load.$(OBJEXT) \
	common/syscall.$(OBJEXT) common/target-newlib-errno.$(OBJEXT) \
	common/target-newlib-open.$(OBJEXT) \
	common/target-newlib-signal.$(OBJEXT) \
	common/target-newlib-syscall.$(OBJEXT) \
	common/version.$(OBJEXT)
common_libcommon_a_OBJECTS = $(am_common_libcommon_a_OBJECTS)
cr16_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_cr16_TRUE@	%,cr16/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_cr16_TRUE@	%,cr16/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/interp.o cr16/modules.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/sim-resume.o cr16/simops.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/table.o
am_cr16_libsim_a_OBJECTS =
cr16_libsim_a_OBJECTS = $(am_cr16_libsim_a_OBJECTS)
cris_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_cris_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_cris_TRUE@	%,cris/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_cris_TRUE@	%,cris/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_cris_TRUE@	%,cris/dv-%.o,$(cris_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/modules.o cris/cgen-run.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-scache.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-trace.o cris/cgen-utils.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/arch.o cris/crisv10f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cpuv10.o cris/decodev10.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/modelv10.o cris/mloopv10f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/crisv32f.o cris/cpuv32.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/decodev32.o cris/modelv32.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/mloopv32f.o cris/sim-if.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/traps.o
am_cris_libsim_a_OBJECTS =
cris_libsim_a_OBJECTS = $(am_cris_libsim_a_OBJECTS)
d10v_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/interp.o $(patsubst \
@SIM_ENABLE_ARCH_d10v_TRUE@	%,d10v/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_d10v_TRUE@	%,d10v/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/endian.o d10v/modules.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/sim-resume.o d10v/simops.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/table.o
am_d10v_libsim_a_OBJECTS =
d10v_libsim_a_OBJECTS = $(am_d10v_libsim_a_OBJECTS)
erc32_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/erc32.o erc32/exec.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/float.o erc32/func.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/help.o erc32/interf.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/modules.o
am_erc32_libsim_a_OBJECTS =
erc32_libsim_a_OBJECTS = $(am_erc32_libsim_a_OBJECTS)
example_synacor_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_examples_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_examples_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_examples_TRUE@	%,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_examples_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_examples_TRUE@	%,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/interp.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/modules.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/sim-main.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/sim-resume.o
am_example_synacor_libsim_a_OBJECTS =
example_synacor_libsim_a_OBJECTS =  \
	$(am_example_synacor_libsim_a_OBJECTS)
frv_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_frv_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_frv_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_frv_TRUE@	%,frv/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_frv_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_frv_TRUE@	%,frv/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/modules.o frv/cgen-accfp.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-fpu.o frv/cgen-run.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-scache.o frv/cgen-trace.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-utils.o frv/arch.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-par.o frv/cpu.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/decode.o frv/frv.o frv/mloop.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/model.o frv/sem.o frv/cache.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/interrupts.o frv/memory.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/options.o frv/pipeline.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile.o frv/profile-fr400.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr450.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr500.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr550.o frv/registers.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/reset.o frv/sim-if.o frv/traps.o
am_frv_libsim_a_OBJECTS =
frv_libsim_a_OBJECTS = $(am_frv_libsim_a_OBJECTS)
ft32_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_ft32_TRUE@	%,ft32/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_ft32_TRUE@	%,ft32/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/interp.o ft32/modules.o \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/sim-resume.o
am_ft32_libsim_a_OBJECTS =
ft32_libsim_a_OBJECTS = $(am_ft32_libsim_a_OBJECTS)
h8300_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/compile.o $(patsubst \
@SIM_ENABLE_ARCH_h8300_TRUE@	%,h8300/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_h8300_TRUE@	%,h8300/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/modules.o h8300/sim-resume.o
am_h8300_libsim_a_OBJECTS =
h8300_libsim_a_OBJECTS = $(am_h8300_libsim_a_OBJECTS)
igen_libigen_a_AR = $(AR) $(ARFLAGS)
igen_libigen_a_LIBADD =
@SIM_ENABLE_IGEN_TRUE@am_igen_libigen_a_OBJECTS =  \
@SIM_ENABLE_IGEN_TRUE@	igen/table.$(OBJEXT) igen/lf.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/misc.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/filter_host.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-decode.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-cache.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/filter.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-insn.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-model.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-itable.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-icache.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-semantics.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-idecode.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-support.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-engine.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/gen.$(OBJEXT)
igen_libigen_a_OBJECTS = $(am_igen_libigen_a_OBJECTS)
iq2000_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_iq2000_TRUE@	%,iq2000/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_iq2000_TRUE@	%,iq2000/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/modules.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-run.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-scache.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-trace.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-utils.o iq2000/arch.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cpu.o iq2000/decode.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/iq2000.o iq2000/sem.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/mloop.o iq2000/model.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/sim-if.o
am_iq2000_libsim_a_OBJECTS =
iq2000_libsim_a_OBJECTS = $(am_iq2000_libsim_a_OBJECTS)
lm32_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_lm32_TRUE@	%,lm32/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_lm32_TRUE@	%,lm32/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_lm32_TRUE@	%,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/modules.o lm32/cgen-run.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-scache.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-trace.o lm32/cgen-utils.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/arch.o lm32/cpu.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/decode.o lm32/sem.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/mloop.o lm32/model.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/lm32.o lm32/sim-if.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/traps.o lm32/user.o
am_lm32_libsim_a_OBJECTS =
lm32_libsim_a_OBJECTS = $(am_lm32_libsim_a_OBJECTS)
m32c_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_m32c_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/gdb-if.o m32c/int.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/load.o m32c/m32c.o m32c/mem.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/misc.o m32c/modules.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/r8c.o m32c/reg.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/srcdest.o m32c/syscalls.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/trace.o
am_m32c_libsim_a_OBJECTS =
m32c_libsim_a_OBJECTS = $(am_m32c_libsim_a_OBJECTS)
m32r_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_m32r_TRUE@	%,m32r/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_m32r_TRUE@	%,m32r/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_m32r_TRUE@	%,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/modules.o m32r/cgen-run.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-scache.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-trace.o m32r/cgen-utils.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/arch.o m32r/m32r.o m32r/cpu.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/decode.o m32r/sem.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/model.o m32r/mloop.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/m32rx.o m32r/cpux.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/decodex.o m32r/modelx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloopx.o m32r/m32r2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cpu2.o m32r/decode2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/model2.o m32r/mloop2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/sim-if.o m32r/traps.o
am_m32r_libsim_a_OBJECTS =
m32r_libsim_a_OBJECTS = $(am_m32r_libsim_a_OBJECTS)
m68hc11_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/interp.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc11int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc12int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/emulos.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/interrupts.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc11_sim.o $(patsubst \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	%,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	%,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	%,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/modules.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/sim-resume.o
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m68hc11_libsim_a_OBJECTS = $(am_m68hc11_libsim_a_OBJECTS)
mcore_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/interp.o $(patsubst \
@SIM_ENABLE_ARCH_mcore_TRUE@	%,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_mcore_TRUE@	%,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/modules.o mcore/sim-resume.o
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mcore_libsim_a_OBJECTS = $(am_mcore_libsim_a_OBJECTS)
microblaze_libsim_a_AR = $(AR) $(ARFLAGS)
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@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/interp.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_microblaze_TRUE@	%,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_microblaze_TRUE@	%,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/modules.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/sim-resume.o
am_microblaze_libsim_a_OBJECTS =
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mips_libsim_a_AR = $(AR) $(ARFLAGS)
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/multi-run.o
@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_88) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_89) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__DEPENDENCIES_2)
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_mips_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/interp.o $(am__DEPENDENCIES_3) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_mips_TRUE@	%,mips/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_mips_TRUE@	%,mips/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst \
@SIM_ENABLE_ARCH_mips_TRUE@	%,mips/dv-%.o,$(mips_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/cp1.o mips/dsp.o mips/mdmx.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/modules.o mips/sim-main.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/sim-resume.o
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mips_libsim_a_OBJECTS = $(am_mips_libsim_a_OBJECTS)
@SIM_ENABLE_IGEN_TRUE@am__EXEEXT_1 = $(IGEN) igen/filter$(EXEEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/gen$(EXEEXT) igen/ld-cache$(EXEEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-decode$(EXEEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-insn$(EXEEXT) \
@SIM_ENABLE_IGEN_TRUE@	igen/table$(EXEEXT)
@SIM_ENABLE_IGEN_TRUE@am__EXEEXT_2 = $(am__EXEEXT_1)
@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_3 = cr16/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_4 = d10v/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_5 = m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_6 = m68hc11/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_7 = sh/gencode$(EXEEXT)
am__EXEEXT_8 = testsuite/common/bits32m0$(EXEEXT) \
	testsuite/common/bits32m31$(EXEEXT) \
	testsuite/common/bits64m0$(EXEEXT) \
	testsuite/common/bits64m63$(EXEEXT) \
	testsuite/common/alu-tst$(EXEEXT)
@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_9 = cris/rvdummy$(EXEEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_10 = aarch64/run$(EXEEXT)
@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_11 = arm/run$(EXEEXT)
@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_12 = avr/run$(EXEEXT)
@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_13 = bfin/run$(EXEEXT)
@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_14 = bpf/run$(EXEEXT)
@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_15 = cr16/run$(EXEEXT)
@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_16 = cris/run$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_17 = d10v/run$(EXEEXT)
@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_18 = erc32/run$(EXEEXT) \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/sis$(EXEEXT)
@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_19 =  \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/run$(EXEEXT)
@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_20 = frv/run$(EXEEXT)
@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_21 = ft32/run$(EXEEXT)
@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_22 = h8300/run$(EXEEXT)
@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_23 = iq2000/run$(EXEEXT)
@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_24 = lm32/run$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_25 = m32c/run$(EXEEXT)
@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_26 = m32r/run$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_27 = m68hc11/run$(EXEEXT)
@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_28 = mcore/run$(EXEEXT)
@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_29 =  \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/run$(EXEEXT)
@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_30 = mips/run$(EXEEXT)
@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_31 = mn10300/run$(EXEEXT)
@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_32 = moxie/run$(EXEEXT)
@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_33 = msp430/run$(EXEEXT)
@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_34 = or1k/run$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_35 = ppc/run$(EXEEXT) \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/psim$(EXEEXT)
@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_36 = pru/run$(EXEEXT)
@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_37 = riscv/run$(EXEEXT)
@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_38 = rl78/run$(EXEEXT)
@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_39 = rx/run$(EXEEXT)
@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_40 = sh/run$(EXEEXT)
@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_41 = v850/run$(EXEEXT)
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am_aarch64_run_OBJECTS =
aarch64_run_OBJECTS = $(am_aarch64_run_OBJECTS)
am__DEPENDENCIES_4 = $(BFD_LIB) $(OPCODES_LIB) $(LIBIBERTY_LIB)
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/nrun.o aarch64/libsim.a \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(am__DEPENDENCIES_4)
AM_V_lt = $(am__v_lt_@AM_V@)
am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
am__v_lt_0 = --silent
am__v_lt_1 = 
am_arm_run_OBJECTS =
arm_run_OBJECTS = $(am_arm_run_OBJECTS)
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_DEPENDENCIES = arm/nrun.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/libsim.a $(am__DEPENDENCIES_4)
am_avr_run_OBJECTS =
avr_run_OBJECTS = $(am_avr_run_OBJECTS)
@SIM_ENABLE_ARCH_avr_TRUE@avr_run_DEPENDENCIES = avr/nrun.o \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/libsim.a $(am__DEPENDENCIES_4)
am_bfin_run_OBJECTS =
bfin_run_OBJECTS = $(am_bfin_run_OBJECTS)
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_DEPENDENCIES = bfin/nrun.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/libsim.a $(am__DEPENDENCIES_4)
am_bpf_run_OBJECTS =
bpf_run_OBJECTS = $(am_bpf_run_OBJECTS)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_DEPENDENCIES = bpf/nrun.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/libsim.a $(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_cr16_TRUE@am_cr16_gencode_OBJECTS =  \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/gencode.$(OBJEXT)
cr16_gencode_OBJECTS = $(am_cr16_gencode_OBJECTS)
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/cr16-opc.o
am_cr16_run_OBJECTS =
cr16_run_OBJECTS = $(am_cr16_run_OBJECTS)
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_DEPENDENCIES = cr16/nrun.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/libsim.a $(am__DEPENDENCIES_4)
am_cris_run_OBJECTS =
cris_run_OBJECTS = $(am_cris_run_OBJECTS)
@SIM_ENABLE_ARCH_cris_TRUE@cris_run_DEPENDENCIES = cris/nrun.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/libsim.a $(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_cris_TRUE@am_cris_rvdummy_OBJECTS =  \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/rvdummy.$(OBJEXT)
cris_rvdummy_OBJECTS = $(am_cris_rvdummy_OBJECTS)
@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_cris_TRUE@	$(LIBIBERTY_LIB)
@SIM_ENABLE_ARCH_d10v_TRUE@am_d10v_gencode_OBJECTS =  \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/gencode.$(OBJEXT)
d10v_gencode_OBJECTS = $(am_d10v_gencode_OBJECTS)
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/d10v-opc.o
am_d10v_run_OBJECTS =
d10v_run_OBJECTS = $(am_d10v_run_OBJECTS)
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_DEPENDENCIES = d10v/nrun.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/libsim.a $(am__DEPENDENCIES_4)
am_erc32_run_OBJECTS =
erc32_run_OBJECTS = $(am_erc32_run_OBJECTS)
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_DEPENDENCIES = erc32/sis.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/libsim.a \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(am__DEPENDENCIES_4) \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(am__DEPENDENCIES_1) \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(am__DEPENDENCIES_1)
erc32_sis_SOURCES = erc32/sis.c
erc32_sis_OBJECTS = erc32/sis.$(OBJEXT)
erc32_sis_LDADD = $(LDADD)
am_example_synacor_run_OBJECTS =
example_synacor_run_OBJECTS = $(am_example_synacor_run_OBJECTS)
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/nrun.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/libsim.a \
@SIM_ENABLE_ARCH_examples_TRUE@	$(am__DEPENDENCIES_4)
am_frv_run_OBJECTS =
frv_run_OBJECTS = $(am_frv_run_OBJECTS)
@SIM_ENABLE_ARCH_frv_TRUE@frv_run_DEPENDENCIES = frv/nrun.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/libsim.a $(am__DEPENDENCIES_4)
am_ft32_run_OBJECTS =
ft32_run_OBJECTS = $(am_ft32_run_OBJECTS)
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_DEPENDENCIES = ft32/nrun.o \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/libsim.a $(am__DEPENDENCIES_4)
am_h8300_run_OBJECTS =
h8300_run_OBJECTS = $(am_h8300_run_OBJECTS)
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_DEPENDENCIES = h8300/nrun.o \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/libsim.a \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(am__DEPENDENCIES_4)
am_igen_filter_OBJECTS =
igen_filter_OBJECTS = $(am_igen_filter_OBJECTS)
@SIM_ENABLE_IGEN_TRUE@igen_filter_DEPENDENCIES = igen/filter-main.o \
@SIM_ENABLE_IGEN_TRUE@	igen/libigen.a
am_igen_gen_OBJECTS =
igen_gen_OBJECTS = $(am_igen_gen_OBJECTS)
@SIM_ENABLE_IGEN_TRUE@igen_gen_DEPENDENCIES = igen/gen-main.o \
@SIM_ENABLE_IGEN_TRUE@	igen/libigen.a
@SIM_ENABLE_IGEN_TRUE@am_igen_igen_OBJECTS = igen/igen.$(OBJEXT)
igen_igen_OBJECTS = $(am_igen_igen_OBJECTS)
@SIM_ENABLE_IGEN_TRUE@igen_igen_DEPENDENCIES = igen/libigen.a
am_igen_ld_cache_OBJECTS =
igen_ld_cache_OBJECTS = $(am_igen_ld_cache_OBJECTS)
@SIM_ENABLE_IGEN_TRUE@igen_ld_cache_DEPENDENCIES =  \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-cache-main.o igen/libigen.a
am_igen_ld_decode_OBJECTS =
igen_ld_decode_OBJECTS = $(am_igen_ld_decode_OBJECTS)
@SIM_ENABLE_IGEN_TRUE@igen_ld_decode_DEPENDENCIES =  \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-decode-main.o igen/libigen.a
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igen_ld_insn_OBJECTS = $(am_igen_ld_insn_OBJECTS)
@SIM_ENABLE_IGEN_TRUE@igen_ld_insn_DEPENDENCIES = igen/ld-insn-main.o \
@SIM_ENABLE_IGEN_TRUE@	igen/libigen.a
am_igen_table_OBJECTS =
igen_table_OBJECTS = $(am_igen_table_OBJECTS)
@SIM_ENABLE_IGEN_TRUE@igen_table_DEPENDENCIES = igen/table-main.o \
@SIM_ENABLE_IGEN_TRUE@	igen/libigen.a
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@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_DEPENDENCIES = iq2000/nrun.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/libsim.a \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(am__DEPENDENCIES_4)
am_lm32_run_OBJECTS =
lm32_run_OBJECTS = $(am_lm32_run_OBJECTS)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_DEPENDENCIES = lm32/nrun.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/libsim.a $(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_m32c_TRUE@am_m32c_opc2c_OBJECTS =  \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/opc2c.$(OBJEXT)
m32c_opc2c_OBJECTS = $(am_m32c_opc2c_OBJECTS)
m32c_opc2c_LDADD = $(LDADD)
am_m32c_run_OBJECTS =
m32c_run_OBJECTS = $(am_m32c_run_OBJECTS)
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_DEPENDENCIES = m32c/main.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/libsim.a $(am__DEPENDENCIES_4)
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@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_DEPENDENCIES = m32r/nrun.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/libsim.a $(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am_m68hc11_gencode_OBJECTS =  \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/gencode.$(OBJEXT)
m68hc11_gencode_OBJECTS = $(am_m68hc11_gencode_OBJECTS)
m68hc11_gencode_LDADD = $(LDADD)
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@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/nrun.o m68hc11/libsim.a \
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mcore_run_OBJECTS = $(am_mcore_run_OBJECTS)
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_DEPENDENCIES = mcore/nrun.o \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/libsim.a \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(am__DEPENDENCIES_4)
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microblaze_run_OBJECTS = $(am_microblaze_run_OBJECTS)
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/nrun.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/libsim.a \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(am__DEPENDENCIES_4)
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mips_run_OBJECTS = $(am_mips_run_OBJECTS)
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_DEPENDENCIES = mips/nrun.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/libsim.a $(am__DEPENDENCIES_4)
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@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_DEPENDENCIES =  \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/nrun.o mn10300/libsim.a \
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@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_DEPENDENCIES = moxie/nrun.o \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/libsim.a \
@SIM_ENABLE_ARCH_moxie_TRUE@	$(am__DEPENDENCIES_4)
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@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_DEPENDENCIES = msp430/nrun.o \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/libsim.a \
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@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_DEPENDENCIES = or1k/nrun.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/libsim.a $(am__DEPENDENCIES_4)
ppc_psim_SOURCES = ppc/psim.c
ppc_psim_OBJECTS = ppc/psim.$(OBJEXT)
ppc_psim_LDADD = $(LDADD)
am_ppc_run_OBJECTS =
ppc_run_OBJECTS = $(am_ppc_run_OBJECTS)
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_DEPENDENCIES = ppc/main.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/libsim.a $(am__DEPENDENCIES_4)
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pru_run_OBJECTS = $(am_pru_run_OBJECTS)
@SIM_ENABLE_ARCH_pru_TRUE@pru_run_DEPENDENCIES = pru/nrun.o \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/libsim.a $(am__DEPENDENCIES_4)
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@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_DEPENDENCIES = riscv/nrun.o \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/libsim.a \
@SIM_ENABLE_ARCH_riscv_TRUE@	$(am__DEPENDENCIES_4)
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rl78_run_OBJECTS = $(am_rl78_run_OBJECTS)
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_DEPENDENCIES = rl78/main.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/libsim.a $(am__DEPENDENCIES_4)
am_rx_run_OBJECTS =
rx_run_OBJECTS = $(am_rx_run_OBJECTS)
@SIM_ENABLE_ARCH_rx_TRUE@rx_run_DEPENDENCIES = rx/main.o rx/libsim.a \
@SIM_ENABLE_ARCH_rx_TRUE@	$(am__DEPENDENCIES_4)
@SIM_ENABLE_ARCH_sh_TRUE@am_sh_gencode_OBJECTS = sh/gencode.$(OBJEXT)
sh_gencode_OBJECTS = $(am_sh_gencode_OBJECTS)
sh_gencode_LDADD = $(LDADD)
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FGREP = @FGREP@
GREP = @GREP@
IGEN_FLAGS_SMP = @IGEN_FLAGS_SMP@
INSTALL = @INSTALL@
INSTALL_DATA = @INSTALL_DATA@
INSTALL_PROGRAM = @INSTALL_PROGRAM@
INSTALL_SCRIPT = @INSTALL_SCRIPT@
INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
LD = @LD@
LDFLAGS = @LDFLAGS@
LDFLAGS_FOR_BUILD = @LDFLAGS_FOR_BUILD@
LD_FOR_TARGET = @LD_FOR_TARGET@
LD_FOR_TARGET_AARCH64 = @LD_FOR_TARGET_AARCH64@
LD_FOR_TARGET_ARM = @LD_FOR_TARGET_ARM@
LD_FOR_TARGET_AVR = @LD_FOR_TARGET_AVR@
LD_FOR_TARGET_BFIN = @LD_FOR_TARGET_BFIN@
LD_FOR_TARGET_BPF = @LD_FOR_TARGET_BPF@
LD_FOR_TARGET_CR16 = @LD_FOR_TARGET_CR16@
LD_FOR_TARGET_CRIS = @LD_FOR_TARGET_CRIS@
LD_FOR_TARGET_D10V = @LD_FOR_TARGET_D10V@
LD_FOR_TARGET_ERC32 = @LD_FOR_TARGET_ERC32@
LD_FOR_TARGET_EXAMPLE_SYNACOR = @LD_FOR_TARGET_EXAMPLE_SYNACOR@
LD_FOR_TARGET_FRV = @LD_FOR_TARGET_FRV@
LD_FOR_TARGET_FT32 = @LD_FOR_TARGET_FT32@
LD_FOR_TARGET_H8300 = @LD_FOR_TARGET_H8300@
LD_FOR_TARGET_IQ2000 = @LD_FOR_TARGET_IQ2000@
LD_FOR_TARGET_LM32 = @LD_FOR_TARGET_LM32@
LD_FOR_TARGET_M32C = @LD_FOR_TARGET_M32C@
LD_FOR_TARGET_M32R = @LD_FOR_TARGET_M32R@
LD_FOR_TARGET_M68HC11 = @LD_FOR_TARGET_M68HC11@
LD_FOR_TARGET_MCORE = @LD_FOR_TARGET_MCORE@
LD_FOR_TARGET_MICROBLAZE = @LD_FOR_TARGET_MICROBLAZE@
LD_FOR_TARGET_MIPS = @LD_FOR_TARGET_MIPS@
LD_FOR_TARGET_MN10300 = @LD_FOR_TARGET_MN10300@
LD_FOR_TARGET_MOXIE = @LD_FOR_TARGET_MOXIE@
LD_FOR_TARGET_MSP430 = @LD_FOR_TARGET_MSP430@
LD_FOR_TARGET_OR1K = @LD_FOR_TARGET_OR1K@
LD_FOR_TARGET_PPC = @LD_FOR_TARGET_PPC@
LD_FOR_TARGET_PRU = @LD_FOR_TARGET_PRU@
LD_FOR_TARGET_RISCV = @LD_FOR_TARGET_RISCV@
LD_FOR_TARGET_RL78 = @LD_FOR_TARGET_RL78@
LD_FOR_TARGET_RX = @LD_FOR_TARGET_RX@
LD_FOR_TARGET_SH = @LD_FOR_TARGET_SH@
LD_FOR_TARGET_V850 = @LD_FOR_TARGET_V850@
LIBOBJS = @LIBOBJS@
LIBS = @LIBS@
LIBTOOL = @LIBTOOL@
LIPO = @LIPO@
LN_S = @LN_S@
LTLIBOBJS = @LTLIBOBJS@
MAINT = @MAINT@
MAKEINFO = @MAKEINFO@
MKDIR_P = @MKDIR_P@
NM = @NM@
NMEDIT = @NMEDIT@
OBJDUMP = @OBJDUMP@
OBJEXT = @OBJEXT@
OTOOL = @OTOOL@
OTOOL64 = @OTOOL64@
PACKAGE = @PACKAGE@
PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
PACKAGE_NAME = @PACKAGE_NAME@
PACKAGE_STRING = @PACKAGE_STRING@
PACKAGE_TARNAME = @PACKAGE_TARNAME@
PACKAGE_URL = @PACKAGE_URL@
PACKAGE_VERSION = @PACKAGE_VERSION@
PATH_SEPARATOR = @PATH_SEPARATOR@
PKGVERSION = @PKGVERSION@
PKG_CONFIG = @PKG_CONFIG@
PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
PKG_CONFIG_PATH = @PKG_CONFIG_PATH@
RANLIB = @RANLIB@
RANLIB_FOR_BUILD = @RANLIB_FOR_BUILD@
READLINE_CFLAGS = @READLINE_CFLAGS@
READLINE_LIB = @READLINE_LIB@
REPORT_BUGS_TEXI = @REPORT_BUGS_TEXI@
REPORT_BUGS_TO = @REPORT_BUGS_TO@
SDL_CFLAGS = @SDL_CFLAGS@
SDL_LIBS = @SDL_LIBS@
SED = @SED@
SET_MAKE = @SET_MAKE@
SHELL = @SHELL@
SIM_COMMON_BUILD_FALSE = @SIM_COMMON_BUILD_FALSE@
SIM_COMMON_BUILD_TRUE = @SIM_COMMON_BUILD_TRUE@
SIM_ENABLED_ARCHES = @SIM_ENABLED_ARCHES@
SIM_FRV_TRAPDUMP_FLAGS = @SIM_FRV_TRAPDUMP_FLAGS@
SIM_HW_CFLAGS = @SIM_HW_CFLAGS@
SIM_HW_SOCKSER = @SIM_HW_SOCKSER@
SIM_INLINE = @SIM_INLINE@
SIM_MIPS_BITSIZE = @SIM_MIPS_BITSIZE@
SIM_MIPS_FPU_BITSIZE = @SIM_MIPS_FPU_BITSIZE@
SIM_MIPS_GEN = @SIM_MIPS_GEN@
SIM_MIPS_IGEN_ITABLE_FLAGS = @SIM_MIPS_IGEN_ITABLE_FLAGS@
SIM_MIPS_M16_FLAGS = @SIM_MIPS_M16_FLAGS@
SIM_MIPS_MULTI_IGEN_CONFIGS = @SIM_MIPS_MULTI_IGEN_CONFIGS@
SIM_MIPS_MULTI_OBJ = @SIM_MIPS_MULTI_OBJ@
SIM_MIPS_MULTI_SRC = @SIM_MIPS_MULTI_SRC@
SIM_MIPS_SINGLE_FLAGS = @SIM_MIPS_SINGLE_FLAGS@
SIM_MIPS_SUBTARGET = @SIM_MIPS_SUBTARGET@
SIM_PRIMARY_TARGET = @SIM_PRIMARY_TARGET@
SIM_RISCV_BITSIZE = @SIM_RISCV_BITSIZE@
SIM_RX_CYCLE_ACCURATE_FLAGS = @SIM_RX_CYCLE_ACCURATE_FLAGS@
SIM_SUBDIRS = @SIM_SUBDIRS@
SIM_TOOLCHAIN_VARS = @SIM_TOOLCHAIN_VARS@
STRIP = @STRIP@
TERMCAP_LIB = @TERMCAP_LIB@
VERSION = @VERSION@
WARN_CFLAGS = @WARN_CFLAGS@
WERROR_CFLAGS = @WERROR_CFLAGS@
abs_builddir = @abs_builddir@
abs_srcdir = @abs_srcdir@
abs_top_builddir = @abs_top_builddir@
abs_top_srcdir = @abs_top_srcdir@
ac_ct_CC = @ac_ct_CC@
ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
am__include = @am__include@
am__leading_dot = @am__leading_dot@
am__quote = @am__quote@
am__tar = @am__tar@
am__untar = @am__untar@
bindir = @bindir@
build = @build@
build_alias = @build_alias@
build_cpu = @build_cpu@
build_os = @build_os@
build_vendor = @build_vendor@
builddir = @builddir@
cgen = @cgen@
cgendir = @cgendir@
datadir = @datadir@
datarootdir = @datarootdir@
docdir = @docdir@
dvidir = @dvidir@
exec_prefix = @exec_prefix@
host = @host@
host_alias = @host_alias@
host_cpu = @host_cpu@
host_os = @host_os@
host_vendor = @host_vendor@
htmldir = @htmldir@
includedir = @includedir@
infodir = @infodir@
install_sh = @install_sh@
libdir = @libdir@
libexecdir = @libexecdir@
localedir = @localedir@
localstatedir = @localstatedir@
mandir = @mandir@
mkdir_p = @mkdir_p@
oldincludedir = @oldincludedir@
pdfdir = @pdfdir@
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
sim_bitsize = @sim_bitsize@
sim_float = @sim_float@
srcdir = @srcdir@
subdirs = @subdirs@
sysconfdir = @sysconfdir@
target = @target@
target_alias = @target_alias@
target_cpu = @target_cpu@
target_os = @target_os@
target_vendor = @target_vendor@
top_build_prefix = @top_build_prefix@
top_builddir = @top_builddir@
top_srcdir = @top_srcdir@
AUTOMAKE_OPTIONS = dejagnu foreign no-dist subdir-objects
ACLOCAL_AMFLAGS = -Im4 -I.. -I../config
GNULIB_PARENT_DIR = ..
srccom = $(srcdir)/common
srcroot = $(srcdir)/..
SUBDIRS = @subdirs@ $(SIM_SUBDIRS)
AM_MAKEFLAGS = SIM_NEW_COMMON_OBJS_="$(SIM_NEW_COMMON_OBJS)" \
	$(am__append_3) $(am__append_16) $(am__append_30) \
	$(am__append_63) $(am__append_74) $(am__append_80) \
	$(am__append_93) $(am__append_102)
pkginclude_HEADERS = $(am__append_1)
noinst_LIBRARIES = common/libcommon.a $(am__append_5) $(am__append_8) \
	$(am__append_10) $(am__append_12) $(am__append_14) \
	$(am__append_17) $(am__append_22) $(am__append_28) \
	$(am__append_35) $(am__append_41) $(am__append_45) \
	$(am__append_47) $(am__append_52) $(am__append_54) \
	$(am__append_56) $(am__append_61) $(am__append_67) \
	$(am__append_72) $(am__append_78) $(am__append_84) \
	$(am__append_86) $(am__append_91)
BUILT_SOURCES = $(am__append_19) $(am__append_24) $(am__append_32) \
	$(am__append_37) $(am__append_49) $(am__append_58) \
	$(am__append_64) $(am__append_75) $(am__append_94) \
	$(am__append_103) $(am__append_109) $(am__append_118) \
	$(am__append_123)
CLEANFILES = common/version.c common/version.c-stamp \
	testsuite/common/bits-gen testsuite/common/bits32m0.c \
	testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
	testsuite/common/bits64m63.c
DISTCLEANFILES = $(am__append_100)
MOSTLYCLEANFILES = core $(common_HW_CONFIG_H_TARGETS) $(patsubst \
	%,%/stamp-hw,$(SIM_ENABLED_ARCHES)) \
	$(common_GEN_MODULES_C_TARGETS) $(patsubst \
	%,%/stamp-modules,$(SIM_ENABLED_ARCHES)) $(am__append_7) \
	site-sim-config.exp testrun.log testrun.sum $(am__append_21) \
	$(am__append_27) $(am__append_34) $(am__append_40) \
	$(am__append_51) $(am__append_60) $(am__append_66) \
	$(am__append_71) $(am__append_77) $(am__append_83) \
	$(am__append_99) $(am__append_105) $(am__append_111) \
	$(am__append_121) $(am__append_125)
AM_CFLAGS = $(WERROR_CFLAGS) $(WARN_CFLAGS)
AM_CPPFLAGS = $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \
	$(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \
	-DSIM_COMMON_BUILD
AM_CPPFLAGS_FOR_BUILD = -I$(srcroot)/include $(SIM_HW_CFLAGS) \
	$(SIM_INLINE) -I$(srcdir)/common
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD)
LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
SIM_ALL_RECURSIVE_DEPS = common/libcommon.a \
	$(common_HW_CONFIG_H_TARGETS) $(common_GEN_MODULES_C_TARGETS) \
	$(am__append_4) $(am__append_20) $(am__append_25) \
	$(am__append_33) $(am__append_38) $(am__append_50) \
	$(am__append_59) $(am__append_65) $(am__append_69) \
	$(am__append_76) $(am__append_81) $(am__append_98) \
	$(am__append_104) $(am__append_110) $(am__append_119) \
	$(am__append_124)
SIM_INSTALL_DATA_LOCAL_DEPS = 
SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_43)
SIM_UNINSTALL_LOCAL_DEPS = $(am__append_44)
common_libcommon_a_SOURCES = \
	common/callback.c \
	common/portability.c \
	common/sim-load.c \
	common/syscall.c \
	common/target-newlib-errno.c \
	common/target-newlib-open.c \
	common/target-newlib-signal.c \
	common/target-newlib-syscall.c \
	common/version.c

SIM_COMMON_HW_OBJS = \
	hw-alloc.o \
	hw-base.o \
	hw-device.o \
	hw-events.o \
	hw-handles.o \
	hw-instances.o \
	hw-ports.o \
	hw-properties.o \
	hw-tree.o \
	sim-hw.o

SIM_NEW_COMMON_OBJS = sim-arange.o sim-bits.o sim-close.o \
	sim-command.o sim-config.o sim-core.o sim-cpu.o sim-endian.o \
	sim-engine.o sim-events.o sim-fpu.o sim-hload.o sim-hrw.o \
	sim-io.o sim-info.o sim-memopt.o sim-model.o sim-module.o \
	sim-options.o sim-profile.o sim-reason.o sim-reg.o \
	sim-signal.o sim-stop.o sim-syscall.o sim-trace.o sim-utils.o \
	sim-watch.o $(am__append_2)
SIM_HW_DEVICES = cfi core pal glue
common_HW_CONFIG_H_TARGETS = $(patsubst %,%/hw-config.h,$(SIM_ENABLED_ARCHES))
am_arch_d = $(subst -,_,$(@D))
GEN_MODULES_C_SRCS = \
	$(wildcard \
		$(patsubst %.o,$(abs_srcdir)/%.c,$($(am_arch_d)_libsim_a_OBJECTS) $($(am_arch_d)_libsim_a_LIBADD)) \
		$(filter-out %.o,$(patsubst $(@D)/%.o,$(abs_srcdir)/common/%.c,$($(am_arch_d)_libsim_a_LIBADD))))

common_GEN_MODULES_C_TARGETS = $(patsubst %,%/modules.c,$(filter-out ppc,$(SIM_ENABLED_ARCHES)))
LIBIBERTY_LIB = ../libiberty/libiberty.a
BFD_LIB = ../bfd/libbfd.la
OPCODES_LIB = ../opcodes/libopcodes.la
SIM_COMMON_LIBS = \
	$(BFD_LIB) \
	$(OPCODES_LIB) \
	$(LIBIBERTY_LIB) \
	$(LIBGNU) \
	$(LIBGNU_EXTRA_LIBS)

GUILE = $(or $(wildcard ../guile/libguile/guile),guile)
CGEN = "$(GUILE) -l $(cgendir)/guile.scm -s"
CGENFLAGS = -v
CGEN_CPU_DIR = $(cgendir)/cpu
CPU_DIR = $(srcroot)/cpu
CGEN_ARCHFILE = $(CPU_DIR)/$(@D).cpu
CGEN_READ_SCM = $(cgendir)/sim.scm
CGEN_ARCH_SCM = $(cgendir)/sim-arch.scm
CGEN_CPU_SCM = $(cgendir)/sim-cpu.scm $(cgendir)/sim-model.scm
CGEN_DECODE_SCM = $(cgendir)/sim-decode.scm
CGEN_DESC_SCM = $(cgendir)/desc.scm $(cgendir)/desc-cpu.scm
CGEN_CPU_EXTR = /extr/
CGEN_CPU_READ = /read/
CGEN_CPU_WRITE = /write/
CGEN_CPU_SEM = /sem/
CGEN_CPU_SEMSW = /semsw/
CGEN_WRAPPER = $(srccom)/cgen.sh
CGEN_GEN_ARCH = \
	$(SHELL) $(CGEN_WRAPPER) arch $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" ignored "$$isa" $$mach ignored \
		$(CGEN_ARCHFILE) ignored

CGEN_GEN_CPU = \
	$(SHELL) $(CGEN_WRAPPER) cpu $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
		$(CGEN_ARCHFILE) "$$EXTRAFILES"

CGEN_GEN_DEFS = \
	$(SHELL) $(CGEN_WRAPPER) defs $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
		$(CGEN_ARCHFILE) ignored

CGEN_GEN_DECODE = \
	$(SHELL) $(CGEN_WRAPPER) decode $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
		$(CGEN_ARCHFILE) "$$EXTRAFILES"

CGEN_GEN_CPU_DECODE = \
	$(SHELL) $(CGEN_WRAPPER) cpu-decode $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
		$(CGEN_ARCHFILE) "$$EXTRAFILES"

CGEN_GEN_CPU_DESC = \
	$(SHELL) $(CGEN_WRAPPER) desc $(srcdir)/$(@D) \
		$(CGEN) $(cgendir) "$(CGENFLAGS)" \
		$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
		$(CGEN_ARCHFILE) ignored $$opcfile


# igen leaks memory, and therefore makes AddressSanitizer unhappy.  Disable
# leak detection while running it.
@SIM_ENABLE_IGEN_TRUE@IGEN = igen/igen$(EXEEXT)
@SIM_ENABLE_IGEN_TRUE@IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(IGEN) $(IGEN_FLAGS_SMP)
@SIM_ENABLE_IGEN_TRUE@igen_libigen_a_SOURCES = \
@SIM_ENABLE_IGEN_TRUE@	igen/table.c \
@SIM_ENABLE_IGEN_TRUE@	igen/lf.c \
@SIM_ENABLE_IGEN_TRUE@	igen/misc.c \
@SIM_ENABLE_IGEN_TRUE@	igen/filter_host.c \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-decode.c \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-cache.c \
@SIM_ENABLE_IGEN_TRUE@	igen/filter.c \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-insn.c \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-model.c \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-itable.c \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-icache.c \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-semantics.c \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-idecode.c \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-support.c \
@SIM_ENABLE_IGEN_TRUE@	igen/gen-engine.c \
@SIM_ENABLE_IGEN_TRUE@	igen/gen.c

@SIM_ENABLE_IGEN_TRUE@igen_igen_SOURCES = igen/igen.c
@SIM_ENABLE_IGEN_TRUE@igen_igen_LDADD = igen/libigen.a
@SIM_ENABLE_IGEN_TRUE@igen_filter_SOURCES = 
@SIM_ENABLE_IGEN_TRUE@igen_filter_LDADD = igen/filter-main.o igen/libigen.a
@SIM_ENABLE_IGEN_TRUE@igen_gen_SOURCES = 
@SIM_ENABLE_IGEN_TRUE@igen_gen_LDADD = igen/gen-main.o igen/libigen.a
@SIM_ENABLE_IGEN_TRUE@igen_ld_cache_SOURCES = 
@SIM_ENABLE_IGEN_TRUE@igen_ld_cache_LDADD = igen/ld-cache-main.o igen/libigen.a
@SIM_ENABLE_IGEN_TRUE@igen_ld_decode_SOURCES = 
@SIM_ENABLE_IGEN_TRUE@igen_ld_decode_LDADD = igen/ld-decode-main.o igen/libigen.a
@SIM_ENABLE_IGEN_TRUE@igen_ld_insn_SOURCES = 
@SIM_ENABLE_IGEN_TRUE@igen_ld_insn_LDADD = igen/ld-insn-main.o igen/libigen.a
@SIM_ENABLE_IGEN_TRUE@igen_table_SOURCES = 
@SIM_ENABLE_IGEN_TRUE@igen_table_LDADD = igen/table-main.o igen/libigen.a
@SIM_ENABLE_IGEN_TRUE@igen_IGEN_TOOLS = \
@SIM_ENABLE_IGEN_TRUE@	$(IGEN) \
@SIM_ENABLE_IGEN_TRUE@	igen/filter \
@SIM_ENABLE_IGEN_TRUE@	igen/gen \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-cache \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-decode \
@SIM_ENABLE_IGEN_TRUE@	igen/ld-insn \
@SIM_ENABLE_IGEN_TRUE@	igen/table

EXTRA_DEJAGNU_SITE_CONFIG = site-sim-config.exp

# Custom verbose test variables that automake doesn't provide (yet?).
AM_V_RUNTEST = $(AM_V_RUNTEST_@AM_V@)
AM_V_RUNTEST_ = $(AM_V_RUNTEST_@AM_DEFAULT_V@)
AM_V_RUNTEST_0 = @echo "  RUNTEST  $(RUNTESTFLAGS) $*";
AM_V_RUNTEST_1 = 
DO_RUNTEST = \
	LC_ALL=C; export LC_ALL; \
	EXPECT=${EXPECT} ; export EXPECT ; \
	runtest=$(RUNTEST); \
	$$runtest $(RUNTESTFLAGS)

testsuite_common_CPPFLAGS = \
	-I$(srcdir)/common \
	-I$(srcroot)/include \
	-I../bfd

@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(patsubst %,aarch64/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(patsubst %,aarch64/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/cpustate.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/interp.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/memory.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/modules.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/sim-resume.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/simulator.o

@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_SOURCES = 
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_LDADD = \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/nrun.o \
@SIM_ENABLE_ARCH_aarch64_TRUE@	aarch64/libsim.a \
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_arm_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/wrapper.o \
@SIM_ENABLE_ARCH_arm_TRUE@	$(patsubst %,arm/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_arm_TRUE@	$(patsubst %,arm/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armemu.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armemu32.o arm/arminit.o arm/armos.o arm/armsupp.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armvirt.o arm/thumbemu.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/armcopro.o arm/maverick.o arm/iwmmxt.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/modules.o

@SIM_ENABLE_ARCH_arm_TRUE@arm_run_SOURCES = 
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_LDADD = \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/nrun.o \
@SIM_ENABLE_ARCH_arm_TRUE@	arm/libsim.a \
@SIM_ENABLE_ARCH_arm_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_arm_TRUE@armdocdir = $(docdir)/arm
@SIM_ENABLE_ARCH_arm_TRUE@armdoc_DATA = arm/README
@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_avr_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/interp.o \
@SIM_ENABLE_ARCH_avr_TRUE@	$(patsubst %,avr/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_avr_TRUE@	$(patsubst %,avr/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/modules.o \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/sim-resume.o

@SIM_ENABLE_ARCH_avr_TRUE@avr_run_SOURCES = 
@SIM_ENABLE_ARCH_avr_TRUE@avr_run_LDADD = \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/nrun.o \
@SIM_ENABLE_ARCH_avr_TRUE@	avr/libsim.a \
@SIM_ENABLE_ARCH_avr_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(patsubst %,bfin/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(patsubst %,bfin/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(patsubst %,bfin/dv-%.o,$(bfin_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/bfin-sim.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/devices.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/gui.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/interp.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/machs.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/modules.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/sim-resume.o

@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_SOURCES = 
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_LDADD = \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/nrun.o \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin/libsim.a \
@SIM_ENABLE_ARCH_bfin_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_bfin_TRUE@bfin_SIM_EXTRA_HW_DEVICES = \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_cec \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_ctimer \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_dma \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_dmac \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_ebiu_amc \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_ebiu_ddrc \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_ebiu_sdc \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_emac \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_eppi \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_evt \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_gpio \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_gpio2 \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_gptimer \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_jtag \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_mmu \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_nfc \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_otp \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_pfmon \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_pint \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_pll \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_ppi \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_rtc \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_sic \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_spi \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_trace \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_twi \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_uart \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_uart2 \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_wdog \
@SIM_ENABLE_ARCH_bfin_TRUE@	bfin_wp \
@SIM_ENABLE_ARCH_bfin_TRUE@	eth_phy

@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(patsubst %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(patsubst %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/modules.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	\
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/cgen-run.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/cgen-scache.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/cgen-trace.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/cgen-utils.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	\
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/arch.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/cpu.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/decode-le.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/decode-be.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/sem-le.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/sem-be.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/mloop-le.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/mloop-be.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	\
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/bpf.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/bpf-helpers.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/sim-if.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/traps.o

@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_SOURCES = 
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_LDADD = \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/nrun.o \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/libsim.a \
@SIM_ENABLE_ARCH_bpf_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_bpf_TRUE@bpf_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/mloop-le.c \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/stamp-mloop-le \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/mloop-be.c \
@SIM_ENABLE_ARCH_bpf_TRUE@	bpf/stamp-mloop-be

@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(patsubst %,cr16/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(patsubst %,cr16/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/interp.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/modules.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/sim-resume.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/simops.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/table.o

@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_SOURCES = 
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_LDADD = \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/nrun.o \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/libsim.a \
@SIM_ENABLE_ARCH_cr16_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_cr16_TRUE@cr16_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_cr16_TRUE@	cr16/table.c

@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_LDADD = cr16/cr16-opc.o
@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_cris_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst %,cris/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst %,cris/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cris_TRUE@	$(patsubst %,cris/dv-%.o,$(cris_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/modules.o \
@SIM_ENABLE_ARCH_cris_TRUE@	\
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-run.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-scache.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-trace.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cgen-utils.o \
@SIM_ENABLE_ARCH_cris_TRUE@	\
@SIM_ENABLE_ARCH_cris_TRUE@	cris/arch.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/crisv10f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cpuv10.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/decodev10.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/modelv10.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/mloopv10f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/crisv32f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/cpuv32.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/decodev32.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/modelv32.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/mloopv32f.o \
@SIM_ENABLE_ARCH_cris_TRUE@	\
@SIM_ENABLE_ARCH_cris_TRUE@	cris/sim-if.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/traps.o

@SIM_ENABLE_ARCH_cris_TRUE@cris_run_SOURCES = 
@SIM_ENABLE_ARCH_cris_TRUE@cris_run_LDADD = \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/nrun.o \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/libsim.a \
@SIM_ENABLE_ARCH_cris_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_cris_TRUE@cris_SIM_EXTRA_HW_DEVICES = rv cris cris_900000xx
@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_SOURCES = cris/rvdummy.c
@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_LDADD = $(LIBIBERTY_LIB)
@SIM_ENABLE_ARCH_cris_TRUE@cris_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/mloopv10f.c \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/stamp-mloop-v10f \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/mloopv32f.c \
@SIM_ENABLE_ARCH_cris_TRUE@	cris/stamp-mloop-v32f

@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/interp.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(patsubst %,d10v/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(patsubst %,d10v/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/endian.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/modules.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/sim-resume.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/simops.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/table.o

@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_SOURCES = 
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_LDADD = \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/nrun.o \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/libsim.a \
@SIM_ENABLE_ARCH_d10v_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_d10v_TRUE@d10v_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_d10v_TRUE@	d10v/table.c

@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_SOURCES = d10v/gencode.c
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_LDADD = d10v/d10v-opc.o
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/erc32.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/exec.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/float.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/func.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/help.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/interf.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/modules.o

@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_SOURCES = 
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_LDADD = \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/sis.o \
@SIM_ENABLE_ARCH_erc32_TRUE@	erc32/libsim.a \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(SIM_COMMON_LIBS) $(READLINE_LIB) $(TERMCAP_LIB)

@SIM_ENABLE_ARCH_erc32_TRUE@erc32docdir = $(docdir)/erc32
@SIM_ENABLE_ARCH_erc32_TRUE@erc32doc_DATA = erc32/README.erc32 erc32/README.gdb erc32/README.sis
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_examples_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_examples_TRUE@	$(patsubst %,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_examples_TRUE@	$(patsubst %,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/interp.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/modules.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/sim-main.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/sim-resume.o

@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_SOURCES = 
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_LDADD = \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/nrun.o \
@SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/libsim.a \
@SIM_ENABLE_ARCH_examples_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_frv_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_frv_TRUE@	$(patsubst %,frv/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_frv_TRUE@	$(patsubst %,frv/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/modules.o \
@SIM_ENABLE_ARCH_frv_TRUE@	\
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-accfp.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-fpu.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-run.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-scache.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-trace.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-utils.o \
@SIM_ENABLE_ARCH_frv_TRUE@	\
@SIM_ENABLE_ARCH_frv_TRUE@	frv/arch.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cgen-par.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cpu.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/decode.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/frv.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/mloop.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/model.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/sem.o \
@SIM_ENABLE_ARCH_frv_TRUE@	\
@SIM_ENABLE_ARCH_frv_TRUE@	frv/cache.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/interrupts.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/memory.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/options.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/pipeline.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr400.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr450.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr500.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/profile-fr550.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/registers.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/reset.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/sim-if.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/traps.o

@SIM_ENABLE_ARCH_frv_TRUE@frv_run_SOURCES = 
@SIM_ENABLE_ARCH_frv_TRUE@frv_run_LDADD = \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/nrun.o \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/libsim.a \
@SIM_ENABLE_ARCH_frv_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_frv_TRUE@frvdocdir = $(docdir)/frv
@SIM_ENABLE_ARCH_frv_TRUE@frvdoc_DATA = frv/README
@SIM_ENABLE_ARCH_frv_TRUE@frv_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/mloop.c \
@SIM_ENABLE_ARCH_frv_TRUE@	frv/stamp-mloop

@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst %,ft32/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst %,ft32/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/interp.o \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/modules.o \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/sim-resume.o

@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_SOURCES = 
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_LDADD = \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/nrun.o \
@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/libsim.a \
@SIM_ENABLE_ARCH_ft32_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/compile.o \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(patsubst %,h8300/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(patsubst %,h8300/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/modules.o \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/sim-resume.o

@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_SOURCES = 
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_LDADD = \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/nrun.o \
@SIM_ENABLE_ARCH_h8300_TRUE@	h8300/libsim.a \
@SIM_ENABLE_ARCH_h8300_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(patsubst %,iq2000/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(patsubst %,iq2000/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/modules.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	\
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-run.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-scache.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-trace.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cgen-utils.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	\
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/arch.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/cpu.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/decode.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/iq2000.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/sem.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/mloop.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/model.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	\
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/sim-if.o

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_SOURCES = 
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_LDADD = \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/nrun.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/libsim.a \
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/mloop.c \
@SIM_ENABLE_ARCH_iq2000_TRUE@	iq2000/stamp-mloop

@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst %,lm32/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst %,lm32/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(patsubst %,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/modules.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	\
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-run.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-scache.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-trace.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cgen-utils.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	\
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/arch.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/cpu.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/decode.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/sem.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/mloop.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/model.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	\
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/lm32.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/sim-if.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/traps.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/user.o

@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_SOURCES = 
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_LDADD = \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/nrun.o \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/libsim.a \
@SIM_ENABLE_ARCH_lm32_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_lm32_TRUE@lm32_SIM_EXTRA_HW_DEVICES = lm32cpu lm32timer lm32uart
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/mloop.c \
@SIM_ENABLE_ARCH_lm32_TRUE@	lm32/stamp-mloop

@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_m32c_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/gdb-if.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/int.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/load.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/m32c.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/mem.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/misc.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/modules.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/r8c.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/reg.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/srcdest.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/syscalls.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/trace.o

@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_SOURCES = 
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_LDADD = \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/main.o \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/libsim.a \
@SIM_ENABLE_ARCH_m32c_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_m32c_TRUE@m32c_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/opc2c$(EXEEXT) \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/m32c.c \
@SIM_ENABLE_ARCH_m32c_TRUE@	m32c/r8c.c

@SIM_ENABLE_ARCH_m32c_TRUE@m32c_opc2c_SOURCES = m32c/opc2c.c

# opc2c leaks memory, and therefore makes AddressSanitizer unhappy.  Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst %,m32r/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst %,m32r/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(patsubst %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/modules.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-run.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-scache.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-trace.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cgen-utils.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/arch.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/m32r.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cpu.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/decode.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/sem.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/model.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloop.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/m32rx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cpux.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/decodex.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/modelx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloopx.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/m32r2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/cpu2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/decode2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/model2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloop2.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	\
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/sim-if.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/traps.o

@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_SOURCES = 
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_LDADD = \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/nrun.o \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/libsim.a \
@SIM_ENABLE_ARCH_m32r_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_m32r_TRUE@m32r_SIM_EXTRA_HW_DEVICES = m32r_cache m32r_uart
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloop.c \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/stamp-mloop \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloopx.c \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/stamp-mloop-x \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/mloop2.c \
@SIM_ENABLE_ARCH_m32r_TRUE@	m32r/stamp-mloop-2

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/interp.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc11int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc12int.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/emulos.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/interrupts.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc11_sim.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(patsubst %,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(patsubst %,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(patsubst %,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/modules.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/sim-resume.o

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_SOURCES = 
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_LDADD = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/nrun.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/libsim.a \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_SIM_EXTRA_HW_DEVICES = m68hc11 m68hc11sio m68hc11eepr m68hc11tim m68hc11spi nvram
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc11int.c \
@SIM_ENABLE_ARCH_m68hc11_TRUE@	m68hc11/m68hc12int.c

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_gencode_SOURCES = m68hc11/gencode.c
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/interp.o \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(patsubst %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(patsubst %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/modules.o \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/sim-resume.o

@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_SOURCES = 
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_LDADD = \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/nrun.o \
@SIM_ENABLE_ARCH_mcore_TRUE@	mcore/libsim.a \
@SIM_ENABLE_ARCH_mcore_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/interp.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(patsubst %,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(patsubst %,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/modules.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/sim-resume.o

@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_SOURCES = 
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_LDADD = \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/nrun.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/libsim.a \
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_88) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_89) $(am__append_90)
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_SOURCES = 
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_mips_TRUE@	$(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/interp.o \
@SIM_ENABLE_ARCH_mips_TRUE@	$(mips_GEN_OBJ) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst %,mips/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst %,mips/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(patsubst %,mips/dv-%.o,$(mips_SIM_EXTRA_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/cp1.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/dsp.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/mdmx.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/modules.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/sim-main.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/sim-resume.o

@SIM_ENABLE_ARCH_mips_TRUE@EXTRA_mips_libsim_a_DEPENDENCIES = $(SIM_MIPS_MULTI_OBJ)
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_SOURCES = 
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_LDADD = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/nrun.o \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/libsim.a \
@SIM_ENABLE_ARCH_mips_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_mips_TRUE@mips_SIM_EXTRA_HW_DEVICES = tx3904cpu tx3904irc tx3904tmr tx3904sio
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_IGEN_ITABLE = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/itable.c

@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_SINGLE = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/model.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/model.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/support.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/support.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/engine.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/engine.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/irun.c

@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M16 = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_model.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_model.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_support.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16_support.c \
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M32 = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_model.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_model.c \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_support.h \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m32_support.c

@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =  \
@SIM_ENABLE_ARCH_mips_TRUE@	$(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/stamp-igen-itable \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_95) $(am__append_96) \
@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_97)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/dsp.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/dsp2.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/m16e.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/mdmx.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/micromipsdsp.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/micromips.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/mips3264r2.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/mips3264r6.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/mips3d.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/sb1.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/tx.igen \
@SIM_ENABLE_ARCH_mips_TRUE@	mips/vr.igen

@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_DC = $(srcdir)/mips/mips.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_M16_DC = $(srcdir)/mips/m16.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS32_DC = $(srcdir)/mips/micromips.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS16_DC = $(srcdir)/mips/micromips16.dc
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_SOURCES = 
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_LDADD = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/nrun.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/libsim.a \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_SIM_EXTRA_HW_DEVICES = mn103cpu mn103int mn103tim mn103ser mn103iop
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILT_SRC_FROM_IGEN = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/icache.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/idecode.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/semantics.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/model.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/model.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/support.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/support.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/itable.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/engine.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/engine.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/irun.c

@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(mn10300_BUILT_SRC_FROM_IGEN) \
@SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/stamp-igen

@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN = $(srcdir)/mn10300/mn10300.igen
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN_INC = mn10300/am33.igen mn10300/am33-2.igen
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_DC = $(srcdir)/mn10300/mn10300.dc
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_SOURCES = 
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_LDADD = \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/nrun.o \
@SIM_ENABLE_ARCH_moxie_TRUE@	moxie/libsim.a \
@SIM_ENABLE_ARCH_moxie_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_moxie_TRUE@dtbdir = $(datadir)/gdb/dtb
@SIM_ENABLE_ARCH_moxie_TRUE@dtb_DATA = moxie/moxie-gdb.dtb
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_SOURCES = 
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_LDADD = \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/nrun.o \
@SIM_ENABLE_ARCH_msp430_TRUE@	msp430/libsim.a \
@SIM_ENABLE_ARCH_msp430_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_SOURCES = 
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_LDADD = \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/nrun.o \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/libsim.a \
@SIM_ENABLE_ARCH_or1k_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_or1k_TRUE@or1kdocdir = $(docdir)/or1k
@SIM_ENABLE_ARCH_or1k_TRUE@or1kdoc_DATA = or1k/README
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/mloop.c \
@SIM_ENABLE_ARCH_or1k_TRUE@	or1k/stamp-mloop

@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_SOURCES = 
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_LDADD = \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/main.o \
@SIM_ENABLE_ARCH_ppc_TRUE@	ppc/libsim.a \
@SIM_ENABLE_ARCH_ppc_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_ppc_TRUE@ppcdocdir = $(docdir)/ppc
@SIM_ENABLE_ARCH_ppc_TRUE@ppcdoc_DATA = ppc/BUGS ppc/INSTALL ppc/README ppc/RUN
@SIM_ENABLE_ARCH_pru_TRUE@pru_run_SOURCES = 
@SIM_ENABLE_ARCH_pru_TRUE@pru_run_LDADD = \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/nrun.o \
@SIM_ENABLE_ARCH_pru_TRUE@	pru/libsim.a \
@SIM_ENABLE_ARCH_pru_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_SOURCES = 
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_LDADD = \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/nrun.o \
@SIM_ENABLE_ARCH_riscv_TRUE@	riscv/libsim.a \
@SIM_ENABLE_ARCH_riscv_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_SOURCES = 
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_LDADD = \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/main.o \
@SIM_ENABLE_ARCH_rl78_TRUE@	rl78/libsim.a \
@SIM_ENABLE_ARCH_rl78_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_rx_TRUE@rx_run_SOURCES = 
@SIM_ENABLE_ARCH_rx_TRUE@rx_run_LDADD = \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/main.o \
@SIM_ENABLE_ARCH_rx_TRUE@	rx/libsim.a \
@SIM_ENABLE_ARCH_rx_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_rx_TRUE@rxdocdir = $(docdir)/rx
@SIM_ENABLE_ARCH_rx_TRUE@rxdoc_DATA = rx/README.txt
@SIM_ENABLE_ARCH_sh_TRUE@sh_run_SOURCES = 
@SIM_ENABLE_ARCH_sh_TRUE@sh_run_LDADD = \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/nrun.o \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/libsim.a \
@SIM_ENABLE_ARCH_sh_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_sh_TRUE@sh_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_sh_TRUE@	sh/table.c

@SIM_ENABLE_ARCH_sh_TRUE@sh_gencode_SOURCES = sh/gencode.c
@SIM_ENABLE_ARCH_v850_TRUE@v850_run_SOURCES = 
@SIM_ENABLE_ARCH_v850_TRUE@v850_run_LDADD = \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/nrun.o \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/libsim.a \
@SIM_ENABLE_ARCH_v850_TRUE@	$(SIM_COMMON_LIBS)

@SIM_ENABLE_ARCH_v850_TRUE@v850_BUILT_SRC_FROM_IGEN = \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/icache.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/idecode.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/semantics.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/model.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/model.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/support.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/support.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/itable.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/engine.h \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/engine.c \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/irun.c

@SIM_ENABLE_ARCH_v850_TRUE@v850_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_v850_TRUE@	$(v850_BUILT_SRC_FROM_IGEN) \
@SIM_ENABLE_ARCH_v850_TRUE@	v850/stamp-igen

@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_INSN = $(srcdir)/v850/v850.igen
@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_DC = $(srcdir)/v850/v850.dc
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pru/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
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riscv/Makefile.sim: $(top_builddir)/config.status $(top_srcdir)/riscv/Makefile.in
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riscv/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
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example-synacor/$(am__dirstamp):
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clean: clean-recursive

clean-am: clean-checkPROGRAMS clean-generic clean-libtool \
	clean-noinstLIBRARIES clean-noinstPROGRAMS mostlyclean-am

distclean: distclean-recursive
	-rm -f $(am__CONFIG_DISTCLEAN_FILES)
	-rm -rf common/$(DEPDIR) cr16/$(DEPDIR) cris/$(DEPDIR) d10v/$(DEPDIR) erc32/$(DEPDIR) igen/$(DEPDIR) m32c/$(DEPDIR) m68hc11/$(DEPDIR) ppc/$(DEPDIR) sh/$(DEPDIR) testsuite/common/$(DEPDIR)
	-rm -f Makefile
distclean-am: clean-am distclean-DEJAGNU distclean-compile \
	distclean-generic distclean-hdr distclean-libtool \
	distclean-tags

dvi: dvi-recursive

dvi-am:

html: html-recursive

html-am:

info: info-recursive

info-am:

install-data-am: install-armdocDATA install-data-local install-dtbDATA \
	install-erc32docDATA install-frvdocDATA install-or1kdocDATA \
	install-pkgincludeHEADERS install-ppcdocDATA install-rxdocDATA

install-dvi: install-dvi-recursive

install-dvi-am:

install-exec-am: install-exec-local

install-html: install-html-recursive

install-html-am:

install-info: install-info-recursive

install-info-am:

install-man:

install-pdf: install-pdf-recursive

install-pdf-am:

install-ps: install-ps-recursive

install-ps-am:

installcheck-am:

maintainer-clean: maintainer-clean-recursive
	-rm -f $(am__CONFIG_DISTCLEAN_FILES)
	-rm -rf $(top_srcdir)/autom4te.cache
	-rm -rf common/$(DEPDIR) cr16/$(DEPDIR) cris/$(DEPDIR) d10v/$(DEPDIR) erc32/$(DEPDIR) igen/$(DEPDIR) m32c/$(DEPDIR) m68hc11/$(DEPDIR) ppc/$(DEPDIR) sh/$(DEPDIR) testsuite/common/$(DEPDIR)
	-rm -f Makefile
maintainer-clean-am: distclean-am maintainer-clean-generic

mostlyclean: mostlyclean-recursive

mostlyclean-am: mostlyclean-compile mostlyclean-generic \
	mostlyclean-libtool

pdf: pdf-recursive

pdf-am:

ps: ps-recursive

ps-am:

uninstall-am: uninstall-armdocDATA uninstall-dtbDATA \
	uninstall-erc32docDATA uninstall-frvdocDATA uninstall-local \
	uninstall-or1kdocDATA uninstall-pkgincludeHEADERS \
	uninstall-ppcdocDATA uninstall-rxdocDATA

.MAKE: $(am__recursive_targets) all check check-am install install-am \
	install-strip

.PHONY: $(am__recursive_targets) CTAGS GTAGS TAGS all all-am \
	am--refresh check check-DEJAGNU check-TESTS check-am clean \
	clean-checkPROGRAMS clean-cscope clean-generic clean-libtool \
	clean-noinstLIBRARIES clean-noinstPROGRAMS cscope \
	cscopelist-am ctags ctags-am distclean distclean-DEJAGNU \
	distclean-compile distclean-generic distclean-hdr \
	distclean-libtool distclean-tags dvi dvi-am html html-am info \
	info-am install install-am install-armdocDATA install-data \
	install-data-am install-data-local install-dtbDATA install-dvi \
	install-dvi-am install-erc32docDATA install-exec \
	install-exec-am install-exec-local install-frvdocDATA \
	install-html install-html-am install-info install-info-am \
	install-man install-or1kdocDATA install-pdf install-pdf-am \
	install-pkgincludeHEADERS install-ppcdocDATA install-ps \
	install-ps-am install-rxdocDATA install-strip installcheck \
	installcheck-am installdirs installdirs-am maintainer-clean \
	maintainer-clean-generic mostlyclean mostlyclean-compile \
	mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
	recheck tags tags-am uninstall uninstall-am \
	uninstall-armdocDATA uninstall-dtbDATA uninstall-erc32docDATA \
	uninstall-frvdocDATA uninstall-local uninstall-or1kdocDATA \
	uninstall-pkgincludeHEADERS uninstall-ppcdocDATA \
	uninstall-rxdocDATA

.PRECIOUS: Makefile

@am__include@ @am__quote@$(GNULIB_PARENT_DIR)/gnulib/Makefile.gnulib.inc@am__quote@

# Generate target constants for newlib/libgloss from its source tree.
# This file is shipped with distributions so we build in the source dir.
# Use `make nltvals' to rebuild.
.PHONY: nltvals
nltvals:
	$(srccom)/gennltvals.py --cpp "$(CPP)"

common/version.c: common/version.c-stamp ; @true
common/version.c-stamp: $(srcroot)/gdb/version.in $(srcroot)/bfd/version.h $(srcdir)/common/create-version.sh
	$(AM_V_GEN)$(SHELL) $(srcdir)/common/create-version.sh $(srcroot)/gdb $@.tmp
	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(@:-stamp=)
	$(AM_V_at)touch $@

# FIXME This is one very simple-minded way of generating the file hw-config.h.
%/hw-config.h: %/stamp-hw ; @true
%/stamp-hw: Makefile
	$(AM_V_GEN)set -e; \
	( \
	sim_hw="$(SIM_HW_DEVICES) $($(@D)_SIM_EXTRA_HW_DEVICES)" ; \
	echo "/* generated by Makefile */" ; \
	printf "extern const struct hw_descriptor dv_%s_descriptor[];\n" $$sim_hw ; \
	echo "const struct hw_descriptor * const hw_descriptors[] = {" ; \
	printf "  dv_%s_descriptor,\n" $$sim_hw ; \
	echo "  NULL," ; \
	echo "};" \
	) > $@.tmp; \
	$(SHELL) $(srcroot)/move-if-change $@.tmp $(@D)/hw-config.h; \
	touch $@
.PRECIOUS: %/stamp-hw
%/modules.c:
	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) GEN_MODULES_C_SRCS="$(GEN_MODULES_C_SRCS)" -C $(@D) $(@F)

# Alias for developers.
@SIM_ENABLE_IGEN_TRUE@igen: $(IGEN)

# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_IGEN_TRUE@igen/libigen.a: $(igen_libigen_a_OBJECTS) $(igen_libigen_a_DEPENDENCIES) $(EXTRA_igen_libigen_a_DEPENDENCIES) igen/$(am__dirstamp)
@SIM_ENABLE_IGEN_TRUE@	$(AM_V_at)-rm -f $@
@SIM_ENABLE_IGEN_TRUE@	$(AM_V_AR)$(AR_FOR_BUILD) $(ARFLAGS) $@ $(igen_libigen_a_OBJECTS) $(igen_libigen_a_LIBADD)
@SIM_ENABLE_IGEN_TRUE@	$(AM_V_at)$(RANLIB_FOR_BUILD) $@

@SIM_ENABLE_IGEN_TRUE@igen/igen$(EXEEXT): $(igen_igen_OBJECTS) $(igen_igen_DEPENDENCIES) igen/$(am__dirstamp)
@SIM_ENABLE_IGEN_TRUE@	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(igen_igen_OBJECTS) $(igen_igen_LDADD)

# igen is a build-time only tool.  Override the default rules for it.
@SIM_ENABLE_IGEN_TRUE@igen/%.o: igen/%.c
@SIM_ENABLE_IGEN_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@

# Build some of the files in standalone mode for developers of igen itself.
@SIM_ENABLE_IGEN_TRUE@igen/%-main.o: igen/%.c
@SIM_ENABLE_IGEN_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -DMAIN -c $< -o $@

site-sim-config.exp: Makefile
	$(AM_V_GEN)( \
	echo "set SIM_PRIMARY_TARGET \"$(SIM_PRIMARY_TARGET)\""; \
	echo "set builddir \"$(builddir)\""; \
	echo "set srcdir \"$(srcdir)/testsuite\""; \
	$(foreach V,$(SIM_TOOLCHAIN_VARS),echo "set $(V) \"$($(V))\"";) \
	) > $@

# Ignore dirs that only contain configuration settings.
check/./config/%.exp: ; @true
check/config/%.exp: ; @true
check/./lib/%.exp: ; @true
check/lib/%.exp: ; @true

check/%.exp:
	$(AM_V_at)mkdir -p testsuite/$*
	$(AM_V_RUNTEST)$(DO_RUNTEST) --objdir testsuite/$* --outdir testsuite/$* $*.exp

check-DEJAGNU-parallel:
	$(AM_V_at)( \
	set -- `cd $(srcdir)/testsuite && find . -name '*.exp' -printf '%P\n' | sed 's:[.]exp$$::'`; \
	$(MAKE) -k `printf 'check/%s.exp ' $$@`; \
	ret=$$?; \
	set -- `printf 'testsuite/%s/ ' $$@`; \
	$(SHELL) $(srcroot)/contrib/dg-extract-results.sh \
	  `find $$@ -maxdepth 1 -name testrun.sum 2>/dev/null | sort` > testrun.sum; \
	$(SHELL) $(srcroot)/contrib/dg-extract-results.sh -L \
	  `find $$@ -maxdepth 1 -name testrun.log 2>/dev/null | sort` > testrun.log; \
	echo; \
	$(SED) -n '/^.*===.*Summary.*===/,$$p' testrun.sum; \
	exit $$ret)

check-DEJAGNU-single:
	$(AM_V_RUNTEST)$(DO_RUNTEST)

# If running a single job, invoking runtest once is faster & has nicer output.
check-DEJAGNU: site.exp
	$(AM_V_at)(set -e; \
	EXPECT=${EXPECT} ; export EXPECT ; \
	runtest=$(RUNTEST); \
	if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
	  case "$(MAKEFLAGS)" in \
	  *-j*) $(MAKE) check-DEJAGNU-parallel;; \
	  *)    $(MAKE) check-DEJAGNU-single;; \
	  esac; \
	else \
	  echo "WARNING: could not find \`runtest'" 1>&2; :;\
	fi)

# These tests are build-time only tools.  Override the default rules for them.
testsuite/common/%.o: testsuite/common/%.c
	$(AM_V_CC)$(COMPILE_FOR_BUILD) $(testsuite_common_CPPFLAGS) -c $< -o $@

testsuite/common/alu-tst$(EXEEXT): $(testsuite_common_alu_tst_OBJECTS) $(testsuite_common_alu_tst_DEPENDENCIES) testsuite/common/$(am__dirstamp)
	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_alu_tst_OBJECTS) $(testsuite_common_alu_tst_LDADD)

testsuite/common/fpu-tst$(EXEEXT): $(testsuite_common_fpu_tst_OBJECTS) $(testsuite_common_fpu_tst_DEPENDENCIES) testsuite/common/$(am__dirstamp)
	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_fpu_tst_OBJECTS) $(testsuite_common_fpu_tst_LDADD)

testsuite/common/bits-gen$(EXEEXT): $(testsuite_common_bits_gen_OBJECTS) $(testsuite_common_bits_gen_DEPENDENCIES) testsuite/common/$(am__dirstamp)
	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_bits_gen_OBJECTS) $(testsuite_common_bits_gen_LDADD)

testsuite/common/bits32m0$(EXEEXT): $(testsuite_common_bits32m0_OBJECTS) $(testsuite_common_bits32m0_DEPENDENCIES) testsuite/common/$(am__dirstamp)
	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_bits32m0_OBJECTS) $(testsuite_common_bits32m0_LDADD)

testsuite/common/bits32m0.c: testsuite/common/bits-gen$(EXEEXT) testsuite/common/bits-tst.c
	$(AM_V_GEN)$< 32 0 big > $@.tmp
	$(AM_V_at)cat $(srcdir)/testsuite/common/bits-tst.c >> $@.tmp
	$(AM_V_at)mv $@.tmp $@

testsuite/common/bits32m31$(EXEEXT): $(testsuite_common_bits32m31_OBJECTS) $(testsuite_common_bits32m31_DEPENDENCIES) testsuite/common/$(am__dirstamp)
	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_bits32m31_OBJECTS) $(testsuite_common_bits32m31_LDADD)

testsuite/common/bits32m31.c: testsuite/common/bits-gen$(EXEEXT) testsuite/common/bits-tst.c
	$(AM_V_GEN)$< 32 31 little > $@.tmp
	$(AM_V_at)cat $(srcdir)/testsuite/common/bits-tst.c >> $@.tmp
	$(AM_V_at)mv $@.tmp $@

testsuite/common/bits64m0$(EXEEXT): $(testsuite_common_bits64m0_OBJECTS) $(testsuite_common_bits64m0_DEPENDENCIES) testsuite/common/$(am__dirstamp)
	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_bits64m0_OBJECTS) $(testsuite_common_bits64m0_LDADD)

testsuite/common/bits64m0.c: testsuite/common/bits-gen$(EXEEXT) testsuite/common/bits-tst.c
	$(AM_V_GEN)$< 64 0 big > $@.tmp
	$(AM_V_at)cat $(srcdir)/testsuite/common/bits-tst.c >> $@.tmp
	$(AM_V_at)mv $@.tmp $@

testsuite/common/bits64m63$(EXEEXT): $(testsuite_common_bits64m63_OBJECTS) $(testsuite_common_bits64m63_DEPENDENCIES) testsuite/common/$(am__dirstamp)
	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_bits64m63_OBJECTS) $(testsuite_common_bits64m63_LDADD)

testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/common/bits-tst.c
	$(AM_V_GEN)$< 64 63 little > $@.tmp
	$(AM_V_at)cat $(srcdir)/testsuite/common/bits-tst.c >> $@.tmp
	$(AM_V_at)mv $@.tmp $@
@SIM_ENABLE_ARCH_aarch64_TRUE@$(aarch64_libsim_a_OBJECTS) $(aarch64_libsim_a_LIBADD): aarch64/hw-config.h

@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64/%.o: aarch64/%.c
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64/%.o: common/%.c
@SIM_ENABLE_ARCH_aarch64_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_arm_TRUE@$(arm_libsim_a_OBJECTS) $(arm_libsim_a_LIBADD): arm/hw-config.h

@SIM_ENABLE_ARCH_arm_TRUE@arm/%.o: arm/%.c
@SIM_ENABLE_ARCH_arm_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_arm_TRUE@arm/%.o: common/%.c
@SIM_ENABLE_ARCH_arm_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_avr_TRUE@$(avr_libsim_a_OBJECTS) $(avr_libsim_a_LIBADD): avr/hw-config.h

@SIM_ENABLE_ARCH_avr_TRUE@avr/%.o: avr/%.c
@SIM_ENABLE_ARCH_avr_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_avr_TRUE@avr/%.o: common/%.c
@SIM_ENABLE_ARCH_avr_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_bfin_TRUE@$(bfin_libsim_a_OBJECTS) $(bfin_libsim_a_LIBADD): bfin/hw-config.h

@SIM_ENABLE_ARCH_bfin_TRUE@bfin/%.o: bfin/%.c
@SIM_ENABLE_ARCH_bfin_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_bfin_TRUE@bfin/%.o: common/%.c
@SIM_ENABLE_ARCH_bfin_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_bfin_TRUE@bfin/linux-fixed-code.h: @MAINT@ $(srcdir)/bfin/linux-fixed-code.s bfin/local.mk bfin/$(am__dirstamp)
@SIM_ENABLE_ARCH_bfin_TRUE@	$(AM_V_GEN)$(AS_FOR_TARGET_BFIN) $(srcdir)/bfin/linux-fixed-code.s -o bfin/linux-fixed-code.o
@SIM_ENABLE_ARCH_bfin_TRUE@	$(AM_V_at)(\
@SIM_ENABLE_ARCH_bfin_TRUE@		set -e; \
@SIM_ENABLE_ARCH_bfin_TRUE@		echo "/* DO NOT EDIT: Autogenerated from linux-fixed-code.s.  */"; \
@SIM_ENABLE_ARCH_bfin_TRUE@		echo "static const unsigned char bfin_linux_fixed_code[] ="; \
@SIM_ENABLE_ARCH_bfin_TRUE@		echo "{"; \
@SIM_ENABLE_ARCH_bfin_TRUE@		$(OBJDUMP_FOR_TARGET_BFIN) -d -z bfin/linux-fixed-code.o > $@.dis; \
@SIM_ENABLE_ARCH_bfin_TRUE@		sed -n \
@SIM_ENABLE_ARCH_bfin_TRUE@			-e 's:^[^	]*	:0x:' \
@SIM_ENABLE_ARCH_bfin_TRUE@			-e '/^0x/{s:	.*::;s: *$$:,:;s: :, 0x:g;p;}' \
@SIM_ENABLE_ARCH_bfin_TRUE@			$@.dis; \
@SIM_ENABLE_ARCH_bfin_TRUE@		rm -f $@.dis; \
@SIM_ENABLE_ARCH_bfin_TRUE@		echo "};" \
@SIM_ENABLE_ARCH_bfin_TRUE@	) > $@.tmp
@SIM_ENABLE_ARCH_bfin_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/bfin/linux-fixed-code.h
@SIM_ENABLE_ARCH_bfin_TRUE@	$(AM_V_at)touch $(srcdir)/bfin/linux-fixed-code.h
@SIM_ENABLE_ARCH_bpf_TRUE@$(bpf_libsim_a_OBJECTS) $(bpf_libsim_a_LIBADD): bpf/hw-config.h

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/%.o: bpf/%.c
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/%.o: common/%.c
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/modules.c: | $(bpf_BUILD_OUTPUTS)

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/mloop-le.c bpf/eng-le.h: bpf/stamp-mloop-le ; @true
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/stamp-mloop-le: $(srccom)/genmloop.sh bpf/mloop.in
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_bpf_TRUE@		-mono -scache -prefix bpfbf_ebpfle -cpu bpfbf \
@SIM_ENABLE_ARCH_bpf_TRUE@		-infile $(srcdir)/bpf/mloop.in \
@SIM_ENABLE_ARCH_bpf_TRUE@		-outfile-prefix bpf/ -outfile-suffix -le
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/eng-le.hin bpf/eng-le.h
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/mloop-le.cin bpf/mloop-le.c
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/mloop-be.c bpf/eng-be.h: bpf/stamp-mloop-be ; @true
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/stamp-mloop-be: $(srccom)/genmloop.sh bpf/mloop.in
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_bpf_TRUE@		-mono -scache -prefix bpfbf_ebpfbe -cpu bpfbf \
@SIM_ENABLE_ARCH_bpf_TRUE@		-infile $(srcdir)/bpf/mloop.in \
@SIM_ENABLE_ARCH_bpf_TRUE@		-outfile-prefix bpf/ -outfile-suffix -be
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/eng-be.hin bpf/eng-be.h
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/mloop-be.cin bpf/mloop-be.c
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen: bpf/cgen-arch bpf/cgen-cpu bpf/cgen-defs-le bpf/cgen-defs-be bpf/cgen-decode-le bpf/cgen-decode-be

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-arch:
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_GEN)mach=bpf cpu=bpfbf FLAGS="with-scache"; $(CGEN_GEN_ARCH)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/arch.h bpf/arch.c bpf/cpuall.h: @CGEN_MAINT@ bpf/cgen-arch

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-cpu:
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_GEN)isa=ebpfle,ebpfbe cpu=bpfbf mach=bpf FLAGS="with-multiple-isa with-scache"; $(CGEN_GEN_CPU)
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_at)rm -f $(srcdir)/bpf/model.c
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cpu.h bpf/cpu.c bpf/model.c: @CGEN_MAINT@ bpf/cgen-cpu

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-defs-le:
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_GEN)isa=ebpfle cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-le"; $(CGEN_GEN_DEFS)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/defs-le.h: @CGEN_MAINT@ bpf/cgen-defs-le

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-defs-be:
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_GEN)isa=ebpfbe cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-be"; $(CGEN_GEN_DEFS)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/defs-be.h: @CGEN_MAINT@ bpf/cgen-defs-be

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-decode-le:
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_GEN)isa=ebpfle cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-le" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_DECODE)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/sem-le.c bpf/decode-le.c bpf/decode-le.h: @CGEN_MAINT@ bpf/cgen-decode-vle

@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-decode-be:
@SIM_ENABLE_ARCH_bpf_TRUE@	$(AM_V_GEN)isa=ebpfbe cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-be" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_DECODE)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/sem-be.c bpf/decode-be.c bpf/decode-be.h: @CGEN_MAINT@ bpf/cgen-decode-be
@SIM_ENABLE_ARCH_cr16_TRUE@$(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_LIBADD): cr16/hw-config.h

@SIM_ENABLE_ARCH_cr16_TRUE@cr16/%.o: cr16/%.c
@SIM_ENABLE_ARCH_cr16_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_cr16_TRUE@cr16/%.o: common/%.c
@SIM_ENABLE_ARCH_cr16_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_cr16_TRUE@cr16/modules.c: | $(cr16_BUILD_OUTPUTS)

# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_ARCH_cr16_TRUE@cr16/gencode$(EXEEXT): $(cr16_gencode_OBJECTS) $(cr16_gencode_DEPENDENCIES) cr16/$(am__dirstamp)
@SIM_ENABLE_ARCH_cr16_TRUE@	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(cr16_gencode_OBJECTS) $(cr16_gencode_LDADD)

# gencode is a build-time only tool.  Override the default rules for it.
@SIM_ENABLE_ARCH_cr16_TRUE@cr16/gencode.o: cr16/gencode.c
@SIM_ENABLE_ARCH_cr16_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@
@SIM_ENABLE_ARCH_cr16_TRUE@cr16/cr16-opc.o: ../opcodes/cr16-opc.c
@SIM_ENABLE_ARCH_cr16_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@

@SIM_ENABLE_ARCH_cr16_TRUE@cr16/simops.h: cr16/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_cr16_TRUE@	$(AM_V_GEN)$< -h >$@

@SIM_ENABLE_ARCH_cr16_TRUE@cr16/table.c: cr16/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_cr16_TRUE@	$(AM_V_GEN)$< >$@
@SIM_ENABLE_ARCH_cris_TRUE@$(cris_libsim_a_OBJECTS) $(cris_libsim_a_LIBADD): cris/hw-config.h

@SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: cris/%.c
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: common/%.c
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_cris_TRUE@cris/modules.c: | $(cris_BUILD_OUTPUTS)

@SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv10f.c cris/engv10.h: cris/stamp-mloop-v10f ; @true
@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v10f: $(srccom)/genmloop.sh cris/mloop.in
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_cris_TRUE@		-mono -no-fast -pbb -switch semcrisv10f-switch.c \
@SIM_ENABLE_ARCH_cris_TRUE@		-cpu crisv10f \
@SIM_ENABLE_ARCH_cris_TRUE@		-infile $(srcdir)/cris/mloop.in -outfile-prefix cris/ -outfile-suffix -v10f
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/eng-v10f.hin cris/engv10.h
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/mloop-v10f.cin cris/mloopv10f.c
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv32f.c cris/engv32.h: cris/stamp-mloop-v32f ; @true
@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v32f: $(srccom)/genmloop.sh cris/mloop.in
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_cris_TRUE@		-mono -no-fast -pbb -switch semcrisv32f-switch.c \
@SIM_ENABLE_ARCH_cris_TRUE@		-cpu crisv32f \
@SIM_ENABLE_ARCH_cris_TRUE@		-infile $(srcdir)/cris/mloop.in -outfile-prefix cris/ -outfile-suffix -v32f
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/eng-v32f.hin cris/engv32.h
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/mloop-v32f.cin cris/mloopv32f.c
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen: cris/cgen-arch cris/cgen-cpu-decode-v10f cris/cgen-cpu-decode-v32f

@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-arch:
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_GEN)mach=crisv10,crisv32 FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
@SIM_ENABLE_ARCH_cris_TRUE@cris/arch.h cris/arch.c cris/cpuall.h: @CGEN_MAINT@ cris/cgen-arch

@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-cpu-decode-v10f:
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_GEN)cpu=crisv10f mach=crisv10 SUFFIX=v10 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change $(srcdir)/cris/semv10-switch.c $(srcdir)/cris/semcrisv10f-switch.c
@SIM_ENABLE_ARCH_cris_TRUE@cris/cpuv10.h cris/cpuv10.c cris/semcrisv10f-switch.c cris/modelv10.c cris/decodev10.c cris/decodev10.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v10f

@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-cpu-decode-v32f:
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_GEN)cpu=crisv32f mach=crisv32 SUFFIX=v32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_cris_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change $(srcdir)/cris/semv32-switch.c $(srcdir)/cris/semcrisv32f-switch.c
@SIM_ENABLE_ARCH_cris_TRUE@cris/cpuv32.h cris/cpuv32.c cris/semcrisv32f-switch.c cris/modelv32.c cris/decodev32.c cris/decodev32.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v32f
@SIM_ENABLE_ARCH_d10v_TRUE@$(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_LIBADD): d10v/hw-config.h

@SIM_ENABLE_ARCH_d10v_TRUE@d10v/%.o: d10v/%.c
@SIM_ENABLE_ARCH_d10v_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_d10v_TRUE@d10v/%.o: common/%.c
@SIM_ENABLE_ARCH_d10v_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_d10v_TRUE@d10v/modules.c: | $(d10v_BUILD_OUTPUTS)

# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_ARCH_d10v_TRUE@d10v/gencode$(EXEEXT): $(d10v_gencode_OBJECTS) $(d10v_gencode_DEPENDENCIES) d10v/$(am__dirstamp)
@SIM_ENABLE_ARCH_d10v_TRUE@	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(d10v_gencode_OBJECTS) $(d10v_gencode_LDADD)

# gencode is a build-time only tool.  Override the default rules for it.
@SIM_ENABLE_ARCH_d10v_TRUE@d10v/gencode.o: d10v/gencode.c
@SIM_ENABLE_ARCH_d10v_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@
@SIM_ENABLE_ARCH_d10v_TRUE@d10v/d10v-opc.o: ../opcodes/d10v-opc.c
@SIM_ENABLE_ARCH_d10v_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@

@SIM_ENABLE_ARCH_d10v_TRUE@d10v/simops.h: d10v/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_TRUE@	$(AM_V_GEN)$< -h >$@

@SIM_ENABLE_ARCH_d10v_TRUE@d10v/table.c: d10v/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_TRUE@	$(AM_V_GEN)$< >$@
@SIM_ENABLE_ARCH_erc32_TRUE@$(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_LIBADD): erc32/hw-config.h

@SIM_ENABLE_ARCH_erc32_TRUE@erc32/%.o: erc32/%.c
@SIM_ENABLE_ARCH_erc32_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_erc32_TRUE@erc32/%.o: common/%.c
@SIM_ENABLE_ARCH_erc32_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_erc32_TRUE@erc32/sis$(EXEEXT): erc32/run$(EXEEXT)
@SIM_ENABLE_ARCH_erc32_TRUE@	$(AM_V_GEN)ln $< $@ 2>/dev/null || $(LN_S) $< $@ 2>/dev/null || cp -p $< $@
@SIM_ENABLE_ARCH_erc32_TRUE@sim-%D-install-exec-local: installdirs
@SIM_ENABLE_ARCH_erc32_TRUE@	$(AM_V_at)$(MKDIR_P) $(DESTDIR)$(bindir)
@SIM_ENABLE_ARCH_erc32_TRUE@	n=`echo sis | sed '$(program_transform_name)'`; \
@SIM_ENABLE_ARCH_erc32_TRUE@	$(LIBTOOL) --mode=install $(INSTALL_PROGRAM) erc32/run$(EXEEXT) $(DESTDIR)$(bindir)/$$n$(EXEEXT)
@SIM_ENABLE_ARCH_erc32_TRUE@sim-erc32-uninstall-local:
@SIM_ENABLE_ARCH_erc32_TRUE@	rm -f $(DESTDIR)$(bindir)/sis
@SIM_ENABLE_ARCH_examples_TRUE@$(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_LIBADD): example-synacor/hw-config.h

@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/%.o: example-synacor/%.c
@SIM_ENABLE_ARCH_examples_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/%.o: common/%.c
@SIM_ENABLE_ARCH_examples_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_frv_TRUE@$(frv_libsim_a_OBJECTS) $(frv_libsim_a_LIBADD): frv/hw-config.h

@SIM_ENABLE_ARCH_frv_TRUE@frv/%.o: frv/%.c
@SIM_ENABLE_ARCH_frv_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_frv_TRUE@frv/%.o: common/%.c
@SIM_ENABLE_ARCH_frv_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_frv_TRUE@frv/modules.c: | $(frv_BUILD_OUTPUTS)

@SIM_ENABLE_ARCH_frv_TRUE@frv/mloop.c frv/eng.h: frv/stamp-mloop ; @true
@SIM_ENABLE_ARCH_frv_TRUE@frv/stamp-mloop: $(srccom)/genmloop.sh frv/mloop.in
@SIM_ENABLE_ARCH_frv_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_frv_TRUE@		-mono -scache -parallel-generic-write -parallel-only \
@SIM_ENABLE_ARCH_frv_TRUE@		-cpu frvbf \
@SIM_ENABLE_ARCH_frv_TRUE@		-infile $(srcdir)/frv/mloop.in -outfile-prefix frv/
@SIM_ENABLE_ARCH_frv_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/eng.hin frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/mloop.cin frv/mloop.c
@SIM_ENABLE_ARCH_frv_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen: frv/cgen-arch frv/cgen-cpu-decode

@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-arch:
@SIM_ENABLE_ARCH_frv_TRUE@	$(AM_V_GEN)mach=all FLAGS="with-scache"; $(CGEN_GEN_ARCH)
@SIM_ENABLE_ARCH_frv_TRUE@frv/arch.h frv/arch.c frv/cpuall.h: @CGEN_MAINT@ frv/cgen-arch

@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-cpu-decode:
@SIM_ENABLE_ARCH_frv_TRUE@	$(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_frv_TRUE@frv/cpu.h frv/sem.c frv/model.c frv/decode.c frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode
@SIM_ENABLE_ARCH_ft32_TRUE@$(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD): ft32/hw-config.h

@SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: ft32/%.c
@SIM_ENABLE_ARCH_ft32_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: common/%.c
@SIM_ENABLE_ARCH_ft32_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_h8300_TRUE@$(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_LIBADD): h8300/hw-config.h

@SIM_ENABLE_ARCH_h8300_TRUE@h8300/%.o: h8300/%.c
@SIM_ENABLE_ARCH_h8300_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_h8300_TRUE@h8300/%.o: common/%.c
@SIM_ENABLE_ARCH_h8300_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_iq2000_TRUE@$(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_LIBADD): iq2000/hw-config.h

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/%.o: iq2000/%.c
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/%.o: common/%.c
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.c: | $(iq2000_BUILD_OUTPUTS)

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mloop ; @true
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop: $(srccom)/genmloop.sh iq2000/mloop.in
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_iq2000_TRUE@		-mono -fast -pbb -switch sem-switch.c \
@SIM_ENABLE_ARCH_iq2000_TRUE@		-cpu iq2000bf \
@SIM_ENABLE_ARCH_iq2000_TRUE@		-infile $(srcdir)/iq2000/mloop.in -outfile-prefix iq2000/
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change iq2000/eng.hin iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change iq2000/mloop.cin iq2000/mloop.c
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen: iq2000/cgen-arch iq2000/cgen-cpu-decode

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-arch:
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(AM_V_GEN)mach=iq2000 FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/arch.h iq2000/arch.c iq2000/cpuall.h: @CGEN_MAINT@ iq2000/cgen-arch

@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-cpu-decode:
@SIM_ENABLE_ARCH_iq2000_TRUE@	$(AM_V_GEN)cpu=iq2000bf mach=iq2000 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cpu.h iq2000/sem.c iq2000/sem-switch.c iq2000/model.c iq2000/decode.c iq2000/decode.h: @CGEN_MAINT@ iq2000/cgen-cpu-decode
@SIM_ENABLE_ARCH_lm32_TRUE@$(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD): lm32/hw-config.h

@SIM_ENABLE_ARCH_lm32_TRUE@lm32/%.o: lm32/%.c
@SIM_ENABLE_ARCH_lm32_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_lm32_TRUE@lm32/%.o: common/%.c
@SIM_ENABLE_ARCH_lm32_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.c: | $(lm32_BUILD_OUTPUTS)

@SIM_ENABLE_ARCH_lm32_TRUE@lm32/mloop.c lm32/eng.h: lm32/stamp-mloop ; @true
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/stamp-mloop: $(srccom)/genmloop.sh lm32/mloop.in
@SIM_ENABLE_ARCH_lm32_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_lm32_TRUE@		-mono -fast -pbb -switch sem-switch.c \
@SIM_ENABLE_ARCH_lm32_TRUE@		-cpu lm32bf \
@SIM_ENABLE_ARCH_lm32_TRUE@		-infile $(srcdir)/lm32/mloop.in -outfile-prefix lm32/
@SIM_ENABLE_ARCH_lm32_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change lm32/eng.hin lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change lm32/mloop.cin lm32/mloop.c
@SIM_ENABLE_ARCH_lm32_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen: lm32/cgen-arch lm32/cgen-cpu-decode

@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-arch:
@SIM_ENABLE_ARCH_lm32_TRUE@	$(AM_V_GEN)mach=all FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/arch.h lm32/arch.c lm32/cpuall.h: @CGEN_MAINT@ lm32/cgen-arch

@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-cpu-decode:
@SIM_ENABLE_ARCH_lm32_TRUE@	$(AM_V_GEN)cpu=lm32bf mach=lm32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cpu.h lm32/sem.c lm32/sem-switch.c lm32/model.c lm32/decode.c lm32/decode.h: @CGEN_MAINT@ lm32/cgen-cpu-decode
@SIM_ENABLE_ARCH_m32c_TRUE@$(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD): m32c/hw-config.h

@SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: m32c/%.c
@SIM_ENABLE_ARCH_m32c_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: common/%.c
@SIM_ENABLE_ARCH_m32c_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.c: | $(m32c_BUILD_OUTPUTS)

# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c/opc2c$(EXEEXT): $(m32c_opc2c_OBJECTS) $(m32c_opc2c_DEPENDENCIES) m32c/$(am__dirstamp)
@SIM_ENABLE_ARCH_m32c_TRUE@	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(m32c_opc2c_OBJECTS) $(m32c_opc2c_LDADD)

# opc2c is a build-time only tool.  Override the default rules for it.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c/opc2c.o: m32c/opc2c.c
@SIM_ENABLE_ARCH_m32c_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@

@SIM_ENABLE_ARCH_m32c_TRUE@m32c/m32c.c: m32c/m32c.opc m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@	$(AM_V_GEN)$(m32c_OPC2C_RUN) -l $@.log $< > $@.tmp
@SIM_ENABLE_ARCH_m32c_TRUE@	$(AM_V_at)mv $@.tmp $@

@SIM_ENABLE_ARCH_m32c_TRUE@m32c/r8c.c: m32c/r8c.opc m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@	$(AM_V_GEN)$(m32c_OPC2C_RUN) -l $@.log $< > $@.tmp
@SIM_ENABLE_ARCH_m32c_TRUE@	$(AM_V_at)mv $@.tmp $@
@SIM_ENABLE_ARCH_m32r_TRUE@$(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_LIBADD): m32r/hw-config.h

@SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: m32r/%.c
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: common/%.c
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.c: | $(m32r_BUILD_OUTPUTS)

@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop.c m32r/eng.h: m32r/stamp-mloop ; @true
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop: $(srccom)/genmloop.sh m32r/mloop.in
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_m32r_TRUE@		-mono -fast -pbb -switch sem-switch.c \
@SIM_ENABLE_ARCH_m32r_TRUE@		-cpu m32rbf \
@SIM_ENABLE_ARCH_m32r_TRUE@		-infile $(srcdir)/m32r/mloop.in -outfile-prefix m32r/
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/eng.hin m32r/eng.h
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloop.cin m32r/mloop.c
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloopx.c m32r/engx.h: m32r/stamp-mloop ; @true
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-x: $(srccom)/genmloop.sh m32r/mloop.in
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_m32r_TRUE@		-mono -no-fast -pbb -parallel-write -switch semx-switch.c \
@SIM_ENABLE_ARCH_m32r_TRUE@		-cpu m32rxf \
@SIM_ENABLE_ARCH_m32r_TRUE@		-infile $(srcdir)/m32r/mloopx.in -outfile-prefix m32r/ -outfile-suffix x
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/engx.hin m32r/engx.h
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloopx.cin m32r/mloopx.c
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop2.c m32r/eng2.h: m32r/stamp-mloop ; @true
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-2: $(srccom)/genmloop.sh m32r/mloop.in
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_m32r_TRUE@		-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
@SIM_ENABLE_ARCH_m32r_TRUE@		-cpu m32r2f \
@SIM_ENABLE_ARCH_m32r_TRUE@		-infile $(srcdir)/m32r/mloop2.in -outfile-prefix m32r/ -outfile-suffix 2
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/eng2.hin m32r/eng2.h
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloop2.cin m32r/mloop2.c
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen: m32r/cgen-arch m32r/cgen-cpu-decode m32r/cgen-cpu-decode-x m32r/cgen-cpu-decode-2

@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-arch:
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_GEN)mach=all FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/arch.h m32r/arch.c m32r/cpuall.h: @CGEN_MAINT@ m32r/cgen-arch

@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode:
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_GEN)cpu=m32rbf mach=m32r FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpu.h m32r/sem.c m32r/sem-switch.c m32r/model.c m32r/decode.c m32r/decode.h: @CGEN_MAINT@ m32r/cgen-cpu-decode

@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-x:
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_GEN)cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpux.h m32r/semx-switch.c m32r/modelx.c m32r/decodex.c m32r/decodex.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-x

@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-2:
@SIM_ENABLE_ARCH_m32r_TRUE@	$(AM_V_GEN)cpu=m32r2f mach=m32r2 SUFFIX=2 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpu2.h m32r/sem2-switch.c m32r/model2.c m32r/decode2.c m32r/decode2.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-2
@SIM_ENABLE_ARCH_m68hc11_TRUE@$(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_LIBADD): m68hc11/hw-config.h

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/%.o: m68hc11/%.c
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/%.o: common/%.c
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.c: | $(m68hc11_BUILD_OUTPUTS)

# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/gencode$(EXEEXT): $(m68hc11_gencode_OBJECTS) $(m68hc11_gencode_DEPENDENCIES) m68hc11/$(am__dirstamp)
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(m68hc11_gencode_OBJECTS) $(m68hc11_gencode_LDADD)

# gencode is a build-time only tool.  Override the default rules for it.
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/gencode.o: m68hc11/gencode.c
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc11int.c: m68hc11/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(AM_V_GEN)$< -m6811 >$@

@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc12int.c: m68hc11/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@	$(AM_V_GEN)$< -m6812 >$@
@SIM_ENABLE_ARCH_mcore_TRUE@$(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIBADD): mcore/hw-config.h

@SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: mcore/%.c
@SIM_ENABLE_ARCH_mcore_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: common/%.c
@SIM_ENABLE_ARCH_mcore_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_microblaze_TRUE@$(microblaze_libsim_a_OBJECTS) $(microblaze_libsim_a_LIBADD): microblaze/hw-config.h

@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/%.o: microblaze/%.c
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/%.o: common/%.c
@SIM_ENABLE_ARCH_microblaze_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_mips_TRUE@$(mips_libsim_a_OBJECTS) $(mips_libsim_a_LIBADD): mips/hw-config.h

@SIM_ENABLE_ARCH_mips_TRUE@mips/%.o: mips/%.c
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_mips_TRUE@mips/%.o: common/%.c
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_mips_TRUE@mips/modules.c: | $(mips_BUILD_OUTPUTS)

@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_IGEN_ITABLE): mips/stamp-igen-itable
@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE): mips/stamp-gen-mode-single
@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16): mips/stamp-gen-mode-m16-m16
@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32): mips/stamp-gen-mode-m16-m32
@SIM_ENABLE_ARCH_mips_TRUE@$(SIM_MIPS_MULTI_SRC): mips/stamp-gen-mode-multi-igen mips/stamp-gen-mode-multi-run

@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-igen-itable: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(IGEN)
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_GEN)$(IGEN_RUN) \
@SIM_ENABLE_ARCH_mips_TRUE@		$(mips_IGEN_TRACE) \
@SIM_ENABLE_ARCH_mips_TRUE@		-I $(srcdir)/mips \
@SIM_ENABLE_ARCH_mips_TRUE@		-Werror \
@SIM_ENABLE_ARCH_mips_TRUE@		-Wnodiscard \
@SIM_ENABLE_ARCH_mips_TRUE@		-Wnowidth \
@SIM_ENABLE_ARCH_mips_TRUE@		-Wnounimplemented \
@SIM_ENABLE_ARCH_mips_TRUE@		$(SIM_MIPS_IGEN_ITABLE_FLAGS) \
@SIM_ENABLE_ARCH_mips_TRUE@		-G gen-direct-access \
@SIM_ENABLE_ARCH_mips_TRUE@		-G gen-zero-r0 \
@SIM_ENABLE_ARCH_mips_TRUE@		-i $(mips_IGEN_INSN) \
@SIM_ENABLE_ARCH_mips_TRUE@		-n itable.h    -ht mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n itable.c    -t  mips/itable.c
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-single: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_IGEN_DC) $(IGEN)
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_GEN)$(IGEN_RUN) \
@SIM_ENABLE_ARCH_mips_TRUE@		$(mips_IGEN_TRACE) \
@SIM_ENABLE_ARCH_mips_TRUE@		-I $(srcdir)/mips \
@SIM_ENABLE_ARCH_mips_TRUE@		-Werror \
@SIM_ENABLE_ARCH_mips_TRUE@		-Wnodiscard \
@SIM_ENABLE_ARCH_mips_TRUE@		$(SIM_MIPS_SINGLE_FLAGS) \
@SIM_ENABLE_ARCH_mips_TRUE@		-G gen-direct-access \
@SIM_ENABLE_ARCH_mips_TRUE@		-G gen-zero-r0 \
@SIM_ENABLE_ARCH_mips_TRUE@		-B 32 \
@SIM_ENABLE_ARCH_mips_TRUE@		-H 31 \
@SIM_ENABLE_ARCH_mips_TRUE@		-i $(mips_IGEN_INSN) \
@SIM_ENABLE_ARCH_mips_TRUE@		-o $(mips_IGEN_DC) \
@SIM_ENABLE_ARCH_mips_TRUE@		-x \
@SIM_ENABLE_ARCH_mips_TRUE@		-n icache.h    -hc mips/icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n icache.c    -c  mips/icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n semantics.h -hs mips/semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n semantics.c -s  mips/semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n idecode.h   -hd mips/idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n idecode.c   -d  mips/idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n model.h     -hm mips/model.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n model.c     -m  mips/model.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n support.h   -hf mips/support.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n support.c   -f  mips/support.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n engine.h    -he mips/engine.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n engine.c    -e  mips/engine.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n irun.c      -r  mips/irun.c
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-m16-m16: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_M16_DC) $(IGEN)
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_GEN)$(IGEN_RUN) \
@SIM_ENABLE_ARCH_mips_TRUE@		$(mips_IGEN_TRACE) \
@SIM_ENABLE_ARCH_mips_TRUE@		-I $(srcdir)/mips \
@SIM_ENABLE_ARCH_mips_TRUE@		-Werror \
@SIM_ENABLE_ARCH_mips_TRUE@		-Wnodiscard \
@SIM_ENABLE_ARCH_mips_TRUE@		$(SIM_MIPS_M16_FLAGS) \
@SIM_ENABLE_ARCH_mips_TRUE@		-G gen-direct-access \
@SIM_ENABLE_ARCH_mips_TRUE@		-G gen-zero-r0 \
@SIM_ENABLE_ARCH_mips_TRUE@		-B 16 \
@SIM_ENABLE_ARCH_mips_TRUE@		-H 15 \
@SIM_ENABLE_ARCH_mips_TRUE@		-i $(mips_IGEN_INSN) \
@SIM_ENABLE_ARCH_mips_TRUE@		-o $(mips_M16_DC) \
@SIM_ENABLE_ARCH_mips_TRUE@		-P m16_ \
@SIM_ENABLE_ARCH_mips_TRUE@		-x \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m16_icache.h    -hc mips/m16_icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m16_icache.c    -c  mips/m16_icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m16_semantics.h -hs mips/m16_semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m16_semantics.c -s  mips/m16_semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m16_idecode.h   -hd mips/m16_idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m16_idecode.c   -d  mips/m16_idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m16_model.h     -hm mips/m16_model.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m16_model.c     -m  mips/m16_model.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m16_support.h   -hf mips/m16_support.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m16_support.c   -f  mips/m16_support.c
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-m16-m32: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_IGEN_DC) $(IGEN)
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_GEN)$(IGEN_RUN) \
@SIM_ENABLE_ARCH_mips_TRUE@		$(mips_IGEN_TRACE) \
@SIM_ENABLE_ARCH_mips_TRUE@		-I $(srcdir)/mips \
@SIM_ENABLE_ARCH_mips_TRUE@		-Werror \
@SIM_ENABLE_ARCH_mips_TRUE@		-Wnodiscard \
@SIM_ENABLE_ARCH_mips_TRUE@		$(SIM_MIPS_SINGLE_FLAGS) \
@SIM_ENABLE_ARCH_mips_TRUE@		-G gen-direct-access \
@SIM_ENABLE_ARCH_mips_TRUE@		-G gen-zero-r0 \
@SIM_ENABLE_ARCH_mips_TRUE@		-B 32 \
@SIM_ENABLE_ARCH_mips_TRUE@		-H 31 \
@SIM_ENABLE_ARCH_mips_TRUE@		-i $(mips_IGEN_INSN) \
@SIM_ENABLE_ARCH_mips_TRUE@		-o $(mips_IGEN_DC) \
@SIM_ENABLE_ARCH_mips_TRUE@		-P m32_ \
@SIM_ENABLE_ARCH_mips_TRUE@		-x \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m32_icache.h    -hc mips/m32_icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m32_icache.c    -c  mips/m32_icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m32_semantics.h -hs mips/m32_semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m32_semantics.c -s  mips/m32_semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m32_idecode.h   -hd mips/m32_idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m32_idecode.c   -d  mips/m32_idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m32_model.h     -hm mips/m32_model.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m32_model.c     -m  mips/m32_model.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m32_support.h   -hf mips/m32_support.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n m32_support.c   -f  mips/m32_support.c
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-multi-igen: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_IGEN_DC) $(mips_M16_DC) $(mips_MICROMIPS32_DC) $(mips_MICROMIPS16_DC) $(IGEN)
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_GEN)\
@SIM_ENABLE_ARCH_mips_TRUE@	for t in $(SIM_MIPS_MULTI_IGEN_CONFIGS); do \
@SIM_ENABLE_ARCH_mips_TRUE@	  p=`echo $${t} | sed -e 's/:.*//'` ; \
@SIM_ENABLE_ARCH_mips_TRUE@	  m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
@SIM_ENABLE_ARCH_mips_TRUE@	  f=`echo $${t} | sed -e 's/.*://'` ; \
@SIM_ENABLE_ARCH_mips_TRUE@	  case $${p} in \
@SIM_ENABLE_ARCH_mips_TRUE@	    micromips16*) \
@SIM_ENABLE_ARCH_mips_TRUE@	      e="-B 16 -H 15 -o $(mips_MICROMIPS16_DC) -F 16" ;; \
@SIM_ENABLE_ARCH_mips_TRUE@	    micromips32* | micromips64*) \
@SIM_ENABLE_ARCH_mips_TRUE@	      e="-B 32 -H 31 -o $(mips_MICROMIPS32_DC) -F $${f}" ;; \
@SIM_ENABLE_ARCH_mips_TRUE@	    micromips_m32*) \
@SIM_ENABLE_ARCH_mips_TRUE@	      e="-B 32 -H 31 -o $(mips_IGEN_DC) -F $${f}"; \
@SIM_ENABLE_ARCH_mips_TRUE@	      m="mips32r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \
@SIM_ENABLE_ARCH_mips_TRUE@	    micromips_m64*) \
@SIM_ENABLE_ARCH_mips_TRUE@	      e="-B 32 -H 31 -o $(mips_IGEN_DC) -F $${f}"; \
@SIM_ENABLE_ARCH_mips_TRUE@	      m="mips64r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \
@SIM_ENABLE_ARCH_mips_TRUE@	    m16*) \
@SIM_ENABLE_ARCH_mips_TRUE@	      e="-B 16 -H 15 -o $(mips_M16_DC) -F 16" ;; \
@SIM_ENABLE_ARCH_mips_TRUE@	    *) \
@SIM_ENABLE_ARCH_mips_TRUE@	      e="-B 32 -H 31 -o $(mips_IGEN_DC) -F $${f}" ;; \
@SIM_ENABLE_ARCH_mips_TRUE@	  esac; \
@SIM_ENABLE_ARCH_mips_TRUE@	  $(IGEN_RUN) \
@SIM_ENABLE_ARCH_mips_TRUE@		$(mips_IGEN_TRACE) \
@SIM_ENABLE_ARCH_mips_TRUE@		$${e} \
@SIM_ENABLE_ARCH_mips_TRUE@		-I $(srcdir)/mips \
@SIM_ENABLE_ARCH_mips_TRUE@		-Werror \
@SIM_ENABLE_ARCH_mips_TRUE@		-Wnodiscard \
@SIM_ENABLE_ARCH_mips_TRUE@		-M $${m} \
@SIM_ENABLE_ARCH_mips_TRUE@		-G gen-direct-access \
@SIM_ENABLE_ARCH_mips_TRUE@		-G gen-zero-r0 \
@SIM_ENABLE_ARCH_mips_TRUE@		-i $(mips_IGEN_INSN) \
@SIM_ENABLE_ARCH_mips_TRUE@		-P $${p}_ \
@SIM_ENABLE_ARCH_mips_TRUE@		-x \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_icache.h    -hc mips/$${p}_icache.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_icache.c    -c  mips/$${p}_icache.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_semantics.h -hs mips/$${p}_semantics.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_semantics.c -s  mips/$${p}_semantics.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_idecode.h   -hd mips/$${p}_idecode.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_idecode.c   -d  mips/$${p}_idecode.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_model.h     -hm mips/$${p}_model.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_model.c     -m  mips/$${p}_model.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_support.h   -hf mips/$${p}_support.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_support.c   -f  mips/$${p}_support.c \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_engine.h    -he mips/$${p}_engine.h \
@SIM_ENABLE_ARCH_mips_TRUE@		-n $${p}_engine.c    -e  mips/$${p}_engine.c \
@SIM_ENABLE_ARCH_mips_TRUE@	    || exit; \
@SIM_ENABLE_ARCH_mips_TRUE@	done
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-multi-run: mips/m16run.c mips/micromipsrun.c
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_GEN)\
@SIM_ENABLE_ARCH_mips_TRUE@	for t in $(SIM_MIPS_MULTI_IGEN_CONFIGS); do \
@SIM_ENABLE_ARCH_mips_TRUE@	  case $${t} in \
@SIM_ENABLE_ARCH_mips_TRUE@	    m16*) \
@SIM_ENABLE_ARCH_mips_TRUE@	      m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
@SIM_ENABLE_ARCH_mips_TRUE@	      o=mips/m16$${m}_run.c; \
@SIM_ENABLE_ARCH_mips_TRUE@	      sed < $(srcdir)/mips/m16run.c > $$o.tmp \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/^sim_/m16$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "/include/s/sim-engine/m16$${m}_engine/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/m16_/m16$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/m32_/m32$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    || exit 1; \
@SIM_ENABLE_ARCH_mips_TRUE@	      $(SHELL) $(srcroot)/move-if-change $$o.tmp $$o; \
@SIM_ENABLE_ARCH_mips_TRUE@	      ;;\
@SIM_ENABLE_ARCH_mips_TRUE@	    micromips32*) \
@SIM_ENABLE_ARCH_mips_TRUE@	      m=`echo $${t} | sed -e 's/^micromips32//' -e 's/:.*//'`; \
@SIM_ENABLE_ARCH_mips_TRUE@	      o=mips/micromips$${m}_run.c; \
@SIM_ENABLE_ARCH_mips_TRUE@	      sed < $(srcdir)/mips/micromipsrun.c > $$o.tmp \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/^sim_/micromips32$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "/include/s/sim-engine/micromips32$${m}_engine/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/micromips16_/micromips16$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/micromips32_/micromips32$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/m32_/m32$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    || exit 1; \
@SIM_ENABLE_ARCH_mips_TRUE@	      $(SHELL) $(srcroot)/move-if-change $$o.tmp $$o; \
@SIM_ENABLE_ARCH_mips_TRUE@	      ;;\
@SIM_ENABLE_ARCH_mips_TRUE@	    micromips64*) \
@SIM_ENABLE_ARCH_mips_TRUE@	      m=`echo $${t} | sed -e 's/^micromips64//' -e 's/:.*//'`; \
@SIM_ENABLE_ARCH_mips_TRUE@	      o=mips/micromips$${m}_run.c; \
@SIM_ENABLE_ARCH_mips_TRUE@	      sed < $(srcdir)/mips/micromipsrun.c > $$o.tmp \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/^sim_/micromips64$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "/include/s/sim-engine/micromips64$${m}_engine/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/micromips16_/micromips16$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/micromips32_/micromips64$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    -e "s/m32_/m64$${m}_/" \
@SIM_ENABLE_ARCH_mips_TRUE@		    || exit 1; \
@SIM_ENABLE_ARCH_mips_TRUE@	      $(SHELL) $(srcroot)/move-if-change $$o.tmp $$o; \
@SIM_ENABLE_ARCH_mips_TRUE@	      ;;\
@SIM_ENABLE_ARCH_mips_TRUE@	  esac \
@SIM_ENABLE_ARCH_mips_TRUE@	done
@SIM_ENABLE_ARCH_mips_TRUE@	$(AM_V_at)touch $@
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/modules.c: | $(mn10300_BUILD_OUTPUTS)

@SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_BUILT_SRC_FROM_IGEN): mn10300/stamp-igen
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/stamp-igen: $(mn10300_IGEN_INSN) $(mn10300_IGEN_INSN_INC) $(mn10300_IGEN_DC) $(IGEN)
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(AM_V_GEN)$(IGEN_RUN) \
@SIM_ENABLE_ARCH_mn10300_TRUE@		$(mn10300_IGEN_TRACE) \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-G gen-direct-access \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-M mn10300,am33 -G gen-multi-sim=am33 \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-M am33_2 \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-I $(srcdir)/mn10300 \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-i $(mn10300_IGEN_INSN) \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-o $(mn10300_IGEN_DC) \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-x \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n icache.h    -hc mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n icache.c    -c  mn10300/icache.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n semantics.h -hs mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n semantics.c -s  mn10300/semantics.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n idecode.h   -hd mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n idecode.c   -d  mn10300/idecode.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n model.h     -hm mn10300/model.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n model.c     -m  mn10300/model.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n support.h   -hf mn10300/support.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n support.c   -f  mn10300/support.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n itable.h    -ht mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n itable.c    -t  mn10300/itable.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n engine.h    -he mn10300/engine.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n engine.c    -e  mn10300/engine.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@		-n irun.c      -r  mn10300/irun.c
@SIM_ENABLE_ARCH_mn10300_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_moxie_TRUE@moxie/moxie-gdb.dtb: @MAINT@ moxie/moxie-gdb.dts moxie/$(am__dirstamp)
@SIM_ENABLE_ARCH_moxie_TRUE@	$(AM_V_GEN) \
@SIM_ENABLE_ARCH_moxie_TRUE@	if test "x$(DTC)" != x; then \
@SIM_ENABLE_ARCH_moxie_TRUE@	  $(DTC) -O dtb -o $@.tmp ${srcdir}/moxie/moxie-gdb.dts || exit 1; \
@SIM_ENABLE_ARCH_moxie_TRUE@	  $(SHELL) $(srcroot)/move-if-change $@.tmp ${srcdir}/moxie/moxie-gdb.dtb || exit 1; \
@SIM_ENABLE_ARCH_moxie_TRUE@	  touch ${srcdir}/moxie/moxie-gdb.dtb; \
@SIM_ENABLE_ARCH_moxie_TRUE@	else \
@SIM_ENABLE_ARCH_moxie_TRUE@	  echo "Could not update the moxie-gdb.dtb file because the device "; \
@SIM_ENABLE_ARCH_moxie_TRUE@	  echo "tree compiler tool (dtc) is missing.  Install the tool to "; \
@SIM_ENABLE_ARCH_moxie_TRUE@	  echo "update the device tree blob."; \
@SIM_ENABLE_ARCH_moxie_TRUE@	fi
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.c: | $(or1k_BUILD_OUTPUTS)

@SIM_ENABLE_ARCH_or1k_TRUE@or1k/mloop.c or1k/eng.h: or1k/stamp-mloop ; @true
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/stamp-mloop: $(srccom)/genmloop.sh or1k/mloop.in
@SIM_ENABLE_ARCH_or1k_TRUE@	$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
@SIM_ENABLE_ARCH_or1k_TRUE@		-mono -fast -pbb -switch sem-switch.c \
@SIM_ENABLE_ARCH_or1k_TRUE@		-cpu or1k32bf \
@SIM_ENABLE_ARCH_or1k_TRUE@		-infile $(srcdir)/or1k/mloop.in -outfile-prefix or1k/
@SIM_ENABLE_ARCH_or1k_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change or1k/eng.hin or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change or1k/mloop.cin or1k/mloop.c
@SIM_ENABLE_ARCH_or1k_TRUE@	$(AM_V_at)touch $@

@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen: or1k/cgen-arch or1k/cgen-cpu-decode

@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen-arch:
@SIM_ENABLE_ARCH_or1k_TRUE@	$(AM_V_GEN)mach=or32,or32nd FLAGS="with-scache"; $(CGEN_GEN_ARCH)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/arch.h or1k/arch.c or1k/cpuall.h: @CGEN_MAINT@ or1k/cgen-arch

@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen-cpu-decode:
@SIM_ENABLE_ARCH_or1k_TRUE@	$(AM_V_GEN)cpu=or1k32bf mach=or32,or32nd FLAGS="with-scache" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cpu.h or1k/cpu.c or1k/model.c or1k/sem.c or1k/sem-switch.c or1k/decode.c or1k/decode.h: @CGEN_MAINT@ or1k/cgen-cpu-decode

@SIM_ENABLE_ARCH_ppc_TRUE@ppc/psim$(EXEEXT): ppc/run$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@	$(AM_V_GEN)ln $< $@ 2>/dev/null || $(LN_S) $< $@ 2>/dev/null || cp -p $< $@

@SIM_ENABLE_ARCH_ppc_TRUE@ppc/%.o: ppc/%.c | ppc/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
@SIM_ENABLE_ARCH_ppc_TRUE@	$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_ppc_TRUE@ppc/spreg.c: @MAINT@ ppc/ppc-spr-table ppc/spreg-gen.py ppc/$(am__dirstamp)
@SIM_ENABLE_ARCH_ppc_TRUE@	$(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --source $@.tmp
@SIM_ENABLE_ARCH_ppc_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/ppc/spreg.c
@SIM_ENABLE_ARCH_ppc_TRUE@	$(AM_V_at)touch $(srcdir)/ppc/spreg.c

@SIM_ENABLE_ARCH_ppc_TRUE@ppc/spreg.h: @MAINT@ ppc/ppc-spr-table ppc/spreg-gen.py ppc/$(am__dirstamp)
@SIM_ENABLE_ARCH_ppc_TRUE@	$(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --header $@.tmp
@SIM_ENABLE_ARCH_ppc_TRUE@	$(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/ppc/spreg.h
@SIM_ENABLE_ARCH_ppc_TRUE@	$(AM_V_at)touch $(srcdir)/ppc/spreg.h

@SIM_ENABLE_ARCH_rl78_TRUE@rl78/%.o: rl78/%.c | rl78/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
@SIM_ENABLE_ARCH_rl78_TRUE@	$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

@SIM_ENABLE_ARCH_rx_TRUE@rx/%.o: rx/%.c | rx/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
@SIM_ENABLE_ARCH_rx_TRUE@	$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_sh_TRUE@sh/modules.c: | $(sh_BUILD_OUTPUTS)

# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_ARCH_sh_TRUE@sh/gencode$(EXEEXT): $(sh_gencode_OBJECTS) $(sh_gencode_DEPENDENCIES) sh/$(am__dirstamp)
@SIM_ENABLE_ARCH_sh_TRUE@	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(sh_gencode_OBJECTS) $(sh_gencode_LDADD)

# gencode is a build-time only tool.  Override the default rules for it.
@SIM_ENABLE_ARCH_sh_TRUE@sh/gencode.o: sh/gencode.c
@SIM_ENABLE_ARCH_sh_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@

@SIM_ENABLE_ARCH_sh_TRUE@sh/code.c: sh/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_sh_TRUE@	$(AM_V_GEN)$< -x >$@

@SIM_ENABLE_ARCH_sh_TRUE@sh/ppi.c: sh/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_sh_TRUE@	$(AM_V_GEN)$< -p >$@

@SIM_ENABLE_ARCH_sh_TRUE@sh/table.c: sh/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_sh_TRUE@	$(AM_V_GEN)$< -s >$@
@SIM_ENABLE_ARCH_v850_TRUE@v850/modules.c: | $(v850_BUILD_OUTPUTS)

@SIM_ENABLE_ARCH_v850_TRUE@$(v850_BUILT_SRC_FROM_IGEN): v850/stamp-igen
@SIM_ENABLE_ARCH_v850_TRUE@v850/stamp-igen: $(v850_IGEN_INSN) $(v850_IGEN_DC) $(IGEN)
@SIM_ENABLE_ARCH_v850_TRUE@	$(AM_V_GEN)$(IGEN_RUN) \
@SIM_ENABLE_ARCH_v850_TRUE@		$(v850_IGEN_TRACE) \
@SIM_ENABLE_ARCH_v850_TRUE@		-G gen-direct-access \
@SIM_ENABLE_ARCH_v850_TRUE@		-G gen-zero-r0 \
@SIM_ENABLE_ARCH_v850_TRUE@		-i $(v850_IGEN_INSN) \
@SIM_ENABLE_ARCH_v850_TRUE@		-o $(v850_IGEN_DC) \
@SIM_ENABLE_ARCH_v850_TRUE@		-x \
@SIM_ENABLE_ARCH_v850_TRUE@		-n icache.h    -hc v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@		-n icache.c    -c  v850/icache.c \
@SIM_ENABLE_ARCH_v850_TRUE@		-n semantics.h -hs v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@		-n semantics.c -s  v850/semantics.c \
@SIM_ENABLE_ARCH_v850_TRUE@		-n idecode.h   -hd v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@		-n idecode.c   -d  v850/idecode.c \
@SIM_ENABLE_ARCH_v850_TRUE@		-n model.h     -hm v850/model.h \
@SIM_ENABLE_ARCH_v850_TRUE@		-n model.c     -m  v850/model.c \
@SIM_ENABLE_ARCH_v850_TRUE@		-n support.h   -hf v850/support.h \
@SIM_ENABLE_ARCH_v850_TRUE@		-n support.c   -f  v850/support.c \
@SIM_ENABLE_ARCH_v850_TRUE@		-n itable.h    -ht v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@		-n itable.c    -t  v850/itable.c \
@SIM_ENABLE_ARCH_v850_TRUE@		-n engine.h    -he v850/engine.h \
@SIM_ENABLE_ARCH_v850_TRUE@		-n engine.c    -e  v850/engine.c \
@SIM_ENABLE_ARCH_v850_TRUE@		-n irun.c      -r  v850/irun.c
@SIM_ENABLE_ARCH_v850_TRUE@	$(AM_V_at)touch $@

%/libsim.a: | $(SIM_ALL_RECURSIVE_DEPS)
	$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

%/nrun.o: common/nrun.c | %/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
	$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)

all-recursive: $(SIM_ALL_RECURSIVE_DEPS)

install-data-local: installdirs $(SIM_INSTALL_DATA_LOCAL_DEPS)
	$(AM_V_at)$(MKDIR_P) $(DESTDIR)$(libdir)
	lib=`echo sim | sed '$(program_transform_name)'`; \
	for d in $(SIM_ENABLED_ARCHES); do \
		n="$$lib"; \
		[ "$(SIM_PRIMARY_TARGET)" = "$$d" ] || n="$$n-$$d"; \
		n="lib$$n.a"; \
		$(INSTALL_DATA) $$d/libsim.a $(DESTDIR)$(libdir)/$$n || exit 1; \
	done

install-exec-local: installdirs $(SIM_INSTALL_EXEC_LOCAL_DEPS)
	$(AM_V_at)$(MKDIR_P) $(DESTDIR)$(bindir)
	run=`echo run | sed '$(program_transform_name)'`; \
	for d in $(SIM_ENABLED_ARCHES); do \
		n="$$run"; \
		[ "$(SIM_PRIMARY_TARGET)" = "$$d" ] || n="$$n-$$d"; \
		$(LIBTOOL) --mode=install \
			$(INSTALL_PROGRAM) $$d/run$(EXEEXT) $(DESTDIR)$(bindir)/$$n$(EXEEXT) || exit 1; \
	done

uninstall-local: $(SIM_UNINSTALL_LOCAL_DEPS)
	rm -f $(DESTDIR)$(bindir)/run $(DESTDIR)$(libdir)/libsim.a
	for d in $(SIM_ENABLED_ARCHES); do \
		rm -f $(DESTDIR)$(bindir)/run-$$d $(DESTDIR)$(libdir)/libsim-$$d.a; \
	done

# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT: