projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 05b3d79d JW |
1 | 2017-01-17 Jim Wilson <jim.wilson@linaro.org> |
| 2 | ||
| 3 | * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of | |
| 4 | aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In | |
| 5 | case 3, call HALT_UNALLOC unconditionally. | |
| 6 | (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to | |
| 7 | i + 2. Delete if on bias, change index to i + bias * X. | |
| 8 | ||
| a4fb5981 JW |
9 | 2017-01-09 Jim Wilson <jim.wilson@linaro.org> |
| 10 | ||
| 11 | * simulator.c (do_vec_UZP): Rewrite. | |
| 12 | ||
| c0386d4d JW |
13 | 2017-01-04 Jim Wilson <jim.wilson@linaro.org> |
| 14 | ||
| 15 | * cpustate.c: Include math.h. | |
| 16 | (aarch64_set_FP_float): Use signbit to check for signed zero. | |
| 17 | (aarch64_set_FP_double): Likewise. | |
| 18 | * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. | |
| 19 | (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth | |
| 20 | args same size as third arg. | |
| 21 | (fmaxnm): Use isnan instead of fpclassify. | |
| 22 | (fminnm, dmaxnm, dminnm): Likewise. | |
| 23 | (do_vec_MLS): Reverse order of subtraction operands. | |
| 24 | (dexSimpleFPCondSelect): Call aarch64_get_FP_double or | |
| 25 | aarch64_get_FP_float to get source register contents. | |
| 26 | (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, | |
| 27 | DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, | |
| 28 | DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. | |
| 29 | (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in | |
| 30 | raise_exception calls. | |
| 31 | ||
| 87903eaf JW |
32 | 2016-12-21 Jim Wilson <jim.wilson@linaro.org> |
| 33 | ||
| 34 | * simulator.c (set_flags_for_float_compare): Add code to handle Inf. | |
| 35 | Add comment to document NaN issue. | |
| 36 | (set_flags_for_double_compare): Likewise. | |
| 37 | ||
| 963201cf JW |
38 | 2016-12-13 Jim Wilson <jim.wilson@linaro.org> |
| 39 | ||
| 40 | * simulator.c (NEG, POS): Move before set_flags_for_add64. | |
| 41 | (set_flags_for_add64): Replace with a modified copy of | |
| 42 | set_flags_for_sub64. | |
| 43 | ||
| 668650d5 JW |
44 | 2016-12-03 Jim Wilson <jim.wilson@linaro.org> |
| 45 | ||
| 46 | * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. | |
| 47 | (dexTestBranchImmediate): Shift high bit of pos by 5 not 4. | |
| 48 | ||
| 88ddd4a1 JW |
49 | 2016-12-01 Jim Wilson <jim.wilson@linaro.org> |
| 50 | ||
| 88256e71 | 51 | * simulator.c (fsturs): Switch use of rn and st variables. |
| 88ddd4a1 JW |
52 | (fsturd, fsturq): Likewise |
| 53 | ||
| 5357150c MF |
54 | 2016-08-15 Mike Frysinger <vapier@gentoo.org> |
| 55 | ||
| 56 | * interp.c: Include bfd.h. | |
| 57 | (symcount, symtab, aarch64_get_sym_value): Delete. | |
| 58 | (remove_useless_symbols): Change count type to long. | |
| 59 | (aarch64_get_func): Add SIM_DESC to arg list. Add symcount | |
| 60 | and symtab local variables. | |
| 61 | (sim_create_inferior): Delete storage. Replace symbol code | |
| 62 | with a call to trace_load_symbols. | |
| 63 | * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h | |
| 64 | includes. | |
| 65 | (aarch64_get_heap_start): Change aarch64_get_sym_value to | |
| 66 | trace_sym_value. | |
| 67 | * memory.h: Delete bfd.h include. | |
| 68 | (mem_add_blk): Delete unused prototype. | |
| 69 | * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func. | |
| 70 | * simulator.c (aarch64_get_func): Add SIM_DESC to arg list. | |
| 71 | (aarch64_get_sym_value): Delete. | |
| 72 | ||
| b14bdb3b NC |
73 | 2016-08-12 Nick Clifton <nickc@redhat.com> |
| 74 | ||
| 75 | * simulator.c (aarch64_step): Revert pervious delta. | |
| 76 | (aarch64_run): Call sim_events_tick after each | |
| 77 | instruction is simulated, and if necessary call | |
| 78 | sim_events_process. | |
| 79 | * simulator.h: Revert previous delta. | |
| 80 | ||
| 6a277579 NC |
81 | 2016-08-11 Nick Clifton <nickc@redhat.com> |
| 82 | ||
| 83 | * interp.c (sim_create_inferior): Allow for being called with a | |
| 84 | NULL abfd parameter. If a bfd is provided, initialise the sim | |
| 85 | with that start address. | |
| 86 | * simulator.c (HALT_NYI): Just print out the numeric value of the | |
| 87 | instruction when not tracing. | |
| b14bdb3b NC |
88 | (aarch64_step): Change from static to global. |
| 89 | * simulator.h: Add a prototype for aarch64_step(). | |
| 6a277579 | 90 | |
| 293acfae AM |
91 | 2016-07-27 Alan Modra <amodra@gmail.com> |
| 92 | ||
| 93 | * memory.c: Don't include libbfd.h. | |
| 94 | ||
| 0f118bc7 NC |
95 | 2016-07-21 Nick Clifton <nickc@redhat.com> |
| 96 | ||
| 0c66ea4c | 97 | * simulator.c (fsqrts): Use sqrtf rather than sqrt. |
| 0f118bc7 | 98 | |
| c7be4414 JW |
99 | 2016-06-30 Jim Wilson <jim.wilson@linaro.org> |
| 100 | ||
| 101 | * cpustate.h: Include config.h. | |
| 102 | (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code | |
| 103 | use anonymous structs to align members. | |
| 104 | * simulator.c (aarch64_step): Use sim_core_read_buffer and | |
| 105 | endian_le2h_4 to read instruction from pc. | |
| 106 | ||
| fd7ed446 NC |
107 | 2016-05-06 Nick Clifton <nickc@redhat.com> |
| 108 | ||
| 109 | * simulator.c (do_FMLA_by_element): New function. | |
| 110 | (do_vec_op2): Call it. | |
| 111 | ||
| 2cdad34c NC |
112 | 2016-04-27 Nick Clifton <nickc@redhat.com> |
| 113 | ||
| 114 | * simulator.c: Add TRACE_DECODE statements to all emulation | |
| 115 | functions. | |
| 116 | ||
| 7517e550 NC |
117 | 2016-03-30 Nick Clifton <nickc@redhat.com> |
| 118 | ||
| 119 | * cpustate.c (aarch64_set_reg_s32): New function. | |
| 120 | (aarch64_set_reg_u32): New function. | |
| 121 | (aarch64_get_FP_half): Place half precision value into the correct | |
| 122 | slot of the union. | |
| 123 | (aarch64_set_FP_half): Likewise. | |
| 124 | * cpustate.h: Add prototypes for aarch64_set_reg_s32 and | |
| 125 | aarch64_set_reg_u32. | |
| 126 | * memory.c (FETCH_FUNC): Cast the read value to the access type | |
| 127 | before converting it to the return type. Rename to FETCH_FUNC64. | |
| 128 | (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit | |
| 129 | accesses. Use for 32-bit memory access functions. | |
| 130 | * simulator.c (ldrsb_wb): Use sign extension not zero extension. | |
| 131 | (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. | |
| 132 | (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. | |
| 133 | (ldrsh_scale_ext, ldrsw_abs): Likewise. | |
| 134 | (ldrh32_abs): Store 32 bit value not 64-bits. | |
| 135 | (ldrh32_wb, ldrh32_scale_ext): Likewise. | |
| 136 | (do_vec_MOV_immediate): Fix computation of val. | |
| 137 | (do_vec_MVNI): Likewise. | |
| 138 | (DO_VEC_WIDENING_MUL): New macro. | |
| 139 | (do_vec_mull): Use new macro. | |
| 140 | (do_vec_mul): Use new macro. | |
| 141 | (do_vec_MLA): Read values before writing. | |
| 142 | (do_vec_xtl): Likewise. | |
| 143 | (do_vec_SSHL): Select correct shift value. | |
| 144 | (do_vec_USHL): Likewise. | |
| 145 | (do_scalar_UCVTF): New function. | |
| 146 | (do_scalar_vec): Call new function. | |
| 147 | (store_pair_u64): Treat reads of SP as reads of XZR. | |
| 148 | ||
| ef0d8ffc NC |
149 | 2016-03-29 Nick Clifton <nickc@redhat.com> |
| 150 | ||
| 151 | * cpustate.c: Remove space after asterisk in function parameters. | |
| 152 | * decode.h (greg): Delete unused function. | |
| 153 | (vreg, shift, extension, scaling, writeback, condcode): Likewise. | |
| 154 | * simulator.c: Use INSTR macro in more places. | |
| 155 | (HALT_NYI): Use sim_io_eprintf in place of fprintf. | |
| 156 | Remove extraneous whitespace. | |
| 157 | ||
| 5ab6d79e NC |
158 | 2016-03-23 Nick Clifton <nickc@redhat.com> |
| 159 | ||
| 160 | * cpustate.c (aarch64_get_FP_half): New function. Read a vector | |
| 161 | register as a half precision floating point number. | |
| 162 | (aarch64_set_FP_half): New function. Similar, but for setting | |
| 163 | a half precision register. | |
| 164 | (aarch64_get_thread_id): New function. Returns the value of the | |
| 165 | CPU's TPIDR register. | |
| 166 | (aarch64_get_FPCR): New function. Returns the value of the CPU's | |
| 167 | floating point control register. | |
| 168 | (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR | |
| 169 | register. | |
| 170 | * cpustate.h: Add prototypes for new functions. | |
| 171 | * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. | |
| 172 | * memory.c: Use unaligned core access functions for all memory | |
| 173 | reads and writes. | |
| 174 | * simulator.c (HALT_NYI): Generate an error message if tracing | |
| 175 | will not tell the user why the simulator is halting. | |
| 176 | (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. | |
| 177 | (INSTR): New time-saver macro. | |
| 178 | (fldrb_abs): New function. Loads an 8-bit value using a scaled | |
| 179 | offset. | |
| 180 | (fldrh_abs): New function. Likewise for 16-bit values. | |
| 181 | (do_vec_SSHL): Allow for negative shift values. | |
| 182 | (do_vec_USHL): Likewise. | |
| 183 | (do_vec_SHL): Correct computation of shift amount. | |
| 184 | (do_vec_SSHR_USHR): Correct decision of signed vs unsigned | |
| 185 | shifts and computation of shift value. | |
| 186 | (clz): New function. Counts leading zero bits. | |
| 187 | (do_vec_CLZ): New function. Implements CLZ (vector). | |
| 188 | (do_vec_MOV_element): Call do_vec_CLZ. | |
| 189 | (dexSimpleFPCondCompare): Implement. | |
| 190 | (do_FCVT_half_to_single): New function. Implements one of the | |
| 191 | FCVT operations. | |
| 192 | (do_FCVT_half_to_double): New function. Likewise. | |
| 193 | (do_FCVT_single_to_half): New function. Likewise. | |
| 194 | (do_FCVT_double_to_half): New function. Likewise. | |
| 195 | (dexSimpleFPDataProc1Source): Call new FCVT functions. | |
| 196 | (do_scalar_SHL): Handle negative shifts. | |
| 197 | (do_scalar_shift): Handle SSHR. | |
| 198 | (do_scalar_USHL): New function. | |
| 199 | (do_double_add): Simplify to just performing a double precision | |
| 200 | add operation. Move remaining code into... | |
| 201 | (do_scalar_vec): ... New function. | |
| 202 | (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs | |
| 203 | functions. | |
| 204 | (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR | |
| 205 | registers. | |
| 206 | (system_set): New function. | |
| 207 | (do_MSR_immediate): New function. Stub for now. | |
| 208 | (do_MSR_reg): New function. Likewise. Partially implements MSR | |
| 209 | instruction. | |
| 210 | (do_SYS): New function. Stub for now, | |
| 211 | (dexSystem): Call new functions. | |
| 212 | ||
| e101a78b NC |
213 | 2016-03-18 Nick Clifton <nickc@redhat.com> |
| 214 | ||
| 215 | * cpustate.c: Remove spurious spaces from TRACE strings. | |
| 216 | Print hex equivalents of floats and doubles. | |
| 217 | Check element number against array size when accessing vector | |
| 218 | registers. | |
| 4c0ca98e NC |
219 | (GET_VEC_ELEMENT): Fix off by one error checking for an invalid |
| 220 | element index. | |
| 221 | (SET_VEC_ELEMENT): Likewise. | |
| 87bba7a5 | 222 | (GET_VEC_ELEMENT): And fix thinko using macro arguments. |
| 4c0ca98e | 223 | |
| e101a78b NC |
224 | * memory.c: Trace memory reads when --trace-memory is enabled. |
| 225 | Remove float and double load and store functions. | |
| 226 | * memory.h (aarch64_get_mem_float): Delete prototype. | |
| 227 | (aarch64_get_mem_double): Likewise. | |
| 228 | (aarch64_set_mem_float): Likewise. | |
| 229 | (aarch64_set_mem_double): Likewise. | |
| 230 | * simulator (IS_SET): Always return either 0 or 1. | |
| 231 | (IS_CLEAR): Likewise. | |
| 232 | (fldrs_pcrel): Load and store floats using 32-bit memory accesses | |
| 233 | and doubles using 64-bit memory accesses. | |
| 234 | (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. | |
| 235 | (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. | |
| 236 | (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. | |
| 237 | (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. | |
| 238 | (store_pair_double, load_pair_float, load_pair_double): Likewise. | |
| 239 | (do_vec_MUL_by_element): New function. | |
| 240 | (do_vec_op2): Call do_vec_MUL_by_element. | |
| 241 | (do_scalar_NEG): New function. | |
| 242 | (do_double_add): Call do_scalar_NEG. | |
| 243 | ||
| 57aa1742 NC |
244 | 2016-03-03 Nick Clifton <nickc@redhat.com> |
| 245 | ||
| 246 | * simulator.c (set_flags_for_sub32): Correct type of signbit. | |
| 247 | (CondCompare): Swap interpretation of bit 30. | |
| 248 | (DO_ADDP): Delete macro. | |
| 249 | (do_vec_ADDP): Copy source registers before starting to update | |
| 250 | destination register. | |
| 251 | (do_vec_FADDP): Likewise. | |
| 252 | (do_vec_load_store): Fix computation of sizeof_operation. | |
| 253 | (rbit64): Fix type of constant. | |
| 254 | (aarch64_step): When displaying insn value, display all 32 bits. | |
| 255 | ||
| ce39bd38 MF |
256 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 257 | ||
| 258 | * config.in, configure: Regenerate. | |
| 259 | ||
| e19418e0 MF |
260 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 261 | ||
| 262 | * configure: Regenerate. | |
| 263 | ||
| 16f7876d MF |
264 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 265 | ||
| 266 | * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call. | |
| 267 | * configure: Regenerate. | |
| 268 | ||
| 99d8e879 MF |
269 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 270 | ||
| 271 | * configure: Regenerate. | |
| 35656e95 MF |
272 | |
| 273 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> | |
| 274 | ||
| 275 | * configure: Regenerate. | |
| 99d8e879 | 276 | |
| 347fe5bb MF |
277 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 278 | ||
| 279 | * configure.ac (SIM_AC_OPTION_INLINE): Delete call. | |
| 280 | * configure: Regenerate. | |
| 281 | ||
| 22be3fbe MF |
282 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 283 | ||
| 284 | * configure: Regenerate. | |
| 285 | ||
| 0dc73ef7 MF |
286 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 287 | ||
| 288 | * configure: Regenerate. | |
| 289 | ||
| 936df756 MF |
290 | 2016-01-09 Mike Frysinger <vapier@gentoo.org> |
| 291 | ||
| 292 | * config.in, configure: Regenerate. | |
| 293 | ||
| 2e3d4f4d MF |
294 | 2016-01-06 Mike Frysinger <vapier@gentoo.org> |
| 295 | ||
| 296 | * interp.c (sim_create_inferior): Mark argv and env const. | |
| 297 | (sim_open): Mark argv const. | |
| 298 | ||
| 1a846c62 MF |
299 | 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
| 300 | ||
| 301 | * interp.c: Delete dis-asm.h include. | |
| 302 | (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete. | |
| 303 | (sim_create_inferior): Delete disassemble init logic. | |
| 304 | (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete. | |
| 305 | (sim_open): Delete sim_add_option_table call. | |
| 306 | * memory.c (mem_error): Delete disas check. | |
| 307 | * simulator.c: Delete dis-asm.h include. | |
| 308 | (disas): Delete. | |
| 309 | (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM. | |
| 310 | (HALT_NYI): Likewise. | |
| 311 | (handle_halt): Delete disas call. | |
| 312 | (aarch64_step): Replace disas logic with TRACE_DISASM. | |
| 313 | * simulator.h: Delete dis-asm.h include. | |
| 314 | (aarch64_print_insn): Delete. | |
| 315 | ||
| bc273e17 MF |
316 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
| 317 | ||
| 318 | * simulator.c (MAX, MIN): Delete. | |
| 319 | (do_vec_maxv): Change MAX to max and MIN to min. | |
| 320 | (do_vec_fminmaxV): Likewise. | |
| 321 | ||
| ac8eefeb TG |
322 | 2016-01-04 Tristan Gingold <gingold@adacore.com> |
| 323 | ||
| 324 | * simulator.c: Remove syscall.h include. | |
| 325 | ||
| 9bbf6f91 MF |
326 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
| 327 | ||
| 328 | * configure: Regenerate. | |
| 329 | ||
| 0cb8d851 MF |
330 | 2016-01-03 Mike Frysinger <vapier@gentoo.org> |
| 331 | ||
| 332 | * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. | |
| 333 | * configure: Regenerate. | |
| 334 | ||
| 1ac72f06 MF |
335 | 2016-01-02 Mike Frysinger <vapier@gentoo.org> |
| 336 | ||
| 337 | * configure: Regenerate. | |
| 338 | ||
| 5d015275 MF |
339 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
| 340 | ||
| 341 | * interp.c (sim_dis_read): Change private_data to application_data. | |
| 342 | (sim_create_inferior): Likewise. | |
| 343 | ||
| 5e744ef8 MF |
344 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
| 345 | ||
| 346 | * Makefile.in (SIM_OBJS): Delete sim-hload.o. | |
| 347 | ||
| 1b393626 MF |
348 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
| 349 | ||
| 350 | * config.in, configure: Regenerate. | |
| 351 | ||
| 0e967299 MF |
352 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
| 353 | ||
| 354 | * interp.c (sim_create_inferior): Update comment and argv check. | |
| 355 | ||
| f66affe9 MF |
356 | 2015-12-14 Nick Clifton <nickc@redhat.com> |
| 357 | ||
| 358 | * simulator.c (system_get): New function. Provides read | |
| 359 | access to the dczid system register. | |
| 360 | (do_mrs): New function - implements the MRS instruction. | |
| 361 | (dexSystem): Call do_mrs for the MRS instruction. Halt on | |
| 362 | unimplemented system instructions. | |
| 363 | ||
| 364 | 2015-11-24 Nick Clifton <nickc@redhat.com> | |
| 365 | ||
| 366 | * configure.ac: New configure template. | |
| 367 | * aclocal.m4: Generate. | |
| 368 | * config.in: Generate. | |
| 369 | * configure: Generate. | |
| 370 | * cpustate.c: New file - functions for accessing AArch64 registers. | |
| 371 | * cpustate.h: New header. | |
| 372 | * decode.h: New header. | |
| 373 | * interp.c: New file - interface between GDB and simulator. | |
| 374 | * Makefile.in: New makefile template. | |
| 375 | * memory.c: New file - functions for simulating aarch64 memory | |
| 376 | accesses. | |
| 377 | * memory.h: New header. | |
| 378 | * sim-main.h: New header. | |
| 379 | * simulator.c: New file - aarch64 simulator functions. | |
| 380 | * simulator.h: New header. |