[thirdparty/binutils-gdb.git] / sim / aarch64 / cpustate.c

/* cpustate.h -- Prototypes for AArch64 simulator functions.

   Copyright (C) 2015-2021 Free Software Foundation, Inc.

   Contributed by Red Hat.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* This must come before any other includes.  */
#include "defs.h"

#include <stdio.h>
#include <math.h>

#include "sim-main.h"
#include "sim-signal.h"
#include "cpustate.h"
#include "simulator.h"
#include "libiberty.h"

/* Some operands are allowed to access the stack pointer (reg 31).
   For others a read from r31 always returns 0, and a write to r31 is ignored.  */
#define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))

void
aarch64_set_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint64_t val)
{
  if (reg == R31 && ! r31_is_sp)
    {
      TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
      return;
    }

  if (val != cpu->gr[reg].u64)
    TRACE_REGISTER (cpu,
		    "GR[%2d] changes from %16" PRIx64 " to %16" PRIx64,
		    reg, cpu->gr[reg].u64, val);

  cpu->gr[reg].u64 = val;
}

void
aarch64_set_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp, int64_t val)
{
  if (reg == R31 && ! r31_is_sp)
    {
      TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
      return;
    }

  if (val != cpu->gr[reg].s64)
    TRACE_REGISTER (cpu,
		    "GR[%2d] changes from %16" PRIx64 " to %16" PRIx64,
		    reg, cpu->gr[reg].s64, val);

  cpu->gr[reg].s64 = val;
}

uint64_t
aarch64_get_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp)
{
  return cpu->gr[reg_num(reg)].u64;
}

int64_t
aarch64_get_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp)
{
  return cpu->gr[reg_num(reg)].s64;
}

uint32_t
aarch64_get_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp)
{
  return cpu->gr[reg_num(reg)].u32;
}

int32_t
aarch64_get_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp)
{
  return cpu->gr[reg_num(reg)].s32;
}

void
aarch64_set_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp, int32_t val)
{
  if (reg == R31 && ! r31_is_sp)
    {
      TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
      return;
    }

  if (val != cpu->gr[reg].s32)
    TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x",
		    reg, cpu->gr[reg].s32, val);

  /* The ARM ARM states that (C1.2.4):
        When the data size is 32 bits, the lower 32 bits of the
	register are used and the upper 32 bits are ignored on
	a read and cleared to zero on a write.
     We simulate this by first clearing the whole 64-bits and
     then writing to the 32-bit value in the GRegister union.  */
  cpu->gr[reg].s64 = 0;
  cpu->gr[reg].s32 = val;
}

void
aarch64_set_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint32_t val)
{
  if (reg == R31 && ! r31_is_sp)
    {
      TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
      return;
    }

  if (val != cpu->gr[reg].u32)
    TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x",
		    reg, cpu->gr[reg].u32, val);

  cpu->gr[reg].u64 = 0;
  cpu->gr[reg].u32 = val;
}

uint32_t
aarch64_get_reg_u16 (sim_cpu *cpu, GReg reg, int r31_is_sp)
{
  return cpu->gr[reg_num(reg)].u16;
}

int32_t
aarch64_get_reg_s16 (sim_cpu *cpu, GReg reg, int r31_is_sp)
{
  return cpu->gr[reg_num(reg)].s16;
}

uint32_t
aarch64_get_reg_u8 (sim_cpu *cpu, GReg reg, int r31_is_sp)
{
  return cpu->gr[reg_num(reg)].u8;
}

int32_t
aarch64_get_reg_s8 (sim_cpu *cpu, GReg reg, int r31_is_sp)
{
  return cpu->gr[reg_num(reg)].s8;
}

uint64_t
aarch64_get_PC (sim_cpu *cpu)
{
  return cpu->pc;
}

uint64_t
aarch64_get_next_PC (sim_cpu *cpu)
{
  return cpu->nextpc;
}

void
aarch64_set_next_PC (sim_cpu *cpu, uint64_t next)
{
  if (next != cpu->nextpc + 4)
    TRACE_REGISTER (cpu,
		    "NextPC changes from %16" PRIx64 " to %16" PRIx64,
		    cpu->nextpc, next);

  cpu->nextpc = next;
}

void
aarch64_set_next_PC_by_offset (sim_cpu *cpu, int64_t offset)
{
  if (cpu->pc + offset != cpu->nextpc + 4)
    TRACE_REGISTER (cpu,
		    "NextPC changes from %16" PRIx64 " to %16" PRIx64,
		    cpu->nextpc, cpu->pc + offset);

  cpu->nextpc = cpu->pc + offset;
}

/* Install nextpc as current pc.  */
void
aarch64_update_PC (sim_cpu *cpu)
{
  cpu->pc = cpu->nextpc;
  /* Rezero the register we hand out when asked for ZR just in case it
     was used as the destination for a write by the previous
     instruction.  */
  cpu->gr[32].u64 = 0UL;
}

/* This instruction can be used to save the next PC to LR
   just before installing a branch PC.  */
void
aarch64_save_LR (sim_cpu *cpu)
{
  if (cpu->gr[LR].u64 != cpu->nextpc)
    TRACE_REGISTER (cpu,
		    "LR    changes from %16" PRIx64 " to %16" PRIx64,
		    cpu->gr[LR].u64, cpu->nextpc);

  cpu->gr[LR].u64 = cpu->nextpc;
}

static const char *
decode_cpsr (FlagMask flags)
{
  switch (flags & CPSR_ALL_FLAGS)
    {
    default:
    case 0:  return "----";
    case 1:  return "---V";
    case 2:  return "--C-";
    case 3:  return "--CV";
    case 4:  return "-Z--";
    case 5:  return "-Z-V";
    case 6:  return "-ZC-";
    case 7:  return "-ZCV";
    case 8:  return "N---";
    case 9:  return "N--V";
    case 10: return "N-C-";
    case 11: return "N-CV";
    case 12: return "NZ--";
    case 13: return "NZ-V";
    case 14: return "NZC-";
    case 15: return "NZCV";
    }
}

/* Retrieve the CPSR register as an int.  */
uint32_t
aarch64_get_CPSR (sim_cpu *cpu)
{
  return cpu->CPSR;
}

/* Set the CPSR register as an int.  */
void
aarch64_set_CPSR (sim_cpu *cpu, uint32_t new_flags)
{
  if (TRACE_REGISTER_P (cpu))
    {
      if (cpu->CPSR != new_flags)
	TRACE_REGISTER (cpu,
			"CPSR changes from %s to %s",
			decode_cpsr (cpu->CPSR), decode_cpsr (new_flags));
      else
	TRACE_REGISTER (cpu,
			"CPSR stays at %s", decode_cpsr (cpu->CPSR));
    }

  cpu->CPSR = new_flags & CPSR_ALL_FLAGS;
}

/* Read a specific subset of the CPSR as a bit pattern.  */
uint32_t
aarch64_get_CPSR_bits (sim_cpu *cpu, FlagMask mask)
{
  return cpu->CPSR & mask;
}

/* Assign a specific subset of the CPSR as a bit pattern.  */
void
aarch64_set_CPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
{
  uint32_t old_flags = cpu->CPSR;

  mask &= CPSR_ALL_FLAGS;
  cpu->CPSR &= ~ mask;
  cpu->CPSR |= (value & mask);

  if (old_flags != cpu->CPSR)
    TRACE_REGISTER (cpu,
		    "CPSR changes from %s to %s",
		    decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
}

/* Test the value of a single CPSR returned as non-zero or zero.  */
uint32_t
aarch64_test_CPSR_bit (sim_cpu *cpu, FlagMask bit)
{
  return cpu->CPSR & bit;
}

/* Set a single flag in the CPSR.  */
void
aarch64_set_CPSR_bit (sim_cpu *cpu, FlagMask bit)
{
  uint32_t old_flags = cpu->CPSR;

  cpu->CPSR |= (bit & CPSR_ALL_FLAGS);

  if (old_flags != cpu->CPSR)
    TRACE_REGISTER (cpu,
		    "CPSR changes from %s to %s",
		    decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
}

/* Clear a single flag in the CPSR.  */
void
aarch64_clear_CPSR_bit (sim_cpu *cpu, FlagMask bit)
{
  uint32_t old_flags = cpu->CPSR;

  cpu->CPSR &= ~(bit & CPSR_ALL_FLAGS);

  if (old_flags != cpu->CPSR)
    TRACE_REGISTER (cpu,
		    "CPSR changes from %s to %s",
		    decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
}

float
aarch64_get_FP_half (sim_cpu *cpu, VReg reg)
{
  union
  {
    uint16_t h[2];
    float    f;
  } u;

  u.h[0] = 0;
  u.h[1] = cpu->fr[reg].h[0];
  return u.f;
}


float
aarch64_get_FP_float (sim_cpu *cpu, VReg reg)
{
  return cpu->fr[reg].s;
}

double
aarch64_get_FP_double (sim_cpu *cpu, VReg reg)
{
  return cpu->fr[reg].d;
}

void
aarch64_get_FP_long_double (sim_cpu *cpu, VReg reg, FRegister *a)
{
  a->v[0] = cpu->fr[reg].v[0];
  a->v[1] = cpu->fr[reg].v[1];
}

void
aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val)
{
  union
  {
    uint16_t h[2];
    float    f;
  } u;

  u.f = val;
  cpu->fr[reg].h[0] = u.h[1];
  cpu->fr[reg].h[1] = 0;
}


void
aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
{
  if (val != cpu->fr[reg].s
      /* Handle +/- zero.  */
      || signbit (val) != signbit (cpu->fr[reg].s))
    {
      FRegister v;

      v.s = val;
      TRACE_REGISTER (cpu,
		      "FR[%d].s changes from %f to %f [hex: %0" PRIx64 "]",
		      reg, cpu->fr[reg].s, val, v.v[0]);
    }

  cpu->fr[reg].s = val;
}

void
aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val)
{
  if (val != cpu->fr[reg].d
      /* Handle +/- zero.  */
      || signbit (val) != signbit (cpu->fr[reg].d))
    {
      FRegister v;

      v.d = val;
      TRACE_REGISTER (cpu,
		      "FR[%d].d changes from %f to %f [hex: %0" PRIx64 "]",
		      reg, cpu->fr[reg].d, val, v.v[0]);
    }
  cpu->fr[reg].d = val;
}

void
aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a)
{
  if (cpu->fr[reg].v[0] != a.v[0]
      || cpu->fr[reg].v[1] != a.v[1])
    TRACE_REGISTER (cpu,
		    "FR[%d].q changes from [%0" PRIx64 " %0" PRIx64 "] to [%0"
		    PRIx64 " %0" PRIx64 "] ",
		    reg,
		    cpu->fr[reg].v[0], cpu->fr[reg].v[1],
		    a.v[0], a.v[1]);

  cpu->fr[reg].v[0] = a.v[0];
  cpu->fr[reg].v[1] = a.v[1];
}

#define GET_VEC_ELEMENT(REG, ELEMENT, FIELD)	   \
  do						   \
    {						   \
      if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
	{								\
	  TRACE_REGISTER (cpu, \
			  "Internal SIM error: invalid element number: %d ",\
			  ELEMENT);					\
	  sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
			   sim_stopped, SIM_SIGBUS);			\
	}								\
      return cpu->fr[REG].FIELD [ELEMENT];				\
    }									\
  while (0)

uint64_t
aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element)
{
  GET_VEC_ELEMENT (reg, element, v);
}

uint32_t
aarch64_get_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element)
{
  GET_VEC_ELEMENT (reg, element, w);
}

uint16_t
aarch64_get_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element)
{
  GET_VEC_ELEMENT (reg, element, h);
}

uint8_t
aarch64_get_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element)
{
  GET_VEC_ELEMENT (reg, element, b);
}

int64_t
aarch64_get_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element)
{
  GET_VEC_ELEMENT (reg, element, V);
}

int32_t
aarch64_get_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element)
{
  GET_VEC_ELEMENT (reg, element, W);
}

int16_t
aarch64_get_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element)
{
  GET_VEC_ELEMENT (reg, element, H);
}

int8_t
aarch64_get_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element)
{
  GET_VEC_ELEMENT (reg, element, B);
}

float
aarch64_get_vec_float (sim_cpu *cpu, VReg reg, unsigned element)
{
  GET_VEC_ELEMENT (reg, element, S);
}

double
aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element)
{
  GET_VEC_ELEMENT (reg, element, D);
}


#define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER)		\
  do									\
    {									\
      if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD))			\
	{								\
	  TRACE_REGISTER (cpu,						\
			  "Internal SIM error: invalid element number: %d ",\
			  ELEMENT);					\
	  sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
			   sim_stopped, SIM_SIGBUS);			\
	}								\
      if (VAL != cpu->fr[REG].FIELD [ELEMENT])				\
	TRACE_REGISTER (cpu,						\
			"VR[%2d]." #FIELD " [%d] changes from " PRINTER \
			" to " PRINTER , REG,				\
			ELEMENT, cpu->fr[REG].FIELD [ELEMENT], VAL);	\
									\
      cpu->fr[REG].FIELD [ELEMENT] = VAL;				\
    }									\
  while (0)

void
aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val)
{
  SET_VEC_ELEMENT (reg, element, val, v, "%16" PRIx64);
}

void
aarch64_set_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element, uint32_t val)
{
  SET_VEC_ELEMENT (reg, element, val, w, "%8x");
}

void
aarch64_set_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element, uint16_t val)
{
  SET_VEC_ELEMENT (reg, element, val, h, "%4x");
}

void
aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val)
{
  SET_VEC_ELEMENT (reg, element, val, b, "%x");
}

void
aarch64_set_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element, int64_t val)
{
  SET_VEC_ELEMENT (reg, element, val, V, "%16" PRIx64);
}

void
aarch64_set_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element, int32_t val)
{
  SET_VEC_ELEMENT (reg, element, val, W, "%8x");
}

void
aarch64_set_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element, int16_t val)
{
  SET_VEC_ELEMENT (reg, element, val, H, "%4x");
}

void
aarch64_set_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element, int8_t val)
{
  SET_VEC_ELEMENT (reg, element, val, B, "%x");
}

void
aarch64_set_vec_float (sim_cpu *cpu, VReg reg, unsigned element, float val)
{
  SET_VEC_ELEMENT (reg, element, val, S, "%f");
}

void
aarch64_set_vec_double (sim_cpu *cpu, VReg reg, unsigned element, double val)
{
  SET_VEC_ELEMENT (reg, element, val, D, "%f");
}

void
aarch64_set_FPSR (sim_cpu *cpu, uint32_t value)
{
  if (cpu->FPSR != value)
    TRACE_REGISTER (cpu,
		    "FPSR changes from %x to %x", cpu->FPSR, value);

  cpu->FPSR = value & FPSR_ALL_FPSRS;
}

uint32_t
aarch64_get_FPSR (sim_cpu *cpu)
{
  return cpu->FPSR;
}

void
aarch64_set_FPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
{
  uint32_t old_FPSR = cpu->FPSR;

  mask &= FPSR_ALL_FPSRS;
  cpu->FPSR &= ~mask;
  cpu->FPSR |= (value & mask);

  if (cpu->FPSR != old_FPSR)
    TRACE_REGISTER (cpu,
		    "FPSR changes from %x to %x", old_FPSR, cpu->FPSR);
}

uint32_t
aarch64_get_FPSR_bits (sim_cpu *cpu, uint32_t mask)
{
  mask &= FPSR_ALL_FPSRS;
  return cpu->FPSR & mask;
}

int
aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag)
{
  return cpu->FPSR & flag;
}

uint64_t
aarch64_get_thread_id (sim_cpu *cpu)
{
  return cpu->tpidr;
}

uint32_t
aarch64_get_FPCR (sim_cpu *cpu)
{
  return cpu->FPCR;
}

void
aarch64_set_FPCR (sim_cpu *cpu, uint32_t val)
{
  if (cpu->FPCR != val)
    TRACE_REGISTER (cpu,
		    "FPCR changes from %x to %x", cpu->FPCR, val);
  cpu->FPCR = val;
}
Commit	Line	Data
2e8cf49e NC	1	/* cpustate.h -- Prototypes for AArch64 simulator functions.
2e8cf49e NC	2
3666a048	3	Copyright (C) 2015-2021 Free Software Foundation, Inc.
2e8cf49e NC	4
	5	Contributed by Red Hat.
	6
	7	This file is part of GDB.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 3 of the License, or
	12	(at your option) any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	21
6df01ab8 MF	22	/* This must come before any other includes. */
	23	#include "defs.h"
	24
2e8cf49e	25	#include <stdio.h>
c0386d4d	26	#include <math.h>
2e8cf49e NC	27
2e8cf49e NC	28	#include "sim-main.h"
1fef66b0	29	#include "sim-signal.h"
2e8cf49e NC	30	#include "cpustate.h"
2e8cf49e NC	31	#include "simulator.h"
cd5b6074	32	#include "libiberty.h"
2e8cf49e NC	33
	34	/* Some operands are allowed to access the stack pointer (reg 31).
	35	For others a read from r31 always returns 0, and a write to r31 is ignored. */
	36	#define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
	37
	38	void
	39	aarch64_set_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint64_t val)
	40	{
	41	if (reg == R31 && ! r31_is_sp)
	42	{
e101a78b	43	TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
2e8cf49e NC	44	return;
	45	}
	46
	47	if (val != cpu->gr[reg].u64)
	48	TRACE_REGISTER (cpu,
e101a78b	49	"GR[%2d] changes from %16" PRIx64 " to %16" PRIx64,
2e8cf49e NC	50	reg, cpu->gr[reg].u64, val);
	51
	52	cpu->gr[reg].u64 = val;
	53	}
	54
	55	void
	56	aarch64_set_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp, int64_t val)
	57	{
	58	if (reg == R31 && ! r31_is_sp)
	59	{
e101a78b	60	TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
2e8cf49e NC	61	return;
	62	}
	63
	64	if (val != cpu->gr[reg].s64)
	65	TRACE_REGISTER (cpu,
e101a78b	66	"GR[%2d] changes from %16" PRIx64 " to %16" PRIx64,
2e8cf49e NC	67	reg, cpu->gr[reg].s64, val);
	68
	69	cpu->gr[reg].s64 = val;
	70	}
	71
	72	uint64_t
	73	aarch64_get_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp)
	74	{
	75	return cpu->gr[reg_num(reg)].u64;
	76	}
	77
	78	int64_t
	79	aarch64_get_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp)
	80	{
	81	return cpu->gr[reg_num(reg)].s64;
	82	}
	83
	84	uint32_t
	85	aarch64_get_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp)
	86	{
	87	return cpu->gr[reg_num(reg)].u32;
	88	}
	89
	90	int32_t
	91	aarch64_get_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp)
	92	{
	93	return cpu->gr[reg_num(reg)].s32;
	94	}
	95
7517e550 NC	96	void
	97	aarch64_set_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp, int32_t val)
	98	{
	99	if (reg == R31 && ! r31_is_sp)
	100	{
	101	TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
	102	return;
	103	}
	104
	105	if (val != cpu->gr[reg].s32)
	106	TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x",
	107	reg, cpu->gr[reg].s32, val);
	108
	109	/* The ARM ARM states that (C1.2.4):
	110	When the data size is 32 bits, the lower 32 bits of the
	111	register are used and the upper 32 bits are ignored on
	112	a read and cleared to zero on a write.
	113	We simulate this by first clearing the whole 64-bits and
	114	then writing to the 32-bit value in the GRegister union. */
	115	cpu->gr[reg].s64 = 0;
	116	cpu->gr[reg].s32 = val;
	117	}
	118
	119	void
	120	aarch64_set_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint32_t val)
	121	{
	122	if (reg == R31 && ! r31_is_sp)
	123	{
	124	TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
	125	return;
	126	}
	127
	128	if (val != cpu->gr[reg].u32)
	129	TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x",
	130	reg, cpu->gr[reg].u32, val);
	131
	132	cpu->gr[reg].u64 = 0;
	133	cpu->gr[reg].u32 = val;
	134	}
	135
2e8cf49e NC	136	uint32_t
	137	aarch64_get_reg_u16 (sim_cpu *cpu, GReg reg, int r31_is_sp)
	138	{
	139	return cpu->gr[reg_num(reg)].u16;
	140	}
	141
	142	int32_t
	143	aarch64_get_reg_s16 (sim_cpu *cpu, GReg reg, int r31_is_sp)
	144	{
	145	return cpu->gr[reg_num(reg)].s16;
	146	}
	147
	148	uint32_t
	149	aarch64_get_reg_u8 (sim_cpu *cpu, GReg reg, int r31_is_sp)
	150	{
	151	return cpu->gr[reg_num(reg)].u8;
	152	}
	153
	154	int32_t
	155	aarch64_get_reg_s8 (sim_cpu *cpu, GReg reg, int r31_is_sp)
	156	{
	157	return cpu->gr[reg_num(reg)].s8;
	158	}
	159
	160	uint64_t
	161	aarch64_get_PC (sim_cpu *cpu)
	162	{
	163	return cpu->pc;
	164	}
	165
	166	uint64_t
	167	aarch64_get_next_PC (sim_cpu *cpu)
	168	{
	169	return cpu->nextpc;
	170	}
	171
	172	void
	173	aarch64_set_next_PC (sim_cpu *cpu, uint64_t next)
	174	{
	175	if (next != cpu->nextpc + 4)
	176	TRACE_REGISTER (cpu,
e101a78b	177	"NextPC changes from %16" PRIx64 " to %16" PRIx64,
2e8cf49e NC	178	cpu->nextpc, next);
	179
	180	cpu->nextpc = next;
	181	}
	182
	183	void
	184	aarch64_set_next_PC_by_offset (sim_cpu *cpu, int64_t offset)
	185	{
	186	if (cpu->pc + offset != cpu->nextpc + 4)
	187	TRACE_REGISTER (cpu,
e101a78b	188	"NextPC changes from %16" PRIx64 " to %16" PRIx64,
2e8cf49e NC	189	cpu->nextpc, cpu->pc + offset);
	190
	191	cpu->nextpc = cpu->pc + offset;
	192	}
	193
	194	/* Install nextpc as current pc. */
	195	void
	196	aarch64_update_PC (sim_cpu *cpu)
	197	{
	198	cpu->pc = cpu->nextpc;
	199	/* Rezero the register we hand out when asked for ZR just in case it
	200	was used as the destination for a write by the previous
	201	instruction. */
	202	cpu->gr[32].u64 = 0UL;
	203	}
	204
	205	/* This instruction can be used to save the next PC to LR
	206	just before installing a branch PC. */
	207	void
	208	aarch64_save_LR (sim_cpu *cpu)
	209	{
	210	if (cpu->gr[LR].u64 != cpu->nextpc)
	211	TRACE_REGISTER (cpu,
e101a78b	212	"LR changes from %16" PRIx64 " to %16" PRIx64,
2e8cf49e NC	213	cpu->gr[LR].u64, cpu->nextpc);
	214
	215	cpu->gr[LR].u64 = cpu->nextpc;
	216	}
	217
	218	static const char *
	219	decode_cpsr (FlagMask flags)
	220	{
	221	switch (flags & CPSR_ALL_FLAGS)
	222	{
	223	default:
	224	case 0: return "----";
	225	case 1: return "---V";
	226	case 2: return "--C-";
	227	case 3: return "--CV";
	228	case 4: return "-Z--";
	229	case 5: return "-Z-V";
	230	case 6: return "-ZC-";
	231	case 7: return "-ZCV";
	232	case 8: return "N---";
	233	case 9: return "N--V";
	234	case 10: return "N-C-";
	235	case 11: return "N-CV";
	236	case 12: return "NZ--";
	237	case 13: return "NZ-V";
	238	case 14: return "NZC-";
	239	case 15: return "NZCV";
	240	}
	241	}
	242
	243	/* Retrieve the CPSR register as an int. */
	244	uint32_t
	245	aarch64_get_CPSR (sim_cpu *cpu)
	246	{
	247	return cpu->CPSR;
	248	}
	249
	250	/* Set the CPSR register as an int. */
	251	void
	252	aarch64_set_CPSR (sim_cpu *cpu, uint32_t new_flags)
	253	{
	254	if (TRACE_REGISTER_P (cpu))
	255	{
	256	if (cpu->CPSR != new_flags)
	257	TRACE_REGISTER (cpu,
e101a78b	258	"CPSR changes from %s to %s",
2e8cf49e NC	259	decode_cpsr (cpu->CPSR), decode_cpsr (new_flags));
	260	else
	261	TRACE_REGISTER (cpu,
e101a78b	262	"CPSR stays at %s", decode_cpsr (cpu->CPSR));
2e8cf49e NC	263	}
	264
	265	cpu->CPSR = new_flags & CPSR_ALL_FLAGS;
	266	}
	267
	268	/* Read a specific subset of the CPSR as a bit pattern. */
	269	uint32_t
	270	aarch64_get_CPSR_bits (sim_cpu *cpu, FlagMask mask)
	271	{
	272	return cpu->CPSR & mask;
	273	}
	274
	275	/* Assign a specific subset of the CPSR as a bit pattern. */
	276	void
	277	aarch64_set_CPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
	278	{
	279	uint32_t old_flags = cpu->CPSR;
	280
	281	mask &= CPSR_ALL_FLAGS;
	282	cpu->CPSR &= ~ mask;
	283	cpu->CPSR \|= (value & mask);
	284
	285	if (old_flags != cpu->CPSR)
	286	TRACE_REGISTER (cpu,
e101a78b	287	"CPSR changes from %s to %s",
2e8cf49e NC	288	decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
	289	}
	290
	291	/* Test the value of a single CPSR returned as non-zero or zero. */
	292	uint32_t
	293	aarch64_test_CPSR_bit (sim_cpu *cpu, FlagMask bit)
	294	{
	295	return cpu->CPSR & bit;
	296	}
	297
	298	/* Set a single flag in the CPSR. */
	299	void
	300	aarch64_set_CPSR_bit (sim_cpu *cpu, FlagMask bit)
	301	{
	302	uint32_t old_flags = cpu->CPSR;
	303
	304	cpu->CPSR \|= (bit & CPSR_ALL_FLAGS);
	305
	306	if (old_flags != cpu->CPSR)
	307	TRACE_REGISTER (cpu,
e101a78b	308	"CPSR changes from %s to %s",
2e8cf49e NC	309	decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
	310	}
	311
	312	/* Clear a single flag in the CPSR. */
	313	void
	314	aarch64_clear_CPSR_bit (sim_cpu *cpu, FlagMask bit)
	315	{
	316	uint32_t old_flags = cpu->CPSR;
	317
	318	cpu->CPSR &= ~(bit & CPSR_ALL_FLAGS);
	319
	320	if (old_flags != cpu->CPSR)
	321	TRACE_REGISTER (cpu,
e101a78b	322	"CPSR changes from %s to %s",
2e8cf49e NC	323	decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
	324	}
	325
5ab6d79e NC	326	float
	327	aarch64_get_FP_half (sim_cpu *cpu, VReg reg)
	328	{
	329	union
	330	{
	331	uint16_t h[2];
	332	float f;
	333	} u;
	334
7517e550 NC	335	u.h[0] = 0;
7517e550 NC	336	u.h[1] = cpu->fr[reg].h[0];
5ab6d79e NC	337	return u.f;
	338	}
	339
	340
2e8cf49e NC	341	float
	342	aarch64_get_FP_float (sim_cpu *cpu, VReg reg)
	343	{
	344	return cpu->fr[reg].s;
	345	}
	346
	347	double
	348	aarch64_get_FP_double (sim_cpu *cpu, VReg reg)
	349	{
	350	return cpu->fr[reg].d;
	351	}
	352
	353	void
	354	aarch64_get_FP_long_double (sim_cpu cpu, VReg reg, FRegister a)
	355	{
	356	a->v[0] = cpu->fr[reg].v[0];
	357	a->v[1] = cpu->fr[reg].v[1];
	358	}
	359
5ab6d79e NC	360	void
	361	aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val)
	362	{
	363	union
	364	{
	365	uint16_t h[2];
	366	float f;
	367	} u;
	368
	369	u.f = val;
7517e550	370	cpu->fr[reg].h[0] = u.h[1];
5ab6d79e NC	371	cpu->fr[reg].h[1] = 0;
	372	}
	373
	374
2e8cf49e NC	375	void
	376	aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
	377	{
c0386d4d JW	378	if (val != cpu->fr[reg].s
	379	/* Handle +/- zero. */
	380	\|\| signbit (val) != signbit (cpu->fr[reg].s))
e101a78b NC	381	{
	382	FRegister v;
	383
	384	v.s = val;
	385	TRACE_REGISTER (cpu,
f1ca3215	386	"FR[%d].s changes from %f to %f [hex: %0" PRIx64 "]",
e101a78b NC	387	reg, cpu->fr[reg].s, val, v.v[0]);
e101a78b NC	388	}
2e8cf49e NC	389
	390	cpu->fr[reg].s = val;
	391	}
	392
	393	void
	394	aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val)
	395	{
c0386d4d JW	396	if (val != cpu->fr[reg].d
	397	/* Handle +/- zero. */
	398	\|\| signbit (val) != signbit (cpu->fr[reg].d))
e101a78b NC	399	{
e101a78b NC	400	FRegister v;
2e8cf49e	401
e101a78b NC	402	v.d = val;
e101a78b NC	403	TRACE_REGISTER (cpu,
f1ca3215	404	"FR[%d].d changes from %f to %f [hex: %0" PRIx64 "]",
e101a78b NC	405	reg, cpu->fr[reg].d, val, v.v[0]);
e101a78b NC	406	}
2e8cf49e NC	407	cpu->fr[reg].d = val;
	408	}
	409
	410	void
	411	aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a)
	412	{
	413	if (cpu->fr[reg].v[0] != a.v[0]
	414	\|\| cpu->fr[reg].v[1] != a.v[1])
	415	TRACE_REGISTER (cpu,
f1ca3215 MF	416	"FR[%d].q changes from [%0" PRIx64 " %0" PRIx64 "] to [%0"
f1ca3215 MF	417	PRIx64 " %0" PRIx64 "] ",
2e8cf49e NC	418	reg,
	419	cpu->fr[reg].v[0], cpu->fr[reg].v[1],
	420	a.v[0], a.v[1]);
	421
	422	cpu->fr[reg].v[0] = a.v[0];
	423	cpu->fr[reg].v[1] = a.v[1];
	424	}
	425
e101a78b NC	426	#define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \
	427	do \
	428	{ \
87bba7a5	429	if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
e101a78b NC	430	{ \
	431	TRACE_REGISTER (cpu, \
	432	"Internal SIM error: invalid element number: %d ",\
	433	ELEMENT); \
	434	sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
	435	sim_stopped, SIM_SIGBUS); \
	436	} \
	437	return cpu->fr[REG].FIELD [ELEMENT]; \
	438	} \
	439	while (0)
	440
2e8cf49e NC	441	uint64_t
	442	aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element)
	443	{
e101a78b	444	GET_VEC_ELEMENT (reg, element, v);
2e8cf49e NC	445	}
	446
	447	uint32_t
e101a78b	448	aarch64_get_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element)
2e8cf49e	449	{
e101a78b	450	GET_VEC_ELEMENT (reg, element, w);
2e8cf49e NC	451	}
	452
	453	uint16_t
e101a78b	454	aarch64_get_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element)
2e8cf49e	455	{
e101a78b	456	GET_VEC_ELEMENT (reg, element, h);
2e8cf49e NC	457	}
	458
	459	uint8_t
e101a78b	460	aarch64_get_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element)
2e8cf49e	461	{
e101a78b	462	GET_VEC_ELEMENT (reg, element, b);
2e8cf49e NC	463	}
2e8cf49e NC	464
e101a78b NC	465	int64_t
e101a78b NC	466	aarch64_get_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element)
2e8cf49e	467	{
e101a78b	468	GET_VEC_ELEMENT (reg, element, V);
2e8cf49e NC	469	}
2e8cf49e NC	470
e101a78b NC	471	int32_t
e101a78b NC	472	aarch64_get_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element)
2e8cf49e	473	{
e101a78b	474	GET_VEC_ELEMENT (reg, element, W);
2e8cf49e NC	475	}
2e8cf49e NC	476
e101a78b NC	477	int16_t
e101a78b NC	478	aarch64_get_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element)
2e8cf49e	479	{
e101a78b	480	GET_VEC_ELEMENT (reg, element, H);
2e8cf49e NC	481	}
2e8cf49e NC	482
e101a78b NC	483	int8_t
e101a78b NC	484	aarch64_get_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element)
2e8cf49e	485	{
e101a78b	486	GET_VEC_ELEMENT (reg, element, B);
2e8cf49e NC	487	}
2e8cf49e NC	488
e101a78b NC	489	float
e101a78b NC	490	aarch64_get_vec_float (sim_cpu *cpu, VReg reg, unsigned element)
2e8cf49e	491	{
e101a78b	492	GET_VEC_ELEMENT (reg, element, S);
2e8cf49e NC	493	}
2e8cf49e NC	494
e101a78b NC	495	double
	496	aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element)
	497	{
	498	GET_VEC_ELEMENT (reg, element, D);
	499	}
	500
	501
7517e550 NC	502	#define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \
	503	do \
	504	{ \
4c0ca98e	505	if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
e101a78b	506	{ \
7517e550	507	TRACE_REGISTER (cpu, \
e101a78b NC	508	"Internal SIM error: invalid element number: %d ",\
	509	ELEMENT); \
	510	sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
	511	sim_stopped, SIM_SIGBUS); \
	512	} \
	513	if (VAL != cpu->fr[REG].FIELD [ELEMENT]) \
	514	TRACE_REGISTER (cpu, \
	515	"VR[%2d]." #FIELD " [%d] changes from " PRINTER \
	516	" to " PRINTER , REG, \
	517	ELEMENT, cpu->fr[REG].FIELD [ELEMENT], VAL); \
7517e550 NC	518	\
	519	cpu->fr[REG].FIELD [ELEMENT] = VAL; \
	520	} \
e101a78b	521	while (0)
2e8cf49e NC	522
2e8cf49e NC	523	void
ef0d8ffc	524	aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val)
2e8cf49e	525	{
f1ca3215	526	SET_VEC_ELEMENT (reg, element, val, v, "%16" PRIx64);
2e8cf49e NC	527	}
2e8cf49e NC	528
e101a78b	529	void
ef0d8ffc	530	aarch64_set_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element, uint32_t val)
2e8cf49e	531	{
e101a78b	532	SET_VEC_ELEMENT (reg, element, val, w, "%8x");
2e8cf49e NC	533	}
2e8cf49e NC	534
e101a78b	535	void
ef0d8ffc	536	aarch64_set_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element, uint16_t val)
2e8cf49e	537	{
e101a78b	538	SET_VEC_ELEMENT (reg, element, val, h, "%4x");
2e8cf49e NC	539	}
2e8cf49e NC	540
e101a78b	541	void
ef0d8ffc	542	aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val)
2e8cf49e	543	{
e101a78b	544	SET_VEC_ELEMENT (reg, element, val, b, "%x");
2e8cf49e NC	545	}
	546
	547	void
e101a78b	548	aarch64_set_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element, int64_t val)
2e8cf49e	549	{
f1ca3215	550	SET_VEC_ELEMENT (reg, element, val, V, "%16" PRIx64);
2e8cf49e NC	551	}
	552
	553	void
e101a78b	554	aarch64_set_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element, int32_t val)
2e8cf49e	555	{
e101a78b	556	SET_VEC_ELEMENT (reg, element, val, W, "%8x");
2e8cf49e NC	557	}
2e8cf49e NC	558
e101a78b NC	559	void
e101a78b NC	560	aarch64_set_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element, int16_t val)
2e8cf49e	561	{
e101a78b	562	SET_VEC_ELEMENT (reg, element, val, H, "%4x");
2e8cf49e NC	563	}
2e8cf49e NC	564
e101a78b NC	565	void
e101a78b NC	566	aarch64_set_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element, int8_t val)
2e8cf49e	567	{
e101a78b	568	SET_VEC_ELEMENT (reg, element, val, B, "%x");
2e8cf49e NC	569	}
2e8cf49e NC	570
e101a78b NC	571	void
e101a78b NC	572	aarch64_set_vec_float (sim_cpu *cpu, VReg reg, unsigned element, float val)
2e8cf49e	573	{
e101a78b	574	SET_VEC_ELEMENT (reg, element, val, S, "%f");
2e8cf49e NC	575	}
2e8cf49e NC	576
e101a78b NC	577	void
e101a78b NC	578	aarch64_set_vec_double (sim_cpu *cpu, VReg reg, unsigned element, double val)
2e8cf49e	579	{
e101a78b	580	SET_VEC_ELEMENT (reg, element, val, D, "%f");
2e8cf49e NC	581	}
	582
	583	void
e101a78b	584	aarch64_set_FPSR (sim_cpu *cpu, uint32_t value)
2e8cf49e	585	{
e101a78b	586	if (cpu->FPSR != value)
2e8cf49e	587	TRACE_REGISTER (cpu,
e101a78b	588	"FPSR changes from %x to %x", cpu->FPSR, value);
2e8cf49e	589
e101a78b	590	cpu->FPSR = value & FPSR_ALL_FPSRS;
2e8cf49e NC	591	}
2e8cf49e NC	592
e101a78b NC	593	uint32_t
e101a78b NC	594	aarch64_get_FPSR (sim_cpu *cpu)
2e8cf49e	595	{
e101a78b	596	return cpu->FPSR;
2e8cf49e NC	597	}
	598
	599	void
e101a78b	600	aarch64_set_FPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
2e8cf49e	601	{
e101a78b NC	602	uint32_t old_FPSR = cpu->FPSR;
	603
	604	mask &= FPSR_ALL_FPSRS;
	605	cpu->FPSR &= ~mask;
	606	cpu->FPSR \|= (value & mask);
2e8cf49e	607
e101a78b NC	608	if (cpu->FPSR != old_FPSR)
	609	TRACE_REGISTER (cpu,
	610	"FPSR changes from %x to %x", old_FPSR, cpu->FPSR);
2e8cf49e NC	611	}
2e8cf49e NC	612
e101a78b NC	613	uint32_t
e101a78b NC	614	aarch64_get_FPSR_bits (sim_cpu *cpu, uint32_t mask)
2e8cf49e	615	{
e101a78b NC	616	mask &= FPSR_ALL_FPSRS;
	617	return cpu->FPSR & mask;
	618	}
2e8cf49e	619
e101a78b NC	620	int
	621	aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag)
	622	{
	623	return cpu->FPSR & flag;
2e8cf49e	624	}
5ab6d79e NC	625
5ab6d79e NC	626	uint64_t
ef0d8ffc	627	aarch64_get_thread_id (sim_cpu *cpu)
5ab6d79e NC	628	{
	629	return cpu->tpidr;
	630	}
	631
	632	uint32_t
ef0d8ffc	633	aarch64_get_FPCR (sim_cpu *cpu)
5ab6d79e NC	634	{
	635	return cpu->FPCR;
	636	}
	637
	638	void
ef0d8ffc	639	aarch64_set_FPCR (sim_cpu *cpu, uint32_t val)
5ab6d79e NC	640	{
	641	if (cpu->FPCR != val)
	642	TRACE_REGISTER (cpu,
	643	"FPCR changes from %x to %x", cpu->FPCR, val);
	644	cpu->FPCR = val;
	645	}