[thirdparty/binutils-gdb.git] / sim / arm / armemu.h

/*  armemu.h -- ARMulator emulation macros:  ARM6 Instruction Emulator.
    Copyright (C) 1994 Advanced RISC Machines Ltd.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, see <http://www.gnu.org/licenses/>. */

extern ARMword isize;

/* Condition code values.  */
#define EQ 0
#define NE 1
#define CS 2
#define CC 3
#define MI 4
#define PL 5
#define VS 6
#define VC 7
#define HI 8
#define LS 9
#define GE 10
#define LT 11
#define GT 12
#define LE 13
#define AL 14
#define NV 15

/* Shift Opcodes.  */
#define LSL 0
#define LSR 1
#define ASR 2
#define ROR 3

/* Macros to twiddle the status flags and mode.  */
#define NBIT ((unsigned)1L << 31)
#define ZBIT (1L << 30)
#define CBIT (1L << 29)
#define VBIT (1L << 28)
#define SBIT (1L << 27)
#define IBIT (1L << 7)
#define FBIT (1L << 6)
#define IFBITS (3L << 6)
#define R15IBIT (1L << 27)
#define R15FBIT (1L << 26)
#define R15IFBITS (3L << 26)

#define POS(i) ( (~(i)) >> 31 )
#define NEG(i) ( (i) >> 31 )

#ifdef MODET			/* Thumb support.  */
/* ??? This bit is actually in the low order bit of the PC in the hardware.
   It isn't clear if the simulator needs to model that or not.  */
#define TBIT (1L << 5)
#define TFLAG state->TFlag
#define SETT state->TFlag = 1
#define CLEART state->TFlag = 0
#define ASSIGNT(res) state->TFlag = res
#define INSN_SIZE (TFLAG ? 2 : 4)
#else
#define INSN_SIZE 4
#endif

#define NFLAG state->NFlag
#define SETN state->NFlag = 1
#define CLEARN state->NFlag = 0
#define ASSIGNN(res) state->NFlag = res

#define ZFLAG state->ZFlag
#define SETZ state->ZFlag = 1
#define CLEARZ state->ZFlag = 0
#define ASSIGNZ(res) state->ZFlag = res

#define CFLAG state->CFlag
#define SETC state->CFlag = 1
#define CLEARC state->CFlag = 0
#define ASSIGNC(res) state->CFlag = res

#define VFLAG state->VFlag
#define SETV state->VFlag = 1
#define CLEARV state->VFlag = 0
#define ASSIGNV(res) state->VFlag = res

#define SFLAG state->SFlag
#define SETS state->SFlag = 1
#define CLEARS state->SFlag = 0
#define ASSIGNS(res) state->SFlag = res

#define IFLAG (state->IFFlags >> 1)
#define FFLAG (state->IFFlags & 1)
#define IFFLAGS state->IFFlags
#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;

#define PSR_FBITS (0xff000000L)
#define PSR_SBITS (0x00ff0000L)
#define PSR_XBITS (0x0000ff00L)
#define PSR_CBITS (0x000000ffL)

#if defined MODE32 || defined MODET
#define CCBITS (0xf8000000L)
#else
#define CCBITS (0xf0000000L)
#endif

#define INTBITS (0xc0L)

#if defined MODET && defined MODE32
#define PCBITS (0xffffffffL)
#else
#define PCBITS (0xfffffffcL)
#endif

#define MODEBITS (0x1fL)
#define R15INTBITS (3L << 26)

#if defined MODET && defined MODE32
#define R15PCBITS (0x03ffffffL)
#else
#define R15PCBITS (0x03fffffcL)
#endif

#define R15PCMODEBITS (0x03ffffffL)
#define R15MODEBITS (0x3L)

#ifdef MODE32
#define PCMASK PCBITS
#define PCWRAP(pc) (pc)
#else
#define PCMASK R15PCBITS
#define PCWRAP(pc) ((pc) & R15PCBITS)
#endif

#define PC (state->Reg[15] & PCMASK)
#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
#define R15INT (state->Reg[15] & R15INTBITS)
#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
#define R15PC (state->Reg[15] & R15PCBITS)
#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
#define R15MODE (state->Reg[15] & R15MODEBITS)

#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27))
#define EINT (IFFLAGS << 6)
#define ER15INT (IFFLAGS << 26)
#define EMODE (state->Mode)

#ifdef MODET
#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
#else
#define CPSR (ECC | EINT | EMODE)
#endif

#ifdef MODE32
#define PATCHR15
#else
#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
#endif

#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)

#define SETR15PSR(s) 								\
  do										\
    {										\
      if (state->Mode == USER26MODE)						\
        {									\
          state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE;		\
          ASSIGNN ((state->Reg[15] & NBIT) != 0);				\
          ASSIGNZ ((state->Reg[15] & ZBIT) != 0);				\
          ASSIGNC ((state->Reg[15] & CBIT) != 0);				\
          ASSIGNV ((state->Reg[15] & VBIT) != 0);				\
        }									\
      else									\
        {									\
          state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS));	\
          ARMul_R15Altered (state);						\
       }									\
    }										\
  while (0)
     
#define SETABORT(i, m, d)						\
  do									\
    { 									\
      int SETABORT_mode = (m);						\
									\
      ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state));	\
      ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT))	\
			     | (i) | SETABORT_mode));			\
      state->Reg[14] = temp - (d);					\
    }									\
  while (0)

#ifndef MODE32
#define VECTORS 0x20
#define LEGALADDR 0x03ffffff
#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
#define ADDREXCEPT(address)   (address > LEGALADDR && !state->data32Sig)
#endif

#define INTERNALABORT(address)			\
  do						\
    {						\
      if (address < VECTORS)			\
	state->Aborted = ARMul_DataAbortV;	\
      else					\
	state->Aborted = ARMul_AddrExceptnV;	\
    }						\
  while (0)

#ifdef MODE32
#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV)
#else
#define TAKEABORT 					\
  do							\
    {							\
      if (state->Aborted == ARMul_AddrExceptnV) 	\
	ARMul_Abort (state, ARMul_AddrExceptnV); 	\
      else 						\
	ARMul_Abort (state, ARMul_DataAbortV);		\
    }							\
  while (0)
#endif

#define CPTAKEABORT					\
  do							\
    {							\
      if (!state->Aborted)				\
	ARMul_Abort (state, ARMul_UndefinedInstrV); 	\
      else if (state->Aborted == ARMul_AddrExceptnV) 	\
	ARMul_Abort (state, ARMul_AddrExceptnV); 	\
      else 						\
	ARMul_Abort (state, ARMul_DataAbortV);		\
    }							\
  while (0);


/* Different ways to start the next instruction.  */
#define SEQ           0
#define NONSEQ        1
#define PCINCEDSEQ    2
#define PCINCEDNONSEQ 3
#define PRIMEPIPE     4
#define RESUME        8

#define NORMALCYCLE state->NextInstr = 0
#define BUSUSEDN    state->NextInstr |= 1  /* The next fetch will be an N cycle.  */
#define BUSUSEDINCPCS						\
  do								\
    {								\
      if (! state->is_v4)					\
        {							\
	  /* A standard PC inc and an S cycle.  */		\
	  state->Reg[15] += isize;				\
	  state->NextInstr = (state->NextInstr & 0xff) | 2;	\
	}							\
    }								\
  while (0)

#define BUSUSEDINCPCN					\
  do							\
    {							\
      if (state->is_v4)					\
	BUSUSEDN;					\
      else						\
	{						\
	  /* A standard PC inc and an N cycle.  */	\
	  state->Reg[15] += isize;			\
	  state->NextInstr |= 3;			\
	}						\
    }							\
  while (0)

#define INCPC 			\
  do				\
    {				\
      /* A standard PC inc.  */	\
      state->Reg[15] += isize;	\
      state->NextInstr |= 2;	\
    }				\
  while (0)

#define FLUSHPIPE state->NextInstr |= PRIMEPIPE

/* Cycle based emulation.  */

#define OUTPUTCP(i,a,b)
#define NCYCLE
#define SCYCLE
#define ICYCLE
#define CCYCLE
#define NEXTCYCLE(c)

/* Macros to extract parts of instructions.  */
#define DESTReg (BITS (12, 15))
#define LHSReg  (BITS (16, 19))
#define RHSReg  (BITS ( 0,  3))

#define DEST (state->Reg[DESTReg])

#ifdef MODE32
#ifdef MODET
#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
#else
#define LHS (state->Reg[LHSReg])
#endif
#else
#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]))
#endif

#define MULDESTReg (BITS (16, 19))
#define MULLHSReg  (BITS ( 0,  3))
#define MULRHSReg  (BITS ( 8, 11))
#define MULACCReg  (BITS (12, 15))

#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)])
#define DPSImmRHS temp = BITS(0,11) ; \
                  rhs = ARMul_ImmedTable[temp] ; \
                  if (temp > 255) /* There was a shift.  */ \
                     ASSIGNC (rhs >> 31) ;

#ifdef MODE32
#define DPRegRHS  ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
                                      : GetDPRegRHS (state, instr))
#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
                                      : GetDPSRegRHS (state, instr))
#else
#define DPRegRHS  ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
                                       : GetDPRegRHS (state, instr))
#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
                                       : GetDPSRegRHS (state, instr))
#endif

#define LSBase state->Reg[LHSReg]
#define LSImmRHS (BITS(0,11))

#ifdef MODE32
#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
                                      : GetLSRegRHS (state, instr))
#else
#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
                                      : GetLSRegRHS (state, instr))
#endif

#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \
                    (ARMword) ARMul_BitList[BITS (8, 15)] )
#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \
                      (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0))

#define SWAPSRC (state->Reg[RHSReg])

#define LSCOff (BITS (0, 7) << 2)
#define CPNum   BITS (8, 11)

/* Determine if access to coprocessor CP is permitted.
   The XScale has a register in CP15 which controls access to CP0 - CP13.  */
#define CP_ACCESS_ALLOWED(STATE, CP)			\
    (   ((CP) >= 14)					\
     || (! (STATE)->is_XScale)				\
     || (read_cp15_reg (15, 0, 1) & (1 << (CP))))

/* Macro to rotate n right by b bits.  */
#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))

/* Macros to store results of instructions.  */
#define WRITEDEST(d)				\
  do						\
    {						\
      if (DESTReg == 15) 			\
	WriteR15 (state, d); 			\
      else 					\
	DEST = d;				\
    }						\
  while (0)

#define WRITESDEST(d)				\
  do						\
    {						\
      if (DESTReg == 15)			\
	WriteSR15 (state, d);			\
      else					\
	{					\
	  DEST = d;				\
	  ARMul_NegZero (state, d);		\
	}					\
    }						\
  while (0)

#define WRITEDESTB(d)				\
  do						\
    {						\
      if (DESTReg == 15)			\
	WriteR15Branch (state, d);		\
      else					\
	DEST = d;				\
    }						\
  while (0)

#define BYTETOBUS(data) ((data & 0xff) | \
                        ((data & 0xff) << 8) | \
                        ((data & 0xff) << 16) | \
                        ((data & 0xff) << 24))

#define BUSTOBYTE(address, data)				\
  do								\
    {								\
      if (state->bigendSig) 					\
	temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff;	\
      else							\
	temp = (data >> ((address & 3) << 3)) & 0xff;		\
    }								\
  while (0)

#define LOADMULT(instr,   address, wb)  LoadMult   (state, instr, address, wb)
#define LOADSMULT(instr,  address, wb)  LoadSMult  (state, instr, address, wb)
#define STOREMULT(instr,  address, wb)  StoreMult  (state, instr, address, wb)
#define STORESMULT(instr, address, wb)  StoreSMult (state, instr, address, wb)

#define POSBRANCH ((instr & 0x7fffff) << 2)
#define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2)


/* Values for Emulate.  */
#define STOP            0	/* stop */
#define CHANGEMODE      1	/* change mode */
#define ONCE            2	/* execute just one interation */
#define RUN             3	/* continuous execution */

/* Stuff that is shared across modes.  */
extern unsigned ARMul_MultTable[];	/* Number of I cycles for a mult.  */
extern ARMword  ARMul_ImmedTable[];	/* Immediate DP LHS values.  */
extern char     ARMul_BitList[];	/* Number of bits in a byte table.  */

#define EVENTLISTSIZE 1024L

/* Thumb support.  */
typedef enum
{
  t_undefined,		/* Undefined Thumb instruction.  */
  t_decoded,		/* Instruction decoded to ARM equivalent.  */
  t_branch		/* Thumb branch (already processed).  */
}
tdstate;

/* Macros to scrutinize instructions.  */
#define UNDEF_Test
#define UNDEF_Shift
#define UNDEF_MSRPC
#define UNDEF_MRSPC
#define UNDEF_MULPCDest
#define UNDEF_MULDestEQOp1
#define UNDEF_LSRBPC
#define UNDEF_LSRBaseEQOffWb
#define UNDEF_LSRBaseEQDestWb
#define UNDEF_LSRPCBaseWb
#define UNDEF_LSRPCOffWb
#define UNDEF_LSMNoRegs
#define UNDEF_LSMPCBase
#define UNDEF_LSMUserBankWb
#define UNDEF_LSMBaseInListWb
#define UNDEF_SWPPC
#define UNDEF_CoProHS
#define UNDEF_MCRPC
#define UNDEF_LSCPCBaseWb
#define UNDEF_UndefNotBounced
#define UNDEF_ShortInt
#define UNDEF_IllegalMode
#define UNDEF_Prog32SigChange
#define UNDEF_Data32SigChange

/* Prototypes for exported functions.  */
extern unsigned ARMul_NthReg        (ARMword, unsigned);
extern int      AddOverflow         (ARMword, ARMword, ARMword);
extern int      SubOverflow         (ARMword, ARMword, ARMword);
extern ARMword  ARMul_Emulate26     (ARMul_State *);
extern ARMword  ARMul_Emulate32     (ARMul_State *);
extern unsigned IntPending          (ARMul_State *);
extern void     ARMul_CPSRAltered   (ARMul_State *);
extern void     ARMul_R15Altered    (ARMul_State *);
extern ARMword  ARMul_GetPC         (ARMul_State *);
extern ARMword  ARMul_GetNextPC     (ARMul_State *);
extern ARMword  ARMul_GetR15        (ARMul_State *);
extern ARMword  ARMul_GetCPSR       (ARMul_State *);
extern void     ARMul_EnvokeEvent   (ARMul_State *);
extern unsigned long ARMul_Time     (ARMul_State *);
extern void     ARMul_NegZero       (ARMul_State *, ARMword);
extern void     ARMul_SetPC         (ARMul_State *, ARMword);
extern void     ARMul_SetR15        (ARMul_State *, ARMword);
extern void     ARMul_SetCPSR       (ARMul_State *, ARMword);
extern ARMword  ARMul_GetSPSR       (ARMul_State *, ARMword);
extern void     ARMul_Abort26       (ARMul_State *, ARMword);
extern void     ARMul_Abort32       (ARMul_State *, ARMword);
extern ARMword  ARMul_MRC           (ARMul_State *, ARMword);
extern void     ARMul_CDP           (ARMul_State *, ARMword);
extern void     ARMul_LDC           (ARMul_State *, ARMword, ARMword);
extern void     ARMul_STC           (ARMul_State *, ARMword, ARMword);
extern void     ARMul_MCR           (ARMul_State *, ARMword, ARMword);
extern void     ARMul_SetSPSR       (ARMul_State *, ARMword, ARMword);
extern ARMword  ARMul_SwitchMode    (ARMul_State *, ARMword, ARMword);
extern ARMword  ARMul_Align         (ARMul_State *, ARMword, ARMword);
extern ARMword  ARMul_SwitchMode    (ARMul_State *, ARMword, ARMword);
extern void     ARMul_MSRCpsr       (ARMul_State *, ARMword, ARMword);
extern void     ARMul_SubOverflow   (ARMul_State *, ARMword, ARMword, ARMword);
extern void     ARMul_AddOverflow   (ARMul_State *, ARMword, ARMword, ARMword);
extern void     ARMul_SubCarry      (ARMul_State *, ARMword, ARMword, ARMword);
extern void     ARMul_AddCarry      (ARMul_State *, ARMword, ARMword, ARMword);
extern tdstate  ARMul_ThumbDecode   (ARMul_State *, ARMword, ARMword, ARMword *);
extern ARMword  ARMul_GetReg        (ARMul_State *, unsigned, unsigned);
extern void     ARMul_SetReg        (ARMul_State *, unsigned, unsigned, ARMword);
extern void     ARMul_ScheduleEvent (ARMul_State *, unsigned long, unsigned (*) (ARMul_State *));
/* Coprocessor support functions.  */
extern unsigned ARMul_CoProInit     (ARMul_State *);
extern void     ARMul_CoProExit     (ARMul_State *);
extern void     ARMul_CoProAttach   (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *,
				     ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *,
				     ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *);
extern void     ARMul_CoProDetach   (ARMul_State *, unsigned);
extern ARMword  read_cp15_reg       (unsigned, unsigned, unsigned);

extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned	DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned	DSPCDP4 (ARMul_State *, unsigned, ARMword);
extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned	DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned	DSPCDP5 (ARMul_State *, unsigned, ARMword);
extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned	DSPCDP6 (ARMul_State *, unsigned, ARMword);
Commit	Line	Data
c906108c SS	1	/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
	2	Copyright (C) 1994 Advanced RISC Machines Ltd.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
3fd725ef	6	the Free Software Foundation; either version 3 of the License, or
c906108c SS	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
51b318de	15	along with this program; if not, see <http://www.gnu.org/licenses/>. */
c906108c SS	16
	17	extern ARMword isize;
	18
ff44f8e3	19	/* Condition code values. */
c906108c SS	20	#define EQ 0
	21	#define NE 1
	22	#define CS 2
	23	#define CC 3
	24	#define MI 4
	25	#define PL 5
	26	#define VS 6
	27	#define VC 7
	28	#define HI 8
	29	#define LS 9
	30	#define GE 10
	31	#define LT 11
	32	#define GT 12
	33	#define LE 13
	34	#define AL 14
	35	#define NV 15
	36
ff44f8e3	37	/* Shift Opcodes. */
c906108c SS	38	#define LSL 0
	39	#define LSR 1
	40	#define ASR 2
	41	#define ROR 3
	42
ff44f8e3	43	/* Macros to twiddle the status flags and mode. */
c906108c SS	44	#define NBIT ((unsigned)1L << 31)
	45	#define ZBIT (1L << 30)
	46	#define CBIT (1L << 29)
	47	#define VBIT (1L << 28)
f1129fb8	48	#define SBIT (1L << 27)
c906108c SS	49	#define IBIT (1L << 7)
	50	#define FBIT (1L << 6)
	51	#define IFBITS (3L << 6)
	52	#define R15IBIT (1L << 27)
	53	#define R15FBIT (1L << 26)
	54	#define R15IFBITS (3L << 26)
	55
	56	#define POS(i) ( (~(i)) >> 31 )
	57	#define NEG(i) ( (i) >> 31 )
	58
ff44f8e3	59	#ifdef MODET /* Thumb support. */
c906108c SS	60	/* ??? This bit is actually in the low order bit of the PC in the hardware.
	61	It isn't clear if the simulator needs to model that or not. */
	62	#define TBIT (1L << 5)
	63	#define TFLAG state->TFlag
	64	#define SETT state->TFlag = 1
	65	#define CLEART state->TFlag = 0
	66	#define ASSIGNT(res) state->TFlag = res
e063aa3b AO	67	#define INSN_SIZE (TFLAG ? 2 : 4)
	68	#else
	69	#define INSN_SIZE 4
c906108c SS	70	#endif
	71
	72	#define NFLAG state->NFlag
	73	#define SETN state->NFlag = 1
	74	#define CLEARN state->NFlag = 0
	75	#define ASSIGNN(res) state->NFlag = res
	76
	77	#define ZFLAG state->ZFlag
	78	#define SETZ state->ZFlag = 1
	79	#define CLEARZ state->ZFlag = 0
	80	#define ASSIGNZ(res) state->ZFlag = res
	81
	82	#define CFLAG state->CFlag
	83	#define SETC state->CFlag = 1
	84	#define CLEARC state->CFlag = 0
	85	#define ASSIGNC(res) state->CFlag = res
	86
	87	#define VFLAG state->VFlag
	88	#define SETV state->VFlag = 1
	89	#define CLEARV state->VFlag = 0
	90	#define ASSIGNV(res) state->VFlag = res
	91
f1129fb8 NC	92	#define SFLAG state->SFlag
	93	#define SETS state->SFlag = 1
	94	#define CLEARS state->SFlag = 0
	95	#define ASSIGNS(res) state->SFlag = res
f743149e	96
c906108c SS	97	#define IFLAG (state->IFFlags >> 1)
	98	#define FFLAG (state->IFFlags & 1)
	99	#define IFFLAGS state->IFFlags
	100	#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
	101	#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
	102
4ef2594f AO	103	#define PSR_FBITS (0xff000000L)
	104	#define PSR_SBITS (0x00ff0000L)
	105	#define PSR_XBITS (0x0000ff00L)
	106	#define PSR_CBITS (0x000000ffL)
	107
f1129fb8 NC	108	#if defined MODE32 \|\| defined MODET
	109	#define CCBITS (0xf8000000L)
	110	#else
c906108c	111	#define CCBITS (0xf0000000L)
f1129fb8 NC	112	#endif
f1129fb8 NC	113
c906108c SS	114	#define INTBITS (0xc0L)
	115
	116	#if defined MODET && defined MODE32
	117	#define PCBITS (0xffffffffL)
	118	#else
	119	#define PCBITS (0xfffffffcL)
	120	#endif
	121
	122	#define MODEBITS (0x1fL)
	123	#define R15INTBITS (3L << 26)
	124
	125	#if defined MODET && defined MODE32
	126	#define R15PCBITS (0x03ffffffL)
	127	#else
	128	#define R15PCBITS (0x03fffffcL)
	129	#endif
	130
	131	#define R15PCMODEBITS (0x03ffffffL)
	132	#define R15MODEBITS (0x3L)
	133
	134	#ifdef MODE32
	135	#define PCMASK PCBITS
	136	#define PCWRAP(pc) (pc)
	137	#else
	138	#define PCMASK R15PCBITS
	139	#define PCWRAP(pc) ((pc) & R15PCBITS)
	140	#endif
	141
	142	#define PC (state->Reg[15] & PCMASK)
	143	#define R15CCINTMODE (state->Reg[15] & (CCBITS \| R15INTBITS \| R15MODEBITS))
	144	#define R15INT (state->Reg[15] & R15INTBITS)
	145	#define R15INTPC (state->Reg[15] & (R15INTBITS \| R15PCBITS))
	146	#define R15INTPCMODE (state->Reg[15] & (R15INTBITS \| R15PCBITS \| R15MODEBITS))
	147	#define R15INTMODE (state->Reg[15] & (R15INTBITS \| R15MODEBITS))
	148	#define R15PC (state->Reg[15] & R15PCBITS)
	149	#define R15PCMODE (state->Reg[15] & (R15PCBITS \| R15MODEBITS))
	150	#define R15MODE (state->Reg[15] & R15MODEBITS)
	151
f1129fb8	152	#define ECC ((NFLAG << 31) \| (ZFLAG << 30) \| (CFLAG << 29) \| (VFLAG << 28) \| (SFLAG << 27))
c906108c SS	153	#define EINT (IFFLAGS << 6)
	154	#define ER15INT (IFFLAGS << 26)
	155	#define EMODE (state->Mode)
	156
	157	#ifdef MODET
	158	#define CPSR (ECC \| EINT \| EMODE \| (TFLAG << 5))
	159	#else
	160	#define CPSR (ECC \| EINT \| EMODE)
	161	#endif
	162
	163	#ifdef MODE32
	164	#define PATCHR15
	165	#else
	166	#define PATCHR15 state->Reg[15] = ECC \| ER15INT \| EMODE \| R15PC
	167	#endif
	168
cf52c765	169	#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
4ef2594f AO	170	#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) \| ((s) & PSR_FBITS)
	171	#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) \| ((s) & PSR_SBITS)
	172	#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) \| ((s) & PSR_XBITS)
	173	#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) \| ((s) & PSR_CBITS)
ff44f8e3 NC	174
	175	#define SETR15PSR(s) \
	176	do \
	177	{ \
	178	if (state->Mode == USER26MODE) \
	179	{ \
	180	state->Reg[15] = ((s) & CCBITS) \| R15PC \| ER15INT \| EMODE; \
	181	ASSIGNN ((state->Reg[15] & NBIT) != 0); \
	182	ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \
	183	ASSIGNC ((state->Reg[15] & CBIT) != 0); \
	184	ASSIGNV ((state->Reg[15] & VBIT) != 0); \
	185	} \
	186	else \
	187	{ \
	188	state->Reg[15] = R15PC \| ((s) & (CCBITS \| R15INTBITS \| R15MODEBITS)); \
	189	ARMul_R15Altered (state); \
	190	} \
	191	} \
	192	while (0)
	193
	194	#define SETABORT(i, m, d) \
	195	do \
	196	{ \
	197	int SETABORT_mode = (m); \
	198	\
	199	ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
	200	ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE \| TBIT)) \
	201	\| (i) \| SETABORT_mode)); \
	202	state->Reg[14] = temp - (d); \
	203	} \
	204	while (0)
c906108c SS	205
	206	#ifndef MODE32
	207	#define VECTORS 0x20
	208	#define LEGALADDR 0x03ffffff
	209	#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
ff44f8e3	210	#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
c906108c SS	211	#endif
c906108c SS	212
ff44f8e3 NC	213	#define INTERNALABORT(address) \
	214	do \
	215	{ \
	216	if (address < VECTORS) \
	217	state->Aborted = ARMul_DataAbortV; \
	218	else \
	219	state->Aborted = ARMul_AddrExceptnV; \
	220	} \
	221	while (0)
c906108c SS	222
c906108c SS	223	#ifdef MODE32
ff44f8e3	224	#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV)
c906108c	225	#else
ff44f8e3 NC	226	#define TAKEABORT \
	227	do \
	228	{ \
	229	if (state->Aborted == ARMul_AddrExceptnV) \
	230	ARMul_Abort (state, ARMul_AddrExceptnV); \
	231	else \
	232	ARMul_Abort (state, ARMul_DataAbortV); \
	233	} \
	234	while (0)
c906108c	235	#endif
c906108c	236
ff44f8e3 NC	237	#define CPTAKEABORT \
	238	do \
	239	{ \
	240	if (!state->Aborted) \
	241	ARMul_Abort (state, ARMul_UndefinedInstrV); \
	242	else if (state->Aborted == ARMul_AddrExceptnV) \
	243	ARMul_Abort (state, ARMul_AddrExceptnV); \
	244	else \
	245	ARMul_Abort (state, ARMul_DataAbortV); \
	246	} \
	247	while (0);
	248
	249
	250	/* Different ways to start the next instruction. */
	251	#define SEQ 0
	252	#define NONSEQ 1
	253	#define PCINCEDSEQ 2
c906108c	254	#define PCINCEDNONSEQ 3
ff44f8e3 NC	255	#define PRIMEPIPE 4
ff44f8e3 NC	256	#define RESUME 8
c906108c SS	257
c906108c SS	258	#define NORMALCYCLE state->NextInstr = 0
3943c96b	259	#define BUSUSEDN state->NextInstr \|= 1 /* The next fetch will be an N cycle. */
ff44f8e3 NC	260	#define BUSUSEDINCPCS \
	261	do \
	262	{ \
	263	if (! state->is_v4) \
	264	{ \
	265	/* A standard PC inc and an S cycle. */ \
	266	state->Reg[15] += isize; \
	267	state->NextInstr = (state->NextInstr & 0xff) \| 2; \
	268	} \
	269	} \
3943c96b	270	while (0)
ff44f8e3 NC	271
	272	#define BUSUSEDINCPCN \
	273	do \
	274	{ \
	275	if (state->is_v4) \
	276	BUSUSEDN; \
	277	else \
	278	{ \
	279	/* A standard PC inc and an N cycle. */ \
	280	state->Reg[15] += isize; \
	281	state->NextInstr \|= 3; \
	282	} \
	283	} \
3943c96b	284	while (0)
ff44f8e3 NC	285
	286	#define INCPC \
	287	do \
	288	{ \
	289	/* A standard PC inc. */ \
	290	state->Reg[15] += isize; \
	291	state->NextInstr \|= 2; \
	292	} \
	293	while (0)
	294
c906108c SS	295	#define FLUSHPIPE state->NextInstr \|= PRIMEPIPE
c906108c SS	296
ff44f8e3	297	/* Cycle based emulation. */
c906108c SS	298
	299	#define OUTPUTCP(i,a,b)
	300	#define NCYCLE
	301	#define SCYCLE
	302	#define ICYCLE
	303	#define CCYCLE
	304	#define NEXTCYCLE(c)
	305
ff44f8e3	306	/* Macros to extract parts of instructions. */
57165fb4 NC	307	#define DESTReg (BITS (12, 15))
	308	#define LHSReg (BITS (16, 19))
	309	#define RHSReg (BITS ( 0, 3))
c906108c SS	310
	311	#define DEST (state->Reg[DESTReg])
	312
	313	#ifdef MODE32
	314	#ifdef MODET
	315	#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
	316	#else
	317	#define LHS (state->Reg[LHSReg])
	318	#endif
	319	#else
ff44f8e3	320	#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]))
c906108c SS	321	#endif
c906108c SS	322
ff44f8e3 NC	323	#define MULDESTReg (BITS (16, 19))
	324	#define MULLHSReg (BITS ( 0, 3))
	325	#define MULRHSReg (BITS ( 8, 11))
	326	#define MULACCReg (BITS (12, 15))
c906108c	327
ff44f8e3	328	#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)])
c906108c SS	329	#define DPSImmRHS temp = BITS(0,11) ; \
c906108c SS	330	rhs = ARMul_ImmedTable[temp] ; \
ff44f8e3 NC	331	if (temp > 255) /* There was a shift. */ \
ff44f8e3 NC	332	ASSIGNC (rhs >> 31) ;
c906108c SS	333
c906108c SS	334	#ifdef MODE32
ff44f8e3 NC	335	#define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
	336	: GetDPRegRHS (state, instr))
	337	#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
	338	: GetDPSRegRHS (state, instr))
c906108c	339	#else
ff44f8e3 NC	340	#define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
	341	: GetDPRegRHS (state, instr))
	342	#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
	343	: GetDPSRegRHS (state, instr))
c906108c SS	344	#endif
	345
	346	#define LSBase state->Reg[LHSReg]
	347	#define LSImmRHS (BITS(0,11))
	348
	349	#ifdef MODE32
ff44f8e3 NC	350	#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
ff44f8e3 NC	351	: GetLSRegRHS (state, instr))
c906108c	352	#else
ff44f8e3 NC	353	#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
ff44f8e3 NC	354	: GetLSRegRHS (state, instr))
c906108c SS	355	#endif
c906108c SS	356
ff44f8e3 NC	357	#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \
	358	(ARMword) ARMul_BitList[BITS (8, 15)] )
	359	#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) \|\| \
	360	(BIT (LHSReg) && BITS (0, LHSReg - 1) == 0))
c906108c SS	361
	362	#define SWAPSRC (state->Reg[RHSReg])
	363
ff44f8e3 NC	364	#define LSCOff (BITS (0, 7) << 2)
ff44f8e3 NC	365	#define CPNum BITS (8, 11)
c906108c	366
ff44f8e3 NC	367	/* Determine if access to coprocessor CP is permitted.
ff44f8e3 NC	368	The XScale has a register in CP15 which controls access to CP0 - CP13. */
57165fb4 NC	369	#define CP_ACCESS_ALLOWED(STATE, CP) \
	370	( ((CP) >= 14) \
	371	\|\| (! (STATE)->is_XScale) \
ff44f8e3	372	\|\| (read_cp15_reg (15, 0, 1) & (1 << (CP))))
c906108c	373
ff44f8e3 NC	374	/* Macro to rotate n right by b bits. */
ff44f8e3 NC	375	#define ROTATER(n, b) (((n) >> (b)) \| ((n) << (32 - (b))))
c906108c	376
ff44f8e3	377	/* Macros to store results of instructions. */
57165fb4 NC	378	#define WRITEDEST(d) \
	379	do \
	380	{ \
	381	if (DESTReg == 15) \
	382	WriteR15 (state, d); \
	383	else \
	384	DEST = d; \
	385	} \
	386	while (0)
	387
	388	#define WRITESDEST(d) \
	389	do \
	390	{ \
	391	if (DESTReg == 15) \
	392	WriteSR15 (state, d); \
	393	else \
	394	{ \
	395	DEST = d; \
	396	ARMul_NegZero (state, d); \
	397	} \
	398	} \
	399	while (0)
	400
	401	#define WRITEDESTB(d) \
	402	do \
	403	{ \
	404	if (DESTReg == 15) \
	405	WriteR15Branch (state, d); \
	406	else \
	407	DEST = d; \
	408	} \
	409	while (0)
892c6b9d	410
c906108c SS	411	#define BYTETOBUS(data) ((data & 0xff) \| \
	412	((data & 0xff) << 8) \| \
	413	((data & 0xff) << 16) \| \
	414	((data & 0xff) << 24))
ff44f8e3	415
57165fb4 NC	416	#define BUSTOBYTE(address, data) \
	417	do \
	418	{ \
	419	if (state->bigendSig) \
	420	temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \
	421	else \
	422	temp = (data >> ((address & 3) << 3)) & 0xff; \
	423	} \
	424	while (0)
c906108c	425
ff44f8e3 NC	426	#define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb)
	427	#define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb)
	428	#define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb)
	429	#define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb)
c906108c SS	430
c906108c SS	431	#define POSBRANCH ((instr & 0x7fffff) << 2)
179ae6ea NC	432	#define NEGBRANCH ((0xff000000 \|(instr & 0xffffff)) << 2)
179ae6ea NC	433
c906108c	434
ff44f8e3	435	/* Values for Emulate. */
dfcd3bfb JM	436	#define STOP 0 /* stop */
	437	#define CHANGEMODE 1 /* change mode */
	438	#define ONCE 2 /* execute just one interation */
	439	#define RUN 3 /* continuous execution */
c906108c	440
ff44f8e3 NC	441	/* Stuff that is shared across modes. */
	442	extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */
	443	extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */
	444	extern char ARMul_BitList[]; /* Number of bits in a byte table. */
c906108c	445
ff44f8e3	446	#define EVENTLISTSIZE 1024L
c906108c	447
ff44f8e3	448	/* Thumb support. */
dfcd3bfb JM	449	typedef enum
dfcd3bfb JM	450	{
ff44f8e3 NC	451	t_undefined, /* Undefined Thumb instruction. */
	452	t_decoded, /* Instruction decoded to ARM equivalent. */
	453	t_branch /* Thumb branch (already processed). */
dfcd3bfb JM	454	}
dfcd3bfb JM	455	tdstate;
c906108c	456
ff44f8e3	457	/* Macros to scrutinize instructions. */
c906108c SS	458	#define UNDEF_Test
	459	#define UNDEF_Shift
	460	#define UNDEF_MSRPC
	461	#define UNDEF_MRSPC
	462	#define UNDEF_MULPCDest
	463	#define UNDEF_MULDestEQOp1
	464	#define UNDEF_LSRBPC
	465	#define UNDEF_LSRBaseEQOffWb
	466	#define UNDEF_LSRBaseEQDestWb
	467	#define UNDEF_LSRPCBaseWb
	468	#define UNDEF_LSRPCOffWb
	469	#define UNDEF_LSMNoRegs
	470	#define UNDEF_LSMPCBase
	471	#define UNDEF_LSMUserBankWb
	472	#define UNDEF_LSMBaseInListWb
	473	#define UNDEF_SWPPC
	474	#define UNDEF_CoProHS
	475	#define UNDEF_MCRPC
	476	#define UNDEF_LSCPCBaseWb
	477	#define UNDEF_UndefNotBounced
	478	#define UNDEF_ShortInt
	479	#define UNDEF_IllegalMode
	480	#define UNDEF_Prog32SigChange
	481	#define UNDEF_Data32SigChange
f1129fb8	482
ff44f8e3 NC	483	/* Prototypes for exported functions. */
	484	extern unsigned ARMul_NthReg (ARMword, unsigned);
	485	extern int AddOverflow (ARMword, ARMword, ARMword);
	486	extern int SubOverflow (ARMword, ARMword, ARMword);
	487	extern ARMword ARMul_Emulate26 (ARMul_State *);
	488	extern ARMword ARMul_Emulate32 (ARMul_State *);
	489	extern unsigned IntPending (ARMul_State *);
	490	extern void ARMul_CPSRAltered (ARMul_State *);
	491	extern void ARMul_R15Altered (ARMul_State *);
	492	extern ARMword ARMul_GetPC (ARMul_State *);
	493	extern ARMword ARMul_GetNextPC (ARMul_State *);
	494	extern ARMword ARMul_GetR15 (ARMul_State *);
	495	extern ARMword ARMul_GetCPSR (ARMul_State *);
	496	extern void ARMul_EnvokeEvent (ARMul_State *);
	497	extern unsigned long ARMul_Time (ARMul_State *);
	498	extern void ARMul_NegZero (ARMul_State *, ARMword);
	499	extern void ARMul_SetPC (ARMul_State *, ARMword);
	500	extern void ARMul_SetR15 (ARMul_State *, ARMword);
	501	extern void ARMul_SetCPSR (ARMul_State *, ARMword);
	502	extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword);
	503	extern void ARMul_Abort26 (ARMul_State *, ARMword);
	504	extern void ARMul_Abort32 (ARMul_State *, ARMword);
	505	extern ARMword ARMul_MRC (ARMul_State *, ARMword);
	506	extern void ARMul_CDP (ARMul_State *, ARMword);
	507	extern void ARMul_LDC (ARMul_State *, ARMword, ARMword);
	508	extern void ARMul_STC (ARMul_State *, ARMword, ARMword);
	509	extern void ARMul_MCR (ARMul_State *, ARMword, ARMword);
	510	extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword);
	511	extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
	512	extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword);
	513	extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
	514	extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword);
	515	extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword);
	516	extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword);
	517	extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword);
	518	extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
	519	extern tdstate ARMul_ThumbDecode (ARMul_State , ARMword, ARMword, ARMword );
	520	extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned);
	521	extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword);
	522	extern void ARMul_ScheduleEvent (ARMul_State , unsigned long, unsigned () (ARMul_State *));
f1129fb8	523	/* Coprocessor support functions. */
ff44f8e3 NC	524	extern unsigned ARMul_CoProInit (ARMul_State *);
	525	extern void ARMul_CoProExit (ARMul_State *);
	526	extern void ARMul_CoProAttach (ARMul_State , unsigned, ARMul_CPInits , ARMul_CPExits *,
	527	ARMul_LDCs , ARMul_STCs , ARMul_MRCs , ARMul_MCRs ,
	528	ARMul_CDPs , ARMul_CPReads , ARMul_CPWrites *);
	529	extern void ARMul_CoProDetach (ARMul_State *, unsigned);
	530	extern ARMword read_cp15_reg (unsigned, unsigned, unsigned);
	531
f603c8fe NC	532	extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword);
	533	extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword);
	534	extern unsigned DSPMRC4 (ARMul_State , unsigned, ARMword, ARMword );
	535	extern unsigned DSPSTC4 (ARMul_State , unsigned, ARMword, ARMword );
	536	extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword);
	537	extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword);
	538	extern unsigned DSPMRC5 (ARMul_State , unsigned, ARMword, ARMword );
	539	extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword);
	540	extern unsigned DSPSTC5 (ARMul_State , unsigned, ARMword, ARMword );
	541	extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword);
	542	extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword);
	543	extern unsigned DSPMRC6 (ARMul_State , unsigned, ARMword, ARMword );
	544	extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword);