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df1756f4 1/* Simulator for Atmel's AVR core.
618f726f 2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
df1756f4
TG		 3 Written by Tristan Gingold, AdaCore.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "config.h"
21
22#ifdef HAVE_STRING_H
23#include <string.h>
24#endif
25#include "bfd.h"
df1756f4
TG		 26#include "libiberty.h"
27#include "gdb/remote-sim.h"
9943d318
MF		 28
29#include "sim-main.h"
30#include "sim-base.h"
31#include "sim-options.h"
df1756f4
TG		 32
33/* As AVR is a 8/16 bits processor, define handy types. */
34typedef unsigned short int word;
35typedef signed short int sword;
36typedef unsigned char byte;
37typedef signed char sbyte;
38
df1756f4
TG		 39/* Max size of I space (which is always flash on avr). */
40#define MAX_AVR_FLASH (128 * 1024)
41#define PC_MASK (MAX_AVR_FLASH - 1)
42
43/* Mac size of D space. */
44#define MAX_AVR_SRAM (64 * 1024)
45#define SRAM_MASK (MAX_AVR_SRAM - 1)
46
47/* D space offset in ELF file. */
48#define SRAM_VADDR 0x800000
49
50/* Simulator specific ports. */
51#define STDIO_PORT 0x52
52#define EXIT_PORT 0x4F
53#define ABORT_PORT 0x49
54
55/* GDB defined register numbers. */
56#define AVR_SREG_REGNUM 32
57#define AVR_SP_REGNUM 33
58#define AVR_PC_REGNUM 34
59
60/* Memory mapped registers. */
61#define SREG 0x5F
62#define REG_SP 0x5D
63#define EIND 0x5C
64#define RAMPZ 0x5B
65
66#define REGX 0x1a
67#define REGY 0x1c
68#define REGZ 0x1e
69#define REGZ_LO 0x1e
70#define REGZ_HI 0x1f
71
72/* Sreg (status) bits. */
73#define SREG_I 0x80
74#define SREG_T 0x40
75#define SREG_H 0x20
76#define SREG_S 0x10
77#define SREG_V 0x08
78#define SREG_N 0x04
79#define SREG_Z 0x02
80#define SREG_C 0x01
81
82/* In order to speed up emulation we use a simple approach:
83 a code is associated with each instruction. The pre-decoding occurs
84 usually once when the instruction is first seen.
85 This works well because I&D spaces are separated.
86
87 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
88*/
89enum avr_opcode
90 {
91 /* Opcode not yet decoded. */
92 OP_unknown,
93 OP_bad,
94
95 OP_nop,
96
97 OP_rjmp,
98 OP_rcall,
99 OP_ret,
100 OP_reti,
101
102 OP_break,
103
104 OP_brbs,
105 OP_brbc,
106
107 OP_bset,
108 OP_bclr,
109
110 OP_bld,
111 OP_bst,
112
113 OP_sbrc,
114 OP_sbrs,
115
116 OP_eor,
117 OP_and,
118 OP_andi,
119 OP_or,
120 OP_ori,
121 OP_com,
122 OP_swap,
123 OP_neg,
124
125 OP_out,
126 OP_in,
127 OP_cbi,
128 OP_sbi,
129
130 OP_sbic,
131 OP_sbis,
132
133 OP_ldi,
134 OP_cpse,
135 OP_cp,
136 OP_cpi,
137 OP_cpc,
138 OP_sub,
139 OP_sbc,
140 OP_sbiw,
141 OP_adiw,
142 OP_add,
143 OP_adc,
144 OP_subi,
145 OP_sbci,
146 OP_inc,
147 OP_dec,
148 OP_lsr,
149 OP_ror,
150 OP_asr,
151
152 OP_mul,
153 OP_muls,
154 OP_mulsu,
155 OP_fmul,
156 OP_fmuls,
157 OP_fmulsu,
158
159 OP_mov,
160 OP_movw,
161
162 OP_push,
163 OP_pop,
164
165 OP_st_X,
166 OP_st_dec_X,
167 OP_st_X_inc,
168 OP_st_Y_inc,
169 OP_st_dec_Y,
170 OP_st_Z_inc,
171 OP_st_dec_Z,
172 OP_std_Y,
173 OP_std_Z,
174 OP_ldd_Y,
175 OP_ldd_Z,
176 OP_ld_Z_inc,
177 OP_ld_dec_Z,
178 OP_ld_Y_inc,
179 OP_ld_dec_Y,
180 OP_ld_X,
181 OP_ld_X_inc,
182 OP_ld_dec_X,
183
184 OP_lpm,
185 OP_lpm_Z,
186 OP_lpm_inc_Z,
187 OP_elpm,
188 OP_elpm_Z,
189 OP_elpm_inc_Z,
190
191 OP_ijmp,
192 OP_icall,
193
194 OP_eijmp,
195 OP_eicall,
196
197 /* 2 words opcodes. */
198#define OP_2words OP_jmp
199 OP_jmp,
200 OP_call,
201 OP_sts,
202 OP_lds
203 };
204
205struct avr_insn_cell
206{
207 /* The insn (16 bits). */
208 word op;
209
210 /* Pre-decoding code. */
211 enum avr_opcode code : 8;
212 /* One byte of additional information. */
213 byte r;
214};
215
216/* I&D memories. */
9943d318 217/* TODO: Should be moved to SIM_CPU. */
df1756f4
TG		 218static struct avr_insn_cell flash[MAX_AVR_FLASH];
219static byte sram[MAX_AVR_SRAM];
220
df1756f4
TG		 221/* Sign extend a value. */
222static int sign_ext (word val, int nb_bits)
223{
224 if (val & (1 << (nb_bits - 1)))
1d19cae7 225 return val | -(1 << nb_bits);
df1756f4
TG		 226 return val;
227}
228
229/* Insn field extractors. */
230
231/* Extract xxxx_xxxRx_xxxx_RRRR. */
232static inline byte get_r (word op)
233{
234 return (op & 0xf) | ((op >> 5) & 0x10);
235}
236
237/* Extract xxxx_xxxxx_xxxx_RRRR. */
238static inline byte get_r16 (word op)
239{
240 return 16 + (op & 0xf);
241}
242
243/* Extract xxxx_xxxxx_xxxx_xRRR. */
244static inline byte get_r16_23 (word op)
245{
246 return 16 + (op & 0x7);
247}
248
249/* Extract xxxx_xxxD_DDDD_xxxx. */
250static inline byte get_d (word op)
251{
252 return (op >> 4) & 0x1f;
253}
254
255/* Extract xxxx_xxxx_DDDD_xxxx. */
256static inline byte get_d16 (word op)
257{
258 return 16 + ((op >> 4) & 0x0f);
259}
260
261/* Extract xxxx_xxxx_xDDD_xxxx. */
262static inline byte get_d16_23 (word op)
263{
264 return 16 + ((op >> 4) & 0x07);
265}
266
267/* Extract xxxx_xAAx_xxxx_AAAA. */
268static inline byte get_A (word op)
269{
270 return (op & 0x0f) | ((op & 0x600) >> 5);
271}
272
273/* Extract xxxx_xxxx_AAAA_Axxx. */
274static inline byte get_biA (word op)
275{
276 return (op >> 3) & 0x1f;
277}
278
279/* Extract xxxx_KKKK_xxxx_KKKK. */
280static inline byte get_K (word op)
281{
282 return (op & 0xf) | ((op & 0xf00) >> 4);
283}
284
285/* Extract xxxx_xxKK_KKKK_Kxxx. */
286static inline int get_k (word op)
287{
288 return sign_ext ((op & 0x3f8) >> 3, 7);
289}
290
291/* Extract xxxx_xxxx_xxDD_xxxx. */
292static inline byte get_d24 (word op)
293{
294 return 24 + ((op >> 3) & 6);
295}
296
297/* Extract xxxx_xxxx_KKxx_KKKK. */
298static inline byte get_k6 (word op)
299{
300 return (op & 0xf) | ((op >> 2) & 0x30);
301}
302
303/* Extract xxQx_QQxx_xxxx_xQQQ. */
304static inline byte get_q (word op)
305{
306 return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20);
307}
308
309/* Extract xxxx_xxxx_xxxx_xBBB. */
310static inline byte get_b (word op)
311{
312 return (op & 7);
313}
314
315/* AVR is little endian. */
316static inline word
317read_word (unsigned int addr)
318{
319 return sram[addr] | (sram[addr + 1] << 8);
320}
321
322static inline void
323write_word (unsigned int addr, word w)
324{
325 sram[addr] = w;
326 sram[addr + 1] = w >> 8;
327}
328
329static inline word
330read_word_post_inc (unsigned int addr)
331{
332 word v = read_word (addr);
333 write_word (addr, v + 1);
334 return v;
335}
336
337static inline word
338read_word_pre_dec (unsigned int addr)
339{
340 word v = read_word (addr) - 1;
341 write_word (addr, v);
342 return v;
343}
344
345static void
346update_flags_logic (byte res)
347{
348 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
349 if (res == 0)
350 sram[SREG] |= SREG_Z;
351 if (res & 0x80)
352 sram[SREG] |= SREG_N | SREG_S;
353}
354
355static void
356update_flags_add (byte r, byte a, byte b)
357{
358 byte carry;
359
360 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
361 if (r & 0x80)
362 sram[SREG] |= SREG_N;
363 carry = (a & b) | (a & ~r) | (b & ~r);
364 if (carry & 0x08)
365 sram[SREG] |= SREG_H;
366 if (carry & 0x80)
367 sram[SREG] |= SREG_C;
368 if (((a & b & ~r) | (~a & ~b & r)) & 0x80)
369 sram[SREG] |= SREG_V;
370 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
371 sram[SREG] |= SREG_S;
372 if (r == 0)
373 sram[SREG] |= SREG_Z;
374}
375
376static void update_flags_sub (byte r, byte a, byte b)
377{
378 byte carry;
379
380 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
381 if (r & 0x80)
382 sram[SREG] |= SREG_N;
383 carry = (~a & b) | (b & r) | (r & ~a);
384 if (carry & 0x08)
385 sram[SREG] |= SREG_H;
386 if (carry & 0x80)
387 sram[SREG] |= SREG_C;
388 if (((a & ~b & ~r) | (~a & b & r)) & 0x80)
389 sram[SREG] |= SREG_V;
390 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
391 sram[SREG] |= SREG_S;
392 /* Note: Z is not set. */
393}
394
395static enum avr_opcode
396decode (unsigned int pc)
397{
398 word op1 = flash[pc].op;
399
400 switch ((op1 >> 12) & 0x0f)
401 {
402 case 0x0:
403 switch ((op1 >> 10) & 0x3)
404 {
405 case 0x0:
406 switch ((op1 >> 8) & 0x3)
407 {
408 case 0x0:
409 if (op1 == 0)
410 return OP_nop;
411 break;
412 case 0x1:
413 return OP_movw;
414 case 0x2:
415 return OP_muls;
416 case 0x3:
417 if (op1 & 0x80)
418 {
419 if (op1 & 0x08)
420 return OP_fmulsu;
421 else
422 return OP_fmuls;
423 }
424 else
425 {
426 if (op1 & 0x08)
427 return OP_fmul;
428 else
429 return OP_mulsu;
430 }
431 }
432 break;
433 case 0x1:
434 return OP_cpc;
435 case 0x2:
436 flash[pc].r = SREG_C;
437 return OP_sbc;
438 case 0x3:
439 flash[pc].r = 0;
440 return OP_add;
441 }
442 break;
443 case 0x1:
444 switch ((op1 >> 10) & 0x3)
445 {
446 case 0x0:
447 return OP_cpse;
448 case 0x1:
449 return OP_cp;
450 case 0x2:
451 flash[pc].r = 0;
452 return OP_sub;
453 case 0x3:
454 flash[pc].r = SREG_C;
455 return OP_adc;
456 }
457 break;
458 case 0x2:
459 switch ((op1 >> 10) & 0x3)
460 {
461 case 0x0:
462 return OP_and;
463 case 0x1:
464 return OP_eor;
465 case 0x2:
466 return OP_or;
467 case 0x3:
468 return OP_mov;
469 }
470 break;
471 case 0x3:
472 return OP_cpi;
473 case 0x4:
474 return OP_sbci;
475 case 0x5:
476 return OP_subi;
477 case 0x6:
478 return OP_ori;
479 case 0x7:
480 return OP_andi;
481 case 0x8:
482 case 0xa:
483 if (op1 & 0x0200)
484 {
485 if (op1 & 0x0008)
486 {
487 flash[pc].r = get_q (op1);
488 return OP_std_Y;
489 }
490 else
491 {
492 flash[pc].r = get_q (op1);
493 return OP_std_Z;
494 }
495 }
496 else
497 {
498 if (op1 & 0x0008)
499 {
500 flash[pc].r = get_q (op1);
501 return OP_ldd_Y;
502 }
503 else
504 {
505 flash[pc].r = get_q (op1);
506 return OP_ldd_Z;
507 }
508 }
509 break;
510 case 0x9: /* 9xxx */
511 switch ((op1 >> 8) & 0xf)
512 {
513 case 0x0:
514 case 0x1:
515 switch ((op1 >> 0) & 0xf)
516 {
517 case 0x0:
518 return OP_lds;
519 case 0x1:
520 return OP_ld_Z_inc;
521 case 0x2:
522 return OP_ld_dec_Z;
523 case 0x4:
524 return OP_lpm_Z;
525 case 0x5:
526 return OP_lpm_inc_Z;
527 case 0x6:
528 return OP_elpm_Z;
529 case 0x7:
530 return OP_elpm_inc_Z;
531 case 0x9:
532 return OP_ld_Y_inc;
533 case 0xa:
534 return OP_ld_dec_Y;
535 case 0xc:
536 return OP_ld_X;
537 case 0xd:
538 return OP_ld_X_inc;
539 case 0xe:
540 return OP_ld_dec_X;
541 case 0xf:
542 return OP_pop;
543 }
544 break;
545 case 0x2:
546 case 0x3:
547 switch ((op1 >> 0) & 0xf)
548 {
549 case 0x0:
550 return OP_sts;
551 case 0x1:
552 return OP_st_Z_inc;
553 case 0x2:
554 return OP_st_dec_Z;
555 case 0x9:
556 return OP_st_Y_inc;
557 case 0xa:
558 return OP_st_dec_Y;
559 case 0xc:
560 return OP_st_X;
561 case 0xd:
562 return OP_st_X_inc;
563 case 0xe:
564 return OP_st_dec_X;
565 case 0xf:
566 return OP_push;
567 }
568 break;
569 case 0x4:
570 case 0x5:
571 switch (op1 & 0xf)
572 {
573 case 0x0:
574 return OP_com;
575 case 0x1:
576 return OP_neg;
577 case 0x2:
578 return OP_swap;
579 case 0x3:
580 return OP_inc;
581 case 0x5:
582 flash[pc].r = 0x80;
583 return OP_asr;
584 case 0x6:
585 flash[pc].r = 0;
586 return OP_lsr;
587 case 0x7:
588 return OP_ror;
589 case 0x8: /* 9[45]x8 */
590 switch ((op1 >> 4) & 0x1f)
591 {
592 case 0x00:
593 case 0x01:
594 case 0x02:
595 case 0x03:
596 case 0x04:
597 case 0x05:
598 case 0x06:
599 case 0x07:
600 return OP_bset;
601 case 0x08:
602 case 0x09:
603 case 0x0a:
604 case 0x0b:
605 case 0x0c:
606 case 0x0d:
607 case 0x0e:
608 case 0x0f:
609 return OP_bclr;
610 case 0x10:
611 return OP_ret;
612 case 0x11:
613 return OP_reti;
614 case 0x19:
615 return OP_break;
616 case 0x1c:
617 return OP_lpm;
618 case 0x1d:
619 return OP_elpm;
620 default:
621 break;
622 }
623 break;
624 case 0x9: /* 9[45]x9 */
625 switch ((op1 >> 4) & 0x1f)
626 {
627 case 0x00:
628 return OP_ijmp;
629 case 0x01:
630 return OP_eijmp;
631 case 0x10:
632 return OP_icall;
633 case 0x11:
634 return OP_eicall;
635 default:
636 break;
637 }
638 break;
639 case 0xa:
640 return OP_dec;
641 case 0xc:
642 case 0xd:
643 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
644 return OP_jmp;
645 case 0xe:
646 case 0xf:
647 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
648 return OP_call;
649 }
650 break;
651 case 0x6:
652 return OP_adiw;
653 case 0x7:
654 return OP_sbiw;
655 case 0x8:
656 return OP_cbi;
657 case 0x9:
658 return OP_sbic;
659 case 0xa:
660 return OP_sbi;
661 case 0xb:
662 return OP_sbis;
663 case 0xc:
664 case 0xd:
665 case 0xe:
666 case 0xf:
667 return OP_mul;
668 }
669 break;
670 case 0xb:
671 flash[pc].r = get_A (op1);
672 if (((op1 >> 11) & 1) == 0)
673 return OP_in;
674 else
675 return OP_out;
676 case 0xc:
677 return OP_rjmp;
678 case 0xd:
679 return OP_rcall;
680 case 0xe:
681 return OP_ldi;
682 case 0xf:
683 switch ((op1 >> 9) & 7)
684 {
685 case 0:
686 case 1:
687 flash[pc].r = 1 << (op1 & 7);
688 return OP_brbs;
689 case 2:
690 case 3:
691 flash[pc].r = 1 << (op1 & 7);
692 return OP_brbc;
693 case 4:
694 if ((op1 & 8) == 0)
695 {
696 flash[pc].r = 1 << (op1 & 7);
697 return OP_bld;
698 }
699 break;
700 case 5:
701 if ((op1 & 8) == 0)
702 {
703 flash[pc].r = 1 << (op1 & 7);
704 return OP_bst;
705 }
706 break;
707 case 6:
708 if ((op1 & 8) == 0)
709 {
710 flash[pc].r = 1 << (op1 & 7);
711 return OP_sbrc;
712 }
713 break;
714 case 7:
715 if ((op1 & 8) == 0)
716 {
717 flash[pc].r = 1 << (op1 & 7);
718 return OP_sbrs;
719 }
720 break;
721 }
722 }
df1756f4 723
9943d318 724 return OP_bad;
df1756f4
TG		 725}
726
727static void
82d442c6 728do_call (SIM_CPU *cpu, unsigned int npc)
df1756f4 729{
82d442c6 730 SIM_DESC sd = CPU_STATE (cpu);
df1756f4
TG		 731 unsigned int sp = read_word (REG_SP);
732
733 /* Big endian! */
82d442c6
MF		 734 sram[sp--] = cpu->pc;
735 sram[sp--] = cpu->pc >> 8;
736 if (sd->avr_pc22)
df1756f4 737 {
82d442c6
MF		 738 sram[sp--] = cpu->pc >> 16;
739 cpu->cycles++;
df1756f4
TG		 740 }
741 write_word (REG_SP, sp);
82d442c6
MF		 742 cpu->pc = npc & PC_MASK;
743 cpu->cycles += 3;
df1756f4
TG		 744}
745
746static int
747get_insn_length (unsigned int p)
748{
749 if (flash[p].code == OP_unknown)
750 flash[p].code = decode(p);
751 if (flash[p].code >= OP_2words)
752 return 2;
753 else
754 return 1;
755}
756
757static unsigned int
758get_z (void)
759{
760 return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO];
761}
762
763static unsigned char
764get_lpm (unsigned int addr)
765{
766 word w;
767
768 w = flash[(addr >> 1) & PC_MASK].op;
769 if (addr & 1)
770 w >>= 8;
771 return w;
772}
773
774static void
82d442c6 775gen_mul (SIM_CPU *cpu, unsigned int res)
df1756f4
TG		 776{
777 write_word (0, res);
778 sram[SREG] &= ~(SREG_Z | SREG_C);
779 if (res == 0)
780 sram[SREG] |= SREG_Z;
781 if (res & 0x8000)
782 sram[SREG] |= SREG_C;
82d442c6 783 cpu->cycles++;
df1756f4
TG		 784}
785
9943d318
MF		 786static void
787step_once (SIM_CPU *cpu)
df1756f4
TG		 788{
789 unsigned int ipc;
790
9943d318
MF		 791 int code;
792 word op;
793 byte res;
794 byte r, d, vd;
df1756f4 795
9943d318 796 again:
82d442c6
MF		 797 code = flash[cpu->pc].code;
798 op = flash[cpu->pc].op;
df1756f4 799
9943d318
MF		 800#if 0
801 if (tracing && code != OP_unknown)
df1756f4
TG		 802 {
803 if (verbose > 0) {
804 int flags;
805 int i;
9943d318 806
df1756f4
TG		 807 sim_cb_eprintf (callback, "R00-07:");
808 for (i = 0; i < 8; i++)
809 sim_cb_eprintf (callback, " %02x", sram[i]);
810 sim_cb_eprintf (callback, " -");
811 for (i = 8; i < 16; i++)
812 sim_cb_eprintf (callback, " %02x", sram[i]);
813 sim_cb_eprintf (callback, " SP: %02x %02x",
814 sram[REG_SP + 1], sram[REG_SP]);
815 sim_cb_eprintf (callback, "\n");
816 sim_cb_eprintf (callback, "R16-31:");
817 for (i = 16; i < 24; i++)
818 sim_cb_eprintf (callback, " %02x", sram[i]);
819 sim_cb_eprintf (callback, " -");
820 for (i = 24; i < 32; i++)
821 sim_cb_eprintf (callback, " %02x", sram[i]);
822 sim_cb_eprintf (callback, " ");
823 flags = sram[SREG];
824 for (i = 0; i < 8; i++)
825 sim_cb_eprintf (callback, "%c",
826 flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-');
827 sim_cb_eprintf (callback, "\n");
828 }
829
9943d318 830 if (!tracing)
82d442c6 831 sim_cb_eprintf (callback, "%06x: %04x\n", 2 * cpu->pc, flash[cpu->pc].op);
df1756f4
TG		 832 else
833 {
834 sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
82d442c6
MF		 835 2 * cpu->pc, flash[cpu->pc].op, code, flash[cpu->pc].r);
836 disassemble_insn (CPU_STATE (cpu), cpu->pc);
df1756f4
TG		 837 sim_cb_eprintf (callback, "\n");
838 }
839 }
9943d318 840#endif
df1756f4 841
82d442c6
MF		 842 ipc = cpu->pc;
843 cpu->pc = (cpu->pc + 1) & PC_MASK;
844 cpu->cycles++;
df1756f4 845
9943d318
MF		 846 switch (code)
847 {
848 case OP_unknown:
849 flash[ipc].code = decode(ipc);
82d442c6
MF		 850 cpu->pc = ipc;
851 cpu->cycles--;
9943d318
MF		 852 goto again;
853
854 case OP_nop:
855 break;
856
857 case OP_jmp:
858 /* 2 words instruction, but we don't care about the pc. */
82d442c6
MF		 859 cpu->pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK;
860 cpu->cycles += 2;
9943d318
MF		 861 break;
862
863 case OP_eijmp:
82d442c6
MF		 864 cpu->pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK;
865 cpu->cycles += 2;
9943d318
MF		 866 break;
867
868 case OP_ijmp:
82d442c6
MF		 869 cpu->pc = read_word (REGZ) & PC_MASK;
870 cpu->cycles += 1;
9943d318
MF		 871 break;
872
873 case OP_call:
874 /* 2 words instruction. */
82d442c6
MF		 875 cpu->pc++;
876 do_call (cpu, (flash[ipc].r << 16) | flash[ipc + 1].op);
9943d318
MF		 877 break;
878
879 case OP_eicall:
82d442c6 880 do_call (cpu, (sram[EIND] << 16) | read_word (REGZ));
9943d318
MF		 881 break;
882
883 case OP_icall:
82d442c6 884 do_call (cpu, read_word (REGZ));
9943d318
MF		 885 break;
886
887 case OP_rcall:
82d442c6 888 do_call (cpu, cpu->pc + sign_ext (op & 0xfff, 12));
9943d318
MF		 889 break;
890
891 case OP_reti:
892 sram[SREG] |= SREG_I;
893 /* Fall through */
894 case OP_ret:
df1756f4 895 {
82d442c6 896 SIM_DESC sd = CPU_STATE (cpu);
9943d318 897 unsigned int sp = read_word (REG_SP);
82d442c6 898 if (sd->avr_pc22)
9943d318 899 {
82d442c6
MF		 900 cpu->pc = sram[++sp] << 16;
901 cpu->cycles++;
9943d318 902 }
df1756f4 903 else
82d442c6
MF		 904 cpu->pc = 0;
905 cpu->pc |= sram[++sp] << 8;
906 cpu->pc |= sram[++sp];
9943d318
MF		 907 write_word (REG_SP, sp);
908 }
82d442c6 909 cpu->cycles += 3;
9943d318
MF		 910 break;
911
912 case OP_break:
913 /* Stop on this address. */
82d442c6
MF		 914 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_stopped, SIM_SIGTRAP);
915 cpu->pc = ipc;
9943d318
MF		 916 break;
917
918 case OP_bld:
919 d = get_d (op);
920 r = flash[ipc].r;
921 if (sram[SREG] & SREG_T)
922 sram[d] |= r;
923 else
924 sram[d] &= ~r;
925 break;
926
927 case OP_bst:
928 if (sram[get_d (op)] & flash[ipc].r)
929 sram[SREG] |= SREG_T;
930 else
931 sram[SREG] &= ~SREG_T;
932 break;
933
934 case OP_sbrc:
935 case OP_sbrs:
936 if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0))
df1756f4 937 {
82d442c6
MF		 938 int l = get_insn_length (cpu->pc);
939 cpu->pc += l;
940 cpu->cycles += l;
df1756f4 941 }
9943d318 942 break;
df1756f4 943
9943d318
MF		 944 case OP_push:
945 {
946 unsigned int sp = read_word (REG_SP);
947 sram[sp--] = sram[get_d (op)];
948 write_word (REG_SP, sp);
949 }
82d442c6 950 cpu->cycles++;
9943d318 951 break;
df1756f4 952
9943d318
MF		 953 case OP_pop:
954 {
955 unsigned int sp = read_word (REG_SP);
956 sram[get_d (op)] = sram[++sp];
957 write_word (REG_SP, sp);
958 }
82d442c6 959 cpu->cycles++;
9943d318
MF		 960 break;
961
962 case OP_bclr:
963 sram[SREG] &= ~(1 << ((op >> 4) & 0x7));
964 break;
965
966 case OP_bset:
967 sram[SREG] |= 1 << ((op >> 4) & 0x7);
968 break;
969
970 case OP_rjmp:
82d442c6
MF		 971 cpu->pc = (cpu->pc + sign_ext (op & 0xfff, 12)) & PC_MASK;
972 cpu->cycles++;
9943d318
MF		 973 break;
974
975 case OP_eor:
976 d = get_d (op);
977 res = sram[d] ^ sram[get_r (op)];
978 sram[d] = res;
979 update_flags_logic (res);
980 break;
981
982 case OP_and:
983 d = get_d (op);
984 res = sram[d] & sram[get_r (op)];
985 sram[d] = res;
986 update_flags_logic (res);
987 break;
988
989 case OP_andi:
990 d = get_d16 (op);
991 res = sram[d] & get_K (op);
992 sram[d] = res;
993 update_flags_logic (res);
994 break;
995
996 case OP_or:
997 d = get_d (op);
998 res = sram[d] | sram[get_r (op)];
999 sram[d] = res;
1000 update_flags_logic (res);
1001 break;
1002
1003 case OP_ori:
1004 d = get_d16 (op);
1005 res = sram[d] | get_K (op);
1006 sram[d] = res;
1007 update_flags_logic (res);
1008 break;
1009
1010 case OP_com:
1011 d = get_d (op);
1012 res = ~sram[d];
1013 sram[d] = res;
1014 update_flags_logic (res);
1015 sram[SREG] |= SREG_C;
1016 break;
1017
1018 case OP_swap:
1019 d = get_d (op);
1020 vd = sram[d];
1021 sram[d] = (vd >> 4) | (vd << 4);
1022 break;
1023
1024 case OP_neg:
1025 d = get_d (op);
1026 vd = sram[d];
1027 res = -vd;
1028 sram[d] = res;
1029 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1030 if (res == 0)
1031 sram[SREG] |= SREG_Z;
1032 else
df1756f4 1033 sram[SREG] |= SREG_C;
9943d318
MF		 1034 if (res == 0x80)
1035 sram[SREG] |= SREG_V | SREG_N;
1036 else if (res & 0x80)
1037 sram[SREG] |= SREG_N | SREG_S;
1038 if ((res | vd) & 0x08)
1039 sram[SREG] |= SREG_H;
1040 break;
1041
1042 case OP_inc:
1043 d = get_d (op);
1044 res = sram[d] + 1;
1045 sram[d] = res;
1046 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1047 if (res == 0x80)
1048 sram[SREG] |= SREG_V | SREG_N;
1049 else if (res & 0x80)
1050 sram[SREG] |= SREG_N | SREG_S;
1051 else if (res == 0)
1052 sram[SREG] |= SREG_Z;
1053 break;
1054
1055 case OP_dec:
1056 d = get_d (op);
1057 res = sram[d] - 1;
1058 sram[d] = res;
1059 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1060 if (res == 0x7f)
1061 sram[SREG] |= SREG_V | SREG_S;
1062 else if (res & 0x80)
1063 sram[SREG] |= SREG_N | SREG_S;
1064 else if (res == 0)
1065 sram[SREG] |= SREG_Z;
1066 break;
1067
1068 case OP_lsr:
1069 case OP_asr:
1070 d = get_d (op);
1071 vd = sram[d];
1072 res = (vd >> 1) | (vd & flash[ipc].r);
1073 sram[d] = res;
1074 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1075 if (vd & 1)
1076 sram[SREG] |= SREG_C | SREG_S;
1077 if (res & 0x80)
1078 sram[SREG] |= SREG_N;
1079 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1080 sram[SREG] |= SREG_V;
1081 if (res == 0)
1082 sram[SREG] |= SREG_Z;
1083 break;
1084
1085 case OP_ror:
1086 d = get_d (op);
1087 vd = sram[d];
1088 res = vd >> 1 | (sram[SREG] << 7);
1089 sram[d] = res;
1090 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1091 if (vd & 1)
1092 sram[SREG] |= SREG_C | SREG_S;
1093 if (res & 0x80)
1094 sram[SREG] |= SREG_N;
1095 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1096 sram[SREG] |= SREG_V;
1097 if (res == 0)
1098 sram[SREG] |= SREG_Z;
1099 break;
1100
1101 case OP_mul:
82d442c6 1102 gen_mul (cpu, (word)sram[get_r (op)] * (word)sram[get_d (op)]);
9943d318
MF		 1103 break;
1104
1105 case OP_muls:
82d442c6
MF		 1106 gen_mul (cpu, (sword)(sbyte)sram[get_r16 (op)]
1107 * (sword)(sbyte)sram[get_d16 (op)]);
9943d318
MF		 1108 break;
1109
1110 case OP_mulsu:
82d442c6
MF		 1111 gen_mul (cpu, (sword)(word)sram[get_r16_23 (op)]
1112 * (sword)(sbyte)sram[get_d16_23 (op)]);
9943d318
MF		 1113 break;
1114
1115 case OP_fmul:
82d442c6
MF		 1116 gen_mul (cpu, ((word)sram[get_r16_23 (op)]
1117 * (word)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1118 break;
1119
1120 case OP_fmuls:
82d442c6
MF		 1121 gen_mul (cpu, ((sword)(sbyte)sram[get_r16_23 (op)]
1122 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1123 break;
1124
1125 case OP_fmulsu:
82d442c6
MF		 1126 gen_mul (cpu, ((sword)(word)sram[get_r16_23 (op)]
1127 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1128 break;
1129
1130 case OP_adc:
1131 case OP_add:
1132 r = sram[get_r (op)];
1133 d = get_d (op);
1134 vd = sram[d];
1135 res = r + vd + (sram[SREG] & flash[ipc].r);
1136 sram[d] = res;
1137 update_flags_add (res, vd, r);
1138 break;
1139
1140 case OP_sub:
1141 d = get_d (op);
1142 vd = sram[d];
1143 r = sram[get_r (op)];
1144 res = vd - r;
1145 sram[d] = res;
1146 update_flags_sub (res, vd, r);
1147 if (res == 0)
1148 sram[SREG] |= SREG_Z;
1149 break;
1150
1151 case OP_sbc:
1152 {
1153 byte old = sram[SREG];
df1756f4
TG		 1154 d = get_d (op);
1155 vd = sram[d];
1156 r = sram[get_r (op)];
9943d318 1157 res = vd - r - (old & SREG_C);
df1756f4
TG		 1158 sram[d] = res;
1159 update_flags_sub (res, vd, r);
9943d318 1160 if (res == 0 && (old & SREG_Z))
df1756f4 1161 sram[SREG] |= SREG_Z;
9943d318
MF		 1162 }
1163 break;
1164
1165 case OP_subi:
1166 d = get_d16 (op);
1167 vd = sram[d];
1168 r = get_K (op);
1169 res = vd - r;
1170 sram[d] = res;
1171 update_flags_sub (res, vd, r);
1172 if (res == 0)
1173 sram[SREG] |= SREG_Z;
1174 break;
1175
1176 case OP_sbci:
1177 {
1178 byte old = sram[SREG];
df1756f4 1179
df1756f4
TG		 1180 d = get_d16 (op);
1181 vd = sram[d];
1182 r = get_K (op);
9943d318 1183 res = vd - r - (old & SREG_C);
df1756f4
TG		 1184 sram[d] = res;
1185 update_flags_sub (res, vd, r);
9943d318 1186 if (res == 0 && (old & SREG_Z))
df1756f4 1187 sram[SREG] |= SREG_Z;
9943d318
MF		 1188 }
1189 break;
1190
1191 case OP_mov:
1192 sram[get_d (op)] = sram[get_r (op)];
1193 break;
1194
1195 case OP_movw:
1196 d = (op & 0xf0) >> 3;
1197 r = (op & 0x0f) << 1;
1198 sram[d] = sram[r];
1199 sram[d + 1] = sram[r + 1];
1200 break;
1201
1202 case OP_out:
1203 d = get_A (op) + 0x20;
1204 res = sram[get_d (op)];
1205 sram[d] = res;
1206 if (d == STDIO_PORT)
1207 putchar (res);
1208 else if (d == EXIT_PORT)
82d442c6 1209 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_exited, 0);
9943d318 1210 else if (d == ABORT_PORT)
82d442c6 1211 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_exited, 1);
9943d318
MF		 1212 break;
1213
1214 case OP_in:
1215 d = get_A (op) + 0x20;
1216 sram[get_d (op)] = sram[d];
1217 break;
1218
1219 case OP_cbi:
1220 d = get_biA (op) + 0x20;
1221 sram[d] &= ~(1 << get_b(op));
1222 break;
1223
1224 case OP_sbi:
1225 d = get_biA (op) + 0x20;
1226 sram[d] |= 1 << get_b(op);
1227 break;
1228
1229 case OP_sbic:
1230 if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op)))
df1756f4 1231 {
82d442c6
MF		 1232 int l = get_insn_length (cpu->pc);
1233 cpu->pc += l;
1234 cpu->cycles += l;
df1756f4 1235 }
9943d318 1236 break;
df1756f4 1237
9943d318
MF		 1238 case OP_sbis:
1239 if (sram[get_biA (op) + 0x20] & 1 << get_b(op))
1240 {
82d442c6
MF		 1241 int l = get_insn_length (cpu->pc);
1242 cpu->pc += l;
1243 cpu->cycles += l;
9943d318
MF		 1244 }
1245 break;
1246
1247 case OP_ldi:
1248 res = get_K (op);
1249 d = get_d16 (op);
1250 sram[d] = res;
1251 break;
1252
1253 case OP_lds:
82d442c6
MF		 1254 sram[get_d (op)] = sram[flash[cpu->pc].op];
1255 cpu->pc++;
1256 cpu->cycles++;
9943d318
MF		 1257 break;
1258
1259 case OP_sts:
82d442c6
MF		 1260 sram[flash[cpu->pc].op] = sram[get_d (op)];
1261 cpu->pc++;
1262 cpu->cycles++;
9943d318
MF		 1263 break;
1264
1265 case OP_cpse:
1266 if (sram[get_r (op)] == sram[get_d (op)])
1267 {
82d442c6
MF		 1268 int l = get_insn_length (cpu->pc);
1269 cpu->pc += l;
1270 cpu->cycles += l;
9943d318
MF		 1271 }
1272 break;
1273
1274 case OP_cp:
1275 r = sram[get_r (op)];
1276 d = sram[get_d (op)];
1277 res = d - r;
1278 update_flags_sub (res, d, r);
1279 if (res == 0)
1280 sram[SREG] |= SREG_Z;
1281 break;
1282
1283 case OP_cpi:
1284 r = get_K (op);
1285 d = sram[get_d16 (op)];
1286 res = d - r;
1287 update_flags_sub (res, d, r);
1288 if (res == 0)
1289 sram[SREG] |= SREG_Z;
1290 break;
1291
1292 case OP_cpc:
1293 {
1294 byte old = sram[SREG];
df1756f4 1295 d = sram[get_d (op)];
9943d318
MF		 1296 r = sram[get_r (op)];
1297 res = d - r - (old & SREG_C);
df1756f4 1298 update_flags_sub (res, d, r);
9943d318 1299 if (res == 0 && (old & SREG_Z))
df1756f4 1300 sram[SREG] |= SREG_Z;
9943d318
MF		 1301 }
1302 break;
df1756f4 1303
9943d318
MF		 1304 case OP_brbc:
1305 if (!(sram[SREG] & flash[ipc].r))
1306 {
82d442c6
MF		 1307 cpu->pc = (cpu->pc + get_k (op)) & PC_MASK;
1308 cpu->cycles++;
9943d318
MF		 1309 }
1310 break;
df1756f4 1311
9943d318
MF		 1312 case OP_brbs:
1313 if (sram[SREG] & flash[ipc].r)
df1756f4 1314 {
82d442c6
MF		 1315 cpu->pc = (cpu->pc + get_k (op)) & PC_MASK;
1316 cpu->cycles++;
df1756f4 1317 }
9943d318
MF		 1318 break;
1319
1320 case OP_lpm:
1321 sram[0] = get_lpm (read_word (REGZ));
82d442c6 1322 cpu->cycles += 2;
9943d318
MF		 1323 break;
1324
1325 case OP_lpm_Z:
1326 sram[get_d (op)] = get_lpm (read_word (REGZ));
82d442c6 1327 cpu->cycles += 2;
9943d318
MF		 1328 break;
1329
1330 case OP_lpm_inc_Z:
1331 sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ));
82d442c6 1332 cpu->cycles += 2;
9943d318
MF		 1333 break;
1334
1335 case OP_elpm:
1336 sram[0] = get_lpm (get_z ());
82d442c6 1337 cpu->cycles += 2;
9943d318
MF		 1338 break;
1339
1340 case OP_elpm_Z:
1341 sram[get_d (op)] = get_lpm (get_z ());
82d442c6 1342 cpu->cycles += 2;
9943d318
MF		 1343 break;
1344
1345 case OP_elpm_inc_Z:
1346 {
1347 unsigned int z = get_z ();
df1756f4 1348
9943d318
MF		 1349 sram[get_d (op)] = get_lpm (z);
1350 z++;
1351 sram[REGZ_LO] = z;
1352 sram[REGZ_HI] = z >> 8;
1353 sram[RAMPZ] = z >> 16;
1354 }
82d442c6 1355 cpu->cycles += 2;
9943d318
MF		 1356 break;
1357
1358 case OP_ld_Z_inc:
1359 sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK];
82d442c6 1360 cpu->cycles++;
9943d318
MF		 1361 break;
1362
1363 case OP_ld_dec_Z:
1364 sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK];
82d442c6 1365 cpu->cycles++;
9943d318
MF		 1366 break;
1367
1368 case OP_ld_X_inc:
1369 sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK];
82d442c6 1370 cpu->cycles++;
9943d318
MF		 1371 break;
1372
1373 case OP_ld_dec_X:
1374 sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK];
82d442c6 1375 cpu->cycles++;
9943d318
MF		 1376 break;
1377
1378 case OP_ld_Y_inc:
1379 sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK];
82d442c6 1380 cpu->cycles++;
9943d318
MF		 1381 break;
1382
1383 case OP_ld_dec_Y:
1384 sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK];
82d442c6 1385 cpu->cycles++;
9943d318
MF		 1386 break;
1387
1388 case OP_st_X:
1389 sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1390 cpu->cycles++;
9943d318
MF		 1391 break;
1392
1393 case OP_st_X_inc:
1394 sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1395 cpu->cycles++;
9943d318
MF		 1396 break;
1397
1398 case OP_st_dec_X:
1399 sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1400 cpu->cycles++;
9943d318
MF		 1401 break;
1402
1403 case OP_st_Z_inc:
1404 sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1405 cpu->cycles++;
9943d318
MF		 1406 break;
1407
1408 case OP_st_dec_Z:
1409 sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1410 cpu->cycles++;
9943d318
MF		 1411 break;
1412
1413 case OP_st_Y_inc:
1414 sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1415 cpu->cycles++;
9943d318
MF		 1416 break;
1417
1418 case OP_st_dec_Y:
1419 sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1420 cpu->cycles++;
9943d318
MF		 1421 break;
1422
1423 case OP_std_Y:
1424 sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)];
82d442c6 1425 cpu->cycles++;
9943d318
MF		 1426 break;
1427
1428 case OP_std_Z:
1429 sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)];
82d442c6 1430 cpu->cycles++;
9943d318
MF		 1431 break;
1432
1433 case OP_ldd_Z:
1434 sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r];
82d442c6 1435 cpu->cycles++;
9943d318
MF		 1436 break;
1437
1438 case OP_ldd_Y:
1439 sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r];
82d442c6 1440 cpu->cycles++;
9943d318
MF		 1441 break;
1442
1443 case OP_ld_X:
1444 sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK];
82d442c6 1445 cpu->cycles++;
9943d318
MF		 1446 break;
1447
1448 case OP_sbiw:
1449 {
1450 word wk = get_k6 (op);
1451 word wres;
1452 word wr;
df1756f4 1453
9943d318
MF		 1454 d = get_d24 (op);
1455 wr = read_word (d);
1456 wres = wr - wk;
df1756f4 1457
9943d318
MF		 1458 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1459 if (wres == 0)
1460 sram[SREG] |= SREG_Z;
1461 if (wres & 0x8000)
1462 sram[SREG] |= SREG_N;
1463 if (wres & ~wr & 0x8000)
1464 sram[SREG] |= SREG_C;
1465 if (~wres & wr & 0x8000)
1466 sram[SREG] |= SREG_V;
1467 if (((~wres & wr) ^ wres) & 0x8000)
1468 sram[SREG] |= SREG_S;
1469 write_word (d, wres);
1470 }
82d442c6 1471 cpu->cycles++;
9943d318 1472 break;
df1756f4 1473
9943d318
MF		 1474 case OP_adiw:
1475 {
1476 word wk = get_k6 (op);
1477 word wres;
1478 word wr;
1479
1480 d = get_d24 (op);
1481 wr = read_word (d);
1482 wres = wr + wk;
1483
1484 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1485 if (wres == 0)
1486 sram[SREG] |= SREG_Z;
1487 if (wres & 0x8000)
1488 sram[SREG] |= SREG_N;
1489 if (~wres & wr & 0x8000)
1490 sram[SREG] |= SREG_C;
1491 if (wres & ~wr & 0x8000)
1492 sram[SREG] |= SREG_V;
1493 if (((wres & ~wr) ^ wres) & 0x8000)
1494 sram[SREG] |= SREG_S;
1495 write_word (d, wres);
df1756f4 1496 }
82d442c6 1497 cpu->cycles++;
9943d318 1498 break;
df1756f4 1499
9943d318 1500 case OP_bad:
82d442c6 1501 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
df1756f4 1502
9943d318 1503 default:
82d442c6 1504 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
9943d318
MF		 1505 }
1506}
1507
1508void
1509sim_engine_run (SIM_DESC sd,
1510 int next_cpu_nr, /* ignore */
1511 int nr_cpus, /* ignore */
1512 int siggnal) /* ignore */
df1756f4 1513{
9943d318
MF		 1514 SIM_CPU *cpu;
1515
1516 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1517
1518 cpu = STATE_CPU (sd, 0);
df1756f4 1519
9943d318
MF		 1520 while (1)
1521 {
1522 step_once (cpu);
1523 if (sim_events_tick (sd))
1524 sim_events_process (sd);
1525 }
df1756f4
TG		 1526}
1527
1528int
5558e7e6 1529sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
df1756f4
TG		 1530{
1531 int osize = size;
1532
1533 if (addr >= 0 && addr < SRAM_VADDR)
1534 {
8f0ac700 1535 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
df1756f4 1536 {
8f0ac700
TG		 1537 word val = flash[addr >> 1].op;
1538
1539 if (addr & 1)
1540 val = (val & 0xff) | (buffer[0] << 8);
1541 else
1542 val = (val & 0xff00) | buffer[0];
1543
1544 flash[addr >> 1].op = val;
1545 flash[addr >> 1].code = OP_unknown;
df1756f4 1546 addr++;
8f0ac700
TG		 1547 buffer++;
1548 size--;
df1756f4
TG		 1549 }
1550 return osize - size;
1551 }
1552 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1553 {
1554 addr -= SRAM_VADDR;
1555 if (addr + size > MAX_AVR_SRAM)
1556 size = MAX_AVR_SRAM - addr;
1557 memcpy (sram + addr, buffer, size);
1558 return size;
1559 }
1560 else
1561 return 0;
1562}
1563
1564int
1565sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1566{
1567 int osize = size;
1568
1569 if (addr >= 0 && addr < SRAM_VADDR)
1570 {
8f0ac700 1571 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
df1756f4 1572 {
8f0ac700
TG		 1573 word val = flash[addr >> 1].op;
1574
1575 if (addr & 1)
1576 val >>= 8;
1577
1578 *buffer++ = val;
df1756f4 1579 addr++;
8f0ac700 1580 size--;
df1756f4
TG		 1581 }
1582 return osize - size;
1583 }
1584 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1585 {
1586 addr -= SRAM_VADDR;
1587 if (addr + size > MAX_AVR_SRAM)
1588 size = MAX_AVR_SRAM - addr;
1589 memcpy (buffer, sram + addr, size);
1590 return size;
1591 }
1592 else
1593 {
1594 /* Avoid errors. */
1595 memset (buffer, 0, size);
1596 return size;
1597 }
1598}
1599
807eaf04
MF		 1600static int
1601avr_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
df1756f4
TG		 1602{
1603 if (rn < 32 && length == 1)
1604 {
1605 sram[rn] = *memory;
1606 return 1;
1607 }
1608 if (rn == AVR_SREG_REGNUM && length == 1)
1609 {
1610 sram[SREG] = *memory;
1611 return 1;
1612 }
1613 if (rn == AVR_SP_REGNUM && length == 2)
1614 {
1615 sram[REG_SP] = memory[0];
1616 sram[REG_SP + 1] = memory[1];
1617 return 2;
1618 }
1619 if (rn == AVR_PC_REGNUM && length == 4)
1620 {
82d442c6
MF		 1621 cpu->pc = (memory[0] >> 1) | (memory[1] << 7)
1622 | (memory[2] << 15) | (memory[3] << 23);
1623 cpu->pc &= PC_MASK;
df1756f4
TG		 1624 return 4;
1625 }
1626 return 0;
1627}
1628
807eaf04
MF		 1629static int
1630avr_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
df1756f4
TG		 1631{
1632 if (rn < 32 && length == 1)
1633 {
1634 *memory = sram[rn];
1635 return 1;
1636 }
1637 if (rn == AVR_SREG_REGNUM && length == 1)
1638 {
1639 *memory = sram[SREG];
1640 return 1;
1641 }
1642 if (rn == AVR_SP_REGNUM && length == 2)
1643 {
1644 memory[0] = sram[REG_SP];
1645 memory[1] = sram[REG_SP + 1];
1646 return 2;
1647 }
1648 if (rn == AVR_PC_REGNUM && length == 4)
1649 {
82d442c6
MF		 1650 memory[0] = cpu->pc << 1;
1651 memory[1] = cpu->pc >> 7;
1652 memory[2] = cpu->pc >> 15;
1653 memory[3] = cpu->pc >> 23;
df1756f4
TG		 1654 return 4;
1655 }
1656 return 0;
1657}
1658
4c0cab1e
MF		 1659static sim_cia
1660avr_pc_get (sim_cpu *cpu)
1661{
82d442c6 1662 return cpu->pc;
4c0cab1e
MF		 1663}
1664
1665static void
82d442c6 1666avr_pc_set (sim_cpu *cpu, sim_cia pc)
4c0cab1e 1667{
82d442c6 1668 cpu->pc = pc;
4c0cab1e
MF		 1669}
1670
9943d318
MF		 1671static void
1672free_state (SIM_DESC sd)
df1756f4 1673{
9943d318
MF		 1674 if (STATE_MODULES (sd) != NULL)
1675 sim_module_uninstall (sd);
1676 sim_cpu_free_all (sd);
1677 sim_state_free (sd);
df1756f4
TG		 1678}
1679
1680SIM_DESC
1681sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
1682{
4c0cab1e 1683 int i;
9943d318
MF		 1684 SIM_DESC sd = sim_state_alloc (kind, cb);
1685 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
df1756f4 1686
9943d318
MF		 1687 /* The cpu data is kept in a separately allocated chunk of memory. */
1688 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
1689 {
1690 free_state (sd);
1691 return 0;
1692 }
df1756f4 1693
82d442c6
MF		 1694 {
1695 /* XXX: Only first core gets profiled ? */
1696 SIM_CPU *cpu = STATE_CPU (sd, 0);
1697 STATE_WATCHPOINTS (sd)->pc = &cpu->pc;
1698 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (cpu->pc);
1699 }
df1756f4 1700
9943d318
MF		 1701 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1702 {
1703 free_state (sd);
1704 return 0;
1705 }
df1756f4 1706
77cf2ef5 1707 /* The parser will print an error message for us, so we silently return. */
9943d318
MF		 1708 if (sim_parse_args (sd, argv) != SIM_RC_OK)
1709 {
1710 free_state (sd);
1711 return 0;
1712 }
33bcfade 1713
9943d318
MF		 1714 /* Check for/establish the a reference program image. */
1715 if (sim_analyze_program (sd,
1716 (STATE_PROG_ARGV (sd) != NULL
1717 ? *STATE_PROG_ARGV (sd)
1718 : NULL), abfd) != SIM_RC_OK)
1719 {
1720 free_state (sd);
1721 return 0;
1722 }
df1756f4 1723
9943d318
MF		 1724 /* Configure/verify the target byte order and other runtime
1725 configuration options. */
1726 if (sim_config (sd) != SIM_RC_OK)
1727 {
1728 sim_module_uninstall (sd);
1729 return 0;
1730 }
df1756f4 1731
9943d318
MF		 1732 if (sim_post_argv_init (sd) != SIM_RC_OK)
1733 {
1734 /* Uninstall the modules to avoid memory leaks,
1735 file descriptor leaks, etc. */
1736 sim_module_uninstall (sd);
1737 return 0;
1738 }
df1756f4 1739
4c0cab1e
MF		 1740 /* CPU specific initialization. */
1741 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
1742 {
1743 SIM_CPU *cpu = STATE_CPU (sd, i);
1744
807eaf04
MF		 1745 CPU_REG_FETCH (cpu) = avr_reg_fetch;
1746 CPU_REG_STORE (cpu) = avr_reg_store;
4c0cab1e
MF		 1747 CPU_PC_FETCH (cpu) = avr_pc_get;
1748 CPU_PC_STORE (cpu) = avr_pc_set;
1749 }
1750
9943d318
MF		 1751 /* Clear all the memory. */
1752 memset (sram, 0, sizeof (sram));
1753 memset (flash, 0, sizeof (flash));
df1756f4 1754
9943d318 1755 return sd;
df1756f4
TG		 1756}
1757
9943d318
MF		 1758SIM_RC
1759sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
df1756f4 1760{
82d442c6
MF		 1761 SIM_CPU *cpu = STATE_CPU (sd, 0);
1762 SIM_ADDR addr;
1763
9943d318
MF		 1764 /* Set the PC. */
1765 if (abfd != NULL)
82d442c6 1766 addr = bfd_get_start_address (abfd);
9943d318 1767 else
82d442c6
MF		 1768 addr = 0;
1769 sim_pc_set (cpu, addr);
af9f7da7 1770
9943d318 1771 if (abfd != NULL)
82d442c6 1772 sd->avr_pc22 = (bfd_get_mach (abfd) >= bfd_mach_avr6);
9943d318
MF		 1773
1774 return SIM_RC_OK;
af9f7da7 1775}
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