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ef016f83 MF |
1 | /* Blackfin External Bus Interface Unit (EBIU) DDR Controller (DDRC) Model. |
2 | ||
8acc9f48 | 3 | Copyright (C) 2010-2013 Free Software Foundation, Inc. |
ef016f83 MF |
4 | Contributed by Analog Devices, Inc. |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | ||
23 | #include "sim-main.h" | |
24 | #include "devices.h" | |
25 | #include "dv-bfin_ebiu_ddrc.h" | |
26 | ||
27 | struct bfin_ebiu_ddrc | |
28 | { | |
29 | bu32 base, reg_size, bank_size; | |
30 | ||
31 | /* Order after here is important -- matches hardware MMR layout. */ | |
32 | union { | |
33 | struct { bu32 ddrctl0, ddrctl1, ddrctl2, ddrctl3; }; | |
34 | bu32 ddrctl[4]; | |
35 | }; | |
36 | bu32 ddrque, erradd; | |
37 | bu16 BFIN_MMR_16(errmst); | |
38 | bu16 BFIN_MMR_16(rstctl); | |
39 | bu32 ddrbrc[8], ddrbwc[8]; | |
40 | bu32 ddracct, ddrtact, ddrarct; | |
41 | bu32 ddrgc[4]; | |
42 | bu32 ddrmcen, ddrmccl; | |
43 | }; | |
44 | #define mmr_base() offsetof(struct bfin_ebiu_ddrc, ddrctl0) | |
45 | #define mmr_offset(mmr) (offsetof(struct bfin_ebiu_ddrc, mmr) - mmr_base()) | |
46 | ||
990d19fd MF |
47 | static const char * const mmr_names[] = |
48 | { | |
ef016f83 MF |
49 | "EBIU_DDRCTL0", "EBIU_DDRCTL1", "EBIU_DDRCTL2", "EBIU_DDRCTL3", "EBIU_DDRQUE", |
50 | "EBIU_ERRADD", "EBIU_ERRMST", "EBIU_RSTCTL", "EBIU_DDRBRC0", "EBIU_DDRBRC1", | |
51 | "EBIU_DDRBRC2", "EBIU_DDRBRC3", "EBIU_DDRBRC4", "EBIU_DDRBRC5", | |
52 | "EBIU_DDRBRC6", "EBIU_DDRBRC7", "EBIU_DDRBWC0", "EBIU_DDRBWC1" | |
53 | "EBIU_DDRBWC2", "EBIU_DDRBWC3", "EBIU_DDRBWC4", "EBIU_DDRBWC5", | |
54 | "EBIU_DDRBWC6", "EBIU_DDRBWC7", "EBIU_DDRACCT", "EBIU_DDRTACT", | |
55 | "EBIU_ARCT", "EBIU_DDRGC0", "EBIU_DDRGC1", "EBIU_DDRGC2", "EBIU_DDRGC3", | |
56 | "EBIU_DDRMCEN", "EBIU_DDRMCCL", | |
57 | }; | |
58 | #define mmr_name(off) mmr_names[(off) / 4] | |
59 | ||
60 | static unsigned | |
61 | bfin_ebiu_ddrc_io_write_buffer (struct hw *me, const void *source, | |
62 | int space, address_word addr, unsigned nr_bytes) | |
63 | { | |
64 | struct bfin_ebiu_ddrc *ddrc = hw_data (me); | |
65 | bu32 mmr_off; | |
66 | bu32 value; | |
67 | bu16 *value16p; | |
68 | bu32 *value32p; | |
69 | void *valuep; | |
70 | ||
71 | if (nr_bytes == 4) | |
72 | value = dv_load_4 (source); | |
73 | else | |
74 | value = dv_load_2 (source); | |
75 | ||
76 | mmr_off = addr - ddrc->base; | |
77 | valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off); | |
78 | value16p = valuep; | |
79 | value32p = valuep; | |
80 | ||
81 | HW_TRACE_WRITE (); | |
82 | ||
83 | switch (mmr_off) | |
84 | { | |
85 | case mmr_offset(errmst): | |
86 | case mmr_offset(rstctl): | |
87 | dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); | |
88 | *value16p = value; | |
89 | break; | |
90 | default: | |
91 | dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); | |
92 | *value32p = value; | |
93 | break; | |
94 | } | |
95 | ||
96 | return nr_bytes; | |
97 | } | |
98 | ||
99 | static unsigned | |
100 | bfin_ebiu_ddrc_io_read_buffer (struct hw *me, void *dest, | |
101 | int space, address_word addr, unsigned nr_bytes) | |
102 | { | |
103 | struct bfin_ebiu_ddrc *ddrc = hw_data (me); | |
104 | bu32 mmr_off; | |
105 | bu32 *value32p; | |
106 | bu16 *value16p; | |
107 | void *valuep; | |
108 | ||
109 | mmr_off = addr - ddrc->base; | |
110 | valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off); | |
111 | value16p = valuep; | |
112 | value32p = valuep; | |
113 | ||
114 | HW_TRACE_READ (); | |
115 | ||
116 | switch (mmr_off) | |
117 | { | |
118 | case mmr_offset(errmst): | |
119 | case mmr_offset(rstctl): | |
120 | dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); | |
121 | dv_store_2 (dest, *value16p); | |
122 | break; | |
123 | default: | |
124 | dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); | |
125 | dv_store_4 (dest, *value32p); | |
126 | break; | |
127 | } | |
128 | ||
129 | return nr_bytes; | |
130 | } | |
131 | ||
132 | static void | |
133 | attach_bfin_ebiu_ddrc_regs (struct hw *me, struct bfin_ebiu_ddrc *ddrc) | |
134 | { | |
135 | address_word attach_address; | |
136 | int attach_space; | |
137 | unsigned attach_size; | |
138 | reg_property_spec reg; | |
139 | ||
140 | if (hw_find_property (me, "reg") == NULL) | |
141 | hw_abort (me, "Missing \"reg\" property"); | |
142 | ||
143 | if (!hw_find_reg_array_property (me, "reg", 0, ®)) | |
144 | hw_abort (me, "\"reg\" property must contain three addr/size entries"); | |
145 | ||
146 | hw_unit_address_to_attach_address (hw_parent (me), | |
147 | ®.address, | |
148 | &attach_space, &attach_address, me); | |
149 | hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); | |
150 | ||
151 | if (attach_size != BFIN_MMR_EBIU_DDRC_SIZE) | |
152 | hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EBIU_DDRC_SIZE); | |
153 | ||
154 | hw_attach_address (hw_parent (me), | |
155 | 0, attach_space, attach_address, attach_size, me); | |
156 | ||
157 | ddrc->base = attach_address; | |
158 | } | |
159 | ||
160 | static void | |
161 | bfin_ebiu_ddrc_finish (struct hw *me) | |
162 | { | |
163 | struct bfin_ebiu_ddrc *ddrc; | |
164 | ||
165 | ddrc = HW_ZALLOC (me, struct bfin_ebiu_ddrc); | |
166 | ||
167 | set_hw_data (me, ddrc); | |
168 | set_hw_io_read_buffer (me, bfin_ebiu_ddrc_io_read_buffer); | |
169 | set_hw_io_write_buffer (me, bfin_ebiu_ddrc_io_write_buffer); | |
170 | ||
171 | attach_bfin_ebiu_ddrc_regs (me, ddrc); | |
172 | ||
173 | /* Initialize the DDRC. */ | |
174 | ddrc->ddrctl0 = 0x098E8411; | |
175 | ddrc->ddrctl1 = 0x10026223; | |
176 | ddrc->ddrctl2 = 0x00000021; | |
177 | ddrc->ddrctl3 = 0x00000003; /* XXX: MDDR is 0x20 ... */ | |
178 | ddrc->ddrque = 0x00001115; | |
179 | ddrc->rstctl = 0x0002; | |
180 | } | |
181 | ||
81d126c3 MF |
182 | const struct hw_descriptor dv_bfin_ebiu_ddrc_descriptor[] = |
183 | { | |
ef016f83 MF |
184 | {"bfin_ebiu_ddrc", bfin_ebiu_ddrc_finish,}, |
185 | {NULL, NULL}, | |
186 | }; |