[thirdparty/binutils-gdb.git] / sim / bfin / dv-bfin_otp.c

/* Blackfin One-Time Programmable Memory (OTP) model

   Copyright (C) 2010-2013 Free Software Foundation, Inc.
   Contributed by Analog Devices, Inc.

   This file is part of simulators.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "sim-main.h"
#include "devices.h"
#include "dv-bfin_otp.h"

/* XXX: No public documentation on this interface.  This seems to work
        with the on-chip ROM functions though and was figured out by
        disassembling & walking that code.  */
/* XXX: About only thing that should be done here are CRC fields.  And
        supposedly there is an interrupt that could be generated.  */

struct bfin_otp
{
  bu32 base;

  /* The actual OTP storage -- 0x200 pages, each page is 128bits.
     While certain pages have predefined and/or secure access, we don't
     bother trying to implement that coverage.  All pages are open for
     reading & writing.  */
  bu32 mem[0x200 * 4];

  /* Order after here is important -- matches hardware MMR layout.  */
  bu16 BFIN_MMR_16(control);
  bu16 BFIN_MMR_16(ben);
  bu16 BFIN_MMR_16(status);
  bu32 timing;
  bu32 _pad0[28];
  bu32 data0, data1, data2, data3;
};
#define mmr_base()      offsetof(struct bfin_otp, control)
#define mmr_offset(mmr) (offsetof(struct bfin_otp, mmr) - mmr_base())
#define mmr_idx(mmr)    (mmr_offset (mmr) / 4)

static const char * const mmr_names[] =
{
  "OTP_CONTROL", "OTP_BEN", "OTP_STATUS", "OTP_TIMING",
  [mmr_idx (data0)] = "OTP_DATA0", "OTP_DATA1", "OTP_DATA2", "OTP_DATA3",
};
#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")

/* XXX: This probably misbehaves with big endian hosts.  */
static void
bfin_otp_transfer (struct bfin_otp *otp, void *vdst, void *vsrc)
{
  bu8 *dst = vdst, *src = vsrc;
  int bidx;
  for (bidx = 0; bidx < 16; ++bidx)
    if (otp->ben & (1 << bidx))
      dst[bidx] = src[bidx];
}

static void
bfin_otp_read_page (struct bfin_otp *otp, bu16 page)
{
  bfin_otp_transfer (otp, &otp->data0, &otp->mem[page * 4]);
}

static void
bfin_otp_write_page_val (struct bfin_otp *otp, bu16 page, bu64 val[2])
{
  bfin_otp_transfer (otp, &otp->mem[page * 4], val);
}
static void
bfin_otp_write_page_val2 (struct bfin_otp *otp, bu16 page, bu64 lo, bu64 hi)
{
  bu64 val[2] = { lo, hi };
  bfin_otp_write_page_val (otp, page, val);
}
static void
bfin_otp_write_page (struct bfin_otp *otp, bu16 page)
{
  bfin_otp_write_page_val (otp, page, (void *)&otp->data0);
}

static unsigned
bfin_otp_io_write_buffer (struct hw *me, const void *source, int space,
			  address_word addr, unsigned nr_bytes)
{
  struct bfin_otp *otp = hw_data (me);
  bu32 mmr_off;
  bu32 value;
  bu16 *value16p;
  bu32 *value32p;
  void *valuep;

  if (nr_bytes == 4)
    value = dv_load_4 (source);
  else
    value = dv_load_2 (source);

  mmr_off = addr - otp->base;
  valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
  value16p = valuep;
  value32p = valuep;

  HW_TRACE_WRITE ();

  switch (mmr_off)
    {
    case mmr_offset(control):
      {
	int page;

	dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
	/* XXX: Seems like these bits aren't writable.  */
	*value16p = value & 0x39FF;

	/* Low bits seem to be the page address.  */
	page = value & PAGE_ADDR;

	/* Write operation.  */
	if (value & DO_WRITE)
	  bfin_otp_write_page (otp, page);

	/* Read operation.  */
	if (value & DO_READ)
	  bfin_otp_read_page (otp, page);

	otp->status |= STATUS_DONE;

	break;
      }
    case mmr_offset(ben):
      dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
      /* XXX: All bits seem to be writable.  */
      *value16p = value;
      break;
    case mmr_offset(status):
      dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
      /* XXX: All bits seem to be W1C.  */
      dv_w1c_2 (value16p, value, -1);
      break;
    case mmr_offset(timing):
    case mmr_offset(data0):
    case mmr_offset(data1):
    case mmr_offset(data2):
    case mmr_offset(data3):
      dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
      *value32p = value;
      break;
    default:
      dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
      break;
    }

  return nr_bytes;
}

static unsigned
bfin_otp_io_read_buffer (struct hw *me, void *dest, int space,
			 address_word addr, unsigned nr_bytes)
{
  struct bfin_otp *otp = hw_data (me);
  bu32 mmr_off;
  bu16 *value16p;
  bu32 *value32p;
  void *valuep;

  mmr_off = addr - otp->base;
  valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
  value16p = valuep;
  value32p = valuep;

  HW_TRACE_READ ();

  switch (mmr_off)
    {
    case mmr_offset(control):
    case mmr_offset(ben):
    case mmr_offset(status):
      dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
      dv_store_2 (dest, *value16p);
      break;
    case mmr_offset(timing):
    case mmr_offset(data0):
    case mmr_offset(data1):
    case mmr_offset(data2):
    case mmr_offset(data3):
      dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
      dv_store_4 (dest, *value32p);
      break;
    default:
      dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
      break;
    }

  return nr_bytes;
}

static void
attach_bfin_otp_regs (struct hw *me, struct bfin_otp *otp)
{
  address_word attach_address;
  int attach_space;
  unsigned attach_size;
  reg_property_spec reg;

  if (hw_find_property (me, "reg") == NULL)
    hw_abort (me, "Missing \"reg\" property");

  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
    hw_abort (me, "\"reg\" property must contain three addr/size entries");

  hw_unit_address_to_attach_address (hw_parent (me),
				     &reg.address,
				     &attach_space, &attach_address, me);
  hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);

  if (attach_size != BFIN_MMR_OTP_SIZE)
    hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_OTP_SIZE);

  hw_attach_address (hw_parent (me),
		     0, attach_space, attach_address, attach_size, me);

  otp->base = attach_address;
}

static const struct hw_port_descriptor bfin_otp_ports[] =
{
  { "stat", 0, 0, output_port, },
  { NULL, 0, 0, 0, },
};

static void
bfin_otp_finish (struct hw *me)
{
  char part_str[16];
  struct bfin_otp *otp;
  unsigned int fps03;
  int type = hw_find_integer_property (me, "type");

  otp = HW_ZALLOC (me, struct bfin_otp);

  set_hw_data (me, otp);
  set_hw_io_read_buffer (me, bfin_otp_io_read_buffer);
  set_hw_io_write_buffer (me, bfin_otp_io_write_buffer);
  set_hw_ports (me, bfin_otp_ports);

  attach_bfin_otp_regs (me, otp);

  /* Initialize the OTP.  */
  otp->ben     = 0xFFFF;
  otp->timing  = 0x00001485;

  /* Semi-random value for unique chip id.  */
  bfin_otp_write_page_val2 (otp, FPS00, (unsigned long)otp, ~(unsigned long)otp);

  memset (part_str, 0, sizeof (part_str));
  sprintf (part_str, "ADSP-BF%iX", type);
  switch (type)
    {
    case 512:
      fps03 = FPS03_BF512;
      break;
    case 514:
      fps03 = FPS03_BF514;
      break;
    case 516:
      fps03 = FPS03_BF516;
      break;
    case 518:
      fps03 = FPS03_BF518;
      break;
    case 522:
      fps03 = FPS03_BF522;
      break;
    case 523:
      fps03 = FPS03_BF523;
      break;
    case 524:
      fps03 = FPS03_BF524;
      break;
    case 525:
      fps03 = FPS03_BF525;
      break;
    case 526:
      fps03 = FPS03_BF526;
      break;
    case 527:
      fps03 = FPS03_BF527;
      break;
    default:
      fps03 = 0;
      break;
    }
  part_str[14] = (fps03 >> 0);
  part_str[15] = (fps03 >> 8);
  bfin_otp_write_page_val (otp, FPS03, (void *)part_str);
}

const struct hw_descriptor dv_bfin_otp_descriptor[] =
{
  {"bfin_otp", bfin_otp_finish,},
  {NULL, NULL},
};
Commit	Line	Data
ef016f83 MF	1	/* Blackfin One-Time Programmable Memory (OTP) model
ef016f83 MF	2
8acc9f48	3	Copyright (C) 2010-2013 Free Software Foundation, Inc.
ef016f83 MF	4	Contributed by Analog Devices, Inc.
	5
	6	This file is part of simulators.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	20
	21	#include "config.h"
	22
	23	#include "sim-main.h"
	24	#include "devices.h"
	25	#include "dv-bfin_otp.h"
	26
	27	/* XXX: No public documentation on this interface. This seems to work
	28	with the on-chip ROM functions though and was figured out by
	29	disassembling & walking that code. */
	30	/* XXX: About only thing that should be done here are CRC fields. And
	31	supposedly there is an interrupt that could be generated. */
	32
	33	struct bfin_otp
	34	{
	35	bu32 base;
	36
	37	/* The actual OTP storage -- 0x200 pages, each page is 128bits.
	38	While certain pages have predefined and/or secure access, we don't
	39	bother trying to implement that coverage. All pages are open for
	40	reading & writing. */
	41	bu32 mem[0x200 * 4];
	42
	43	/* Order after here is important -- matches hardware MMR layout. */
	44	bu16 BFIN_MMR_16(control);
	45	bu16 BFIN_MMR_16(ben);
	46	bu16 BFIN_MMR_16(status);
	47	bu32 timing;
	48	bu32 _pad0[28];
	49	bu32 data0, data1, data2, data3;
	50	};
	51	#define mmr_base() offsetof(struct bfin_otp, control)
	52	#define mmr_offset(mmr) (offsetof(struct bfin_otp, mmr) - mmr_base())
	53	#define mmr_idx(mmr) (mmr_offset (mmr) / 4)
	54
990d19fd MF	55	static const char * const mmr_names[] =
990d19fd MF	56	{
ef016f83 MF	57	"OTP_CONTROL", "OTP_BEN", "OTP_STATUS", "OTP_TIMING",
	58	[mmr_idx (data0)] = "OTP_DATA0", "OTP_DATA1", "OTP_DATA2", "OTP_DATA3",
	59	};
	60	#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
	61
	62	/* XXX: This probably misbehaves with big endian hosts. */
	63	static void
	64	bfin_otp_transfer (struct bfin_otp otp, void vdst, void *vsrc)
	65	{
	66	bu8 dst = vdst, src = vsrc;
	67	int bidx;
	68	for (bidx = 0; bidx < 16; ++bidx)
	69	if (otp->ben & (1 << bidx))
	70	dst[bidx] = src[bidx];
	71	}
	72
	73	static void
	74	bfin_otp_read_page (struct bfin_otp *otp, bu16 page)
	75	{
	76	bfin_otp_transfer (otp, &otp->data0, &otp->mem[page * 4]);
	77	}
	78
	79	static void
	80	bfin_otp_write_page_val (struct bfin_otp *otp, bu16 page, bu64 val[2])
	81	{
	82	bfin_otp_transfer (otp, &otp->mem[page * 4], val);
	83	}
	84	static void
	85	bfin_otp_write_page_val2 (struct bfin_otp *otp, bu16 page, bu64 lo, bu64 hi)
	86	{
	87	bu64 val[2] = { lo, hi };
	88	bfin_otp_write_page_val (otp, page, val);
	89	}
	90	static void
	91	bfin_otp_write_page (struct bfin_otp *otp, bu16 page)
	92	{
	93	bfin_otp_write_page_val (otp, page, (void *)&otp->data0);
	94	}
	95
	96	static unsigned
	97	bfin_otp_io_write_buffer (struct hw me, const void source, int space,
	98	address_word addr, unsigned nr_bytes)
	99	{
	100	struct bfin_otp *otp = hw_data (me);
	101	bu32 mmr_off;
	102	bu32 value;
	103	bu16 *value16p;
	104	bu32 *value32p;
	105	void *valuep;
	106
	107	if (nr_bytes == 4)
	108	value = dv_load_4 (source);
	109	else
	110	value = dv_load_2 (source);
	111
	112	mmr_off = addr - otp->base;
	113	valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
	114	value16p = valuep;
	115	value32p = valuep;
	116
	117	HW_TRACE_WRITE ();
	118
	119	switch (mmr_off)
	120	{
121	case mmr_offset(control):
122	{
123	int page;
124
125	dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
126	/* XXX: Seems like these bits aren't writable. */
127	*value16p = value & 0x39FF;
128
129	/* Low bits seem to be the page address. */
130	page = value & PAGE_ADDR;
131
132	/* Write operation. */
133	if (value & DO_WRITE)
134	bfin_otp_write_page (otp, page);
135
136	/* Read operation. */
137	if (value & DO_READ)
138	bfin_otp_read_page (otp, page);
139
140	otp->status \|= STATUS_DONE;
141
142	break;
143	}
144	case mmr_offset(ben):
145	dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
146	/* XXX: All bits seem to be writable. */
147	*value16p = value;
148	break;
149	case mmr_offset(status):
150	dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
151	/* XXX: All bits seem to be W1C. */
9922f803	152	dv_w1c_2 (value16p, value, -1);
ef016f83 MF	153	break;
	154	case mmr_offset(timing):
	155	case mmr_offset(data0):
	156	case mmr_offset(data1):
	157	case mmr_offset(data2):
	158	case mmr_offset(data3):
	159	dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
	160	*value32p = value;
	161	break;
	162	default:
	163	dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
	164	break;
	165	}
	166
	167	return nr_bytes;
	168	}
	169
	170	static unsigned
	171	bfin_otp_io_read_buffer (struct hw me, void dest, int space,
	172	address_word addr, unsigned nr_bytes)
	173	{
	174	struct bfin_otp *otp = hw_data (me);
	175	bu32 mmr_off;
	176	bu16 *value16p;
	177	bu32 *value32p;
	178	void *valuep;
	179
	180	mmr_off = addr - otp->base;
	181	valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
	182	value16p = valuep;
	183	value32p = valuep;
	184
	185	HW_TRACE_READ ();
	186
	187	switch (mmr_off)
	188	{
	189	case mmr_offset(control):
	190	case mmr_offset(ben):
	191	case mmr_offset(status):
	192	dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
	193	dv_store_2 (dest, *value16p);
	194	break;
	195	case mmr_offset(timing):
	196	case mmr_offset(data0):
	197	case mmr_offset(data1):
	198	case mmr_offset(data2):
	199	case mmr_offset(data3):
	200	dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
	201	dv_store_4 (dest, *value32p);
	202	break;
	203	default:
	204	dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
	205	break;
	206	}
	207
	208	return nr_bytes;
	209	}
	210
	211	static void
	212	attach_bfin_otp_regs (struct hw me, struct bfin_otp otp)
	213	{
	214	address_word attach_address;
	215	int attach_space;
	216	unsigned attach_size;
217	reg_property_spec reg;
218
219	if (hw_find_property (me, "reg") == NULL)
220	hw_abort (me, "Missing \"reg\" property");
221
222	if (!hw_find_reg_array_property (me, "reg", 0, &reg))
223	hw_abort (me, "\"reg\" property must contain three addr/size entries");
224
225	hw_unit_address_to_attach_address (hw_parent (me),
226	&reg.address,
227	&attach_space, &attach_address, me);
228	hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
229
230	if (attach_size != BFIN_MMR_OTP_SIZE)
231	hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_OTP_SIZE);
232
233	hw_attach_address (hw_parent (me),
234	0, attach_space, attach_address, attach_size, me);
235
236	otp->base = attach_address;
237	}
238
2b12772f MF	239	static const struct hw_port_descriptor bfin_otp_ports[] =
	240	{
	241	{ "stat", 0, 0, output_port, },
	242	{ NULL, 0, 0, 0, },
	243	};
	244
ef016f83 MF	245	static void
	246	bfin_otp_finish (struct hw *me)
	247	{
	248	char part_str[16];
	249	struct bfin_otp *otp;
	250	unsigned int fps03;
	251	int type = hw_find_integer_property (me, "type");
	252
	253	otp = HW_ZALLOC (me, struct bfin_otp);
	254
	255	set_hw_data (me, otp);
	256	set_hw_io_read_buffer (me, bfin_otp_io_read_buffer);
	257	set_hw_io_write_buffer (me, bfin_otp_io_write_buffer);
2b12772f	258	set_hw_ports (me, bfin_otp_ports);
ef016f83 MF	259
	260	attach_bfin_otp_regs (me, otp);
	261
	262	/* Initialize the OTP. */
	263	otp->ben = 0xFFFF;
	264	otp->timing = 0x00001485;
	265
	266	/* Semi-random value for unique chip id. */
	267	bfin_otp_write_page_val2 (otp, FPS00, (unsigned long)otp, ~(unsigned long)otp);
	268
	269	memset (part_str, 0, sizeof (part_str));
	270	sprintf (part_str, "ADSP-BF%iX", type);
	271	switch (type)
	272	{
	273	case 512:
	274	fps03 = FPS03_BF512;
	275	break;
	276	case 514:
	277	fps03 = FPS03_BF514;
	278	break;
	279	case 516:
	280	fps03 = FPS03_BF516;
	281	break;
	282	case 518:
	283	fps03 = FPS03_BF518;
	284	break;
	285	case 522:
	286	fps03 = FPS03_BF522;
	287	break;
	288	case 523:
	289	fps03 = FPS03_BF523;
	290	break;
	291	case 524:
	292	fps03 = FPS03_BF524;
	293	break;
	294	case 525:
	295	fps03 = FPS03_BF525;
	296	break;
	297	case 526:
	298	fps03 = FPS03_BF526;
	299	break;
	300	case 527:
	301	fps03 = FPS03_BF527;
	302	break;
	303	default:
	304	fps03 = 0;
	305	break;
	306	}
	307	part_str[14] = (fps03 >> 0);
	308	part_str[15] = (fps03 >> 8);
	309	bfin_otp_write_page_val (otp, FPS03, (void *)part_str);
	310	}
	311
81d126c3 MF	312	const struct hw_descriptor dv_bfin_otp_descriptor[] =
81d126c3 MF	313	{
ef016f83 MF	314	{"bfin_otp", bfin_otp_finish,},
	315	{NULL, NULL},
	316	};