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sim: bfin: move model data into machs.h
[thirdparty/binutils-gdb.git] / sim / bfin / machs.c
CommitLineData
ef016f83
MF		 1/* Simulator for Analog Devices Blackfin processors.
2
3 Copyright (C) 2005-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "config.h"
22
23#include "sim-main.h"
24#include "gdb/sim-bfin.h"
25#include "bfd.h"
26
27#include "sim-hw.h"
28#include "devices.h"
29#include "dv-bfin_cec.h"
ef016f83 30#include "dv-bfin_dmac.h"
ef016f83
MF		 31
32static const MACH bfin_mach;
33
34struct bfin_memory_layout {
35 address_word addr, len;
36 unsigned mask; /* see mapmask in sim_core_attach() */
37};
38struct bfin_dev_layout {
39 address_word base, len;
40 unsigned int dmac;
41 const char *dev;
42};
43struct bfin_dmac_layout {
44 address_word base;
45 unsigned int dma_count;
46};
47struct bfin_model_data {
48 bu32 chipid;
49 int model_num;
50 const struct bfin_memory_layout *mem;
51 size_t mem_count;
52 const struct bfin_dev_layout *dev;
53 size_t dev_count;
54 const struct bfin_dmac_layout *dmac;
55 size_t dmac_count;
56};
57
58#define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, }
59#define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, }
60#define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0)
61
62/* [1] Common sim code can't model exec-only memory.
63 http://sourceware.org/ml/gdb/2010-02/msg00047.html */
64
65#define bf000_chipid 0
66static const struct bfin_memory_layout bf000_mem[] = {};
67static const struct bfin_dev_layout bf000_dev[] = {};
68static const struct bfin_dmac_layout bf000_dmac[] = {};
69
70#define bf50x_chipid 0x2800
71#define bf504_chipid bf50x_chipid
72#define bf506_chipid bf50x_chipid
990d19fd
MF		 73static const struct bfin_memory_layout bf50x_mem[] =
74{
ef016f83
MF		 75 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
76 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 77 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
78 LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
79 LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
80 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
81 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
82 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
83 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */
84};
85#define bf504_mem bf50x_mem
86#define bf506_mem bf50x_mem
990d19fd
MF		 87static const struct bfin_dev_layout bf50x_dev[] =
88{
ef016f83
MF		 89 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
90 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
91 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
92 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
93 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
94 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
95 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
96 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
97 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
98 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
99 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 100 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 101 DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
102 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
103 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 104 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
105 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 106 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
107 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
108};
109#define bf504_dev bf50x_dev
110#define bf506_dev bf50x_dev
990d19fd
MF		 111static const struct bfin_dmac_layout bf50x_dmac[] =
112{
ef016f83
MF		 113 { BFIN_MMR_DMAC0_BASE, 12, },
114};
115#define bf504_dmac bf50x_dmac
116#define bf506_dmac bf50x_dmac
117
118#define bf51x_chipid 0x27e8
119#define bf512_chipid bf51x_chipid
120#define bf514_chipid bf51x_chipid
121#define bf516_chipid bf51x_chipid
122#define bf518_chipid bf51x_chipid
990d19fd
MF		 123static const struct bfin_memory_layout bf51x_mem[] =
124{
ef016f83 125 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 126 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
127 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 128 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
129 LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
130 LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
131 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
132 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
133 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
134 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
135 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
136 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
137};
138#define bf512_mem bf51x_mem
139#define bf514_mem bf51x_mem
140#define bf516_mem bf51x_mem
141#define bf518_mem bf51x_mem
990d19fd
MF		 142static const struct bfin_dev_layout bf512_dev[] =
143{
ef016f83
MF		 144 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
145 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
146 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
147 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
148 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
149 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
150 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
151 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
152 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
153 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
154 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
155 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 156 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 157 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
158 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
159 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
160 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 161 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
162 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 163 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
164 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
165 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
166};
167#define bf514_dev bf512_dev
990d19fd
MF		 168static const struct bfin_dev_layout bf516_dev[] =
169{
ef016f83
MF		 170 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
171 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
172 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
173 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
174 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
175 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
176 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
177 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
178 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
179 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
180 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
181 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 182 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 183 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
184 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
185 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
186 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 187 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
188 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 189 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
190 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
191 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
192 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
193 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
194};
195#define bf518_dev bf516_dev
196#define bf512_dmac bf50x_dmac
197#define bf514_dmac bf50x_dmac
198#define bf516_dmac bf50x_dmac
199#define bf518_dmac bf50x_dmac
200
201#define bf522_chipid 0x27e4
202#define bf523_chipid 0x27e0
203#define bf524_chipid bf522_chipid
204#define bf525_chipid bf523_chipid
205#define bf526_chipid bf522_chipid
206#define bf527_chipid bf523_chipid
990d19fd
MF		 207static const struct bfin_memory_layout bf52x_mem[] =
208{
ef016f83 209 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 210 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
211 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 212 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
213 LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
214 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
215 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
216 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
217 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
218 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
219 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
220 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
221};
222#define bf522_mem bf52x_mem
223#define bf523_mem bf52x_mem
224#define bf524_mem bf52x_mem
225#define bf525_mem bf52x_mem
226#define bf526_mem bf52x_mem
227#define bf527_mem bf52x_mem
990d19fd
MF		 228static const struct bfin_dev_layout bf522_dev[] =
229{
ef016f83
MF		 230 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
231 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
232 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
233 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
234 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
235 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
236 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
237 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
238 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
239 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
240 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
241 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 242 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 243 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
244 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
245 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
246 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 247 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
248 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 249 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
250 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
251 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
252};
253#define bf523_dev bf522_dev
254#define bf524_dev bf522_dev
255#define bf525_dev bf522_dev
990d19fd
MF		 256static const struct bfin_dev_layout bf526_dev[] =
257{
ef016f83
MF		 258 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
259 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
260 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
261 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
262 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
263 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
264 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
265 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
266 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
267 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
268 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
269 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 270 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 271 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
272 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
273 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
274 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 275 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
276 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 277 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
278 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
279 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
280 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
281 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
282};
283#define bf527_dev bf526_dev
284#define bf522_dmac bf50x_dmac
285#define bf523_dmac bf50x_dmac
286#define bf524_dmac bf50x_dmac
287#define bf525_dmac bf50x_dmac
288#define bf526_dmac bf50x_dmac
289#define bf527_dmac bf50x_dmac
290
291#define bf531_chipid 0x27a5
292#define bf532_chipid bf531_chipid
293#define bf533_chipid bf531_chipid
990d19fd
MF		 294static const struct bfin_memory_layout bf531_mem[] =
295{
ef016f83 296 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 297 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
298 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
299 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
300 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
301 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
302};
990d19fd
MF		 303static const struct bfin_memory_layout bf532_mem[] =
304{
ef016f83 305 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 306 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
307 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
308 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
309 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
310 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
311 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
312 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
313};
990d19fd
MF		 314static const struct bfin_memory_layout bf533_mem[] =
315{
ef016f83 316 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 317 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
318 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
319 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
320 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
321 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
322 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
323 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
324 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
325 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
326 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
327};
990d19fd
MF		 328static const struct bfin_dev_layout bf533_dev[] =
329{
ef016f83
MF		 330 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
331 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
332 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
333 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
334 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
335 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
336 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
a9c3ef47 337 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 338 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
339 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
340 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
341};
342#define bf531_dev bf533_dev
343#define bf532_dev bf533_dev
990d19fd
MF		 344static const struct bfin_dmac_layout bf533_dmac[] =
345{
ef016f83
MF		 346 { BFIN_MMR_DMAC0_BASE, 8, },
347};
348#define bf531_dmac bf533_dmac
349#define bf532_dmac bf533_dmac
350
351#define bf534_chipid 0x27c6
352#define bf536_chipid 0x27c8
353#define bf537_chipid bf536_chipid
990d19fd
MF		 354static const struct bfin_memory_layout bf534_mem[] =
355{
ef016f83 356 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 357 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
358 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 359 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
360 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
361 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
362 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
363 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
364 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
365 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
366 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
367};
990d19fd
MF		 368static const struct bfin_memory_layout bf536_mem[] =
369{
ef016f83 370 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 371 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
372 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 373 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
374 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
375 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
376 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
377 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
378 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
379};
990d19fd
MF		 380static const struct bfin_memory_layout bf537_mem[] =
381{
ef016f83 382 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 383 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
384 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 385 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
386 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
387 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
388 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
389 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
390 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
391 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
392 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
393};
990d19fd
MF		 394static const struct bfin_dev_layout bf534_dev[] =
395{
ef016f83
MF		 396 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
397 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
398 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
399 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
400 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
401 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
402 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
403 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
404 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
405 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
406 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
407 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 408 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 409 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
410 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
411 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
412 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 413 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
414 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 415 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
416};
990d19fd
MF		 417static const struct bfin_dev_layout bf537_dev[] =
418{
ef016f83
MF		 419 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
420 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
421 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
422 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
423 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
424 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
425 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
426 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
427 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
428 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
429 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
430 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 431 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 432 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
433 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
434 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
435 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 436 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
437 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 438 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
439 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
440 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
441};
442#define bf536_dev bf537_dev
443#define bf534_dmac bf50x_dmac
444#define bf536_dmac bf50x_dmac
445#define bf537_dmac bf50x_dmac
446
447#define bf538_chipid 0x27c4
448#define bf539_chipid bf538_chipid
990d19fd
MF		 449static const struct bfin_memory_layout bf538_mem[] =
450{
ef016f83
MF		 451 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
452 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
453 LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
454 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
455 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
456 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
457 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
458 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
459 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
460 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
461 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
462 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
463 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
464};
465#define bf539_mem bf538_mem
990d19fd
MF		 466static const struct bfin_dev_layout bf538_dev[] =
467{
ef016f83
MF		 468 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
469 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
470 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
471 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
472 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
473 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
474 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
475 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
476 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
477 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
478 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47 479 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 480 _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
481 _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
482 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
483 _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1),
484 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
485};
486#define bf539_dev bf538_dev
990d19fd
MF		 487static const struct bfin_dmac_layout bf538_dmac[] =
488{
ef016f83
MF		 489 { BFIN_MMR_DMAC0_BASE, 8, },
490 { BFIN_MMR_DMAC1_BASE, 12, },
491};
492#define bf539_dmac bf538_dmac
493
494#define bf54x_chipid 0x27de
495#define bf542_chipid bf54x_chipid
496#define bf544_chipid bf54x_chipid
497#define bf547_chipid bf54x_chipid
498#define bf548_chipid bf54x_chipid
499#define bf549_chipid bf54x_chipid
990d19fd
MF		 500static const struct bfin_memory_layout bf54x_mem[] =
501{
ef016f83
MF		 502 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */
503 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
504 LAYOUT (0xFFC01400, 0x200, read_write), /* PORT/GPIO stub */
505 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
506 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
507 LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */
508 LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */
509 LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */
510 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
511 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
512 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
513 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
514 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
515 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
516 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
517 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
518};
519#define bf542_mem bf54x_mem
520#define bf544_mem bf54x_mem
521#define bf547_mem bf54x_mem
522#define bf548_mem bf54x_mem
523#define bf549_mem bf54x_mem
990d19fd
MF		 524static const struct bfin_dev_layout bf542_dev[] =
525{
ef016f83
MF		 526 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
527 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
528 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
529 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
530 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
531 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
532 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
533 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
534 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
535 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
536 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
537 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
538 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
539 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
540 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
541 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
542 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
543 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
544 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
545 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
546 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
547 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
548 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
549};
990d19fd
MF		 550static const struct bfin_dev_layout bf544_dev[] =
551{
ef016f83
MF		 552 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
553 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
554 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
555 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
556 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
557 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
558 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
559 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
560 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
561 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
562 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
563 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
564 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
565 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
566 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
567 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
568 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
569 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
570 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
571 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
572 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
573 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
574 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
575 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
576 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
577 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
578 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
579 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
580};
990d19fd
MF		 581static const struct bfin_dev_layout bf547_dev[] =
582{
ef016f83
MF		 583 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
584 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
585 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
586 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
587 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
588 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
589 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
590 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
591 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
592 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
593 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
594 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
595 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
596 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
597 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
598 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
599 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
600 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
601 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
602 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
603 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
604 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
605 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
606 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
607 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
608 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
609 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
610 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
611};
612#define bf548_dev bf547_dev
613#define bf549_dev bf547_dev
990d19fd
MF		 614static const struct bfin_dmac_layout bf54x_dmac[] =
615{
ef016f83
MF		 616 { BFIN_MMR_DMAC0_BASE, 12, },
617 { BFIN_MMR_DMAC1_BASE, 12, },
618};
619#define bf542_dmac bf54x_dmac
620#define bf544_dmac bf54x_dmac
621#define bf547_dmac bf54x_dmac
622#define bf548_dmac bf54x_dmac
623#define bf549_dmac bf54x_dmac
624
625/* This is only Core A of course ... */
626#define bf561_chipid 0x27bb
990d19fd
MF		 627static const struct bfin_memory_layout bf561_mem[] =
628{
ef016f83
MF		 629 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
630 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 631 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
632 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
633 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
634 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
635 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
636 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
637 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
638};
990d19fd
MF		 639static const struct bfin_dev_layout bf561_dev[] =
640{
ef016f83
MF		 641 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
642 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
643 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
644 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
645 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
646 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
647 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
648 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
649 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
650 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
651 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 652 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 653 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
654 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
655 _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
656 DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
657 _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
a9c3ef47 658 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
ef016f83
MF		 659 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
660 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
661 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
662 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
a9c3ef47 663 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83 664};
990d19fd
MF		 665static const struct bfin_dmac_layout bf561_dmac[] =
666{
ef016f83
MF		 667 { BFIN_MMR_DMAC0_BASE, 12, },
668 { BFIN_MMR_DMAC1_BASE, 12, },
669 /* XXX: IMDMA: { 0xFFC01800, 4, }, */
670};
671
672#define bf592_chipid 0x20cb
990d19fd
MF		 673static const struct bfin_memory_layout bf592_mem[] =
674{
ef016f83
MF		 675 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
676 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 677 LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
678 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
679 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
680};
990d19fd
MF		 681static const struct bfin_dev_layout bf592_dev[] =
682{
ef016f83
MF		 683 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
684 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
685 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
686 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
687 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
688 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
a9c3ef47 689 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 690 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
691 DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
692 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47 693 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
ef016f83 694};
990d19fd
MF		 695static const struct bfin_dmac_layout bf592_dmac[] =
696{
ef016f83
MF		 697 /* XXX: there are only 9 channels, but mdma code below assumes that they
698 start right after the dma channels ... */
699 { BFIN_MMR_DMAC0_BASE, 12, },
700};
701
702static const struct bfin_model_data bfin_model_data[] =
703{
704#define P(n) \
705 [MODEL_BF##n] = { \
706 bf##n##_chipid, n, \
707 bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \
708 bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \
709 bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \
710 },
711#include "proc_list.def"
712#undef P
713};
714
715#define CORE_DEVICE(dev, DEV) \
716 DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev)
990d19fd
MF		 717static const struct bfin_dev_layout bfin_core_dev[] =
718{
ef016f83
MF		 719 CORE_DEVICE (cec, CEC),
720 CORE_DEVICE (ctimer, CTIMER),
721 CORE_DEVICE (evt, EVT),
722 CORE_DEVICE (jtag, JTAG),
723 CORE_DEVICE (mmu, MMU),
c43aadca 724 CORE_DEVICE (pfmon, PFMON),
ef016f83
MF		 725 CORE_DEVICE (trace, TRACE),
726 CORE_DEVICE (wp, WP),
727};
728
729#define dv_bfin_hw_parse(sd, dv, DV) \
730 do { \
731 bu32 base = BFIN_MMR_##DV##_BASE; \
732 bu32 size = BFIN_MMR_##DV##_SIZE; \
733 sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \
734 sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \
735 } while (0)
736
737static void
738bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
739{
740 const MODEL *model = CPU_MODEL (cpu);
741 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
742 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
743 int mnum = MODEL_NUM (model);
744 unsigned i, j, dma_chan;
745
746 /* Map the core devices. */
747 for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i)
748 {
749 const struct bfin_dev_layout *dev = &bfin_core_dev[i];
750 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
751 }
752 sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec");
753
754 if (mnum == MODEL_BF000)
755 goto done;
756
757 /* Map the system devices. */
758 dv_bfin_hw_parse (sd, sic, SIC);
759 sim_hw_parse (sd, "/core/bfin_sic/type %i", mdata->model_num);
760 for (i = 7; i < 16; ++i)
761 sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
762
763 dv_bfin_hw_parse (sd, pll, PLL);
764 sim_hw_parse (sd, "/core/bfin_pll > pll pll /core/bfin_sic");
765
766 dma_chan = 0;
767 for (i = 0; i < mdata->dmac_count; ++i)
768 {
769 const struct bfin_dmac_layout *dmac = &mdata->dmac[i];
770
771 sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num);
772
773 /* Hook up the non-mdma channels. */
774 for (j = 0; j < dmac->dma_count; ++j)
775 {
776 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i", i,
777 dma_chan, dmac->base + j * BFIN_MMR_DMA_SIZE,
778 BFIN_MMR_DMA_SIZE);
779
780 /* Could route these into the bfin_dmac and let that
781 forward it to the SIC, but not much value. */
782 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di dma@%u /core/bfin_sic",
783 i, dma_chan, dma_chan);
784
785 ++dma_chan;
786 }
787
788 /* Hook up the mdma channels -- assume every DMAC has 4. */
789 for (j = 0; j < 4; ++j)
790 {
791 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i",
792 i, j + BFIN_DMAC_MDMA_BASE,
793 dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE,
794 BFIN_MMR_DMA_SIZE);
795 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di mdma@%u /core/bfin_sic",
796 i, j + BFIN_DMAC_MDMA_BASE, (2 * i) + (j / 2));
797 }
798 }
799
800 for (i = 0; i < mdata->dev_count; ++i)
801 {
802 const struct bfin_dev_layout *dev = &mdata->dev[i];
803 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
804 sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
805 if (strchr (dev->dev, '/'))
806 continue;
807 if (!strncmp (dev->dev, "bfin_uart", 9)
808 || !strncmp (dev->dev, "bfin_emac", 9)
809 || !strncmp (dev->dev, "bfin_sport", 10))
810 {
811 const char *sint = dev->dev + 5;
812 sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
813 sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
814 sim_hw_parse (sd, "/core/%s > stat %s_stat /core/bfin_sic", dev->dev, sint);
815 }
816 else if (!strncmp (dev->dev, "bfin_gptimer", 12)
817 || !strncmp (dev->dev, "bfin_ppi", 8)
818 || !strncmp (dev->dev, "bfin_spi", 8)
819 || !strncmp (dev->dev, "bfin_twi", 8))
820 {
821 const char *sint = dev->dev + 5;
822 sim_hw_parse (sd, "/core/%s > stat %s /core/bfin_sic", dev->dev, sint);
823 }
824 else if (!strncmp (dev->dev, "bfin_rtc", 8))
825 {
826 const char *sint = dev->dev + 5;
827 sim_hw_parse (sd, "/core/%s > %s %s /core/bfin_sic", dev->dev, sint, sint);
828 }
829 else if (!strncmp (dev->dev, "bfin_wdog", 9))
830 {
831 sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev);
832 sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
833 sim_hw_parse (sd, "/core/%s > gpi wdog /core/bfin_sic", dev->dev);
834 }
b5215db0
MF		 835 else if (!strncmp (dev->dev, "bfin_gpio", 9))
836 {
a9c3ef47 837 char port = 'a' + strtol(&dev->dev[10], NULL, 0);
b5215db0 838 sim_hw_parse (sd, "/core/%s > mask_a port%c_irq_a /core/bfin_sic",
a9c3ef47 839 dev->dev, port);
b5215db0 840 sim_hw_parse (sd, "/core/%s > mask_b port%c_irq_b /core/bfin_sic",
a9c3ef47 841 dev->dev, port);
b5215db0 842 }
ef016f83
MF		 843 }
844
845 done:
846 /* Add any additional user board content. */
847 if (board->hw_file)
848 sim_do_commandf (sd, "hw-file %s", board->hw_file);
849
850 /* Trigger all the new devices' finish func. */
851 hw_tree_finish (dv_get_device (cpu, "/"));
852}
853
854#include "bfroms/all.h"
855
856struct bfrom {
857 bu32 addr, len, alias_len;
858 int sirev;
859 const char *buf;
860};
861
862#define BFROMA(addr, rom, sirev, alias_len) \
863 { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \
864 sirev, bfrom_bf##rom##_0_##sirev, }
865#define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len)
866#define BFROM_STUB { 0, 0, 0, 0, NULL, }
990d19fd
MF		 867static const struct bfrom bf50x_roms[] =
868{
ef016f83
MF		 869 BFROM (50x, 0, 0x1000000),
870 BFROM_STUB,
871};
990d19fd
MF		 872static const struct bfrom bf51x_roms[] =
873{
ef016f83
MF		 874 BFROM (51x, 2, 0x1000000),
875 BFROM (51x, 1, 0x1000000),
876 BFROM (51x, 0, 0x1000000),
877 BFROM_STUB,
878};
990d19fd
MF		 879static const struct bfrom bf526_roms[] =
880{
dfb61fb6 881 BFROM (526, 2, 0x1000000),
ef016f83
MF		 882 BFROM (526, 1, 0x1000000),
883 BFROM (526, 0, 0x1000000),
884 BFROM_STUB,
885};
990d19fd
MF		 886static const struct bfrom bf527_roms[] =
887{
ef016f83
MF		 888 BFROM (527, 2, 0x1000000),
889 BFROM (527, 1, 0x1000000),
890 BFROM (527, 0, 0x1000000),
891 BFROM_STUB,
892};
990d19fd
MF		 893static const struct bfrom bf533_roms[] =
894{
ef016f83
MF		 895 BFROM (533, 6, 0x1000000),
896 BFROM (533, 5, 0x1000000),
897 BFROM (533, 4, 0x1000000),
898 BFROM (533, 3, 0x1000000),
899 BFROM (533, 2, 0x1000000),
900 BFROM (533, 1, 0x1000000),
901 BFROM_STUB,
902};
990d19fd
MF		 903static const struct bfrom bf537_roms[] =
904{
ef016f83
MF		 905 BFROM (537, 3, 0x100000),
906 BFROM (537, 2, 0x100000),
907 BFROM (537, 1, 0x100000),
908 BFROM (537, 0, 0x100000),
909 BFROM_STUB,
910};
990d19fd
MF		 911static const struct bfrom bf538_roms[] =
912{
ef016f83
MF		 913 BFROM (538, 5, 0x1000000),
914 BFROM (538, 4, 0x1000000),
915 BFROM (538, 3, 0x1000000),
916 BFROM (538, 2, 0x1000000),
917 BFROM (538, 1, 0x1000000),
918 BFROM (538, 0, 0x1000000),
919 BFROM_STUB,
920};
990d19fd
MF		 921static const struct bfrom bf54x_roms[] =
922{
dfb61fb6 923 BFROM (54x, 4, 0),
ef016f83
MF		 924 BFROM (54x, 2, 0),
925 BFROM (54x, 1, 0),
926 BFROM (54x, 0, 0),
dfb61fb6 927 BFROMA (0xffa14000, 54x_l1, 4, 0),
ef016f83
MF		 928 BFROMA (0xffa14000, 54x_l1, 2, 0),
929 BFROMA (0xffa14000, 54x_l1, 1, 0),
930 BFROMA (0xffa14000, 54x_l1, 0, 0),
931 BFROM_STUB,
932};
990d19fd
MF		 933static const struct bfrom bf561_roms[] =
934{
ef016f83
MF		 935 /* XXX: No idea what the actual wrap limit is here. */
936 BFROM (561, 5, 0),
937 BFROM_STUB,
938};
990d19fd
MF		 939static const struct bfrom bf59x_roms[] =
940{
ef016f83
MF		 941 BFROM (59x, 1, 0x1000000),
942 BFROM (59x, 0, 0x1000000),
943 BFROMA (0xffa10000, 59x_l1, 1, 0),
944 BFROM_STUB,
945};
946
947static void
948bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu)
949{
950 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
951 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
952 int mnum = mdata->model_num;
953 const struct bfrom *bfrom;
954 unsigned int sirev;
955
956 if (mnum >= 500 && mnum <= 509)
957 bfrom = bf50x_roms;
958 else if (mnum >= 510 && mnum <= 519)
959 bfrom = bf51x_roms;
960 else if (mnum >= 520 && mnum <= 529)
961 bfrom = (mnum & 1) ? bf527_roms : bf526_roms;
962 else if (mnum >= 531 && mnum <= 533)
963 bfrom = bf533_roms;
964 else if (mnum == 535)
965 /* Stub. */;
966 else if (mnum >= 534 && mnum <= 537)
967 bfrom = bf537_roms;
968 else if (mnum >= 538 && mnum <= 539)
969 bfrom = bf538_roms;
970 else if (mnum >= 540 && mnum <= 549)
971 bfrom = bf54x_roms;
972 else if (mnum == 561)
973 bfrom = bf561_roms;
974 else if (mnum >= 590 && mnum <= 599)
975 bfrom = bf59x_roms;
976 else
977 return;
978
979 if (board->sirev_valid)
980 sirev = board->sirev;
981 else
982 sirev = bfrom->sirev;
983 while (bfrom->buf)
984 {
985 /* Map all the ranges for this model/sirev. */
986 if (bfrom->sirev == sirev)
987 sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr,
988 bfrom->alias_len ? : bfrom->len, bfrom->len, NULL,
989 (char *)bfrom->buf);
990 ++bfrom;
991 }
992}
993
994void
995bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu)
996{
997 const MODEL *model = CPU_MODEL (cpu);
998 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
999 int mnum = MODEL_NUM (model);
1000 size_t idx;
1001
1002 /* These memory maps are supposed to be cpu-specific, but the common sim
1003 code does not yet allow that (2nd arg is "cpu" rather than "NULL". */
1004 sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH,
1005 BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL);
1006
1007 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
1008 return;
1009
1010 if (mnum == MODEL_BF000)
1011 goto core_only;
1012
1013 /* Map in the on-chip memories (SRAMs). */
1014 mdata = &bfin_model_data[MODEL_NUM (model)];
1015 for (idx = 0; idx < mdata->mem_count; ++idx)
1016 {
1017 const struct bfin_memory_layout *mem = &mdata->mem[idx];
1018 sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr,
1019 mem->len, 0, NULL, NULL);
1020 }
1021
1022 /* Map the on-chip ROMs. */
1023 bfin_model_map_bfrom (sd, cpu);
1024
1025 core_only:
1026 /* Finally, build up the tree for this cpu model. */
1027 bfin_model_hw_tree_init (sd, cpu);
1028}
1029
1030bu32
1031bfin_model_get_chipid (SIM_DESC sd)
1032{
1033 SIM_CPU *cpu = STATE_CPU (sd, 0);
1034 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1035 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1036 return
1037 (board->sirev << 28) |
1038 (mdata->chipid << 12) |
1039 (((0xE5 << 1) | 1) & 0xFF);
1040}
1041
1042bu32
1043bfin_model_get_dspid (SIM_DESC sd)
1044{
1045 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1046 return
1047 (0xE5 << 24) |
1048 (0x04 << 16) |
1049 (board->sirev);
1050}
1051
1052static void
1053bfin_model_init (SIM_CPU *cpu)
1054{
1055 CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))];
1056}
1057
1058static bu32
1059bfin_extract_unsigned_integer (unsigned char *addr, int len)
1060{
1061 bu32 retval;
1062 unsigned char * p;
1063 unsigned char * startaddr = (unsigned char *)addr;
1064 unsigned char * endaddr = startaddr + len;
1065
1066 retval = 0;
1067
1068 for (p = endaddr; p > startaddr;)
1069 retval = (retval << 8) | *--p;
1070
1071 return retval;
1072}
1073
1074static void
1075bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val)
1076{
1077 unsigned char *p;
1078 unsigned char *startaddr = addr;
1079 unsigned char *endaddr = startaddr + len;
1080
1081 for (p = startaddr; p < endaddr;)
1082 {
1083 *p++ = val & 0xff;
1084 val >>= 8;
1085 }
1086}
1087
1088static bu32 *
1089bfin_get_reg (SIM_CPU *cpu, int rn)
1090{
1091 switch (rn)
1092 {
1093 case SIM_BFIN_R0_REGNUM: return &DREG (0);
1094 case SIM_BFIN_R1_REGNUM: return &DREG (1);
1095 case SIM_BFIN_R2_REGNUM: return &DREG (2);
1096 case SIM_BFIN_R3_REGNUM: return &DREG (3);
1097 case SIM_BFIN_R4_REGNUM: return &DREG (4);
1098 case SIM_BFIN_R5_REGNUM: return &DREG (5);
1099 case SIM_BFIN_R6_REGNUM: return &DREG (6);
1100 case SIM_BFIN_R7_REGNUM: return &DREG (7);
1101 case SIM_BFIN_P0_REGNUM: return &PREG (0);
1102 case SIM_BFIN_P1_REGNUM: return &PREG (1);
1103 case SIM_BFIN_P2_REGNUM: return &PREG (2);
1104 case SIM_BFIN_P3_REGNUM: return &PREG (3);
1105 case SIM_BFIN_P4_REGNUM: return &PREG (4);
1106 case SIM_BFIN_P5_REGNUM: return &PREG (5);
1107 case SIM_BFIN_SP_REGNUM: return &SPREG;
1108 case SIM_BFIN_FP_REGNUM: return &FPREG;
1109 case SIM_BFIN_I0_REGNUM: return &IREG (0);
1110 case SIM_BFIN_I1_REGNUM: return &IREG (1);
1111 case SIM_BFIN_I2_REGNUM: return &IREG (2);
1112 case SIM_BFIN_I3_REGNUM: return &IREG (3);
1113 case SIM_BFIN_M0_REGNUM: return &MREG (0);
1114 case SIM_BFIN_M1_REGNUM: return &MREG (1);
1115 case SIM_BFIN_M2_REGNUM: return &MREG (2);
1116 case SIM_BFIN_M3_REGNUM: return &MREG (3);
1117 case SIM_BFIN_B0_REGNUM: return &BREG (0);
1118 case SIM_BFIN_B1_REGNUM: return &BREG (1);
1119 case SIM_BFIN_B2_REGNUM: return &BREG (2);
1120 case SIM_BFIN_B3_REGNUM: return &BREG (3);
1121 case SIM_BFIN_L0_REGNUM: return &LREG (0);
1122 case SIM_BFIN_L1_REGNUM: return &LREG (1);
1123 case SIM_BFIN_L2_REGNUM: return &LREG (2);
1124 case SIM_BFIN_L3_REGNUM: return &LREG (3);
1125 case SIM_BFIN_RETS_REGNUM: return &RETSREG;
1126 case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0);
1127 case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0);
1128 case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1);
1129 case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1);
1130 case SIM_BFIN_LC0_REGNUM: return &LCREG (0);
1131 case SIM_BFIN_LT0_REGNUM: return &LTREG (0);
1132 case SIM_BFIN_LB0_REGNUM: return &LBREG (0);
1133 case SIM_BFIN_LC1_REGNUM: return &LCREG (1);
1134 case SIM_BFIN_LT1_REGNUM: return &LTREG (1);
1135 case SIM_BFIN_LB1_REGNUM: return &LBREG (1);
1136 case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG;
1137 case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG;
1138 case SIM_BFIN_USP_REGNUM: return &USPREG;
1139 case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG;
1140 case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG;
1141 case SIM_BFIN_RETI_REGNUM: return &RETIREG;
1142 case SIM_BFIN_RETX_REGNUM: return &RETXREG;
1143 case SIM_BFIN_RETN_REGNUM: return &RETNREG;
1144 case SIM_BFIN_RETE_REGNUM: return &RETEREG;
1145 case SIM_BFIN_PC_REGNUM: return &PCREG;
1146 default: return NULL;
1147 }
1148}
1149
1150static int
1151bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1152{
1153 bu32 value, *reg;
1154
1155 reg = bfin_get_reg (cpu, rn);
1156 if (reg)
1157 value = *reg;
1158 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1159 value = ASTAT;
1160 else if (rn == SIM_BFIN_CC_REGNUM)
1161 value = CCREG;
1162 else
1163 return 0; // will be an error in gdb
1164
1165 /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we
1166 have the normal SP/USP behavior. User mode is tricky though. */
1167 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT
1168 && cec_is_user_mode (cpu))
1169 {
1170 if (rn == SIM_BFIN_SP_REGNUM)
1171 value = KSPREG;
1172 else if (rn == SIM_BFIN_USP_REGNUM)
1173 value = SPREG;
1174 }
1175
1176 bfin_store_unsigned_integer (buf, 4, value);
1177
1178 return -1; // disables size checking in gdb
1179}
1180
1181static int
1182bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1183{
1184 bu32 value, *reg;
1185
1186 value = bfin_extract_unsigned_integer (buf, 4);
1187 reg = bfin_get_reg (cpu, rn);
1188
1189 if (reg)
1190 /* XXX: Need register trace ? */
1191 *reg = value;
1192 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1193 SET_ASTAT (value);
1194 else if (rn == SIM_BFIN_CC_REGNUM)
1195 SET_CCREG (value);
1196 else
1197 return 0; // will be an error in gdb
1198
1199 return -1; // disables size checking in gdb
1200}
1201
1202static sim_cia
1203bfin_pc_get (SIM_CPU *cpu)
1204{
1205 return PCREG;
1206}
1207
1208static void
1209bfin_pc_set (SIM_CPU *cpu, sim_cia newpc)
1210{
1211 SET_PCREG (newpc);
1212}
1213
1214static const char *
1215bfin_insn_name (SIM_CPU *cpu, int i)
1216{
1217 static const char * const insn_name[] = {
1218#define I(insn) #insn,
1219#include "insn_list.def"
1220#undef I
1221 };
1222 return insn_name[i];
1223}
1224
1225static void
1226bfin_init_cpu (SIM_CPU *cpu)
1227{
1228 CPU_REG_FETCH (cpu) = bfin_reg_fetch;
1229 CPU_REG_STORE (cpu) = bfin_reg_store;
1230 CPU_PC_FETCH (cpu) = bfin_pc_get;
1231 CPU_PC_STORE (cpu) = bfin_pc_set;
1232 CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX;
1233 CPU_INSN_NAME (cpu) = bfin_insn_name;
1234}
1235
1236static void
1237bfin_prepare_run (SIM_CPU *cpu)
1238{
1239}
1240
1241static const MODEL bfin_models[] =
1242{
1243#define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init },
1244#include "proc_list.def"
1245#undef P
1246 { 0, NULL, 0, NULL, NULL, }
1247};
1248
1249static const MACH_IMP_PROPERTIES bfin_imp_properties =
1250{
1251 sizeof (SIM_CPU),
1252 0,
1253};
1254
1255static const MACH bfin_mach =
1256{
1257 "bfin", "bfin", MACH_BFIN,
1258 32, 32, & bfin_models[0], & bfin_imp_properties,
1259 bfin_init_cpu,
1260 bfin_prepare_run
1261};
1262
1263const MACH *sim_machs[] =
1264{
1265 & bfin_mach,
1266 NULL
1267};
1268\f
1269/* Device option parsing. */
1270
1271static DECLARE_OPTION_HANDLER (bfin_mach_option_handler);
1272
1273enum {
1274 OPTION_MACH_SIREV = OPTION_START,
1275 OPTION_MACH_HW_BOARD_FILE,
1276};
1277
1278const OPTION bfin_mach_options[] =
1279{
1280 { {"sirev", required_argument, NULL, OPTION_MACH_SIREV },
1281 '\0', "NUMBER", "Set CPU silicon revision",
1282 bfin_mach_option_handler, NULL },
1283
1284 { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE },
1285 '\0', "FILE", "Add the supplemental devices listed in the file",
1286 bfin_mach_option_handler, NULL },
1287
1288 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
1289};
1290
1291static SIM_RC
1292bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
1293 char *arg, int is_command)
1294{
1295 struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1296
1297 switch (opt)
1298 {
1299 case OPTION_MACH_SIREV:
1300 board->sirev_valid = 1;
1301 /* Accept (and throw away) a leading "0." in the version. */
1302 if (!strncmp (arg, "0.", 2))
1303 arg += 2;
1304 board->sirev = atoi (arg);
1305 if (board->sirev > 0xf)
1306 {
1307 sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg);
1308 return SIM_RC_FAIL;
1309 }
1310 return SIM_RC_OK;
1311
1312 case OPTION_MACH_HW_BOARD_FILE:
1313 board->hw_file = xstrdup (arg);
1314 return SIM_RC_OK;
1315
1316 default:
1317 sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt);
1318 return SIM_RC_FAIL;
1319 }
1320}
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