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c906108c | 1 | /* General Cpu tools GENerated simulator support. |
1d506c26 | 2 | Copyright (C) 1996-2024 Free Software Foundation, Inc. |
c906108c SS |
3 | Contributed by Cygnus Support. |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
c906108c SS |
11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
c906108c SS |
19 | |
20 | #ifndef CGEN_DEFS_H | |
21 | #define CGEN_DEFS_H | |
22 | ||
d9e217e9 MF |
23 | #include "cgen-types.h" |
24 | ||
c906108c SS |
25 | /* Compute number of longs required to hold N bits. */ |
26 | #define HOST_LONGS_FOR_BITS(n) \ | |
27 | (((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8) | |
28 | \f | |
29 | /* Forward decls. Defined in the machine generated files. */ | |
30 | ||
31 | /* This holds the contents of the extracted insn. | |
32 | There are a few common entries (e.g. pc address), and then one big | |
33 | union with an entry for each of the instruction formats. */ | |
34 | typedef struct argbuf ARGBUF; | |
35 | ||
36 | /* ARGBUF accessors. */ | |
37 | #define ARGBUF_ADDR(abuf) ((abuf)->addr) | |
38 | #define ARGBUF_IDESC(abuf) ((abuf)->idesc) | |
39 | #define ARGBUF_TRACE_P(abuf) ((abuf)->trace_p) | |
40 | #define ARGBUF_PROFILE_P(abuf) ((abuf)->profile_p) | |
41 | ||
42 | /* This is one ARGBUF plus whatever else is needed for WITH_SCACHE support. | |
43 | At present there is nothing else, but it also provides a level of | |
44 | abstraction. */ | |
45 | typedef struct scache SCACHE; | |
46 | ||
47 | /* This is a union with one entry for each instruction format. | |
48 | Each entry contains all of the non-constant inputs of the instruction | |
49 | in the case of read-before-exec support, or all outputs of the instruction | |
50 | in the case of write-after-exec support. */ | |
51 | typedef struct parexec PAREXEC; | |
52 | ||
53 | /* An "Instruction DESCriptor". | |
54 | This is the main handle on an instruction for the simulator. */ | |
55 | typedef struct idesc IDESC; | |
56 | \f | |
57 | /* Engine support. | |
58 | ??? This is here because it's needed before eng.h (built by genmloop.sh) | |
59 | which is needed before cgen-engine.h and cpu.h. | |
60 | ??? This depends on a cpu family specific type, IADDR, but no machine | |
61 | generated headers will have been included yet. sim/common currently | |
62 | requires the typedef of sim_cia in sim-main.h between the inclusion of | |
63 | sim-basics.h and sim-base.h so this is no different. */ | |
64 | ||
65 | /* SEM_ARG is intended to hide whether or not the scache is in use from the | |
66 | semantic routines. In reality for the with-extraction case it is always | |
67 | an SCACHE * even when not using the SCACHE since there's no current win to | |
68 | making it something else ("not using the SCACHE" is like having a cache | |
69 | size of 1). | |
70 | The without-extraction case still uses an ARGBUF: | |
71 | - consistency with scache version | |
72 | - still need to record which operands are written | |
73 | This wouldn't be needed if modeling was done in the semantic routines | |
74 | but this isn't as general as handling it outside of the semantic routines. | |
75 | For example Shade allows calling user-supplied code before/after each | |
76 | instruction and this is something that is being planned. | |
77 | ??? There is still some clumsiness in how much of ARGBUF to use. */ | |
78 | typedef SCACHE *SEM_ARG; | |
79 | ||
80 | /* instruction address | |
81 | ??? This was intended to be a struct of two elements in the WITH_SCACHE_PBB | |
82 | case. The first element is the IADDR, the second element is the SCACHE *. | |
83 | Haven't found the time yet to make this work, but it seemed a nicer approach | |
84 | than the current br_cache stuff. */ | |
85 | typedef IADDR PCADDR; | |
86 | ||
87 | /* Current instruction address, used by common. */ | |
88 | typedef IADDR CIA; | |
89 | ||
90 | /* Semantic routines' version of the PC. */ | |
91 | #if WITH_SCACHE_PBB | |
92 | typedef SCACHE *SEM_PC; | |
93 | #else | |
94 | typedef IADDR SEM_PC; | |
95 | #endif | |
96baa820 JM |
96 | |
97 | /* Kinds of branches. */ | |
98 | typedef enum { | |
99 | SEM_BRANCH_UNTAKEN, | |
100 | /* Branch to an uncacheable address (e.g. j reg). */ | |
101 | SEM_BRANCH_UNCACHEABLE, | |
102 | /* Branch to a cacheable (fixed) address. */ | |
103 | SEM_BRANCH_CACHEABLE | |
104 | } SEM_BRANCH_TYPE; | |
c906108c SS |
105 | \f |
106 | /* Virtual insn support. */ | |
107 | ||
108 | /* Opcode table for virtual insns (only used by the simulator). */ | |
109 | extern const CGEN_INSN cgen_virtual_insn_table[]; | |
110 | ||
111 | /* -ve of indices of virtual insns in cgen_virtual_insn_table. */ | |
112 | typedef enum { | |
113 | VIRTUAL_INSN_X_INVALID = 0, | |
114 | VIRTUAL_INSN_X_BEFORE = -1, VIRTUAL_INSN_X_AFTER = -2, | |
115 | VIRTUAL_INSN_X_BEGIN = -3, | |
116 | VIRTUAL_INSN_X_CHAIN= -4, VIRTUAL_INSN_X_CTI_CHAIN = -5 | |
117 | } CGEN_INSN_VIRTUAL_TYPE; | |
118 | ||
2acceee2 | 119 | /* Return non-zero if CGEN_INSN* INSN is a virtual insn. */ |
c906108c SS |
120 | #define CGEN_INSN_VIRTUAL_P(insn) \ |
121 | CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_VIRTUAL) | |
122 | \f | |
123 | /* GNU C's "computed goto" facility is used to speed things up where | |
124 | possible. These macros provide a portable way to use them. | |
125 | Nesting of these switch statements is done by providing an extra argument | |
126 | that distinguishes them. `N' can be a number or symbol. | |
127 | Variable `labels_##N' must be initialized with the labels of each case. */ | |
128 | ||
129 | #ifdef __GNUC__ | |
130 | #define SWITCH(N, X) goto *X; | |
131 | #define CASE(N, X) case_##N##_##X | |
132 | #define BREAK(N) goto end_switch_##N | |
133 | #define DEFAULT(N) default_##N | |
a3bb1089 | 134 | #define ENDSWITCH(N) end_switch_##N:; |
c906108c SS |
135 | #else |
136 | #define SWITCH(N, X) switch (X) | |
137 | #define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */ | |
138 | #define BREAK(N) break | |
139 | #define DEFAULT(N) default | |
140 | #define ENDSWITCH(N) | |
141 | #endif | |
142 | \f | |
c906108c SS |
143 | /* Various utilities. */ |
144 | ||
c906108c SS |
145 | /* Return the name of an insn. */ |
146 | extern CPU_INSN_NAME_FN cgen_insn_name; | |
147 | ||
148 | /* Return the maximum number of extra bytes required for a sim_cpu struct. */ | |
149 | /* ??? Ok, yes, this is less pretty than it should be. Give me a better | |
150 | language [or suggest a better way]. */ | |
1c636da0 | 151 | extern int cgen_cpu_max_extra_bytes (SIM_DESC); |
c906108c | 152 | |
2acceee2 JM |
153 | /* Target supplied routine to process an invalid instruction. */ |
154 | extern SEM_PC sim_engine_invalid_insn (SIM_CPU *, IADDR, SEM_PC); | |
c906108c SS |
155 | |
156 | #endif /* CGEN_DEFS_H */ |