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Commit | Line | Data |
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f2de7dfd AC |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
169c7476 DE |
22 | #ifndef SIM_CORE_C |
23 | #define SIM_CORE_C | |
f2de7dfd | 24 | |
c967f187 DE |
25 | #include "sim-main.h" |
26 | #include "sim-assert.h" | |
f2de7dfd | 27 | |
169c7476 DE |
28 | #if (WITH_HW) |
29 | #include "sim-hw.h" | |
30 | #endif | |
31 | ||
c967f187 | 32 | /* "core" module install handler. |
cd0d873d | 33 | |
c967f187 DE |
34 | This is called via sim_module_install to install the "core" subsystem |
35 | into the simulator. */ | |
36 | ||
cd0d873d AC |
37 | static MODULE_INIT_FN sim_core_init; |
38 | static MODULE_UNINSTALL_FN sim_core_uninstall; | |
39 | ||
d147d384 AC |
40 | #if (WITH_DEVICES) |
41 | /* TODO: create sim/common/device.h */ | |
42 | void device_error (device *me, char* message, ...); | |
43 | int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia); | |
44 | int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia); | |
45 | #endif | |
46 | ||
c967f187 DE |
47 | EXTERN_SIM_CORE\ |
48 | (SIM_RC) | |
49 | sim_core_install (SIM_DESC sd) | |
50 | { | |
50a2a691 | 51 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
a34abff8 AC |
52 | |
53 | /* establish the other handlers */ | |
c967f187 DE |
54 | sim_module_add_uninstall_fn (sd, sim_core_uninstall); |
55 | sim_module_add_init_fn (sd, sim_core_init); | |
a34abff8 AC |
56 | |
57 | /* establish any initial data structures - none */ | |
c967f187 DE |
58 | return SIM_RC_OK; |
59 | } | |
60 | ||
61 | ||
62 | /* Uninstall the "core" subsystem from the simulator. */ | |
63 | ||
cd0d873d | 64 | STATIC_SIM_CORE\ |
f2de7dfd | 65 | (void) |
c967f187 | 66 | sim_core_uninstall (SIM_DESC sd) |
f2de7dfd | 67 | { |
f90b720b | 68 | sim_core *core = STATE_CORE(sd); |
169c7476 | 69 | unsigned map; |
a34abff8 | 70 | /* blow away any mappings */ |
169c7476 | 71 | for (map = 0; map < nr_maps; map++) { |
f90b720b | 72 | sim_core_mapping *curr = core->common.map[map].first; |
f2de7dfd | 73 | while (curr != NULL) { |
c967f187 | 74 | sim_core_mapping *tbd = curr; |
f2de7dfd | 75 | curr = curr->next; |
fd89abc2 | 76 | if (tbd->free_buffer != NULL) { |
c967f187 | 77 | SIM_ASSERT(tbd->buffer != NULL); |
fd89abc2 | 78 | zfree(tbd->free_buffer); |
f2de7dfd AC |
79 | } |
80 | zfree(tbd); | |
81 | } | |
f90b720b AC |
82 | core->common.map[map].first = NULL; |
83 | } | |
a34abff8 AC |
84 | } |
85 | ||
86 | ||
87 | STATIC_SIM_CORE\ | |
88 | (SIM_RC) | |
89 | sim_core_init (SIM_DESC sd) | |
90 | { | |
91 | /* Nothing to do */ | |
c967f187 | 92 | return SIM_RC_OK; |
f2de7dfd AC |
93 | } |
94 | ||
95 | ||
96 | ||
50a2a691 AC |
97 | #ifndef SIM_CORE_SIGNAL |
98 | #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ | |
99 | sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) | |
169c7476 | 100 | #endif |
50a2a691 | 101 | |
169c7476 | 102 | EXTERN_SIM_CORE\ |
cd0d873d | 103 | (void) |
50a2a691 AC |
104 | sim_core_signal (SIM_DESC sd, |
105 | sim_cpu *cpu, | |
106 | sim_cia cia, | |
169c7476 | 107 | unsigned map, |
50a2a691 AC |
108 | int nr_bytes, |
109 | address_word addr, | |
110 | transfer_type transfer, | |
111 | sim_core_signals sig) | |
112 | { | |
113 | const char *copy = (transfer == read_transfer ? "read" : "write"); | |
340d8e20 | 114 | address_word ip = CIA_ADDR (cia); |
50a2a691 AC |
115 | switch (sig) |
116 | { | |
117 | case sim_core_unmapped_signal: | |
d147d384 | 118 | sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n", |
cf02c13c | 119 | nr_bytes, copy, (unsigned long) addr, (unsigned long) ip); |
a4b44a2b | 120 | sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGSEGV); |
50a2a691 AC |
121 | break; |
122 | case sim_core_unaligned_signal: | |
cf02c13c DE |
123 | sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n", |
124 | nr_bytes, copy, (unsigned long) addr, (unsigned long) ip); | |
a4b44a2b | 125 | sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGBUS); |
50a2a691 AC |
126 | break; |
127 | default: | |
fd89abc2 AC |
128 | sim_engine_abort (sd, cpu, cia, |
129 | "sim_core_signal - internal error - bad switch"); | |
50a2a691 AC |
130 | } |
131 | } | |
1fe05280 AC |
132 | |
133 | ||
cd0d873d | 134 | STATIC_SIM_CORE\ |
c967f187 | 135 | (sim_core_mapping *) |
a34abff8 | 136 | new_sim_core_mapping (SIM_DESC sd, |
fcc86d82 | 137 | int level, |
a34abff8 AC |
138 | int space, |
139 | address_word addr, | |
140 | address_word nr_bytes, | |
141 | unsigned modulo, | |
169c7476 DE |
142 | #if WITH_HW |
143 | struct hw *device, | |
144 | #else | |
a34abff8 | 145 | device *device, |
169c7476 | 146 | #endif |
a34abff8 | 147 | void *buffer, |
fd89abc2 | 148 | void *free_buffer) |
f2de7dfd | 149 | { |
c967f187 | 150 | sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping); |
f2de7dfd | 151 | /* common */ |
fcc86d82 | 152 | new_mapping->level = level; |
f2de7dfd AC |
153 | new_mapping->space = space; |
154 | new_mapping->base = addr; | |
155 | new_mapping->nr_bytes = nr_bytes; | |
156 | new_mapping->bound = addr + (nr_bytes - 1); | |
a34abff8 AC |
157 | if (modulo == 0) |
158 | new_mapping->mask = (unsigned) 0 - 1; | |
159 | else | |
160 | new_mapping->mask = modulo - 1; | |
fcc86d82 AC |
161 | new_mapping->buffer = buffer; |
162 | new_mapping->free_buffer = free_buffer; | |
163 | new_mapping->device = device; | |
f2de7dfd AC |
164 | return new_mapping; |
165 | } | |
166 | ||
167 | ||
cd0d873d | 168 | STATIC_SIM_CORE\ |
f2de7dfd | 169 | (void) |
a34abff8 AC |
170 | sim_core_map_attach (SIM_DESC sd, |
171 | sim_core_map *access_map, | |
fcc86d82 | 172 | int level, |
a34abff8 AC |
173 | int space, |
174 | address_word addr, | |
175 | address_word nr_bytes, | |
176 | unsigned modulo, | |
169c7476 DE |
177 | #if WITH_HW |
178 | struct hw *client, /*callback/default*/ | |
179 | #else | |
a34abff8 | 180 | device *client, /*callback/default*/ |
169c7476 | 181 | #endif |
a34abff8 | 182 | void *buffer, /*raw_memory*/ |
fd89abc2 | 183 | void *free_buffer) /*raw_memory*/ |
f2de7dfd AC |
184 | { |
185 | /* find the insertion point for this additional mapping and then | |
186 | insert */ | |
c967f187 DE |
187 | sim_core_mapping *next_mapping; |
188 | sim_core_mapping **last_mapping; | |
f2de7dfd | 189 | |
fcc86d82 AC |
190 | SIM_ASSERT ((client == NULL) != (buffer == NULL)); |
191 | SIM_ASSERT ((client == NULL) >= (free_buffer != NULL)); | |
f2de7dfd AC |
192 | |
193 | /* actually do occasionally get a zero size map */ | |
a34abff8 AC |
194 | if (nr_bytes == 0) |
195 | { | |
f2de7dfd | 196 | #if (WITH_DEVICES) |
a34abff8 | 197 | device_error(client, "called on sim_core_map_attach with size zero"); |
f2de7dfd | 198 | #endif |
169c7476 DE |
199 | #if (WITH_HW) |
200 | sim_hw_abort (sd, client, "called on sim_core_map_attach with size zero"); | |
201 | #endif | |
202 | sim_io_error (sd, "called on sim_core_map_attach with size zero"); | |
a34abff8 | 203 | } |
f2de7dfd AC |
204 | |
205 | /* find the insertion point (between last/next) */ | |
206 | next_mapping = access_map->first; | |
207 | last_mapping = &access_map->first; | |
208 | while(next_mapping != NULL | |
fcc86d82 AC |
209 | && (next_mapping->level < level |
210 | || (next_mapping->level == level | |
a34abff8 AC |
211 | && next_mapping->bound < addr))) |
212 | { | |
213 | /* provided levels are the same */ | |
214 | /* assert: next_mapping->base > all bases before next_mapping */ | |
215 | /* assert: next_mapping->bound >= all bounds before next_mapping */ | |
216 | last_mapping = &next_mapping->next; | |
217 | next_mapping = next_mapping->next; | |
218 | } | |
219 | ||
f2de7dfd | 220 | /* check insertion point correct */ |
fcc86d82 AC |
221 | SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level); |
222 | if (next_mapping != NULL && next_mapping->level == level | |
80c651f0 AC |
223 | && next_mapping->base < (addr + (nr_bytes - 1))) |
224 | { | |
f2de7dfd | 225 | #if (WITH_DEVICES) |
80c651f0 AC |
226 | device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", |
227 | space, | |
228 | (long) addr, | |
229 | (long) nr_bytes, | |
230 | (long) (addr + (nr_bytes - 1)), | |
231 | next_mapping->space, | |
232 | (long) next_mapping->base, | |
233 | (long) next_mapping->bound, | |
234 | (long) next_mapping->nr_bytes); | |
169c7476 DE |
235 | #endif |
236 | #if WITH_HW | |
237 | sim_hw_abort (sd, client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", | |
80c651f0 AC |
238 | space, |
239 | (long) addr, | |
240 | (long) nr_bytes, | |
241 | (long) (addr + (nr_bytes - 1)), | |
242 | next_mapping->space, | |
243 | (long) next_mapping->base, | |
244 | (long) next_mapping->bound, | |
245 | (long) next_mapping->nr_bytes); | |
f2de7dfd | 246 | #endif |
169c7476 DE |
247 | sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", |
248 | space, | |
249 | (long) addr, | |
250 | (long) nr_bytes, | |
251 | (long) (addr + (nr_bytes - 1)), | |
252 | next_mapping->space, | |
253 | (long) next_mapping->base, | |
254 | (long) next_mapping->bound, | |
255 | (long) next_mapping->nr_bytes); | |
f2de7dfd AC |
256 | } |
257 | ||
258 | /* create/insert the new mapping */ | |
c967f187 | 259 | *last_mapping = new_sim_core_mapping(sd, |
fcc86d82 | 260 | level, |
a34abff8 | 261 | space, addr, nr_bytes, modulo, |
80c651f0 | 262 | client, buffer, free_buffer); |
f2de7dfd AC |
263 | (*last_mapping)->next = next_mapping; |
264 | } | |
265 | ||
84fc6bd9 | 266 | /* Attach memory or a memory mapped device to the simulator. |
2307e0ee | 267 | See sim-core.h for a full description. */ |
f2de7dfd | 268 | |
cd0d873d | 269 | EXTERN_SIM_CORE\ |
f2de7dfd | 270 | (void) |
a34abff8 AC |
271 | sim_core_attach (SIM_DESC sd, |
272 | sim_cpu *cpu, | |
fcc86d82 | 273 | int level, |
169c7476 | 274 | unsigned mapmask, |
a34abff8 AC |
275 | int space, |
276 | address_word addr, | |
277 | address_word nr_bytes, | |
278 | unsigned modulo, | |
169c7476 DE |
279 | #if WITH_HW |
280 | struct hw *client, | |
281 | #else | |
a34abff8 | 282 | device *client, |
169c7476 | 283 | #endif |
a34abff8 | 284 | void *optional_buffer) |
f2de7dfd | 285 | { |
1fe05280 | 286 | sim_core *memory = STATE_CORE(sd); |
169c7476 | 287 | unsigned map; |
f2de7dfd | 288 | void *buffer; |
fd89abc2 | 289 | void *free_buffer; |
7a418800 AC |
290 | |
291 | /* check for for attempt to use unimplemented per-processor core map */ | |
292 | if (cpu != NULL) | |
293 | sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported"); | |
294 | ||
fcc86d82 AC |
295 | /* verify modulo memory */ |
296 | if (!WITH_MODULO_MEMORY && modulo != 0) | |
297 | { | |
298 | #if (WITH_DEVICES) | |
299 | device_error (client, "sim_core_attach - internal error - modulo memory disabled"); | |
fcc86d82 | 300 | #endif |
169c7476 DE |
301 | #if (WITH_HW) |
302 | sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo memory disabled"); | |
303 | #endif | |
304 | sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled"); | |
fcc86d82 AC |
305 | } |
306 | if (client != NULL && modulo != 0) | |
a34abff8 | 307 | { |
a34abff8 | 308 | #if (WITH_DEVICES) |
fcc86d82 | 309 | device_error (client, "sim_core_attach - internal error - modulo and callback memory conflict"); |
a34abff8 | 310 | #endif |
169c7476 DE |
311 | #if (WITH_HW) |
312 | sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo and callback memory conflict"); | |
313 | #endif | |
314 | sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict"); | |
fcc86d82 AC |
315 | } |
316 | if (modulo != 0) | |
317 | { | |
318 | unsigned mask = modulo - 1; | |
319 | /* any zero bits */ | |
320 | while (mask >= sizeof (unsigned64)) /* minimum modulo */ | |
321 | { | |
322 | if ((mask & 1) == 0) | |
323 | mask = 0; | |
324 | else | |
325 | mask >>= 1; | |
a34abff8 | 326 | } |
fcc86d82 | 327 | if (mask != sizeof (unsigned64) - 1) |
a34abff8 AC |
328 | { |
329 | #if (WITH_DEVICES) | |
fcc86d82 | 330 | device_error (client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo); |
a34abff8 | 331 | #endif |
169c7476 DE |
332 | #if (WITH_HW) |
333 | sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo); | |
334 | #endif | |
335 | sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo); | |
a34abff8 | 336 | } |
fcc86d82 AC |
337 | } |
338 | ||
339 | /* verify consistency between device and buffer */ | |
340 | if (client != NULL && optional_buffer != NULL) | |
341 | { | |
342 | #if (WITH_DEVICES) | |
343 | device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments"); | |
fcc86d82 | 344 | #endif |
169c7476 DE |
345 | #if (WITH_HW) |
346 | sim_hw_abort (sd, client, "sim_core_attach - internal error - conflicting buffer and attach arguments"); | |
347 | #endif | |
348 | sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments"); | |
fcc86d82 AC |
349 | } |
350 | if (client == NULL) | |
351 | { | |
a34abff8 AC |
352 | if (optional_buffer == NULL) |
353 | { | |
fd89abc2 | 354 | int padding = (addr % sizeof (unsigned64)); |
e4726e6d DE |
355 | unsigned long bytes = (modulo == 0 ? nr_bytes : modulo) + padding; |
356 | free_buffer = zalloc (bytes); | |
fd89abc2 | 357 | buffer = (char*) free_buffer + padding; |
a34abff8 AC |
358 | } |
359 | else | |
360 | { | |
361 | buffer = optional_buffer; | |
fd89abc2 | 362 | free_buffer = NULL; |
a34abff8 | 363 | } |
f2de7dfd | 364 | } |
a34abff8 AC |
365 | else |
366 | { | |
fcc86d82 | 367 | /* a device */ |
a34abff8 | 368 | buffer = NULL; |
fd89abc2 | 369 | free_buffer = NULL; |
a34abff8 AC |
370 | } |
371 | ||
f2de7dfd AC |
372 | /* attach the region to all applicable access maps */ |
373 | for (map = 0; | |
169c7476 | 374 | map < nr_maps; |
a34abff8 AC |
375 | map++) |
376 | { | |
169c7476 | 377 | if (mapmask & (1 << map)) |
a34abff8 | 378 | { |
169c7476 DE |
379 | sim_core_map_attach (sd, &memory->common.map[map], |
380 | level, space, addr, nr_bytes, modulo, | |
381 | client, buffer, free_buffer); | |
fd89abc2 | 382 | free_buffer = NULL; |
a34abff8 | 383 | } |
f2de7dfd | 384 | } |
a34abff8 | 385 | |
7a418800 AC |
386 | /* Just copy this map to each of the processor specific data structures. |
387 | FIXME - later this will be replaced by true processor specific | |
388 | maps. */ | |
f90b720b AC |
389 | { |
390 | int i; | |
391 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
392 | { | |
393 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
394 | } | |
395 | } | |
f2de7dfd AC |
396 | } |
397 | ||
398 | ||
a34abff8 AC |
399 | /* Remove any memory reference related to this address */ |
400 | STATIC_INLINE_SIM_CORE\ | |
401 | (void) | |
402 | sim_core_map_detach (SIM_DESC sd, | |
403 | sim_core_map *access_map, | |
fcc86d82 | 404 | int level, |
a34abff8 AC |
405 | int space, |
406 | address_word addr) | |
407 | { | |
408 | sim_core_mapping **entry; | |
409 | for (entry = &access_map->first; | |
410 | (*entry) != NULL; | |
411 | entry = &(*entry)->next) | |
412 | { | |
413 | if ((*entry)->base == addr | |
fcc86d82 | 414 | && (*entry)->level == level |
a34abff8 AC |
415 | && (*entry)->space == space) |
416 | { | |
417 | sim_core_mapping *dead = (*entry); | |
418 | (*entry) = dead->next; | |
fd89abc2 | 419 | if (dead->free_buffer != NULL) |
e4726e6d | 420 | zfree (dead->free_buffer); |
a34abff8 AC |
421 | zfree (dead); |
422 | return; | |
423 | } | |
424 | } | |
425 | } | |
426 | ||
427 | EXTERN_SIM_CORE\ | |
428 | (void) | |
429 | sim_core_detach (SIM_DESC sd, | |
430 | sim_cpu *cpu, | |
fcc86d82 | 431 | int level, |
a34abff8 AC |
432 | int address_space, |
433 | address_word addr) | |
434 | { | |
435 | sim_core *memory = STATE_CORE (sd); | |
169c7476 DE |
436 | unsigned map; |
437 | for (map = 0; map < nr_maps; map++) | |
a34abff8 AC |
438 | { |
439 | sim_core_map_detach (sd, &memory->common.map[map], | |
fcc86d82 | 440 | level, address_space, addr); |
a34abff8 AC |
441 | } |
442 | /* Just copy this update to each of the processor specific data | |
443 | structures. FIXME - later this will be replaced by true | |
444 | processor specific maps. */ | |
445 | { | |
446 | int i; | |
447 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
448 | { | |
449 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
450 | } | |
451 | } | |
452 | } | |
453 | ||
454 | ||
f2de7dfd | 455 | STATIC_INLINE_SIM_CORE\ |
c967f187 | 456 | (sim_core_mapping *) |
f90b720b | 457 | sim_core_find_mapping(sim_core_common *core, |
169c7476 | 458 | unsigned map, |
cd0d873d | 459 | address_word addr, |
f2de7dfd | 460 | unsigned nr_bytes, |
50a2a691 | 461 | transfer_type transfer, |
7a418800 AC |
462 | int abort, /*either 0 or 1 - hint to inline/-O */ |
463 | sim_cpu *cpu, /* abort => cpu != NULL */ | |
1fe05280 | 464 | sim_cia cia) |
f2de7dfd | 465 | { |
7a418800 AC |
466 | sim_core_mapping *mapping = core->map[map].first; |
467 | ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */ | |
468 | ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */ | |
469 | ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */ | |
470 | while (mapping != NULL) | |
471 | { | |
472 | if (addr >= mapping->base | |
473 | && (addr + (nr_bytes - 1)) <= mapping->bound) | |
474 | return mapping; | |
475 | mapping = mapping->next; | |
476 | } | |
f2de7dfd | 477 | if (abort) |
7a418800 | 478 | { |
50a2a691 AC |
479 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer, |
480 | sim_core_unmapped_signal); | |
7a418800 | 481 | } |
f2de7dfd AC |
482 | return NULL; |
483 | } | |
484 | ||
485 | ||
486 | STATIC_INLINE_SIM_CORE\ | |
487 | (void *) | |
f90b720b AC |
488 | sim_core_translate (sim_core_mapping *mapping, |
489 | address_word addr) | |
f2de7dfd | 490 | { |
a34abff8 AC |
491 | if (WITH_MODULO_MEMORY) |
492 | return (void *)((unsigned8 *) mapping->buffer | |
493 | + ((addr - mapping->base) & mapping->mask)); | |
494 | else | |
495 | return (void *)((unsigned8 *) mapping->buffer | |
496 | + addr - mapping->base); | |
f2de7dfd AC |
497 | } |
498 | ||
499 | ||
cd0d873d | 500 | EXTERN_SIM_CORE\ |
f2de7dfd | 501 | (unsigned) |
f90b720b AC |
502 | sim_core_read_buffer (SIM_DESC sd, |
503 | sim_cpu *cpu, | |
169c7476 | 504 | unsigned map, |
f90b720b AC |
505 | void *buffer, |
506 | address_word addr, | |
507 | unsigned len) | |
f2de7dfd | 508 | { |
f90b720b | 509 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); |
f2de7dfd | 510 | unsigned count = 0; |
169c7476 DE |
511 | while (count < len) |
512 | { | |
f2de7dfd | 513 | unsigned_word raddr = addr + count; |
c967f187 | 514 | sim_core_mapping *mapping = |
169c7476 | 515 | sim_core_find_mapping (core, map, |
50a2a691 AC |
516 | raddr, /*nr-bytes*/1, |
517 | read_transfer, | |
f90b720b | 518 | 0 /*dont-abort*/, NULL, NULL_CIA); |
f2de7dfd AC |
519 | if (mapping == NULL) |
520 | break; | |
521 | #if (WITH_DEVICES) | |
169c7476 DE |
522 | if (mapping->device != NULL) |
523 | { | |
524 | int nr_bytes = len - count; | |
525 | if (raddr + nr_bytes - 1> mapping->bound) | |
526 | nr_bytes = mapping->bound - raddr + 1; | |
527 | if (device_io_read_buffer (mapping->device, | |
528 | (unsigned_1*)buffer + count, | |
529 | mapping->space, | |
530 | raddr, | |
531 | nr_bytes, | |
532 | cpu, | |
533 | CIA_GET (cpu)) != nr_bytes) | |
534 | break; | |
535 | count += nr_bytes; | |
536 | continue; | |
537 | } | |
f2de7dfd | 538 | #endif |
169c7476 DE |
539 | #if (WITH_HW) |
540 | if (mapping->device != NULL) | |
f2de7dfd | 541 | { |
169c7476 DE |
542 | int nr_bytes = len - count; |
543 | if (raddr + nr_bytes - 1> mapping->bound) | |
544 | nr_bytes = mapping->bound - raddr + 1; | |
545 | if (sim_hw_io_read_buffer (sd, mapping->device, | |
546 | (unsigned_1*)buffer + count, | |
547 | mapping->space, | |
548 | raddr, | |
549 | nr_bytes) != nr_bytes) | |
550 | break; | |
551 | count += nr_bytes; | |
552 | continue; | |
f2de7dfd | 553 | } |
169c7476 DE |
554 | #endif |
555 | ((unsigned_1*)buffer)[count] = | |
556 | *(unsigned_1*)sim_core_translate(mapping, raddr); | |
557 | count += 1; | |
558 | } | |
f2de7dfd AC |
559 | return count; |
560 | } | |
561 | ||
562 | ||
cd0d873d | 563 | EXTERN_SIM_CORE\ |
f2de7dfd | 564 | (unsigned) |
f90b720b AC |
565 | sim_core_write_buffer (SIM_DESC sd, |
566 | sim_cpu *cpu, | |
169c7476 | 567 | unsigned map, |
f90b720b AC |
568 | const void *buffer, |
569 | address_word addr, | |
570 | unsigned len) | |
f2de7dfd | 571 | { |
f90b720b | 572 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); |
f2de7dfd | 573 | unsigned count = 0; |
169c7476 DE |
574 | while (count < len) |
575 | { | |
576 | unsigned_word raddr = addr + count; | |
577 | sim_core_mapping *mapping = | |
578 | sim_core_find_mapping (core, map, | |
579 | raddr, /*nr-bytes*/1, | |
580 | write_transfer, | |
581 | 0 /*dont-abort*/, NULL, NULL_CIA); | |
582 | if (mapping == NULL) | |
f2de7dfd | 583 | break; |
169c7476 DE |
584 | #if (WITH_DEVICES) |
585 | if (WITH_CALLBACK_MEMORY | |
586 | && mapping->device != NULL) | |
587 | { | |
588 | int nr_bytes = len - count; | |
589 | if (raddr + nr_bytes - 1 > mapping->bound) | |
590 | nr_bytes = mapping->bound - raddr + 1; | |
591 | if (device_io_write_buffer (mapping->device, | |
592 | (unsigned_1*)buffer + count, | |
593 | mapping->space, | |
594 | raddr, | |
595 | nr_bytes, | |
596 | cpu, | |
597 | CIA_GET(cpu)) != nr_bytes) | |
598 | break; | |
599 | count += nr_bytes; | |
600 | continue; | |
601 | } | |
f2de7dfd | 602 | #endif |
169c7476 DE |
603 | #if (WITH_HW) |
604 | if (WITH_CALLBACK_MEMORY | |
605 | && mapping->device != NULL) | |
606 | { | |
607 | int nr_bytes = len - count; | |
608 | if (raddr + nr_bytes - 1 > mapping->bound) | |
609 | nr_bytes = mapping->bound - raddr + 1; | |
610 | if (sim_hw_io_write_buffer (sd, mapping->device, | |
611 | (unsigned_1*)buffer + count, | |
612 | mapping->space, | |
613 | raddr, | |
614 | nr_bytes) != nr_bytes) | |
615 | break; | |
616 | count += nr_bytes; | |
617 | continue; | |
618 | } | |
619 | #endif | |
620 | *(unsigned_1*)sim_core_translate(mapping, raddr) = | |
621 | ((unsigned_1*)buffer)[count]; | |
622 | count += 1; | |
623 | } | |
f2de7dfd AC |
624 | return count; |
625 | } | |
626 | ||
627 | ||
cd0d873d AC |
628 | EXTERN_SIM_CORE\ |
629 | (void) | |
f90b720b AC |
630 | sim_core_set_xor (SIM_DESC sd, |
631 | sim_cpu *cpu, | |
cd0d873d AC |
632 | int is_xor) |
633 | { | |
f90b720b | 634 | /* set up the XOR map if required. */ |
cd0d873d AC |
635 | if (WITH_XOR_ENDIAN) { |
636 | { | |
f90b720b AC |
637 | sim_core *core = STATE_CORE (sd); |
638 | sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL); | |
639 | if (cpu_core != NULL) | |
cd0d873d | 640 | { |
f90b720b AC |
641 | int i = 1; |
642 | unsigned mask; | |
643 | if (is_xor) | |
644 | mask = WITH_XOR_ENDIAN - 1; | |
645 | else | |
646 | mask = 0; | |
647 | while (i - 1 < WITH_XOR_ENDIAN) | |
648 | { | |
649 | cpu_core->xor[i-1] = mask; | |
650 | mask = (mask << 1) & (WITH_XOR_ENDIAN - 1); | |
651 | i = (i << 1); | |
652 | } | |
cd0d873d | 653 | } |
f90b720b AC |
654 | else |
655 | { | |
656 | if (is_xor) | |
657 | core->byte_xor = WITH_XOR_ENDIAN - 1; | |
658 | else | |
659 | core->byte_xor = 0; | |
660 | } | |
cd0d873d AC |
661 | } |
662 | } | |
663 | else { | |
664 | if (is_xor) | |
169c7476 | 665 | sim_engine_abort (sd, NULL, NULL_CIA, |
cd0d873d AC |
666 | "Attempted to enable xor-endian mode when permenantly disabled."); |
667 | } | |
668 | } | |
669 | ||
f90b720b AC |
670 | STATIC_INLINE_SIM_CORE\ |
671 | (void) | |
672 | reverse_n (unsigned_1 *dest, | |
673 | const unsigned_1 *src, | |
674 | int nr_bytes) | |
675 | { | |
676 | int i; | |
677 | for (i = 0; i < nr_bytes; i++) | |
678 | { | |
679 | dest [nr_bytes - i - 1] = src [i]; | |
680 | } | |
681 | } | |
682 | ||
683 | ||
684 | EXTERN_SIM_CORE\ | |
685 | (unsigned) | |
686 | sim_core_xor_read_buffer (SIM_DESC sd, | |
687 | sim_cpu *cpu, | |
169c7476 | 688 | unsigned map, |
f90b720b AC |
689 | void *buffer, |
690 | address_word addr, | |
691 | unsigned nr_bytes) | |
692 | { | |
693 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
694 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
695 | return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
696 | else | |
697 | /* only break up transfers when xor-endian is both selected and enabled */ | |
698 | { | |
31dda65a | 699 | unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */ |
f90b720b AC |
700 | unsigned nr_transfered = 0; |
701 | address_word start = addr; | |
702 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
703 | address_word stop; | |
704 | /* initial and intermediate transfers are broken when they cross | |
705 | an XOR endian boundary */ | |
706 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
707 | /* initial/intermediate transfers */ | |
708 | { | |
709 | /* since xor-endian is enabled stop^xor defines the start | |
710 | address of the transfer */ | |
711 | stop = start + nr_this_transfer - 1; | |
712 | SIM_ASSERT (start <= stop); | |
713 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
714 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
715 | != nr_this_transfer) | |
716 | return nr_transfered; | |
717 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
718 | nr_transfered += nr_this_transfer; | |
719 | nr_this_transfer = WITH_XOR_ENDIAN; | |
720 | start = stop + 1; | |
721 | } | |
722 | /* final transfer */ | |
723 | nr_this_transfer = nr_bytes - nr_transfered; | |
724 | stop = start + nr_this_transfer - 1; | |
725 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
726 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
727 | != nr_this_transfer) | |
728 | return nr_transfered; | |
729 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
730 | return nr_bytes; | |
731 | } | |
732 | } | |
733 | ||
734 | ||
735 | EXTERN_SIM_CORE\ | |
736 | (unsigned) | |
737 | sim_core_xor_write_buffer (SIM_DESC sd, | |
738 | sim_cpu *cpu, | |
169c7476 | 739 | unsigned map, |
f90b720b AC |
740 | const void *buffer, |
741 | address_word addr, | |
742 | unsigned nr_bytes) | |
743 | { | |
744 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
745 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
746 | return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
747 | else | |
748 | /* only break up transfers when xor-endian is both selected and enabled */ | |
749 | { | |
fd89abc2 | 750 | unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */ |
f90b720b AC |
751 | unsigned nr_transfered = 0; |
752 | address_word start = addr; | |
753 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
754 | address_word stop; | |
755 | /* initial and intermediate transfers are broken when they cross | |
756 | an XOR endian boundary */ | |
757 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
758 | /* initial/intermediate transfers */ | |
759 | { | |
760 | /* since xor-endian is enabled stop^xor defines the start | |
761 | address of the transfer */ | |
762 | stop = start + nr_this_transfer - 1; | |
763 | SIM_ASSERT (start <= stop); | |
764 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
765 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
766 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
767 | != nr_this_transfer) | |
768 | return nr_transfered; | |
769 | nr_transfered += nr_this_transfer; | |
770 | nr_this_transfer = WITH_XOR_ENDIAN; | |
771 | start = stop + 1; | |
772 | } | |
773 | /* final transfer */ | |
774 | nr_this_transfer = nr_bytes - nr_transfered; | |
775 | stop = start + nr_this_transfer - 1; | |
776 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
777 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
778 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
779 | != nr_this_transfer) | |
780 | return nr_transfered; | |
781 | return nr_bytes; | |
782 | } | |
783 | } | |
cd0d873d AC |
784 | |
785 | ||
786 | ||
f45dd42b | 787 | /* define the read/write 1/2/4/8/16/word functions */ |
f2de7dfd | 788 | |
63be8feb | 789 | #define N 16 |
f2de7dfd | 790 | #include "sim-n-core.h" |
f2de7dfd | 791 | |
63be8feb AC |
792 | #define N 8 |
793 | #include "sim-n-core.h" | |
794 | ||
795 | #define N 7 | |
796 | #define M 8 | |
797 | #include "sim-n-core.h" | |
798 | ||
799 | #define N 6 | |
800 | #define M 8 | |
801 | #include "sim-n-core.h" | |
802 | ||
803 | #define N 5 | |
804 | #define M 8 | |
f2de7dfd | 805 | #include "sim-n-core.h" |
f2de7dfd AC |
806 | |
807 | #define N 4 | |
808 | #include "sim-n-core.h" | |
f2de7dfd | 809 | |
63be8feb AC |
810 | #define N 3 |
811 | #define M 4 | |
f2de7dfd | 812 | #include "sim-n-core.h" |
f2de7dfd | 813 | |
63be8feb AC |
814 | #define N 2 |
815 | #include "sim-n-core.h" | |
816 | ||
817 | #define N 1 | |
f45dd42b | 818 | #include "sim-n-core.h" |
f45dd42b | 819 | |
f2de7dfd | 820 | #endif |