[thirdparty/binutils-gdb.git] / sim / common / sim-n-core.h

/* The common simulator framework for GDB, the GNU Debugger.

   Copyright 2002, 2007 Free Software Foundation, Inc.

   Contributed by Andrew Cagney and Red Hat.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */


#ifndef N
#error "N must be #defined"
#endif
#ifndef M
#define M N
#endif

/* N: The number of bytes of data to transfer.
   M: The number of bytes in the type used to transfer the data */

#if (N > M)
#error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
#endif


#include "symcat.h"

/* NOTE: see end of file for #undef of these macros */

#define unsigned_M XCONCAT2(unsigned_,M)

#define T2H_M XCONCAT2(T2H_,M)
#define H2T_M XCONCAT2(H2T_,M)
#define SWAP_M XCONCAT2(SWAP_,M)

#define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
#define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
#define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N)
#define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
#define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
#define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
#define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
#define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)


#if (M == N && N > 1)
/* dummy variable used as a return value when nothing else is
   available and the compiler is complaining */
static unsigned_M sim_core_dummy_M;
#endif


/* TAGS: sim_core_trace_1 sim_core_trace_2 */
/* TAGS: sim_core_trace_4 sim_core_trace_8 */
/* TAGS: sim_core_trace_16 */

#if (M == N)
STATIC_SIM_CORE(void)
sim_core_trace_M (sim_cpu *cpu,
		  sim_cia cia,
		  int line_nr,
		  transfer_type type,
		  unsigned map,
		  address_word addr,
		  unsigned_M val,
		  int nr_bytes)
{
  const char *transfer = (type == read_transfer ? "read" : "write");
  const char *direction = (type == read_transfer ? "->" : "<-");

  if (TRACE_DEBUG_P (cpu))
    trace_printf (CPU_STATE (cpu), cpu, "sim-n-core.h:%d: ", line_nr);

#if (M == 16)
  trace_printf (CPU_STATE (cpu), cpu,
		"%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n",
		transfer, nr_bytes,
		map_to_str (map),
		(unsigned long) addr,
		direction,
		(unsigned long) V4_16 (val, 0),
		(unsigned long) V4_16 (val, 1),
		(unsigned long) V4_16 (val, 2),
		(unsigned long) V4_16 (val, 3));
#endif
#if (M == 8)
  trace_printf (CPU_STATE (cpu), cpu,
		"%s-%d %s:0x%08lx %s 0x%08lx%08lx\n",
		transfer, nr_bytes,
		map_to_str (map),
		(unsigned long) addr,
		direction,
		(unsigned long) V4_8 (val, 0),
		(unsigned long) V4_8 (val, 1));
#endif
#if (M == 4)
  trace_printf (CPU_STATE (cpu), cpu,
		"%s-%d %s:0x%08lx %s 0x%08lx\n",
		transfer,
		nr_bytes,
		map_to_str (map),
		(unsigned long) addr,
		direction,
		(unsigned long) val);
#endif
#if (M == 2)
  trace_printf (CPU_STATE (cpu), cpu,
		"%s-%d %s:0x%08lx %s 0x%04lx\n",
		transfer,
		nr_bytes,
		map_to_str (map),
		(unsigned long) addr,
		direction,
		(unsigned long) val);
#endif
#if (M == 1)
  trace_printf (CPU_STATE (cpu), cpu,
		"%s-%d %s:0x%08lx %s 0x%02lx\n",
		transfer,
		nr_bytes,
		map_to_str (map),
		(unsigned long) addr,
		direction,
		(unsigned long) val);
#endif
}
#endif

  
/* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
/* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
/* TAGS: sim_core_read_aligned_16 */

#if (M == N)
INLINE_SIM_CORE(unsigned_M)
sim_core_read_aligned_N(sim_cpu *cpu,
			sim_cia cia,
			unsigned map,
			address_word xaddr)
{
  sim_cpu_core *cpu_core = CPU_CORE (cpu);
  sim_core_common *core = &cpu_core->common;
  unsigned_M val;
  sim_core_mapping *mapping;
  address_word addr;
#if WITH_XOR_ENDIAN != 0
  if (WITH_XOR_ENDIAN)
    addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
  else
#endif
    addr = xaddr;
  mapping = sim_core_find_mapping (core, map, addr, N, read_transfer, 1 /*abort*/, cpu, cia);
  do
    {
#if (WITH_DEVICES)
      if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
	{
	  unsigned_M data;
	  if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
	    device_error (mapping->device, "internal error - %s - io_read_buffer should not fail",
			  XSTRING (sim_core_read_aligned_N));
	  val = T2H_M (data);
	  break;
	}
#endif
#if (WITH_HW)
      if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
	{
	  unsigned_M data;
	  sim_cpu_hw_io_read_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
	  val = T2H_M (data);
	  break;
	}
#endif
      val = T2H_M (*(unsigned_M*) sim_core_translate (mapping, addr));
    }
  while (0);
  PROFILE_COUNT_CORE (cpu, addr, N, map);
  if (TRACE_P (cpu, TRACE_CORE_IDX))
    sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
  return val;
}
#endif
  
/* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
/* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
/* TAGS: sim_core_read_unaligned_16 */

#if (M == N && N > 1)
INLINE_SIM_CORE(unsigned_M)
sim_core_read_unaligned_N(sim_cpu *cpu,
			  sim_cia cia,
			  unsigned map,
			  address_word addr)
{
  int alignment = N - 1;
  /* if hardwired to forced alignment just do it */
  if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
    return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
  else if ((addr & alignment) == 0)
    return sim_core_read_aligned_N (cpu, cia, map, addr);
  else
    switch (CURRENT_ALIGNMENT)
      {
      case STRICT_ALIGNMENT:
	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
			 read_transfer, sim_core_unaligned_signal);
      case NONSTRICT_ALIGNMENT:
	{
	  unsigned_M val;
	  if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
	    SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
			     read_transfer, sim_core_unaligned_signal);
	  val = T2H_M(val);
	  PROFILE_COUNT_CORE (cpu, addr, N, map);
	  if (TRACE_P (cpu, TRACE_CORE_IDX))
	    sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
	  return val;
	}
      case FORCED_ALIGNMENT:
	return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
      case MIXED_ALIGNMENT:
	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
			  "internal error - %s - mixed alignment",
			  XSTRING (sim_core_read_unaligned_N));
      default:
	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
			  "internal error - %s - bad switch",
			  XSTRING (sim_core_read_unaligned_N));
	/* to keep some compilers happy, we return a dummy */
	return sim_core_dummy_M;
      }
}
#endif

/* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */
/* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */

#if (M != N)
INLINE_SIM_CORE(unsigned_M)
sim_core_read_misaligned_N(sim_cpu *cpu,
			  sim_cia cia,
			  unsigned map,
			  address_word addr)
{
  unsigned_M val = 0;
  if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
    SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
		     read_transfer, sim_core_unaligned_signal);
  if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
    val = SWAP_M (val);
  if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
    val >>= (M - N) * 8;
  PROFILE_COUNT_CORE (cpu, addr, N, map);
  if (TRACE_P (cpu, TRACE_CORE_IDX))
    sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
  return val;
}
#endif

/* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
/* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
/* TAGS: sim_core_write_aligned_16 */

#if (M == N)
INLINE_SIM_CORE(void)
sim_core_write_aligned_N(sim_cpu *cpu,
			 sim_cia cia,
			 unsigned map,
			 address_word xaddr,
			 unsigned_M val)
{
  sim_cpu_core *cpu_core = CPU_CORE (cpu);
  sim_core_common *core = &cpu_core->common;
  sim_core_mapping *mapping;
  address_word addr;
#if WITH_XOR_ENDIAN != 0
  if (WITH_XOR_ENDIAN)
    addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
  else
#endif
    addr = xaddr;
  mapping = sim_core_find_mapping (core, map, addr, N, write_transfer, 1 /*abort*/, cpu, cia);
  do
    {
#if (WITH_DEVICES)
      if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
	{
	  unsigned_M data = H2T_M (val);
	  if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
	    device_error (mapping->device, "internal error - %s - io_write_buffer should not fail",
			  XSTRING (sim_core_write_aligned_N));
	  break;
	}
#endif
#if (WITH_HW)
      if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
	{
	  unsigned_M data = H2T_M (val);
	  sim_cpu_hw_io_write_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
	  break;
	}
#endif
      *(unsigned_M*) sim_core_translate (mapping, addr) = H2T_M (val);
    }
  while (0);
  PROFILE_COUNT_CORE (cpu, addr, N, map);
  if (TRACE_P (cpu, TRACE_CORE_IDX))
    sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
}
#endif

/* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
/* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
/* TAGS: sim_core_write_unaligned_16 */

#if (M == N && N > 1)
INLINE_SIM_CORE(void)
sim_core_write_unaligned_N(sim_cpu *cpu,
			   sim_cia cia,
			   unsigned map,
			   address_word addr,
			   unsigned_M val)
{
  int alignment = N - 1;
  /* if hardwired to forced alignment just do it */
  if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
    sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
  else if ((addr & alignment) == 0)
    sim_core_write_aligned_N (cpu, cia, map, addr, val);
  else
    switch (CURRENT_ALIGNMENT)
      {
      case STRICT_ALIGNMENT:
	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
			 write_transfer, sim_core_unaligned_signal);
	break;
      case NONSTRICT_ALIGNMENT:
	{
	  unsigned_M data = H2T_M (val);
	  if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
	    SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
			     write_transfer, sim_core_unaligned_signal);
	  PROFILE_COUNT_CORE (cpu, addr, N, map);
	  if (TRACE_P (cpu, TRACE_CORE_IDX))
	    sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
	  break;
	}
      case FORCED_ALIGNMENT:
	sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
	break;
      case MIXED_ALIGNMENT:
	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
			  "internal error - %s - mixed alignment",
			  XSTRING (sim_core_write_unaligned_N));
	break;
      default:
	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
			  "internal error - %s - bad switch",
			  XSTRING (sim_core_write_unaligned_N));
	break;
      }
}
#endif

/* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */
/* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */

#if (M != N)
INLINE_SIM_CORE(void)
sim_core_write_misaligned_N(sim_cpu *cpu,
			   sim_cia cia,
			   unsigned map,
			   address_word addr,
			   unsigned_M val)
{
  unsigned_M data = val;
  if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
    data <<= (M - N) * 8;
  if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
    data = SWAP_M (data);
  if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
    SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
		     write_transfer, sim_core_unaligned_signal);
  PROFILE_COUNT_CORE (cpu, addr, N, map);
  if (TRACE_P (cpu, TRACE_CORE_IDX))
    sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
}
#endif


/* NOTE: see start of file for #define of these macros */
#undef unsigned_M
#undef T2H_M
#undef H2T_M
#undef SWAP_M
#undef sim_core_read_aligned_N
#undef sim_core_read_unaligned_N
#undef sim_core_read_misaligned_N
#undef sim_core_write_aligned_N
#undef sim_core_write_unaligned_N
#undef sim_core_write_misaligned_N
#undef sim_core_trace_M
#undef sim_core_dummy_M
#undef M
#undef N
Commit	Line	Data
b85e4829 AC	1	/* The common simulator framework for GDB, the GNU Debugger.
b85e4829 AC	2
6aba47ca	3	Copyright 2002, 2007 Free Software Foundation, Inc.
b85e4829 AC	4
	5	Contributed by Andrew Cagney and Red Hat.
	6
	7	This file is part of GDB.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 2 of the License, or
	12	(at your option) any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with this program; if not, write to the Free Software
	21	Foundation, Inc., 59 Temple Place - Suite 330,
	22	Boston, MA 02111-1307, USA. */
c906108c SS	23
	24
	25	#ifndef N
	26	#error "N must be #defined"
	27	#endif
	28	#ifndef M
	29	#define M N
	30	#endif
	31
	32	/* N: The number of bytes of data to transfer.
	33	M: The number of bytes in the type used to transfer the data */
	34
	35	#if (N > M)
	36	#error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
	37	#endif
	38
	39
	40	#include "symcat.h"
	41
	42	/* NOTE: see end of file for #undef of these macros */
	43
	44	#define unsigned_M XCONCAT2(unsigned_,M)
	45
	46	#define T2H_M XCONCAT2(T2H_,M)
	47	#define H2T_M XCONCAT2(H2T_,M)
	48	#define SWAP_M XCONCAT2(SWAP_,M)
	49
	50	#define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
	51	#define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
	52	#define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N)
	53	#define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
	54	#define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
	55	#define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
	56	#define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
	57	#define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)
	58
	59
	60	#if (M == N && N > 1)
	61	/* dummy variable used as a return value when nothing else is
	62	available and the compiler is complaining */
	63	static unsigned_M sim_core_dummy_M;
	64	#endif
	65
	66
	67	/* TAGS: sim_core_trace_1 sim_core_trace_2 */
	68	/* TAGS: sim_core_trace_4 sim_core_trace_8 */
	69	/* TAGS: sim_core_trace_16 */
	70
	71	#if (M == N)
	72	STATIC_SIM_CORE(void)
	73	sim_core_trace_M (sim_cpu *cpu,
	74	sim_cia cia,
	75	int line_nr,
	76	transfer_type type,
	77	unsigned map,
	78	address_word addr,
	79	unsigned_M val,
	80	int nr_bytes)
	81	{
	82	const char *transfer = (type == read_transfer ? "read" : "write");
	83	const char *direction = (type == read_transfer ? "->" : "<-");
	84
	85	if (TRACE_DEBUG_P (cpu))
	86	trace_printf (CPU_STATE (cpu), cpu, "sim-n-core.h:%d: ", line_nr);
87
88	#if (M == 16)
89	trace_printf (CPU_STATE (cpu), cpu,
90	"%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n",
91	transfer, nr_bytes,
92	map_to_str (map),
93	(unsigned long) addr,
94	direction,
95	(unsigned long) V4_16 (val, 0),
96	(unsigned long) V4_16 (val, 1),
97	(unsigned long) V4_16 (val, 2),
98	(unsigned long) V4_16 (val, 3));
99	#endif
100	#if (M == 8)
101	trace_printf (CPU_STATE (cpu), cpu,
102	"%s-%d %s:0x%08lx %s 0x%08lx%08lx\n",
103	transfer, nr_bytes,
104	map_to_str (map),
105	(unsigned long) addr,
106	direction,
107	(unsigned long) V4_8 (val, 0),
108	(unsigned long) V4_8 (val, 1));
109	#endif
110	#if (M == 4)
111	trace_printf (CPU_STATE (cpu), cpu,
112	"%s-%d %s:0x%08lx %s 0x%08lx\n",
113	transfer,
114	nr_bytes,
115	map_to_str (map),
116	(unsigned long) addr,
117	direction,
118	(unsigned long) val);
119	#endif
120	#if (M == 2)
121	trace_printf (CPU_STATE (cpu), cpu,
122	"%s-%d %s:0x%08lx %s 0x%04lx\n",
123	transfer,
124	nr_bytes,
125	map_to_str (map),
126	(unsigned long) addr,
127	direction,
128	(unsigned long) val);
129	#endif
130	#if (M == 1)
131	trace_printf (CPU_STATE (cpu), cpu,
132	"%s-%d %s:0x%08lx %s 0x%02lx\n",
133	transfer,
134	nr_bytes,
135	map_to_str (map),
136	(unsigned long) addr,
137	direction,
138	(unsigned long) val);
139	#endif
140	}
141	#endif
142
143
144	/* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
145	/* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
146	/* TAGS: sim_core_read_aligned_16 */
147
148	#if (M == N)
149	INLINE_SIM_CORE(unsigned_M)
150	sim_core_read_aligned_N(sim_cpu *cpu,
151	sim_cia cia,
152	unsigned map,
153	address_word xaddr)
154	{
155	sim_cpu_core *cpu_core = CPU_CORE (cpu);
156	sim_core_common *core = &cpu_core->common;
157	unsigned_M val;
158	sim_core_mapping *mapping;
159	address_word addr;
160	#if WITH_XOR_ENDIAN != 0
161	if (WITH_XOR_ENDIAN)
162	addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
163	else
164	#endif
165	addr = xaddr;
166	mapping = sim_core_find_mapping (core, map, addr, N, read_transfer, 1 /abort/, cpu, cia);
167	do
168	{
169	#if (WITH_DEVICES)
170	if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
171	{
172	unsigned_M data;
7a292a7a	173	if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
c906108c SS	174	device_error (mapping->device, "internal error - %s - io_read_buffer should not fail",
	175	XSTRING (sim_core_read_aligned_N));
	176	val = T2H_M (data);
	177	break;
	178	}
	179	#endif
	180	#if (WITH_HW)
	181	if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
	182	{
	183	unsigned_M data;
	184	sim_cpu_hw_io_read_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
	185	val = T2H_M (data);
	186	break;
	187	}
	188	#endif
	189	val = T2H_M ((unsigned_M) sim_core_translate (mapping, addr));
	190	}
	191	while (0);
	192	PROFILE_COUNT_CORE (cpu, addr, N, map);
	193	if (TRACE_P (cpu, TRACE_CORE_IDX))
	194	sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
	195	return val;
	196	}
	197	#endif
	198
	199	/* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
	200	/* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
	201	/* TAGS: sim_core_read_unaligned_16 */
	202
	203	#if (M == N && N > 1)
	204	INLINE_SIM_CORE(unsigned_M)
	205	sim_core_read_unaligned_N(sim_cpu *cpu,
	206	sim_cia cia,
	207	unsigned map,
	208	address_word addr)
	209	{
	210	int alignment = N - 1;
	211	/* if hardwired to forced alignment just do it */
	212	if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
	213	return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
	214	else if ((addr & alignment) == 0)
	215	return sim_core_read_aligned_N (cpu, cia, map, addr);
	216	else
	217	switch (CURRENT_ALIGNMENT)
	218	{
	219	case STRICT_ALIGNMENT:
	220	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
	221	read_transfer, sim_core_unaligned_signal);
	222	case NONSTRICT_ALIGNMENT:
	223	{
	224	unsigned_M val;
	225	if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
	226	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
	227	read_transfer, sim_core_unaligned_signal);
	228	val = T2H_M(val);
	229	PROFILE_COUNT_CORE (cpu, addr, N, map);
	230	if (TRACE_P (cpu, TRACE_CORE_IDX))
	231	sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
	232	return val;
	233	}
	234	case FORCED_ALIGNMENT:
	235	return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
	236	case MIXED_ALIGNMENT:
	237	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
238	"internal error - %s - mixed alignment",
239	XSTRING (sim_core_read_unaligned_N));
240	default:
241	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
242	"internal error - %s - bad switch",
243	XSTRING (sim_core_read_unaligned_N));
244	/* to keep some compilers happy, we return a dummy */
245	return sim_core_dummy_M;
246	}
247	}
248	#endif
249
250	/* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */
251	/* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */
252
253	#if (M != N)
254	INLINE_SIM_CORE(unsigned_M)
255	sim_core_read_misaligned_N(sim_cpu *cpu,
256	sim_cia cia,
257	unsigned map,
258	address_word addr)
259	{
260	unsigned_M val = 0;
261	if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
262	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
263	read_transfer, sim_core_unaligned_signal);
264	if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
265	val = SWAP_M (val);
266	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
267	val >>= (M - N) * 8;
268	PROFILE_COUNT_CORE (cpu, addr, N, map);
269	if (TRACE_P (cpu, TRACE_CORE_IDX))
270	sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
271	return val;
272	}
273	#endif
274
275	/* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
276	/* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
277	/* TAGS: sim_core_write_aligned_16 */
278
279	#if (M == N)
280	INLINE_SIM_CORE(void)
281	sim_core_write_aligned_N(sim_cpu *cpu,
282	sim_cia cia,
283	unsigned map,
284	address_word xaddr,
285	unsigned_M val)
286	{
287	sim_cpu_core *cpu_core = CPU_CORE (cpu);
288	sim_core_common *core = &cpu_core->common;
289	sim_core_mapping *mapping;
290	address_word addr;
291	#if WITH_XOR_ENDIAN != 0
292	if (WITH_XOR_ENDIAN)
293	addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
294	else
295	#endif
296	addr = xaddr;
297	mapping = sim_core_find_mapping (core, map, addr, N, write_transfer, 1 /abort/, cpu, cia);
298	do
299	{
300	#if (WITH_DEVICES)
301	if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
302	{
303	unsigned_M data = H2T_M (val);
7a292a7a	304	if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
c906108c SS	305	device_error (mapping->device, "internal error - %s - io_write_buffer should not fail",
	306	XSTRING (sim_core_write_aligned_N));
	307	break;
	308	}
	309	#endif
	310	#if (WITH_HW)
	311	if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
	312	{
	313	unsigned_M data = H2T_M (val);
	314	sim_cpu_hw_io_write_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
	315	break;
	316	}
	317	#endif
	318	(unsigned_M) sim_core_translate (mapping, addr) = H2T_M (val);
	319	}
	320	while (0);
	321	PROFILE_COUNT_CORE (cpu, addr, N, map);
	322	if (TRACE_P (cpu, TRACE_CORE_IDX))
	323	sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
	324	}
	325	#endif
	326
	327	/* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
	328	/* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
	329	/* TAGS: sim_core_write_unaligned_16 */
	330
	331	#if (M == N && N > 1)
	332	INLINE_SIM_CORE(void)
	333	sim_core_write_unaligned_N(sim_cpu *cpu,
	334	sim_cia cia,
	335	unsigned map,
	336	address_word addr,
	337	unsigned_M val)
	338	{
	339	int alignment = N - 1;
	340	/* if hardwired to forced alignment just do it */
	341	if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
	342	sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
	343	else if ((addr & alignment) == 0)
	344	sim_core_write_aligned_N (cpu, cia, map, addr, val);
	345	else
	346	switch (CURRENT_ALIGNMENT)
	347	{
	348	case STRICT_ALIGNMENT:
	349	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
	350	write_transfer, sim_core_unaligned_signal);
	351	break;
	352	case NONSTRICT_ALIGNMENT:
	353	{
	354	unsigned_M data = H2T_M (val);
	355	if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
	356	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
	357	write_transfer, sim_core_unaligned_signal);
	358	PROFILE_COUNT_CORE (cpu, addr, N, map);
	359	if (TRACE_P (cpu, TRACE_CORE_IDX))
	360	sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
	361	break;
	362	}
	363	case FORCED_ALIGNMENT:
	364	sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
	365	break;
	366	case MIXED_ALIGNMENT:
	367	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
	368	"internal error - %s - mixed alignment",
369	XSTRING (sim_core_write_unaligned_N));
370	break;
371	default:
372	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
373	"internal error - %s - bad switch",
374	XSTRING (sim_core_write_unaligned_N));
375	break;
376	}
377	}
378	#endif
379
380	/* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */
381	/* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */
382
383	#if (M != N)
384	INLINE_SIM_CORE(void)
385	sim_core_write_misaligned_N(sim_cpu *cpu,
386	sim_cia cia,
387	unsigned map,
388	address_word addr,
389	unsigned_M val)
390	{
391	unsigned_M data = val;
392	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
393	data <<= (M - N) * 8;
394	if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
395	data = SWAP_M (data);
396	if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
397	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
398	write_transfer, sim_core_unaligned_signal);
399	PROFILE_COUNT_CORE (cpu, addr, N, map);
400	if (TRACE_P (cpu, TRACE_CORE_IDX))
401	sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
402	}
403	#endif
404
405
406	/* NOTE: see start of file for #define of these macros */
407	#undef unsigned_M
408	#undef T2H_M
409	#undef H2T_M
410	#undef SWAP_M
411	#undef sim_core_read_aligned_N
412	#undef sim_core_read_unaligned_N
413	#undef sim_core_read_misaligned_N
414	#undef sim_core_write_aligned_N
415	#undef sim_core_write_unaligned_N
416	#undef sim_core_write_misaligned_N
417	#undef sim_core_trace_M
418	#undef sim_core_dummy_M
419	#undef M
420	#undef N