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* inf-loop.c (inferior_event_handler): Call bpstat_do_action,
[thirdparty/binutils-gdb.git] / sim / cr16 / interp.c
CommitLineData
fee8ec00
SR		 1/* Simulation code for the CR16 processor.
2 Copyright (C) 2008 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License along
18 with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include <signal.h>
21#include "sysdep.h"
22#include "bfd.h"
23#include "gdb/callback.h"
24#include "gdb/remote-sim.h"
25
26#include "cr16_sim.h"
27#include "gdb/sim-cr16.h"
28#include "gdb/signals.h"
29#include "opcode/cr16.h"
30
31enum _leftright { LEFT_FIRST, RIGHT_FIRST };
32
33static char *myname;
34static SIM_OPEN_KIND sim_kind;
35int cr16_debug;
36
37/* Set this to true to get the previous segment layout. */
38
39int old_segment_mapping;
40
41host_callback *cr16_callback;
42unsigned long ins_type_counters[ (int)INS_MAX ];
43
44uint32 OP[4];
45uint32 sign_flag;
46
47static int init_text_p = 0;
48/* non-zero if we opened prog_bfd */
49static int prog_bfd_was_opened_p;
50bfd *prog_bfd;
51asection *text;
52bfd_vma text_start;
53bfd_vma text_end;
54
55static void get_operands PARAMS ((operand_desc *s, uint64 mcode, int isize));
56static void do_run PARAMS ((inst *ins, uint64 mc));
57static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
58extern void sim_set_profile PARAMS ((int n));
59extern void sim_set_profile_size PARAMS ((int n));
60static INLINE uint8 *map_memory (unsigned phys_addr);
61
62#ifdef NEED_UI_LOOP_HOOK
63/* How often to run the ui_loop update, when in use */
64#define UI_LOOP_POLL_INTERVAL 0x14000
65
66/* Counter for the ui_loop_hook update */
67static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
68
69/* Actual hook to call to run through gdb's gui event loop */
70extern int (*deprecated_ui_loop_hook) PARAMS ((int signo));
71#endif /* NEED_UI_LOOP_HOOK */
72
73#ifndef INLINE
74#if defined(__GNUC__) && defined(__OPTIMIZE__)
75#define INLINE __inline__
76#else
77#define INLINE
78#endif
79#endif
80
81INLINE static void
82get_operands (operand_desc *s, uint64 ins, int isize)
83{
84 uint32 i, opn = 0, start_bit = 0, op_type = 0;
85 int32 op_size = 0, mask = 0;
86
87 if (isize == 1) /* Trunkcate the extra 16 bits of INS. */
88 ins = ins >> 16;
89
90 for (i=0; i < 3; ++i,++opn)
91 {
92 if ((s[opn].op_type == dummy) || (s[opn].op_type > cr16_num_optab))
93 break;
94 else
95 op_type = s[opn].op_type;
96
97 start_bit = s[opn].shift;
98 op_size = cr16_optab[op_type].bit_size;
99
100 switch (op_type)
101 {
102 case imm3: case imm4: case imm5: case imm6:
103 {
104 if (isize == 1)
105 OP[i] = ((ins >> 4) & ((1 << op_size) -1));
106 else
107 OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));
108
109 if (OP[i] & ((long)1 << (op_size -1)))
110 {
111 sign_flag = 1;
112 OP[i] = ~(OP[i]) + 1;
113 }
114 OP[i] = (unsigned long int)(OP[i] & (((long)1 << op_size) -1));
115 }
116 break;
117
118 case uimm3: case uimm3_1: case uimm4_1:
119 if (isize == 1)
120 OP[i] = ((ins >> 4) & ((1 << op_size) -1));
121 else
122 OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));
123 break;
124
125 case uimm4:
126 switch (isize)
127 {
128 case 1:
129 if (start_bit == 20)
130 OP[i] = ((ins >> 4) & ((1 << op_size) -1));
131 else
132 OP[i] = (ins & ((1 << op_size) -1));
133 break;
134 case 2:
135 OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
136 break;
137 case 3:
138 OP[i] = ((ins >> (start_bit + 16)) & ((1 << op_size) -1));
139 break;
140 default:
141 OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
142 break;
143 }
144 break;
145
146 case imm16: case uimm16:
147 OP[i] = ins & 0xFFFF;
148 break;
149
150 case uimm20: case imm20:
151 OP[i] = ins & (((long)1 << op_size) - 1);
152 break;
153
154 case imm32: case uimm32:
155 OP[i] = ins & 0xFFFFFFFF;
156 break;
157
158 case uimm5: break; /*NOT USED. */
159 OP[i] = ins & ((1 << op_size) - 1); break;
160
161 case disps5:
162 OP[i] = (ins >> 4) & ((1 << 4) - 1);
163 OP[i] = (OP[i] * 2) + 2;
164 if (OP[i] & ((long)1 << 5))
165 {
166 sign_flag = 1;
167 OP[i] = ~(OP[i]) + 1;
168 OP[i] = (unsigned long int)(OP[i] & 0x1F);
169 }
170 break;
171
172 case dispe9:
173 OP[i] = ((((ins >> 8) & 0xf) << 4) | (ins & 0xf));
174 OP[i] <<= 1;
175 if (OP[i] & ((long)1 << 8))
176 {
177 sign_flag = 1;
178 OP[i] = ~(OP[i]) + 1;
179 OP[i] = (unsigned long int)(OP[i] & 0xFF);
180 }
181 break;
182
183 case disps17:
184 OP[i] = (ins & 0xFFFF);
185 if (OP[i] & 1)
186 {
187 OP[i] = (OP[i] & 0xFFFE);
188 sign_flag = 1;
189 OP[i] = ~(OP[i]) + 1;
190 OP[i] = (unsigned long int)(OP[i] & 0xFFFF);
191 }
192 break;
193
194 case disps25:
195 if (isize == 2)
196 OP[i] = (ins & 0xFFFFFF);
197 else
198 OP[i] = (ins & 0xFFFF) | (((ins >> 24) & 0xf) << 16) |
199 (((ins >> 16) & 0xf) << 20);
200
201 if (OP[i] & 1)
202 {
203 OP[i] = (OP[i] & 0xFFFFFE);
204 sign_flag = 1;
205 OP[i] = ~(OP[i]) + 1;
206 OP[i] = (unsigned long int)(OP[i] & 0xFFFFFF);
207 }
208 break;
209
210 case abs20:
211 if (isize == 3)
212 OP[i] = (ins) & 0xFFFFF;
213 else
214 OP[i] = (ins >> start_bit) & 0xFFFFF;
215 break;
216 case abs24:
217 if (isize == 3)
218 OP[i] = ((ins & 0xFFFF) | (((ins >> 16) & 0xf) << 20)
219 | (((ins >> 24) & 0xf) << 16));
220 else
221 OP[i] = (ins >> 16) & 0xFFFFFF;
222 break;
223
224 case rra:
225 case rbase: break; /* NOT USED. */
226 case rbase_disps20: case rbase_dispe20:
227 case rpbase_disps20: case rpindex_disps20:
228 OP[i] = ((((ins >> 24)&0xf) << 16)|((ins) & 0xFFFF));
229 OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */
230 break;
231 case rpbase_disps0:
232 OP[i] = 0; /* 4 bit disp const. */
233 OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */
234 break;
235 case rpbase_dispe4:
236 OP[i] = ((ins >> 8) & 0xF) * 2; /* 4 bit disp const. */
237 OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */
238 break;
239 case rpbase_disps4:
240 OP[i] = ((ins >> 8) & 0xF); /* 4 bit disp const. */
241 OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */
242 break;
243 case rpbase_disps16:
244 OP[i] = (ins) & 0xFFFF;
245 OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */
246 break;
247 case rpindex_disps0:
248 OP[i] = 0;
249 OP[++i] = (ins >> 4) & 0xF; /* get 4 bit for reg. */
250 OP[++i] = (ins >> 8) & 0x1; /* get 1 bit for index-reg. */
251 break;
252 case rpindex_disps14:
253 OP[i] = (ins) & 0x3FFF;
254 OP[++i] = (ins >> 14) & 0x1; /* get 1 bit for index-reg. */
255 OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */
256 case rindex7_abs20:
257 case rindex8_abs20:
258 OP[i] = (ins) & 0xFFFFF;
259 OP[++i] = (ins >> 24) & 0x1; /* get 1 bit for index-reg. */
260 OP[++i] = (ins >> 20) & 0xF; /* get 4 bit for reg. */
261 break;
262 case regr: case regp: case pregr: case pregrp:
263 switch(isize)
264 {
265 case 1:
266 if (start_bit == 20) OP[i] = (ins >> 4) & 0xF;
267 else if (start_bit == 16) OP[i] = ins & 0xF;
268 break;
269 case 2: OP[i] = (ins >> start_bit) & 0xF; break;
270 case 3: OP[i] = (ins >> (start_bit + 16)) & 0xF; break;
271 }
272 break;
273 case cc:
274 {
275 if (isize == 1) OP[i] = (ins >> 4) & 0xF;
276 else if (isize == 2) OP[i] = (ins >> start_bit) & 0xF;
277 else OP[i] = (ins >> (start_bit + 16)) & 0xF;
278 break;
279 }
280 default: break;
281 }
282
283 /* For ESC on uimm4_1 operand */
284 if (op_type == uimm4_1)
285 if (OP[i] == 9)
286 OP[i] = -1;
287 }
288 /* FIXME: for tracing, update values that need to be updated each
289 instruction decode cycle */
290#if 0 // DEBUG
291 (*cr16_callback->printf_filtered) (cr16_callback, "OP0=0x%X\t,OP1=0x%X\t,OP2=0x%X\t,OP3=0X%X\n",OP[0],OP[1],OP[2],OP[3]);
292#endif
293 State.trace.psw = PSR;
294
295}
296
297bfd_vma
298decode_pc ()
299{
300 asection *s;
301 if (!init_text_p && prog_bfd != NULL)
302 {
303 init_text_p = 1;
304 for (s = prog_bfd->sections; s; s = s->next)
305 if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
306 {
307 text = s;
308 text_start = bfd_get_section_vma (prog_bfd, s);
309 text_end = text_start + bfd_section_size (prog_bfd, s);
310 break;
311 }
312 }
313
314 return (PC) + text_start;
315}
316
317
318
319static void
320do_run(inst *instruction, uint64 mcode)
321{
322 struct simops *s= Simops;
323 char func[12]="\0";
324#ifdef DEBUG
325 if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
326 (*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", instruction);
327#endif
328
329 /* Re-set OP list */
330 OP[0] = OP[1] = OP[2] = OP[3] = sign_flag = 0;
331
332 /* for push/pop/pushrtn with RA instructions */
333 if ((INST_HAS_REG_LIST) && (mcode & 0x800000))
334 OP[2] = 1; /* Set 1 for RA operand */
335
336 get_operands (&instruction->operands, mcode, instruction->size);
337
338 State.ins_type = instruction->flags;
339 //ins_type_counters[ (int)State.ins_type ]++;
340 sprintf(func,"OP_%X_%X",instruction->match,(32 - instruction->match_bits));
341 /* Check for appropriate opcode function */
342 for ( ;s->opcode!=0;s++)
343 {
344 if (strcmp(s->fname,func) == 0)
345 break;
346 }
347 (s->func)();
348}
349
350static char *
351add_commas(char *buf, int sizeof_buf, unsigned long value)
352{
353 int comma = 3;
354 char *endbuf = buf + sizeof_buf - 1;
355
356 *--endbuf = '\0';
357 do {
358 if (comma-- == 0)
359 {
360 *--endbuf = ',';
361 comma = 2;
362 }
363
364 *--endbuf = (value % 10) + '0';
365 } while ((value /= 10) != 0);
366
367 return endbuf;
368}
369
370void
371sim_size (int power)
372{
373 int i;
374 for (i = 0; i < IMEM_SEGMENTS; i++)
375 {
376 if (State.mem.insn[i])
377 free (State.mem.insn[i]);
378 }
379 for (i = 0; i < DMEM_SEGMENTS; i++)
380 {
381 if (State.mem.data[i])
382 free (State.mem.data[i]);
383 }
384 for (i = 0; i < UMEM_SEGMENTS; i++)
385 {
386 if (State.mem.unif[i])
387 free (State.mem.unif[i]);
388 }
389 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
390 registers. */
391 State.mem.data[0] = calloc (1, SEGMENT_SIZE);
392}
393
394/* For tracing - leave info on last access around. */
395static char *last_segname = "invalid";
396static char *last_from = "invalid";
397static char *last_to = "invalid";
398
399enum
400 {
401 IMAP0_OFFSET = 0xff00,
402 DMAP0_OFFSET = 0xff08,
403 DMAP2_SHADDOW = 0xff04,
404 DMAP2_OFFSET = 0xff0c
405 };
406
407static void
408set_dmap_register (int reg_nr, unsigned long value)
409{
410 uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
411 + DMAP0_OFFSET + 2 * reg_nr);
412 WRITE_16 (raw, value);
413#ifdef DEBUG
414 if ((cr16_debug & DEBUG_MEMORY))
415 {
416 (*cr16_callback->printf_filtered)
417 (cr16_callback, "mem: dmap%d=0x%04lx\n", reg_nr, value);
418 }
419#endif
420}
421
422static unsigned long
423dmap_register (void *regcache, int reg_nr)
424{
425 uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
426 + DMAP0_OFFSET + 2 * reg_nr);
427 return READ_16 (raw);
428}
429
430static void
431set_imap_register (int reg_nr, unsigned long value)
432{
433 uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
434 + IMAP0_OFFSET + 2 * reg_nr);
435 WRITE_16 (raw, value);
436#ifdef DEBUG
437 if ((cr16_debug & DEBUG_MEMORY))
438 {
439 (*cr16_callback->printf_filtered)
440 (cr16_callback, "mem: imap%d=0x%04lx\n", reg_nr, value);
441 }
442#endif
443}
444
445static unsigned long
446imap_register (void *regcache, int reg_nr)
447{
448 uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
449 + IMAP0_OFFSET + 2 * reg_nr);
450 return READ_16 (raw);
451}
452
453enum
454 {
455 HELD_SPI_IDX = 0,
456 HELD_SPU_IDX = 1
457 };
458
459static unsigned long
460spu_register (void)
461{
462 return GPR (SP_IDX);
463}
464
465static unsigned long
466spi_register (void)
467{
468 return GPR (SP_IDX);
469}
470
471static void
472set_spi_register (unsigned long value)
473{
474 SET_GPR (SP_IDX, value);
475}
476
477static void
478set_spu_register (unsigned long value)
479{
480 SET_GPR (SP_IDX, value);
481}
482
483/* Given a virtual address in the DMAP address space, translate it
484 into a physical address. */
485
486unsigned long
487sim_cr16_translate_dmap_addr (unsigned long offset,
488 int nr_bytes,
489 unsigned long *phys,
490 void *regcache,
491 unsigned long (*dmap_register) (void *regcache,
492 int reg_nr))
493{
494 short map;
495 int regno;
496 last_from = "logical-data";
497 if (offset >= DMAP_BLOCK_SIZE * SIM_CR16_NR_DMAP_REGS)
498 {
499 /* Logical address out side of data segments, not supported */
500 return 0;
501 }
502 regno = (offset / DMAP_BLOCK_SIZE);
503 offset = (offset % DMAP_BLOCK_SIZE);
504
505#if 1
506 if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE)
507 {
508 /* Don't cross a BLOCK boundary */
509 nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
510 }
511 map = dmap_register (regcache, regno);
512 if (regno == 3)
513 {
514 /* Always maps to data memory */
515 int iospi = (offset / 0x1000) % 4;
516 int iosp = (map >> (4 * (3 - iospi))) % 0x10;
517 last_to = "io-space";
518 *phys = (SIM_CR16_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset);
519 }
520 else
521 {
522 int sp = ((map & 0x3000) >> 12);
523 int segno = (map & 0x3ff);
524 switch (sp)
525 {
526 case 0: /* 00: Unified memory */
527 *phys = SIM_CR16_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
528 last_to = "unified";
529 break;
530 case 1: /* 01: Instruction Memory */
531 *phys = SIM_CR16_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
532 last_to = "chip-insn";
533 break;
534 case 2: /* 10: Internal data memory */
535 *phys = SIM_CR16_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
536 last_to = "chip-data";
537 break;
538 case 3: /* 11: Reserved */
539 return 0;
540 }
541 }
542#endif
543 return nr_bytes;
544}
545
546/* Given a virtual address in the IMAP address space, translate it
547 into a physical address. */
548
549unsigned long
550sim_cr16_translate_imap_addr (unsigned long offset,
551 int nr_bytes,
552 unsigned long *phys,
553 void *regcache,
554 unsigned long (*imap_register) (void *regcache,
555 int reg_nr))
556{
557 short map;
558 int regno;
559 int sp;
560 int segno;
561 last_from = "logical-insn";
562 if (offset >= (IMAP_BLOCK_SIZE * SIM_CR16_NR_IMAP_REGS))
563 {
564 /* Logical address outside of IMAP segments, not supported */
565 return 0;
566 }
567 regno = (offset / IMAP_BLOCK_SIZE);
568 offset = (offset % IMAP_BLOCK_SIZE);
569 if (offset + nr_bytes > IMAP_BLOCK_SIZE)
570 {
571 /* Don't cross a BLOCK boundary */
572 nr_bytes = IMAP_BLOCK_SIZE - offset;
573 }
574 map = imap_register (regcache, regno);
575 sp = (map & 0x3000) >> 12;
576 segno = (map & 0x007f);
577 switch (sp)
578 {
579 case 0: /* 00: unified memory */
580 *phys = SIM_CR16_MEMORY_UNIFIED + (segno << 17) + offset;
581 last_to = "unified";
582 break;
583 case 1: /* 01: instruction memory */
584 *phys = SIM_CR16_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset;
585 last_to = "chip-insn";
586 break;
587 case 2: /*10*/
588 /* Reserved. */
589 return 0;
590 case 3: /* 11: for testing - instruction memory */
591 offset = (offset % 0x800);
592 *phys = SIM_CR16_MEMORY_INSN + offset;
593 if (offset + nr_bytes > 0x800)
594 /* don't cross VM boundary */
595 nr_bytes = 0x800 - offset;
596 last_to = "test-insn";
597 break;
598 }
599 return nr_bytes;
600}
601
602unsigned long
603sim_cr16_translate_addr (unsigned long memaddr,
604 int nr_bytes,
605 unsigned long *targ_addr,
606 void *regcache,
607 unsigned long (*dmap_register) (void *regcache,
608 int reg_nr),
609 unsigned long (*imap_register) (void *regcache,
610 int reg_nr))
611{
612 unsigned long phys;
613 unsigned long seg;
614 unsigned long off;
615
616 last_from = "unknown";
617 last_to = "unknown";
618
619 seg = (memaddr >> 24);
620 off = (memaddr & 0xffffffL);
621
622 /* However, if we've asked to use the previous generation of segment
623 mapping, rearrange the segments as follows. */
624
625 if (old_segment_mapping)
626 {
627 switch (seg)
628 {
629 case 0x00: /* DMAP translated memory */
630 seg = 0x10;
631 break;
632 case 0x01: /* IMAP translated memory */
633 seg = 0x11;
634 break;
635 case 0x10: /* On-chip data memory */
636 seg = 0x02;
637 break;
638 case 0x11: /* On-chip insn memory */
639 seg = 0x01;
640 break;
641 case 0x12: /* Unified memory */
642 seg = 0x00;
643 break;
644 }
645 }
646
647 switch (seg)
648 {
649 case 0x00: /* Physical unified memory */
650 last_from = "phys-unified";
651 last_to = "unified";
652 phys = SIM_CR16_MEMORY_UNIFIED + off;
653 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
654 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
655 break;
656
657 case 0x01: /* Physical instruction memory */
658 last_from = "phys-insn";
659 last_to = "chip-insn";
660 phys = SIM_CR16_MEMORY_INSN + off;
661 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
662 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
663 break;
664
665 case 0x02: /* Physical data memory segment */
666 last_from = "phys-data";
667 last_to = "chip-data";
668 phys = SIM_CR16_MEMORY_DATA + off;
669 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
670 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
671 break;
672
673 case 0x10: /* in logical data address segment */
674 nr_bytes = sim_cr16_translate_dmap_addr (off, nr_bytes, &phys, regcache,
675 dmap_register);
676 break;
677
678 case 0x11: /* in logical instruction address segment */
679 nr_bytes = sim_cr16_translate_imap_addr (off, nr_bytes, &phys, regcache,
680 imap_register);
681 break;
682
683 default:
684 return 0;
685 }
686
687 *targ_addr = phys;
688 return nr_bytes;
689}
690
691/* Return a pointer into the raw buffer designated by phys_addr. It
692 is assumed that the client has already ensured that the access
693 isn't going to cross a segment boundary. */
694
695uint8 *
696map_memory (unsigned phys_addr)
697{
698 uint8 **memory;
699 uint8 *raw;
700 unsigned offset;
701 int segment = ((phys_addr >> 24) & 0xff);
702
703 switch (segment)
704 {
705
706 case 0x00: /* Unified memory */
707 {
708 memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
709 last_segname = "umem";
710 break;
711 }
712
713 case 0x01: /* On-chip insn memory */
714 {
715 memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
716 last_segname = "imem";
717 break;
718 }
719
720 case 0x02: /* On-chip data memory */
721 {
722 if ((phys_addr & 0xff00) == 0xff00)
723 {
724 phys_addr = (phys_addr & 0xffff);
725 if (phys_addr == DMAP2_SHADDOW)
726 {
727 phys_addr = DMAP2_OFFSET;
728 last_segname = "dmap";
729 }
730 else
731 last_segname = "reg";
732 }
733 else
734 last_segname = "dmem";
735 memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
736 break;
737 }
738
739 default:
740 /* OOPS! */
741 last_segname = "scrap";
742 return State.mem.fault;
743 }
744
745 if (*memory == NULL)
746 {
747 *memory = calloc (1, SEGMENT_SIZE);
748 if (*memory == NULL)
749 {
750 (*cr16_callback->printf_filtered) (cr16_callback, "Malloc failed.\n");
751 return State.mem.fault;
752 }
753 }
754
755 offset = (phys_addr % SEGMENT_SIZE);
756 raw = *memory + offset;
757 return raw;
758}
759
760/* Transfer data to/from simulated memory. Since a bug in either the
761 simulated program or in gdb or the simulator itself may cause a
762 bogus address to be passed in, we need to do some sanity checking
763 on addresses to make sure they are within bounds. When an address
764 fails the bounds check, treat it as a zero length read/write rather
765 than aborting the entire run. */
766
767static int
768xfer_mem (SIM_ADDR virt,
769 unsigned char *buffer,
770 int size,
771 int write_p)
772{
773 uint8 *memory;
774 unsigned long phys;
775 int phys_size;
776 phys_size = sim_cr16_translate_addr (virt, size, &phys, NULL,
777 dmap_register, imap_register);
778 if (phys_size == 0)
779 return 0;
780
781 memory = map_memory (phys);
782
783#ifdef DEBUG
784 if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
785 {
786 (*cr16_callback->printf_filtered)
787 (cr16_callback,
788 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
789 (write_p ? "write" : "read"),
790 phys_size, virt, last_from,
791 phys, last_to,
792 (long) memory, last_segname);
793 }
794#endif
795
796 if (write_p)
797 {
798 memcpy (memory, buffer, phys_size);
799 }
800 else
801 {
802 memcpy (buffer, memory, phys_size);
803 }
804
805 return phys_size;
806}
807
808
809int
810sim_write (sd, addr, buffer, size)
811 SIM_DESC sd;
812 SIM_ADDR addr;
813 unsigned char *buffer;
814 int size;
815{
816 /* FIXME: this should be performing a virtual transfer */
817 return xfer_mem( addr, buffer, size, 1);
818}
819
820int
821sim_read (sd, addr, buffer, size)
822 SIM_DESC sd;
823 SIM_ADDR addr;
824 unsigned char *buffer;
825 int size;
826{
827 /* FIXME: this should be performing a virtual transfer */
828 return xfer_mem( addr, buffer, size, 0);
829}
830
831
832SIM_DESC
833sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct bfd *abfd, char **argv)
834{
835 struct simops *s;
836 static int init_p = 0;
837 char **p;
838
839 sim_kind = kind;
840 cr16_callback = callback;
841 myname = argv[0];
842 old_segment_mapping = 0;
843
844 /* NOTE: This argument parsing is only effective when this function
845 is called by GDB. Standalone argument parsing is handled by
846 sim/common/run.c. */
847#if 0
848 for (p = argv + 1; *p; ++p)
849 {
850 if (strcmp (*p, "-oldseg") == 0)
851 old_segment_mapping = 1;
852#ifdef DEBUG
853 else if (strcmp (*p, "-t") == 0)
854 cr16_debug = DEBUG;
855 else if (strncmp (*p, "-t", 2) == 0)
856 cr16_debug = atoi (*p + 2);
857#endif
858 else
859 (*cr16_callback->printf_filtered) (cr16_callback, "ERROR: unsupported option(s): %s\n",*p);
860 }
861#endif
862
863 /* reset the processor state */
864 if (!State.mem.data[0])
865 sim_size (1);
866 sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL);
867
868 /* Fudge our descriptor. */
869 return (SIM_DESC) 1;
870}
871
872
873void
874sim_close (sd, quitting)
875 SIM_DESC sd;
876 int quitting;
877{
878 if (prog_bfd != NULL && prog_bfd_was_opened_p)
879 {
880 bfd_close (prog_bfd);
881 prog_bfd = NULL;
882 prog_bfd_was_opened_p = 0;
883 }
884}
885
886void
887sim_set_profile (int n)
888{
889 (*cr16_callback->printf_filtered) (cr16_callback, "sim_set_profile %d\n",n);
890}
891
892void
893sim_set_profile_size (int n)
894{
895 (*cr16_callback->printf_filtered) (cr16_callback, "sim_set_profile_size %d\n",n);
896}
897
898uint8 *
899dmem_addr (uint32 offset)
900{
901 unsigned long phys;
902 uint8 *mem;
903 int phys_size;
904
905 /* Note: DMEM address range is 0..0x10000. Calling code can compute
906 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
907 is uint16 this is modulo'ed onto 0x0e5d. */
908
909 phys_size = sim_cr16_translate_dmap_addr (offset, 1, &phys, NULL,
910 dmap_register);
911 if (phys_size == 0)
912 {
913 mem = State.mem.fault;
914 }
915 else
916 mem = map_memory (phys);
917#ifdef DEBUG
918 if ((cr16_debug & DEBUG_MEMORY))
919 {
920 (*cr16_callback->printf_filtered)
921 (cr16_callback,
922 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
923 offset, last_from,
924 phys, phys_size, last_to,
925 (long) mem, last_segname);
926 }
927#endif
928 return mem;
929}
930
931uint8 *
932imem_addr (uint32 offset)
933{
934 unsigned long phys;
935 uint8 *mem;
936 int phys_size = sim_cr16_translate_imap_addr (offset, 1, &phys, NULL,
937 imap_register);
938 if (phys_size == 0)
939 {
940 return State.mem.fault;
941 }
942 mem = map_memory (phys);
943#ifdef DEBUG
944 if ((cr16_debug & DEBUG_MEMORY))
945 {
946 (*cr16_callback->printf_filtered)
947 (cr16_callback,
948 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
949 offset, last_from,
950 phys, phys_size, last_to,
951 (long) mem, last_segname);
952 }
953#endif
954 return mem;
955}
956
957static int stop_simulator = 0;
958
959int
960sim_stop (sd)
961 SIM_DESC sd;
962{
963 stop_simulator = 1;
964 return 1;
965}
966
967
968/* Run (or resume) the program. */
969void
970sim_resume (SIM_DESC sd, int step, int siggnal)
971{
972 uint32 mask = 0, ins_found = 0;
973 uint64 mcode=0;
974 uint8 *iaddr;
975
976#ifdef DEBUG
977// (*cr16_callback->printf_filtered) (cr16_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC);
978#endif
979
980 State.exception = 0;
981 if (step)
982 sim_stop (sd);
983
984 switch (siggnal)
985 {
986 case 0:
987 break;
988#ifdef SIGBUS
989 case SIGBUS:
990#endif
991 case SIGSEGV:
992 SET_PC (PC);
993 SET_PSR (PSR);
994 JMP (AE_VECTOR_START);
995 SLOT_FLUSH ();
996 break;
997 case SIGILL:
998 SET_PC (PC);
999 SET_PSR (PSR);
1000 SET_HW_PSR ((PSR & (PSR_C_BIT)));
1001 JMP (RIE_VECTOR_START);
1002 SLOT_FLUSH ();
1003 break;
1004 default:
1005 /* just ignore it */
1006 break;
1007 }
1008
1009 do
1010 {
1011 iaddr = imem_addr ((uint32)PC);
1012 ins_found = 0;
1013 if (iaddr == State.mem.fault)
1014 {
1015 State.exception = SIGBUS;
1016 break;
1017 }
1018
1019 mcode = get_longword( iaddr );
1020
1021 State.pc_changed = 0;
1022
1023 /* Start searching from end of instruction table. */
1024 const inst *instruction = &cr16_instruction[NUMOPCODES - 2];
1025
1026 /* Loop over instruction table until a full match is found. */
1027 while (instruction >= cr16_instruction)
1028 {
1029 mask = (((1 << (32 - instruction->match_bits)) -1) <<
1030 instruction->match_bits);
1031
1032 /* Adjuest mask for branch with 2 word instructions. */
1033 if ((IS_INSN_MNEMONIC("b") && instruction->size == 2))
1034 mask = 0xff0f0000;
1035
1036 if ((mcode & mask) == (BIN(instruction->match, instruction->match_bits)))
1037 {
1038 ins_found = 1;
1039 break;
1040 }
1041 else
1042 instruction--;
1043 }
1044
1045#if CR16_DEBUG
1046 (*cr16_callback->printf_filtered) (cr16_callback, "INS: PC=0x%X, mcode=0x%X\n",PC,mcode);
1047#endif
1048 if ((mcode == 0x0L) /*|| (!ins_found )*/)
1049 {
1050 State.exception = SIG_CR16_EXIT; /* exit trap */
1051 break;
1052 }
1053
1054 /* Check if the ins_found is '0', then set illigel instruction trap */
1055 if ( !ins_found )
1056 State.exception = SIGILL;
1057 else
1058 {
1059 /* For 3 word instructions only */
1060 if (instruction->size == 3)
1061 {
1062 iaddr = imem_addr ((uint32)PC + 2);
1063 mcode = (mcode << 16) | get_longword( iaddr );
1064 }
1065
1066 do_run(instruction, mcode);
1067 }
1068
1069 /* If the PC of the current instruction matches RPT_E then
1070 schedule a branch to the loop start. If one of those
1071 instructions happens to be a branch, than that instruction
1072 will be ignored */
1073 if (!State.pc_changed)
1074 {
1075 switch (instruction->size)
1076 {
1077 case 1:
1078 SET_PC (PC + 2); /* For 1 word instructions */
1079 break;
1080 case 2:
1081 SET_PC (PC + 4); /* For 2 word instructions */
1082 break;
1083 case 3:
1084 SET_PC (PC + 6); /* For 3 word instructions */
1085 break;
1086 default: break;
1087 }
1088
1089 }
1090
1091 /* Check for a breakpoint trap on this instruction. This
1092 overrides any pending branches or loops */
1093#if 0
1094 if (PSR_DB && PC == DBS)
1095 {
1096 SET_BPC (PC);
1097 SET_BPSR (PSR);
1098 SET_PC (SDBT_VECTOR_START);
1099 }
1100#endif
1101
1102 /* Writeback all the DATA / PC changes */
1103 SLOT_FLUSH ();
1104
1105#ifdef NEED_UI_LOOP_HOOK
1106 if (deprecated_ui_loop_hook != NULL && ui_loop_hook_counter-- < 0)
1107 {
1108 ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
1109 deprecated_ui_loop_hook (0);
1110 }
1111#endif /* NEED_UI_LOOP_HOOK */
1112 }
1113 while ( !State.exception && !stop_simulator);
1114
1115 if (step && !State.exception)
1116 State.exception = SIGTRAP;
1117}
1118
1119void
1120sim_set_trace (void)
1121{
1122#ifdef DEBUG
1123 cr16_debug = DEBUG;
1124#endif
1125}
1126
1127void
1128sim_info (SIM_DESC sd, int verbose)
1129{
1130 char buf1[40];
1131 char buf2[40];
1132 char buf3[40];
1133 char buf4[40];
1134 char buf5[40];
1135#if 0
1136 unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
1137 unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ];
1138 unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ];
1139 unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ];
1140 unsigned long left_total = left + left_parallel + left_cond + left_nops;
1141
1142 unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
1143 unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ];
1144 unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
1145 unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
1146 unsigned long right_total = right + right_parallel + right_cond + right_nops;
1147
1148 unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ];
1149 unsigned long ins_long = ins_type_counters[ (int)INS_LONG ];
1150 unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ];
1151 unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ];
1152 unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ];
1153 unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ];
1154 unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ];
1155 unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ];
1156 unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ];
1157 unsigned long total = (unknown + left_total + right_total + ins_long);
1158
1159 int size = strlen (add_commas (buf1, sizeof (buf1), total));
1160 int parallel_size = strlen (add_commas (buf1, sizeof (buf1),
1161 (left_parallel > right_parallel) ? left_parallel : right_parallel));
1162 int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
1163 int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
1164 int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
1165
1166 (*cr16_callback->printf_filtered) (cr16_callback,
1167 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1168 size, add_commas (buf1, sizeof (buf1), left_total),
1169 normal_size, add_commas (buf2, sizeof (buf2), left),
1170 parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
1171 cond_size, add_commas (buf4, sizeof (buf4), left_cond),
1172 nop_size, add_commas (buf5, sizeof (buf5), left_nops));
1173
1174 (*cr16_callback->printf_filtered) (cr16_callback,
1175 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1176 size, add_commas (buf1, sizeof (buf1), right_total),
1177 normal_size, add_commas (buf2, sizeof (buf2), right),
1178 parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
1179 cond_size, add_commas (buf4, sizeof (buf4), right_cond),
1180 nop_size, add_commas (buf5, sizeof (buf5), right_nops));
1181
1182 if (ins_long)
1183 (*cr16_callback->printf_filtered) (cr16_callback,
1184 "executed %*s long instruction(s)\n",
1185 size, add_commas (buf1, sizeof (buf1), ins_long));
1186
1187 if (parallel)
1188 (*cr16_callback->printf_filtered) (cr16_callback,
1189 "executed %*s parallel instruction(s)\n",
1190 size, add_commas (buf1, sizeof (buf1), parallel));
1191
1192 if (leftright)
1193 (*cr16_callback->printf_filtered) (cr16_callback,
1194 "executed %*s instruction(s) encoded L->R\n",
1195 size, add_commas (buf1, sizeof (buf1), leftright));
1196
1197 if (rightleft)
1198 (*cr16_callback->printf_filtered) (cr16_callback,
1199 "executed %*s instruction(s) encoded R->L\n",
1200 size, add_commas (buf1, sizeof (buf1), rightleft));
1201
1202 if (unknown)
1203 (*cr16_callback->printf_filtered) (cr16_callback,
1204 "executed %*s unknown instruction(s)\n",
1205 size, add_commas (buf1, sizeof (buf1), unknown));
1206
1207 if (cond_true)
1208 (*cr16_callback->printf_filtered) (cr16_callback,
1209 "executed %*s instruction(s) due to EXExxx condition being true\n",
1210 size, add_commas (buf1, sizeof (buf1), cond_true));
1211
1212 if (cond_false)
1213 (*cr16_callback->printf_filtered) (cr16_callback,
1214 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1215 size, add_commas (buf1, sizeof (buf1), cond_false));
1216
1217 if (cond_jump)
1218 (*cr16_callback->printf_filtered) (cr16_callback,
1219 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1220 size, add_commas (buf1, sizeof (buf1), cond_jump));
1221
1222 (*cr16_callback->printf_filtered) (cr16_callback,
1223 "executed %*s cycle(s)\n",
1224 size, add_commas (buf1, sizeof (buf1), cycles));
1225
1226 (*cr16_callback->printf_filtered) (cr16_callback,
1227 "executed %*s total instructions\n",
1228 size, add_commas (buf1, sizeof (buf1), total));
1229#endif
1230}
1231
1232SIM_RC
1233sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
1234{
1235 bfd_vma start_address;
1236
1237 /* reset all state information */
1238 memset (&State.regs, 0, (int)&State.mem - (int)&State.regs);
1239
1240 /* There was a hack here to copy the values of argc and argv into r0
1241 and r1. The values were also saved into some high memory that
1242 won't be overwritten by the stack (0x7C00). The reason for doing
1243 this was to allow the 'run' program to accept arguments. Without
1244 the hack, this is not possible anymore. If the simulator is run
1245 from the debugger, arguments cannot be passed in, so this makes
1246 no difference. */
1247
1248 /* set PC */
1249 if (abfd != NULL)
1250 start_address = bfd_get_start_address (abfd);
1251 else
1252 start_address = 0x0;
1253#ifdef DEBUG
1254 if (cr16_debug)
1255 (*cr16_callback->printf_filtered) (cr16_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address);
1256#endif
1257 SET_CREG (PC_CR, start_address);
1258
1259 SLOT_FLUSH ();
1260 return SIM_RC_OK;
1261}
1262
1263
1264void
1265sim_set_callbacks (p)
1266 host_callback *p;
1267{
1268 cr16_callback = p;
1269}
1270
1271void
1272sim_stop_reason (sd, reason, sigrc)
1273 SIM_DESC sd;
1274 enum sim_stop *reason;
1275 int *sigrc;
1276{
1277/* (*cr16_callback->printf_filtered) (cr16_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
1278
1279 switch (State.exception)
1280 {
1281 case SIG_CR16_STOP: /* stop instruction */
1282 *reason = sim_stopped;
1283 *sigrc = 0;
1284 break;
1285
1286 case SIG_CR16_EXIT: /* exit trap */
1287 *reason = sim_exited;
1288 *sigrc = GPR (2);
1289 break;
1290
1291 case SIG_CR16_BUS:
1292 *reason = sim_stopped;
1293 *sigrc = TARGET_SIGNAL_BUS;
1294 break;
1295//
1296// case SIG_CR16_IAD:
1297// *reason = sim_stopped;
1298// *sigrc = TARGET_SIGNAL_IAD;
1299// break;
1300
1301 default: /* some signal */
1302 *reason = sim_stopped;
1303 if (stop_simulator && !State.exception)
1304 *sigrc = TARGET_SIGNAL_INT;
1305 else
1306 *sigrc = State.exception;
1307 break;
1308 }
1309
1310 stop_simulator = 0;
1311}
1312
1313int
1314sim_fetch_register (sd, rn, memory, length)
1315 SIM_DESC sd;
1316 int rn;
1317 unsigned char *memory;
1318 int length;
1319{
1320 int size;
1321 switch ((enum sim_cr16_regs) rn)
1322 {
1323 case SIM_CR16_R0_REGNUM:
1324 case SIM_CR16_R1_REGNUM:
1325 case SIM_CR16_R2_REGNUM:
1326 case SIM_CR16_R3_REGNUM:
1327 case SIM_CR16_R4_REGNUM:
1328 case SIM_CR16_R5_REGNUM:
1329 case SIM_CR16_R6_REGNUM:
1330 case SIM_CR16_R7_REGNUM:
1331 case SIM_CR16_R8_REGNUM:
1332 case SIM_CR16_R9_REGNUM:
1333 case SIM_CR16_R10_REGNUM:
1334 case SIM_CR16_R11_REGNUM:
1335 WRITE_16 (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1336 size = 2;
1337 break;
1338 case SIM_CR16_R12_REGNUM:
1339 case SIM_CR16_R13_REGNUM:
1340 case SIM_CR16_R14_REGNUM:
1341 case SIM_CR16_R15_REGNUM:
1342 //WRITE_32 (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1343 write_longword (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1344 size = 4;
1345 break;
1346 case SIM_CR16_PC_REGNUM:
1347 case SIM_CR16_ISP_REGNUM:
1348 case SIM_CR16_USP_REGNUM:
1349 case SIM_CR16_INTBASE_REGNUM:
1350 case SIM_CR16_PSR_REGNUM:
1351 case SIM_CR16_CFG_REGNUM:
1352 case SIM_CR16_DBS_REGNUM:
1353 case SIM_CR16_DCR_REGNUM:
1354 case SIM_CR16_DSR_REGNUM:
1355 case SIM_CR16_CAR0_REGNUM:
1356 case SIM_CR16_CAR1_REGNUM:
1357 //WRITE_32 (memory, CREG (rn - SIM_CR16_PC_REGNUM));
1358 write_longword (memory, CREG (rn - SIM_CR16_PC_REGNUM));
1359 size = 4;
1360 break;
1361 default:
1362 size = 0;
1363 break;
1364 }
1365 return size;
1366}
1367
1368int
1369sim_store_register (sd, rn, memory, length)
1370 SIM_DESC sd;
1371 int rn;
1372 unsigned char *memory;
1373 int length;
1374{
1375 int size;
1376 switch ((enum sim_cr16_regs) rn)
1377 {
1378 case SIM_CR16_R0_REGNUM:
1379 case SIM_CR16_R1_REGNUM:
1380 case SIM_CR16_R2_REGNUM:
1381 case SIM_CR16_R3_REGNUM:
1382 case SIM_CR16_R4_REGNUM:
1383 case SIM_CR16_R5_REGNUM:
1384 case SIM_CR16_R6_REGNUM:
1385 case SIM_CR16_R7_REGNUM:
1386 case SIM_CR16_R8_REGNUM:
1387 case SIM_CR16_R9_REGNUM:
1388 case SIM_CR16_R10_REGNUM:
1389 case SIM_CR16_R11_REGNUM:
1390 SET_GPR (rn - SIM_CR16_R0_REGNUM, READ_16 (memory));
1391 size = 2;
1392 break;
1393 case SIM_CR16_R12_REGNUM:
1394 case SIM_CR16_R13_REGNUM:
1395 case SIM_CR16_R14_REGNUM:
1396 case SIM_CR16_R15_REGNUM:
1397 SET_GPR32 (rn - SIM_CR16_R0_REGNUM, get_longword (memory));
1398 size = 4;
1399 break;
1400 case SIM_CR16_PC_REGNUM:
1401 case SIM_CR16_ISP_REGNUM:
1402 case SIM_CR16_USP_REGNUM:
1403 case SIM_CR16_INTBASE_REGNUM:
1404 case SIM_CR16_PSR_REGNUM:
1405 case SIM_CR16_CFG_REGNUM:
1406 case SIM_CR16_DBS_REGNUM:
1407 case SIM_CR16_DCR_REGNUM:
1408 case SIM_CR16_DSR_REGNUM:
1409 case SIM_CR16_CAR0_REGNUM:
1410 case SIM_CR16_CAR1_REGNUM:
1411 SET_CREG (rn - SIM_CR16_PC_REGNUM, get_longword (memory));
1412 size = 4;
1413 break;
1414 default:
1415 size = 0;
1416 break;
1417 }
1418 SLOT_FLUSH ();
1419 return size;
1420}
1421
1422
1423void
1424sim_do_command (sd, cmd)
1425 SIM_DESC sd;
1426 char *cmd;
1427{
1428 (*cr16_callback->printf_filtered) (cr16_callback, "sim_do_command: %s\n",cmd);
1429}
1430
1431SIM_RC
1432sim_load (SIM_DESC sd, char *prog, struct bfd *abfd, int from_tty)
1433{
1434 extern bfd *sim_load_file (); /* ??? Don't know where this should live. */
1435
1436 if (prog_bfd != NULL && prog_bfd_was_opened_p)
1437 {
1438 bfd_close (prog_bfd);
1439 prog_bfd_was_opened_p = 0;
1440 }
1441 prog_bfd = sim_load_file (sd, myname, cr16_callback, prog, abfd,
1442 sim_kind == SIM_OPEN_DEBUG,
1443 1/*LMA*/, sim_write);
1444 if (prog_bfd == NULL)
1445 return SIM_RC_FAIL;
1446 prog_bfd_was_opened_p = abfd == NULL;
1447 return SIM_RC_OK;
1448}
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