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Commit | Line | Data |
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6df01ab8 MF |
1 | /* This must come before any other includes. */ |
2 | #include "defs.h" | |
3 | ||
11558abc | 4 | #include <inttypes.h> |
c906108c | 5 | #include <signal.h> |
c906108c | 6 | #include "bfd.h" |
df68e12b MF |
7 | #include "sim/callback.h" |
8 | #include "sim/sim.h" | |
c906108c | 9 | |
541ebcee MF |
10 | #include "sim-main.h" |
11 | #include "sim-options.h" | |
12 | ||
b91b96f4 | 13 | #include "gdb/sim-d10v.h" |
aba6488e | 14 | #include "gdb/signals.h" |
c906108c | 15 | |
d0a5a356 | 16 | #include <string.h> |
d0a5a356 | 17 | #include <stdlib.h> |
e7e40ced | 18 | #include <assert.h> |
d0a5a356 | 19 | |
c906108c SS |
20 | enum _leftright { LEFT_FIRST, RIGHT_FIRST }; |
21 | ||
7eb99e5e MF |
22 | struct _state State; |
23 | ||
c906108c | 24 | int d10v_debug; |
cff3e48b JM |
25 | |
26 | /* Set this to true to get the previous segment layout. */ | |
27 | ||
28 | int old_segment_mapping; | |
29 | ||
c906108c SS |
30 | unsigned long ins_type_counters[ (int)INS_MAX ]; |
31 | ||
32 | uint16 OP[4]; | |
33 | ||
bdca5ee4 | 34 | static long hash (long insn, int format); |
67954606 | 35 | static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32 ins, int size); |
bdca5ee4 | 36 | static void get_operands (struct simops *s, uint32 ins); |
67954606 MF |
37 | static void do_long (SIM_DESC, SIM_CPU *, uint32 ins); |
38 | static void do_2_short (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2, enum _leftright leftright); | |
39 | static void do_parallel (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2); | |
bdca5ee4 | 40 | static char *add_commas (char *buf, int sizeof_buf, unsigned long value); |
67954606 | 41 | static INLINE uint8 *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr); |
c906108c | 42 | |
c906108c SS |
43 | #define MAX_HASH 63 |
44 | struct hash_entry | |
45 | { | |
46 | struct hash_entry *next; | |
47 | uint32 opcode; | |
48 | uint32 mask; | |
49 | int size; | |
50 | struct simops *ops; | |
51 | }; | |
52 | ||
53 | struct hash_entry hash_table[MAX_HASH+1]; | |
54 | ||
55 | INLINE static long | |
11558abc | 56 | hash (long insn, int format) |
c906108c SS |
57 | { |
58 | if (format & LONG_OPCODE) | |
59 | return ((insn & 0x3F000000) >> 24); | |
60 | else | |
61 | return((insn & 0x7E00) >> 9); | |
62 | } | |
63 | ||
64 | INLINE static struct hash_entry * | |
67954606 | 65 | lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32 ins, int size) |
c906108c SS |
66 | { |
67 | struct hash_entry *h; | |
68 | ||
69 | if (size) | |
70 | h = &hash_table[(ins & 0x3F000000) >> 24]; | |
71 | else | |
72 | h = &hash_table[(ins & 0x7E00) >> 9]; | |
73 | ||
74 | while ((ins & h->mask) != h->opcode || h->size != size) | |
75 | { | |
76 | if (h->next == NULL) | |
aadc1740 | 77 | sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGILL); |
c906108c SS |
78 | h = h->next; |
79 | } | |
80 | return (h); | |
81 | } | |
82 | ||
83 | INLINE static void | |
84 | get_operands (struct simops *s, uint32 ins) | |
85 | { | |
86 | int i, shift, bits, flags; | |
87 | uint32 mask; | |
88 | for (i=0; i < s->numops; i++) | |
89 | { | |
90 | shift = s->operands[3*i]; | |
91 | bits = s->operands[3*i+1]; | |
92 | flags = s->operands[3*i+2]; | |
93 | mask = 0x7FFFFFFF >> (31 - bits); | |
94 | OP[i] = (ins >> shift) & mask; | |
95 | } | |
96 | /* FIXME: for tracing, update values that need to be updated each | |
97 | instruction decode cycle */ | |
98 | State.trace.psw = PSW; | |
99 | } | |
100 | ||
c906108c | 101 | static void |
67954606 | 102 | do_long (SIM_DESC sd, SIM_CPU *cpu, uint32 ins) |
c906108c SS |
103 | { |
104 | struct hash_entry *h; | |
105 | #ifdef DEBUG | |
106 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
e9b0081f | 107 | sim_io_printf (sd, "do_long 0x%x\n", ins); |
c906108c | 108 | #endif |
67954606 | 109 | h = lookup_hash (sd, cpu, ins, 1); |
4ce44c66 JM |
110 | if (h == NULL) |
111 | return; | |
c906108c SS |
112 | get_operands (h->ops, ins); |
113 | State.ins_type = INS_LONG; | |
114 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 115 | (h->ops->func) (sd, cpu); |
c906108c SS |
116 | } |
117 | ||
118 | static void | |
67954606 | 119 | do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2, enum _leftright leftright) |
c906108c SS |
120 | { |
121 | struct hash_entry *h; | |
122 | enum _ins_type first, second; | |
123 | ||
124 | #ifdef DEBUG | |
125 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
e9b0081f MF |
126 | sim_io_printf (sd, "do_2_short 0x%x (%s) -> 0x%x\n", ins1, |
127 | leftright ? "left" : "right", ins2); | |
c906108c SS |
128 | #endif |
129 | ||
130 | if (leftright == LEFT_FIRST) | |
131 | { | |
132 | first = INS_LEFT; | |
133 | second = INS_RIGHT; | |
134 | ins_type_counters[ (int)INS_LEFTRIGHT ]++; | |
135 | } | |
136 | else | |
137 | { | |
138 | first = INS_RIGHT; | |
139 | second = INS_LEFT; | |
140 | ins_type_counters[ (int)INS_RIGHTLEFT ]++; | |
141 | } | |
142 | ||
143 | /* Issue the first instruction */ | |
67954606 | 144 | h = lookup_hash (sd, cpu, ins1, 0); |
4ce44c66 JM |
145 | if (h == NULL) |
146 | return; | |
c906108c SS |
147 | get_operands (h->ops, ins1); |
148 | State.ins_type = first; | |
149 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 150 | (h->ops->func) (sd, cpu); |
c906108c SS |
151 | |
152 | /* Issue the second instruction (if the PC hasn't changed) */ | |
aadc1740 | 153 | if (!State.pc_changed) |
c906108c SS |
154 | { |
155 | /* finish any existing instructions */ | |
156 | SLOT_FLUSH (); | |
67954606 | 157 | h = lookup_hash (sd, cpu, ins2, 0); |
4ce44c66 JM |
158 | if (h == NULL) |
159 | return; | |
c906108c SS |
160 | get_operands (h->ops, ins2); |
161 | State.ins_type = second; | |
162 | ins_type_counters[ (int)State.ins_type ]++; | |
163 | ins_type_counters[ (int)INS_CYCLES ]++; | |
67954606 | 164 | (h->ops->func) (sd, cpu); |
c906108c | 165 | } |
aadc1740 | 166 | else |
c906108c SS |
167 | ins_type_counters[ (int)INS_COND_JUMP ]++; |
168 | } | |
169 | ||
170 | static void | |
67954606 | 171 | do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2) |
c906108c SS |
172 | { |
173 | struct hash_entry *h1, *h2; | |
174 | #ifdef DEBUG | |
175 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
e9b0081f | 176 | sim_io_printf (sd, "do_parallel 0x%x || 0x%x\n", ins1, ins2); |
c906108c SS |
177 | #endif |
178 | ins_type_counters[ (int)INS_PARALLEL ]++; | |
67954606 | 179 | h1 = lookup_hash (sd, cpu, ins1, 0); |
4ce44c66 JM |
180 | if (h1 == NULL) |
181 | return; | |
67954606 | 182 | h2 = lookup_hash (sd, cpu, ins2, 0); |
4ce44c66 JM |
183 | if (h2 == NULL) |
184 | return; | |
c906108c SS |
185 | |
186 | if (h1->ops->exec_type == PARONLY) | |
187 | { | |
188 | get_operands (h1->ops, ins1); | |
189 | State.ins_type = INS_LEFT_COND_TEST; | |
190 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 191 | (h1->ops->func) (sd, cpu); |
c906108c SS |
192 | if (State.exe) |
193 | { | |
194 | ins_type_counters[ (int)INS_COND_TRUE ]++; | |
195 | get_operands (h2->ops, ins2); | |
196 | State.ins_type = INS_RIGHT_COND_EXE; | |
197 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 198 | (h2->ops->func) (sd, cpu); |
c906108c SS |
199 | } |
200 | else | |
201 | ins_type_counters[ (int)INS_COND_FALSE ]++; | |
202 | } | |
203 | else if (h2->ops->exec_type == PARONLY) | |
204 | { | |
205 | get_operands (h2->ops, ins2); | |
206 | State.ins_type = INS_RIGHT_COND_TEST; | |
207 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 208 | (h2->ops->func) (sd, cpu); |
c906108c SS |
209 | if (State.exe) |
210 | { | |
211 | ins_type_counters[ (int)INS_COND_TRUE ]++; | |
212 | get_operands (h1->ops, ins1); | |
213 | State.ins_type = INS_LEFT_COND_EXE; | |
214 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 215 | (h1->ops->func) (sd, cpu); |
c906108c SS |
216 | } |
217 | else | |
218 | ins_type_counters[ (int)INS_COND_FALSE ]++; | |
219 | } | |
220 | else | |
221 | { | |
222 | get_operands (h1->ops, ins1); | |
223 | State.ins_type = INS_LEFT_PARALLEL; | |
224 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 225 | (h1->ops->func) (sd, cpu); |
aadc1740 MF |
226 | get_operands (h2->ops, ins2); |
227 | State.ins_type = INS_RIGHT_PARALLEL; | |
228 | ins_type_counters[ (int)State.ins_type ]++; | |
229 | (h2->ops->func) (sd, cpu); | |
c906108c SS |
230 | } |
231 | } | |
232 | ||
233 | static char * | |
11558abc | 234 | add_commas (char *buf, int sizeof_buf, unsigned long value) |
c906108c SS |
235 | { |
236 | int comma = 3; | |
237 | char *endbuf = buf + sizeof_buf - 1; | |
238 | ||
239 | *--endbuf = '\0'; | |
240 | do { | |
241 | if (comma-- == 0) | |
242 | { | |
243 | *--endbuf = ','; | |
244 | comma = 2; | |
245 | } | |
246 | ||
247 | *--endbuf = (value % 10) + '0'; | |
248 | } while ((value /= 10) != 0); | |
249 | ||
250 | return endbuf; | |
251 | } | |
252 | ||
aadc1740 | 253 | static void |
11558abc | 254 | sim_size (int power) |
c906108c SS |
255 | { |
256 | int i; | |
4ce44c66 | 257 | for (i = 0; i < IMEM_SEGMENTS; i++) |
c906108c | 258 | { |
4ce44c66 JM |
259 | if (State.mem.insn[i]) |
260 | free (State.mem.insn[i]); | |
c906108c | 261 | } |
4ce44c66 | 262 | for (i = 0; i < DMEM_SEGMENTS; i++) |
c906108c | 263 | { |
4ce44c66 JM |
264 | if (State.mem.data[i]) |
265 | free (State.mem.data[i]); | |
c906108c | 266 | } |
4ce44c66 JM |
267 | for (i = 0; i < UMEM_SEGMENTS; i++) |
268 | { | |
269 | if (State.mem.unif[i]) | |
270 | free (State.mem.unif[i]); | |
271 | } | |
272 | /* Always allocate dmem segment 0. This contains the IMAP and DMAP | |
273 | registers. */ | |
274 | State.mem.data[0] = calloc (1, SEGMENT_SIZE); | |
275 | } | |
276 | ||
277 | /* For tracing - leave info on last access around. */ | |
278 | static char *last_segname = "invalid"; | |
279 | static char *last_from = "invalid"; | |
280 | static char *last_to = "invalid"; | |
281 | ||
282 | enum | |
283 | { | |
284 | IMAP0_OFFSET = 0xff00, | |
285 | DMAP0_OFFSET = 0xff08, | |
286 | DMAP2_SHADDOW = 0xff04, | |
287 | DMAP2_OFFSET = 0xff0c | |
288 | }; | |
289 | ||
290 | static void | |
67954606 | 291 | set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value) |
4ce44c66 | 292 | { |
67954606 | 293 | uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA |
4ce44c66 JM |
294 | + DMAP0_OFFSET + 2 * reg_nr); |
295 | WRITE_16 (raw, value); | |
c906108c | 296 | #ifdef DEBUG |
4ce44c66 | 297 | if ((d10v_debug & DEBUG_MEMORY)) |
c906108c | 298 | { |
e9b0081f | 299 | sim_io_printf (sd, "mem: dmap%d=0x%04lx\n", reg_nr, value); |
4ce44c66 JM |
300 | } |
301 | #endif | |
302 | } | |
c906108c | 303 | |
4ce44c66 | 304 | static unsigned long |
67954606 | 305 | dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr) |
4ce44c66 | 306 | { |
67954606 | 307 | uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA |
4ce44c66 JM |
308 | + DMAP0_OFFSET + 2 * reg_nr); |
309 | return READ_16 (raw); | |
310 | } | |
311 | ||
312 | static void | |
67954606 | 313 | set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value) |
4ce44c66 | 314 | { |
67954606 | 315 | uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA |
4ce44c66 JM |
316 | + IMAP0_OFFSET + 2 * reg_nr); |
317 | WRITE_16 (raw, value); | |
318 | #ifdef DEBUG | |
319 | if ((d10v_debug & DEBUG_MEMORY)) | |
320 | { | |
e9b0081f | 321 | sim_io_printf (sd, "mem: imap%d=0x%04lx\n", reg_nr, value); |
c906108c SS |
322 | } |
323 | #endif | |
324 | } | |
325 | ||
4ce44c66 | 326 | static unsigned long |
67954606 | 327 | imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr) |
4ce44c66 | 328 | { |
67954606 | 329 | uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA |
4ce44c66 JM |
330 | + IMAP0_OFFSET + 2 * reg_nr); |
331 | return READ_16 (raw); | |
332 | } | |
c906108c | 333 | |
4ce44c66 JM |
334 | enum |
335 | { | |
336 | HELD_SPI_IDX = 0, | |
337 | HELD_SPU_IDX = 1 | |
338 | }; | |
339 | ||
340 | static unsigned long | |
341 | spu_register (void) | |
c906108c | 342 | { |
4ce44c66 JM |
343 | if (PSW_SM) |
344 | return GPR (SP_IDX); | |
345 | else | |
346 | return HELD_SP (HELD_SPU_IDX); | |
347 | } | |
c906108c | 348 | |
4ce44c66 JM |
349 | static unsigned long |
350 | spi_register (void) | |
351 | { | |
352 | if (!PSW_SM) | |
353 | return GPR (SP_IDX); | |
354 | else | |
355 | return HELD_SP (HELD_SPI_IDX); | |
356 | } | |
357 | ||
358 | static void | |
359 | set_spi_register (unsigned long value) | |
360 | { | |
361 | if (!PSW_SM) | |
362 | SET_GPR (SP_IDX, value); | |
363 | SET_HELD_SP (HELD_SPI_IDX, value); | |
364 | } | |
365 | ||
366 | static void | |
367 | set_spu_register (unsigned long value) | |
368 | { | |
369 | if (PSW_SM) | |
370 | SET_GPR (SP_IDX, value); | |
371 | SET_HELD_SP (HELD_SPU_IDX, value); | |
372 | } | |
373 | ||
374 | /* Given a virtual address in the DMAP address space, translate it | |
375 | into a physical address. */ | |
376 | ||
6637a426 | 377 | static unsigned long |
67954606 MF |
378 | sim_d10v_translate_dmap_addr (SIM_DESC sd, |
379 | SIM_CPU *cpu, | |
380 | unsigned long offset, | |
4ce44c66 JM |
381 | int nr_bytes, |
382 | unsigned long *phys, | |
f6684c31 | 383 | void *regcache, |
67954606 MF |
384 | unsigned long (*dmap_register) (SIM_DESC, |
385 | SIM_CPU *, | |
386 | void *regcache, | |
f6684c31 | 387 | int reg_nr)) |
4ce44c66 JM |
388 | { |
389 | short map; | |
390 | int regno; | |
391 | last_from = "logical-data"; | |
392 | if (offset >= DMAP_BLOCK_SIZE * SIM_D10V_NR_DMAP_REGS) | |
c906108c | 393 | { |
4ce44c66 JM |
394 | /* Logical address out side of data segments, not supported */ |
395 | return 0; | |
396 | } | |
397 | regno = (offset / DMAP_BLOCK_SIZE); | |
398 | offset = (offset % DMAP_BLOCK_SIZE); | |
399 | if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE) | |
400 | { | |
401 | /* Don't cross a BLOCK boundary */ | |
402 | nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE); | |
403 | } | |
67954606 | 404 | map = dmap_register (sd, cpu, regcache, regno); |
4ce44c66 JM |
405 | if (regno == 3) |
406 | { | |
407 | /* Always maps to data memory */ | |
408 | int iospi = (offset / 0x1000) % 4; | |
409 | int iosp = (map >> (4 * (3 - iospi))) % 0x10; | |
410 | last_to = "io-space"; | |
411 | *phys = (SIM_D10V_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset); | |
412 | } | |
413 | else | |
414 | { | |
415 | int sp = ((map & 0x3000) >> 12); | |
416 | int segno = (map & 0x3ff); | |
417 | switch (sp) | |
c906108c | 418 | { |
4ce44c66 JM |
419 | case 0: /* 00: Unified memory */ |
420 | *phys = SIM_D10V_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset; | |
421 | last_to = "unified"; | |
422 | break; | |
423 | case 1: /* 01: Instruction Memory */ | |
424 | *phys = SIM_D10V_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset; | |
425 | last_to = "chip-insn"; | |
426 | break; | |
427 | case 2: /* 10: Internal data memory */ | |
428 | *phys = SIM_D10V_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset; | |
429 | last_to = "chip-data"; | |
430 | break; | |
431 | case 3: /* 11: Reserved */ | |
432 | return 0; | |
c906108c SS |
433 | } |
434 | } | |
4ce44c66 JM |
435 | return nr_bytes; |
436 | } | |
c906108c | 437 | |
4ce44c66 JM |
438 | /* Given a virtual address in the IMAP address space, translate it |
439 | into a physical address. */ | |
cff3e48b | 440 | |
6637a426 | 441 | static unsigned long |
67954606 MF |
442 | sim_d10v_translate_imap_addr (SIM_DESC sd, |
443 | SIM_CPU *cpu, | |
444 | unsigned long offset, | |
4ce44c66 JM |
445 | int nr_bytes, |
446 | unsigned long *phys, | |
f6684c31 | 447 | void *regcache, |
67954606 MF |
448 | unsigned long (*imap_register) (SIM_DESC, |
449 | SIM_CPU *, | |
450 | void *regcache, | |
f6684c31 | 451 | int reg_nr)) |
4ce44c66 JM |
452 | { |
453 | short map; | |
454 | int regno; | |
455 | int sp; | |
456 | int segno; | |
457 | last_from = "logical-insn"; | |
458 | if (offset >= (IMAP_BLOCK_SIZE * SIM_D10V_NR_IMAP_REGS)) | |
459 | { | |
460 | /* Logical address outside of IMAP segments, not supported */ | |
461 | return 0; | |
462 | } | |
463 | regno = (offset / IMAP_BLOCK_SIZE); | |
464 | offset = (offset % IMAP_BLOCK_SIZE); | |
465 | if (offset + nr_bytes > IMAP_BLOCK_SIZE) | |
466 | { | |
467 | /* Don't cross a BLOCK boundary */ | |
468 | nr_bytes = IMAP_BLOCK_SIZE - offset; | |
469 | } | |
67954606 | 470 | map = imap_register (sd, cpu, regcache, regno); |
4ce44c66 JM |
471 | sp = (map & 0x3000) >> 12; |
472 | segno = (map & 0x007f); | |
473 | switch (sp) | |
474 | { | |
475 | case 0: /* 00: unified memory */ | |
476 | *phys = SIM_D10V_MEMORY_UNIFIED + (segno << 17) + offset; | |
477 | last_to = "unified"; | |
478 | break; | |
479 | case 1: /* 01: instruction memory */ | |
480 | *phys = SIM_D10V_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset; | |
481 | last_to = "chip-insn"; | |
482 | break; | |
483 | case 2: /*10*/ | |
484 | /* Reserved. */ | |
485 | return 0; | |
486 | case 3: /* 11: for testing - instruction memory */ | |
487 | offset = (offset % 0x800); | |
488 | *phys = SIM_D10V_MEMORY_INSN + offset; | |
489 | if (offset + nr_bytes > 0x800) | |
490 | /* don't cross VM boundary */ | |
491 | nr_bytes = 0x800 - offset; | |
492 | last_to = "test-insn"; | |
493 | break; | |
494 | } | |
495 | return nr_bytes; | |
496 | } | |
cff3e48b | 497 | |
6637a426 | 498 | static unsigned long |
67954606 MF |
499 | sim_d10v_translate_addr (SIM_DESC sd, |
500 | SIM_CPU *cpu, | |
501 | unsigned long memaddr, | |
4ce44c66 JM |
502 | int nr_bytes, |
503 | unsigned long *targ_addr, | |
f6684c31 | 504 | void *regcache, |
67954606 MF |
505 | unsigned long (*dmap_register) (SIM_DESC, |
506 | SIM_CPU *, | |
507 | void *regcache, | |
f6684c31 | 508 | int reg_nr), |
67954606 MF |
509 | unsigned long (*imap_register) (SIM_DESC, |
510 | SIM_CPU *, | |
511 | void *regcache, | |
f6684c31 | 512 | int reg_nr)) |
4ce44c66 JM |
513 | { |
514 | unsigned long phys; | |
515 | unsigned long seg; | |
516 | unsigned long off; | |
cff3e48b | 517 | |
4ce44c66 JM |
518 | last_from = "unknown"; |
519 | last_to = "unknown"; | |
cff3e48b | 520 | |
4ce44c66 JM |
521 | seg = (memaddr >> 24); |
522 | off = (memaddr & 0xffffffL); | |
c906108c | 523 | |
cff3e48b JM |
524 | /* However, if we've asked to use the previous generation of segment |
525 | mapping, rearrange the segments as follows. */ | |
526 | ||
527 | if (old_segment_mapping) | |
528 | { | |
4ce44c66 | 529 | switch (seg) |
cff3e48b JM |
530 | { |
531 | case 0x00: /* DMAP translated memory */ | |
4ce44c66 | 532 | seg = 0x10; |
cff3e48b JM |
533 | break; |
534 | case 0x01: /* IMAP translated memory */ | |
4ce44c66 | 535 | seg = 0x11; |
cff3e48b JM |
536 | break; |
537 | case 0x10: /* On-chip data memory */ | |
4ce44c66 | 538 | seg = 0x02; |
cff3e48b JM |
539 | break; |
540 | case 0x11: /* On-chip insn memory */ | |
4ce44c66 | 541 | seg = 0x01; |
cff3e48b JM |
542 | break; |
543 | case 0x12: /* Unified memory */ | |
4ce44c66 | 544 | seg = 0x00; |
cff3e48b JM |
545 | break; |
546 | } | |
547 | } | |
548 | ||
4ce44c66 | 549 | switch (seg) |
c906108c | 550 | { |
4ce44c66 JM |
551 | case 0x00: /* Physical unified memory */ |
552 | last_from = "phys-unified"; | |
553 | last_to = "unified"; | |
554 | phys = SIM_D10V_MEMORY_UNIFIED + off; | |
555 | if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) | |
556 | nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); | |
557 | break; | |
c906108c | 558 | |
4ce44c66 JM |
559 | case 0x01: /* Physical instruction memory */ |
560 | last_from = "phys-insn"; | |
561 | last_to = "chip-insn"; | |
562 | phys = SIM_D10V_MEMORY_INSN + off; | |
563 | if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) | |
564 | nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); | |
565 | break; | |
c906108c | 566 | |
4ce44c66 JM |
567 | case 0x02: /* Physical data memory segment */ |
568 | last_from = "phys-data"; | |
569 | last_to = "chip-data"; | |
570 | phys = SIM_D10V_MEMORY_DATA + off; | |
571 | if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) | |
572 | nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); | |
573 | break; | |
574 | ||
575 | case 0x10: /* in logical data address segment */ | |
67954606 MF |
576 | nr_bytes = sim_d10v_translate_dmap_addr (sd, cpu, off, nr_bytes, &phys, |
577 | regcache, dmap_register); | |
4ce44c66 JM |
578 | break; |
579 | ||
580 | case 0x11: /* in logical instruction address segment */ | |
67954606 MF |
581 | nr_bytes = sim_d10v_translate_imap_addr (sd, cpu, off, nr_bytes, &phys, |
582 | regcache, imap_register); | |
4ce44c66 JM |
583 | break; |
584 | ||
585 | default: | |
586 | return 0; | |
587 | } | |
588 | ||
589 | *targ_addr = phys; | |
590 | return nr_bytes; | |
591 | } | |
592 | ||
593 | /* Return a pointer into the raw buffer designated by phys_addr. It | |
594 | is assumed that the client has already ensured that the access | |
595 | isn't going to cross a segment boundary. */ | |
596 | ||
597 | uint8 * | |
67954606 | 598 | map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr) |
4ce44c66 JM |
599 | { |
600 | uint8 **memory; | |
601 | uint8 *raw; | |
602 | unsigned offset; | |
603 | int segment = ((phys_addr >> 24) & 0xff); | |
604 | ||
605 | switch (segment) | |
606 | { | |
607 | ||
608 | case 0x00: /* Unified memory */ | |
c906108c | 609 | { |
4ce44c66 JM |
610 | memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS]; |
611 | last_segname = "umem"; | |
c906108c SS |
612 | break; |
613 | } | |
4ce44c66 | 614 | |
cff3e48b | 615 | case 0x01: /* On-chip insn memory */ |
c906108c | 616 | { |
4ce44c66 JM |
617 | memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS]; |
618 | last_segname = "imem"; | |
c906108c SS |
619 | break; |
620 | } | |
4ce44c66 JM |
621 | |
622 | case 0x02: /* On-chip data memory */ | |
c906108c | 623 | { |
4ce44c66 | 624 | if ((phys_addr & 0xff00) == 0xff00) |
c906108c | 625 | { |
4ce44c66 JM |
626 | phys_addr = (phys_addr & 0xffff); |
627 | if (phys_addr == DMAP2_SHADDOW) | |
c906108c | 628 | { |
4ce44c66 JM |
629 | phys_addr = DMAP2_OFFSET; |
630 | last_segname = "dmap"; | |
c906108c | 631 | } |
4ce44c66 JM |
632 | else |
633 | last_segname = "reg"; | |
c906108c | 634 | } |
4ce44c66 JM |
635 | else |
636 | last_segname = "dmem"; | |
637 | memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS]; | |
c906108c SS |
638 | break; |
639 | } | |
4ce44c66 | 640 | |
c906108c | 641 | default: |
4ce44c66 JM |
642 | /* OOPS! */ |
643 | last_segname = "scrap"; | |
aadc1740 | 644 | sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS); |
c906108c | 645 | } |
4ce44c66 JM |
646 | |
647 | if (*memory == NULL) | |
aadc1740 | 648 | *memory = xcalloc (1, SEGMENT_SIZE); |
4ce44c66 JM |
649 | |
650 | offset = (phys_addr % SEGMENT_SIZE); | |
651 | raw = *memory + offset; | |
652 | return raw; | |
653 | } | |
654 | ||
655 | /* Transfer data to/from simulated memory. Since a bug in either the | |
656 | simulated program or in gdb or the simulator itself may cause a | |
657 | bogus address to be passed in, we need to do some sanity checking | |
658 | on addresses to make sure they are within bounds. When an address | |
659 | fails the bounds check, treat it as a zero length read/write rather | |
660 | than aborting the entire run. */ | |
661 | ||
662 | static int | |
67954606 MF |
663 | xfer_mem (SIM_DESC sd, |
664 | SIM_ADDR virt, | |
4ce44c66 JM |
665 | unsigned char *buffer, |
666 | int size, | |
667 | int write_p) | |
668 | { | |
ea086965 AC |
669 | uint8 *memory; |
670 | unsigned long phys; | |
671 | int phys_size; | |
67954606 | 672 | phys_size = sim_d10v_translate_addr (sd, NULL, virt, size, &phys, NULL, |
ea086965 AC |
673 | dmap_register, imap_register); |
674 | if (phys_size == 0) | |
675 | return 0; | |
4ce44c66 | 676 | |
67954606 | 677 | memory = map_memory (sd, NULL, phys); |
4ce44c66 JM |
678 | |
679 | #ifdef DEBUG | |
ea086965 AC |
680 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) |
681 | { | |
e9b0081f MF |
682 | sim_io_printf |
683 | (sd, | |
d3b0ab8b | 684 | "sim_%s %d bytes: 0x%08" PRIxTA " (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n", |
e9b0081f | 685 | write_p ? "write" : "read", |
ea086965 AC |
686 | phys_size, virt, last_from, |
687 | phys, last_to, | |
688 | (long) memory, last_segname); | |
689 | } | |
4ce44c66 JM |
690 | #endif |
691 | ||
ea086965 AC |
692 | if (write_p) |
693 | { | |
694 | memcpy (memory, buffer, phys_size); | |
c906108c | 695 | } |
ea086965 AC |
696 | else |
697 | { | |
698 | memcpy (buffer, memory, phys_size); | |
699 | } | |
700 | ||
701 | return phys_size; | |
c906108c SS |
702 | } |
703 | ||
704 | ||
705 | int | |
11558abc | 706 | sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size) |
c906108c SS |
707 | { |
708 | /* FIXME: this should be performing a virtual transfer */ | |
d3b0ab8b MF |
709 | /* FIXME: We cast the const away, but it's safe because xfer_mem only reads |
710 | when write_p==1. This is still ugly. */ | |
711 | return xfer_mem (sd, addr, (void *) buffer, size, 1); | |
c906108c SS |
712 | } |
713 | ||
714 | int | |
11558abc | 715 | sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) |
c906108c SS |
716 | { |
717 | /* FIXME: this should be performing a virtual transfer */ | |
67954606 | 718 | return xfer_mem (sd, addr, buffer, size, 0); |
c906108c SS |
719 | } |
720 | ||
27b97b40 MF |
721 | static sim_cia |
722 | d10v_pc_get (sim_cpu *cpu) | |
723 | { | |
724 | return PC; | |
725 | } | |
726 | ||
727 | static void | |
728 | d10v_pc_set (sim_cpu *cpu, sim_cia pc) | |
729 | { | |
67954606 | 730 | SIM_DESC sd = CPU_STATE (cpu); |
27b97b40 MF |
731 | SET_PC (pc); |
732 | } | |
733 | ||
541ebcee MF |
734 | static void |
735 | free_state (SIM_DESC sd) | |
736 | { | |
737 | if (STATE_MODULES (sd) != NULL) | |
738 | sim_module_uninstall (sd); | |
739 | sim_cpu_free_all (sd); | |
740 | sim_state_free (sd); | |
741 | } | |
742 | ||
e1211e55 MF |
743 | static int d10v_reg_fetch (SIM_CPU *, int, unsigned char *, int); |
744 | static int d10v_reg_store (SIM_CPU *, int, unsigned char *, int); | |
745 | ||
c906108c | 746 | SIM_DESC |
2e3d4f4d MF |
747 | sim_open (SIM_OPEN_KIND kind, host_callback *cb, |
748 | struct bfd *abfd, char * const *argv) | |
c906108c SS |
749 | { |
750 | struct simops *s; | |
751 | struct hash_entry *h; | |
752 | static int init_p = 0; | |
d3b0ab8b | 753 | char * const *p; |
27b97b40 | 754 | int i; |
541ebcee MF |
755 | SIM_DESC sd = sim_state_alloc (kind, cb); |
756 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
c906108c | 757 | |
541ebcee | 758 | /* The cpu data is kept in a separately allocated chunk of memory. */ |
d5a71b11 | 759 | if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) |
541ebcee MF |
760 | { |
761 | free_state (sd); | |
762 | return 0; | |
763 | } | |
764 | ||
765 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
766 | { | |
767 | free_state (sd); | |
768 | return 0; | |
769 | } | |
770 | ||
77cf2ef5 | 771 | /* The parser will print an error message for us, so we silently return. */ |
541ebcee MF |
772 | if (sim_parse_args (sd, argv) != SIM_RC_OK) |
773 | { | |
774 | free_state (sd); | |
775 | return 0; | |
776 | } | |
777 | ||
778 | /* Check for/establish the a reference program image. */ | |
779 | if (sim_analyze_program (sd, | |
780 | (STATE_PROG_ARGV (sd) != NULL | |
781 | ? *STATE_PROG_ARGV (sd) | |
782 | : NULL), abfd) != SIM_RC_OK) | |
783 | { | |
784 | free_state (sd); | |
785 | return 0; | |
786 | } | |
787 | ||
788 | /* Configure/verify the target byte order and other runtime | |
789 | configuration options. */ | |
790 | if (sim_config (sd) != SIM_RC_OK) | |
791 | { | |
792 | sim_module_uninstall (sd); | |
793 | return 0; | |
794 | } | |
795 | ||
796 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
797 | { | |
798 | /* Uninstall the modules to avoid memory leaks, | |
799 | file descriptor leaks, etc. */ | |
800 | sim_module_uninstall (sd); | |
801 | return 0; | |
802 | } | |
803 | ||
27b97b40 MF |
804 | /* CPU specific initialization. */ |
805 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
806 | { | |
807 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
808 | ||
e1211e55 MF |
809 | CPU_REG_FETCH (cpu) = d10v_reg_fetch; |
810 | CPU_REG_STORE (cpu) = d10v_reg_store; | |
27b97b40 MF |
811 | CPU_PC_FETCH (cpu) = d10v_pc_get; |
812 | CPU_PC_STORE (cpu) = d10v_pc_set; | |
813 | } | |
814 | ||
cff3e48b | 815 | old_segment_mapping = 0; |
c906108c | 816 | |
4ce44c66 JM |
817 | /* NOTE: This argument parsing is only effective when this function |
818 | is called by GDB. Standalone argument parsing is handled by | |
819 | sim/common/run.c. */ | |
c906108c SS |
820 | for (p = argv + 1; *p; ++p) |
821 | { | |
cff3e48b JM |
822 | if (strcmp (*p, "-oldseg") == 0) |
823 | old_segment_mapping = 1; | |
c906108c | 824 | #ifdef DEBUG |
cff3e48b | 825 | else if (strcmp (*p, "-t") == 0) |
c906108c | 826 | d10v_debug = DEBUG; |
4ce44c66 JM |
827 | else if (strncmp (*p, "-t", 2) == 0) |
828 | d10v_debug = atoi (*p + 2); | |
c906108c | 829 | #endif |
c906108c SS |
830 | } |
831 | ||
832 | /* put all the opcodes in the hash table */ | |
833 | if (!init_p++) | |
834 | { | |
835 | for (s = Simops; s->func; s++) | |
836 | { | |
837 | h = &hash_table[hash(s->opcode,s->format)]; | |
838 | ||
839 | /* go to the last entry in the chain */ | |
840 | while (h->next) | |
841 | h = h->next; | |
842 | ||
843 | if (h->ops) | |
844 | { | |
845 | h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry)); | |
846 | if (!h->next) | |
847 | perror ("malloc failure"); | |
848 | ||
849 | h = h->next; | |
850 | } | |
851 | h->ops = s; | |
852 | h->mask = s->mask; | |
853 | h->opcode = s->opcode; | |
854 | h->size = s->is_long; | |
855 | } | |
856 | } | |
857 | ||
858 | /* reset the processor state */ | |
4ce44c66 JM |
859 | if (!State.mem.data[0]) |
860 | sim_size (1); | |
c906108c | 861 | |
541ebcee | 862 | return sd; |
c906108c SS |
863 | } |
864 | ||
c906108c | 865 | uint8 * |
67954606 | 866 | dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16 offset) |
c906108c | 867 | { |
4ce44c66 JM |
868 | unsigned long phys; |
869 | uint8 *mem; | |
870 | int phys_size; | |
c906108c | 871 | |
4ce44c66 JM |
872 | /* Note: DMEM address range is 0..0x10000. Calling code can compute |
873 | things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type | |
874 | is uint16 this is modulo'ed onto 0x0e5d. */ | |
c906108c | 875 | |
67954606 | 876 | phys_size = sim_d10v_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL, |
4ce44c66 JM |
877 | dmap_register); |
878 | if (phys_size == 0) | |
aadc1740 MF |
879 | sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS); |
880 | mem = map_memory (sd, cpu, phys); | |
c906108c | 881 | #ifdef DEBUG |
4ce44c66 JM |
882 | if ((d10v_debug & DEBUG_MEMORY)) |
883 | { | |
e9b0081f MF |
884 | sim_io_printf |
885 | (sd, | |
4ce44c66 JM |
886 | "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", |
887 | offset, last_from, | |
888 | phys, phys_size, last_to, | |
889 | (long) mem, last_segname); | |
c906108c | 890 | } |
4ce44c66 JM |
891 | #endif |
892 | return mem; | |
c906108c SS |
893 | } |
894 | ||
c906108c | 895 | uint8 * |
67954606 | 896 | imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset) |
c906108c | 897 | { |
4ce44c66 JM |
898 | unsigned long phys; |
899 | uint8 *mem; | |
67954606 | 900 | int phys_size = sim_d10v_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL, |
f6684c31 | 901 | imap_register); |
4ce44c66 | 902 | if (phys_size == 0) |
aadc1740 | 903 | sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS); |
67954606 | 904 | mem = map_memory (sd, cpu, phys); |
4ce44c66 JM |
905 | #ifdef DEBUG |
906 | if ((d10v_debug & DEBUG_MEMORY)) | |
907 | { | |
e9b0081f MF |
908 | sim_io_printf |
909 | (sd, | |
4ce44c66 JM |
910 | "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", |
911 | offset, last_from, | |
912 | phys, phys_size, last_to, | |
913 | (long) mem, last_segname); | |
914 | } | |
915 | #endif | |
916 | return mem; | |
c906108c SS |
917 | } |
918 | ||
aadc1740 MF |
919 | static void |
920 | step_once (SIM_DESC sd, SIM_CPU *cpu) | |
c906108c SS |
921 | { |
922 | uint32 inst; | |
923 | uint8 *iaddr; | |
924 | ||
aadc1740 | 925 | /* TODO: Unindent this block. */ |
c906108c | 926 | { |
67954606 | 927 | iaddr = imem_addr (sd, cpu, (uint32)PC << 2); |
c906108c SS |
928 | |
929 | inst = get_longword( iaddr ); | |
930 | ||
931 | State.pc_changed = 0; | |
932 | ins_type_counters[ (int)INS_CYCLES ]++; | |
933 | ||
934 | switch (inst & 0xC0000000) | |
935 | { | |
936 | case 0xC0000000: | |
937 | /* long instruction */ | |
67954606 | 938 | do_long (sd, cpu, inst & 0x3FFFFFFF); |
c906108c SS |
939 | break; |
940 | case 0x80000000: | |
941 | /* R -> L */ | |
67954606 | 942 | do_2_short (sd, cpu, inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, RIGHT_FIRST); |
c906108c SS |
943 | break; |
944 | case 0x40000000: | |
945 | /* L -> R */ | |
67954606 | 946 | do_2_short (sd, cpu, (inst & 0x3FFF8000) >> 15, inst & 0x7FFF, LEFT_FIRST); |
c906108c SS |
947 | break; |
948 | case 0: | |
67954606 | 949 | do_parallel (sd, cpu, (inst & 0x3FFF8000) >> 15, inst & 0x7FFF); |
c906108c SS |
950 | break; |
951 | } | |
952 | ||
953 | /* If the PC of the current instruction matches RPT_E then | |
954 | schedule a branch to the loop start. If one of those | |
955 | instructions happens to be a branch, than that instruction | |
956 | will be ignored */ | |
957 | if (!State.pc_changed) | |
958 | { | |
959 | if (PSW_RP && PC == RPT_E) | |
960 | { | |
961 | /* Note: The behavour of a branch instruction at RPT_E | |
962 | is implementation dependant, this simulator takes the | |
963 | branch. Branching to RPT_E is valid, the instruction | |
964 | must be executed before the loop is taken. */ | |
965 | if (RPT_C == 1) | |
966 | { | |
967 | SET_PSW_RP (0); | |
968 | SET_RPT_C (0); | |
969 | SET_PC (PC + 1); | |
970 | } | |
971 | else | |
972 | { | |
973 | SET_RPT_C (RPT_C - 1); | |
974 | SET_PC (RPT_S); | |
975 | } | |
976 | } | |
977 | else | |
978 | SET_PC (PC + 1); | |
979 | } | |
980 | ||
981 | /* Check for a breakpoint trap on this instruction. This | |
982 | overrides any pending branches or loops */ | |
983 | if (PSW_DB && PC == IBA) | |
984 | { | |
985 | SET_BPC (PC); | |
986 | SET_BPSW (PSW); | |
987 | SET_PSW (PSW & PSW_SM_BIT); | |
988 | SET_PC (SDBT_VECTOR_START); | |
989 | } | |
990 | ||
991 | /* Writeback all the DATA / PC changes */ | |
992 | SLOT_FLUSH (); | |
c906108c | 993 | } |
aadc1740 MF |
994 | } |
995 | ||
996 | void | |
997 | sim_engine_run (SIM_DESC sd, | |
998 | int next_cpu_nr, /* ignore */ | |
999 | int nr_cpus, /* ignore */ | |
1000 | int siggnal) | |
1001 | { | |
1002 | sim_cpu *cpu; | |
1003 | ||
1004 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
1005 | ||
1006 | cpu = STATE_CPU (sd, 0); | |
1007 | ||
1008 | switch (siggnal) | |
1009 | { | |
1010 | case 0: | |
1011 | break; | |
1012 | case GDB_SIGNAL_BUS: | |
1013 | SET_BPC (PC); | |
1014 | SET_BPSW (PSW); | |
1015 | SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); | |
1016 | JMP (AE_VECTOR_START); | |
1017 | SLOT_FLUSH (); | |
1018 | break; | |
1019 | case GDB_SIGNAL_ILL: | |
1020 | SET_BPC (PC); | |
1021 | SET_BPSW (PSW); | |
1022 | SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); | |
1023 | JMP (RIE_VECTOR_START); | |
1024 | SLOT_FLUSH (); | |
1025 | break; | |
1026 | default: | |
1027 | /* just ignore it */ | |
1028 | break; | |
1029 | } | |
1030 | ||
1031 | while (1) | |
1032 | { | |
1033 | step_once (sd, cpu); | |
1034 | if (sim_events_tick (sd)) | |
1035 | sim_events_process (sd); | |
1036 | } | |
c906108c SS |
1037 | } |
1038 | ||
c906108c | 1039 | void |
11558abc | 1040 | sim_info (SIM_DESC sd, int verbose) |
c906108c SS |
1041 | { |
1042 | char buf1[40]; | |
1043 | char buf2[40]; | |
1044 | char buf3[40]; | |
1045 | char buf4[40]; | |
1046 | char buf5[40]; | |
1047 | unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ]; | |
1048 | unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ]; | |
1049 | unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ]; | |
1050 | unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ]; | |
1051 | unsigned long left_total = left + left_parallel + left_cond + left_nops; | |
1052 | ||
1053 | unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ]; | |
1054 | unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ]; | |
1055 | unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ]; | |
1056 | unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ]; | |
1057 | unsigned long right_total = right + right_parallel + right_cond + right_nops; | |
1058 | ||
1059 | unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ]; | |
1060 | unsigned long ins_long = ins_type_counters[ (int)INS_LONG ]; | |
1061 | unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ]; | |
1062 | unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ]; | |
1063 | unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ]; | |
1064 | unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ]; | |
1065 | unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ]; | |
1066 | unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ]; | |
1067 | unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ]; | |
1068 | unsigned long total = (unknown + left_total + right_total + ins_long); | |
1069 | ||
1070 | int size = strlen (add_commas (buf1, sizeof (buf1), total)); | |
1071 | int parallel_size = strlen (add_commas (buf1, sizeof (buf1), | |
1072 | (left_parallel > right_parallel) ? left_parallel : right_parallel)); | |
1073 | int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond)); | |
1074 | int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops)); | |
1075 | int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right)); | |
1076 | ||
e9b0081f MF |
1077 | sim_io_printf (sd, |
1078 | "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", | |
1079 | size, add_commas (buf1, sizeof (buf1), left_total), | |
1080 | normal_size, add_commas (buf2, sizeof (buf2), left), | |
1081 | parallel_size, add_commas (buf3, sizeof (buf3), left_parallel), | |
1082 | cond_size, add_commas (buf4, sizeof (buf4), left_cond), | |
1083 | nop_size, add_commas (buf5, sizeof (buf5), left_nops)); | |
1084 | ||
1085 | sim_io_printf (sd, | |
1086 | "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", | |
1087 | size, add_commas (buf1, sizeof (buf1), right_total), | |
1088 | normal_size, add_commas (buf2, sizeof (buf2), right), | |
1089 | parallel_size, add_commas (buf3, sizeof (buf3), right_parallel), | |
1090 | cond_size, add_commas (buf4, sizeof (buf4), right_cond), | |
1091 | nop_size, add_commas (buf5, sizeof (buf5), right_nops)); | |
c906108c SS |
1092 | |
1093 | if (ins_long) | |
e9b0081f MF |
1094 | sim_io_printf (sd, |
1095 | "executed %*s long instruction(s)\n", | |
1096 | size, add_commas (buf1, sizeof (buf1), ins_long)); | |
c906108c SS |
1097 | |
1098 | if (parallel) | |
e9b0081f MF |
1099 | sim_io_printf (sd, |
1100 | "executed %*s parallel instruction(s)\n", | |
1101 | size, add_commas (buf1, sizeof (buf1), parallel)); | |
c906108c SS |
1102 | |
1103 | if (leftright) | |
e9b0081f MF |
1104 | sim_io_printf (sd, |
1105 | "executed %*s instruction(s) encoded L->R\n", | |
1106 | size, add_commas (buf1, sizeof (buf1), leftright)); | |
c906108c SS |
1107 | |
1108 | if (rightleft) | |
e9b0081f MF |
1109 | sim_io_printf (sd, |
1110 | "executed %*s instruction(s) encoded R->L\n", | |
1111 | size, add_commas (buf1, sizeof (buf1), rightleft)); | |
c906108c SS |
1112 | |
1113 | if (unknown) | |
e9b0081f MF |
1114 | sim_io_printf (sd, |
1115 | "executed %*s unknown instruction(s)\n", | |
1116 | size, add_commas (buf1, sizeof (buf1), unknown)); | |
c906108c SS |
1117 | |
1118 | if (cond_true) | |
e9b0081f MF |
1119 | sim_io_printf (sd, |
1120 | "executed %*s instruction(s) due to EXExxx condition being true\n", | |
1121 | size, add_commas (buf1, sizeof (buf1), cond_true)); | |
c906108c SS |
1122 | |
1123 | if (cond_false) | |
e9b0081f MF |
1124 | sim_io_printf (sd, |
1125 | "skipped %*s instruction(s) due to EXExxx condition being false\n", | |
1126 | size, add_commas (buf1, sizeof (buf1), cond_false)); | |
c906108c SS |
1127 | |
1128 | if (cond_jump) | |
e9b0081f MF |
1129 | sim_io_printf (sd, |
1130 | "skipped %*s instruction(s) due to conditional branch succeeding\n", | |
1131 | size, add_commas (buf1, sizeof (buf1), cond_jump)); | |
c906108c | 1132 | |
e9b0081f MF |
1133 | sim_io_printf (sd, |
1134 | "executed %*s cycle(s)\n", | |
1135 | size, add_commas (buf1, sizeof (buf1), cycles)); | |
c906108c | 1136 | |
e9b0081f MF |
1137 | sim_io_printf (sd, |
1138 | "executed %*s total instructions\n", | |
1139 | size, add_commas (buf1, sizeof (buf1), total)); | |
c906108c SS |
1140 | } |
1141 | ||
1142 | SIM_RC | |
2e3d4f4d MF |
1143 | sim_create_inferior (SIM_DESC sd, struct bfd *abfd, |
1144 | char * const *argv, char * const *env) | |
c906108c SS |
1145 | { |
1146 | bfd_vma start_address; | |
1147 | ||
e7e40ced LM |
1148 | /* Make sure we have the right structure for the following memset. */ |
1149 | static_assert ((uintptr_t) &State == (uintptr_t) &State.regs, | |
1150 | "&State != &State.regs"); | |
1151 | ||
1152 | /* Reset state from the regs field until the mem field. */ | |
1153 | memset (&State, 0, (uintptr_t) &State.mem - (uintptr_t) &State.regs); | |
c906108c | 1154 | |
1aa5e64f EZ |
1155 | /* There was a hack here to copy the values of argc and argv into r0 |
1156 | and r1. The values were also saved into some high memory that | |
1157 | won't be overwritten by the stack (0x7C00). The reason for doing | |
1158 | this was to allow the 'run' program to accept arguments. Without | |
1159 | the hack, this is not possible anymore. If the simulator is run | |
1160 | from the debugger, arguments cannot be passed in, so this makes | |
1161 | no difference. */ | |
1162 | ||
c906108c SS |
1163 | /* set PC */ |
1164 | if (abfd != NULL) | |
1165 | start_address = bfd_get_start_address (abfd); | |
1166 | else | |
1167 | start_address = 0xffc0 << 2; | |
1168 | #ifdef DEBUG | |
1169 | if (d10v_debug) | |
5ee0bc23 MF |
1170 | sim_io_printf (sd, "sim_create_inferior: PC=0x%" BFD_VMA_FMT "x\n", |
1171 | start_address); | |
c906108c | 1172 | #endif |
67954606 MF |
1173 | { |
1174 | SIM_CPU *cpu = STATE_CPU (sd, 0); | |
1175 | SET_CREG (PC_CR, start_address >> 2); | |
1176 | } | |
c906108c | 1177 | |
4ce44c66 JM |
1178 | /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board |
1179 | initializes imap0 and imap1 to 0x1000 as part of its ROM | |
1180 | initialization. */ | |
cff3e48b | 1181 | if (old_segment_mapping) |
c906108c | 1182 | { |
4ce44c66 | 1183 | /* External memory startup. This is the HARD reset state. */ |
67954606 MF |
1184 | set_imap_register (sd, 0, 0x0000); |
1185 | set_imap_register (sd, 1, 0x007f); | |
1186 | set_dmap_register (sd, 0, 0x2000); | |
1187 | set_dmap_register (sd, 1, 0x2000); | |
1188 | set_dmap_register (sd, 2, 0x0000); /* Old DMAP */ | |
1189 | set_dmap_register (sd, 3, 0x0000); | |
c906108c SS |
1190 | } |
1191 | else | |
1192 | { | |
4ce44c66 | 1193 | /* Internal memory startup. This is the ROM intialized state. */ |
67954606 MF |
1194 | set_imap_register (sd, 0, 0x1000); |
1195 | set_imap_register (sd, 1, 0x1000); | |
1196 | set_dmap_register (sd, 0, 0x2000); | |
1197 | set_dmap_register (sd, 1, 0x2000); | |
1198 | set_dmap_register (sd, 2, 0x2000); /* DMAP2 initial internal value is | |
1199 | 0x2000 on the new board. */ | |
1200 | set_dmap_register (sd, 3, 0x0000); | |
c906108c SS |
1201 | } |
1202 | ||
1203 | SLOT_FLUSH (); | |
1204 | return SIM_RC_OK; | |
1205 | } | |
1206 | ||
e1211e55 MF |
1207 | static int |
1208 | d10v_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) | |
c906108c | 1209 | { |
e1211e55 | 1210 | SIM_DESC sd = CPU_STATE (cpu); |
4ce44c66 | 1211 | int size; |
983b727e | 1212 | switch ((enum sim_d10v_regs) rn) |
4ce44c66 | 1213 | { |
18c0df9e AC |
1214 | case SIM_D10V_R0_REGNUM: |
1215 | case SIM_D10V_R1_REGNUM: | |
1216 | case SIM_D10V_R2_REGNUM: | |
1217 | case SIM_D10V_R3_REGNUM: | |
1218 | case SIM_D10V_R4_REGNUM: | |
1219 | case SIM_D10V_R5_REGNUM: | |
1220 | case SIM_D10V_R6_REGNUM: | |
1221 | case SIM_D10V_R7_REGNUM: | |
1222 | case SIM_D10V_R8_REGNUM: | |
1223 | case SIM_D10V_R9_REGNUM: | |
1224 | case SIM_D10V_R10_REGNUM: | |
1225 | case SIM_D10V_R11_REGNUM: | |
1226 | case SIM_D10V_R12_REGNUM: | |
1227 | case SIM_D10V_R13_REGNUM: | |
1228 | case SIM_D10V_R14_REGNUM: | |
1229 | case SIM_D10V_R15_REGNUM: | |
4ce44c66 JM |
1230 | WRITE_16 (memory, GPR (rn - SIM_D10V_R0_REGNUM)); |
1231 | size = 2; | |
18c0df9e AC |
1232 | break; |
1233 | case SIM_D10V_CR0_REGNUM: | |
1234 | case SIM_D10V_CR1_REGNUM: | |
1235 | case SIM_D10V_CR2_REGNUM: | |
1236 | case SIM_D10V_CR3_REGNUM: | |
1237 | case SIM_D10V_CR4_REGNUM: | |
1238 | case SIM_D10V_CR5_REGNUM: | |
1239 | case SIM_D10V_CR6_REGNUM: | |
1240 | case SIM_D10V_CR7_REGNUM: | |
1241 | case SIM_D10V_CR8_REGNUM: | |
1242 | case SIM_D10V_CR9_REGNUM: | |
1243 | case SIM_D10V_CR10_REGNUM: | |
1244 | case SIM_D10V_CR11_REGNUM: | |
1245 | case SIM_D10V_CR12_REGNUM: | |
1246 | case SIM_D10V_CR13_REGNUM: | |
1247 | case SIM_D10V_CR14_REGNUM: | |
1248 | case SIM_D10V_CR15_REGNUM: | |
4ce44c66 JM |
1249 | WRITE_16 (memory, CREG (rn - SIM_D10V_CR0_REGNUM)); |
1250 | size = 2; | |
18c0df9e AC |
1251 | break; |
1252 | case SIM_D10V_A0_REGNUM: | |
1253 | case SIM_D10V_A1_REGNUM: | |
4ce44c66 JM |
1254 | WRITE_64 (memory, ACC (rn - SIM_D10V_A0_REGNUM)); |
1255 | size = 8; | |
18c0df9e AC |
1256 | break; |
1257 | case SIM_D10V_SPI_REGNUM: | |
4ce44c66 JM |
1258 | /* PSW_SM indicates that the current SP is the USER |
1259 | stack-pointer. */ | |
1260 | WRITE_16 (memory, spi_register ()); | |
1261 | size = 2; | |
18c0df9e AC |
1262 | break; |
1263 | case SIM_D10V_SPU_REGNUM: | |
4ce44c66 JM |
1264 | /* PSW_SM indicates that the current SP is the USER |
1265 | stack-pointer. */ | |
1266 | WRITE_16 (memory, spu_register ()); | |
1267 | size = 2; | |
18c0df9e AC |
1268 | break; |
1269 | case SIM_D10V_IMAP0_REGNUM: | |
1270 | case SIM_D10V_IMAP1_REGNUM: | |
67954606 | 1271 | WRITE_16 (memory, imap_register (sd, cpu, NULL, rn - SIM_D10V_IMAP0_REGNUM)); |
4ce44c66 | 1272 | size = 2; |
18c0df9e AC |
1273 | break; |
1274 | case SIM_D10V_DMAP0_REGNUM: | |
1275 | case SIM_D10V_DMAP1_REGNUM: | |
1276 | case SIM_D10V_DMAP2_REGNUM: | |
1277 | case SIM_D10V_DMAP3_REGNUM: | |
67954606 | 1278 | WRITE_16 (memory, dmap_register (sd, cpu, NULL, rn - SIM_D10V_DMAP0_REGNUM)); |
4ce44c66 | 1279 | size = 2; |
18c0df9e AC |
1280 | break; |
1281 | case SIM_D10V_TS2_DMAP_REGNUM: | |
1282 | size = 0; | |
1283 | break; | |
1284 | default: | |
1285 | size = 0; | |
1286 | break; | |
4ce44c66 | 1287 | } |
4ce44c66 | 1288 | return size; |
c906108c SS |
1289 | } |
1290 | ||
e1211e55 MF |
1291 | static int |
1292 | d10v_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) | |
c906108c | 1293 | { |
e1211e55 | 1294 | SIM_DESC sd = CPU_STATE (cpu); |
4ce44c66 | 1295 | int size; |
983b727e | 1296 | switch ((enum sim_d10v_regs) rn) |
4ce44c66 | 1297 | { |
18c0df9e AC |
1298 | case SIM_D10V_R0_REGNUM: |
1299 | case SIM_D10V_R1_REGNUM: | |
1300 | case SIM_D10V_R2_REGNUM: | |
1301 | case SIM_D10V_R3_REGNUM: | |
1302 | case SIM_D10V_R4_REGNUM: | |
1303 | case SIM_D10V_R5_REGNUM: | |
1304 | case SIM_D10V_R6_REGNUM: | |
1305 | case SIM_D10V_R7_REGNUM: | |
1306 | case SIM_D10V_R8_REGNUM: | |
1307 | case SIM_D10V_R9_REGNUM: | |
1308 | case SIM_D10V_R10_REGNUM: | |
1309 | case SIM_D10V_R11_REGNUM: | |
1310 | case SIM_D10V_R12_REGNUM: | |
1311 | case SIM_D10V_R13_REGNUM: | |
1312 | case SIM_D10V_R14_REGNUM: | |
1313 | case SIM_D10V_R15_REGNUM: | |
4ce44c66 JM |
1314 | SET_GPR (rn - SIM_D10V_R0_REGNUM, READ_16 (memory)); |
1315 | size = 2; | |
18c0df9e AC |
1316 | break; |
1317 | case SIM_D10V_CR0_REGNUM: | |
1318 | case SIM_D10V_CR1_REGNUM: | |
1319 | case SIM_D10V_CR2_REGNUM: | |
1320 | case SIM_D10V_CR3_REGNUM: | |
1321 | case SIM_D10V_CR4_REGNUM: | |
1322 | case SIM_D10V_CR5_REGNUM: | |
1323 | case SIM_D10V_CR6_REGNUM: | |
1324 | case SIM_D10V_CR7_REGNUM: | |
1325 | case SIM_D10V_CR8_REGNUM: | |
1326 | case SIM_D10V_CR9_REGNUM: | |
1327 | case SIM_D10V_CR10_REGNUM: | |
1328 | case SIM_D10V_CR11_REGNUM: | |
1329 | case SIM_D10V_CR12_REGNUM: | |
1330 | case SIM_D10V_CR13_REGNUM: | |
1331 | case SIM_D10V_CR14_REGNUM: | |
1332 | case SIM_D10V_CR15_REGNUM: | |
4ce44c66 JM |
1333 | SET_CREG (rn - SIM_D10V_CR0_REGNUM, READ_16 (memory)); |
1334 | size = 2; | |
18c0df9e AC |
1335 | break; |
1336 | case SIM_D10V_A0_REGNUM: | |
1337 | case SIM_D10V_A1_REGNUM: | |
4ce44c66 JM |
1338 | SET_ACC (rn - SIM_D10V_A0_REGNUM, READ_64 (memory) & MASK40); |
1339 | size = 8; | |
18c0df9e AC |
1340 | break; |
1341 | case SIM_D10V_SPI_REGNUM: | |
4ce44c66 JM |
1342 | /* PSW_SM indicates that the current SP is the USER |
1343 | stack-pointer. */ | |
1344 | set_spi_register (READ_16 (memory)); | |
1345 | size = 2; | |
18c0df9e AC |
1346 | break; |
1347 | case SIM_D10V_SPU_REGNUM: | |
4ce44c66 JM |
1348 | set_spu_register (READ_16 (memory)); |
1349 | size = 2; | |
18c0df9e AC |
1350 | break; |
1351 | case SIM_D10V_IMAP0_REGNUM: | |
1352 | case SIM_D10V_IMAP1_REGNUM: | |
67954606 | 1353 | set_imap_register (sd, rn - SIM_D10V_IMAP0_REGNUM, READ_16(memory)); |
4ce44c66 | 1354 | size = 2; |
18c0df9e AC |
1355 | break; |
1356 | case SIM_D10V_DMAP0_REGNUM: | |
1357 | case SIM_D10V_DMAP1_REGNUM: | |
1358 | case SIM_D10V_DMAP2_REGNUM: | |
1359 | case SIM_D10V_DMAP3_REGNUM: | |
67954606 | 1360 | set_dmap_register (sd, rn - SIM_D10V_DMAP0_REGNUM, READ_16(memory)); |
4ce44c66 | 1361 | size = 2; |
18c0df9e AC |
1362 | break; |
1363 | case SIM_D10V_TS2_DMAP_REGNUM: | |
1364 | size = 0; | |
1365 | break; | |
1366 | default: | |
1367 | size = 0; | |
1368 | break; | |
4ce44c66 | 1369 | } |
c906108c | 1370 | SLOT_FLUSH (); |
4ce44c66 | 1371 | return size; |
c906108c | 1372 | } |