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[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
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4f425a32 1#include <signal.h>
2934d1c9
MH		 2#include "d10v_sim.h"
3#include "simops.h"
4
5/* #define DEBUG 1 */
6
7/* abs */
8void
9OP_4607 ()
10{
11#ifdef DEBUG
12 printf(" abs\tr%d\n",OP[0]);
13#endif
14 State.F1 = State.F0;
15 if ((int16)(State.regs[OP[0]]) < 0)
16 {
17 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
18 State.F0 = 1;
19 }
20 else
21 State.F0 = 0;
22}
23
24/* abs */
25void
26OP_5607 ()
27{
28 int64 tmp;
29
30#ifdef DEBUG
31 printf(" abs\ta%d\n",OP[0]);
32#endif
4f425a32
MH		 33 State.F1 = State.F0;
34 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
35
4c38885c 36 if (State.a[OP[0]] < 0 )
2934d1c9 37 {
4c38885c 38 tmp = -State.a[OP[0]];
2934d1c9
MH		 39 if (State.ST)
40 {
4c38885c 41 if (tmp > MAX32)
2934d1c9 42 State.a[OP[0]] = MAX32;
4c38885c 43 else if (tmp < MIN32)
2934d1c9
MH		 44 State.a[OP[0]] = MIN32;
45 else
4f425a32 46 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 47 }
48 else
4f425a32 49 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 50 State.F0 = 1;
51 }
52 else
53 State.F0 = 0;
54}
55
56/* add */
57void
58OP_200 ()
59{
60 uint16 tmp = State.regs[OP[0]];
61#ifdef DEBUG
62 printf(" add\tr%d,r%d\n",OP[0],OP[1]);
63#endif
64 State.regs[OP[0]] += State.regs[OP[1]];
65 if ( tmp > State.regs[OP[0]])
66 State.C = 1;
67 else
68 State.C = 0;
69}
70
71/* add */
72void
73OP_1201 ()
74{
4c38885c 75 int64 tmp;
2934d1c9
MH		 76#ifdef DEBUG
77 printf(" add\ta%d,r%d\n",OP[0],OP[1]);
78#endif
4f425a32 79 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
4c38885c
MH		 80 if (State.ST)
81 {
82 if ( tmp > MAX32)
83 State.a[OP[0]] = MAX32;
84 else if ( tmp < MIN32)
85 State.a[OP[0]] = MIN32;
86 else
4f425a32 87 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 88 }
89 else
4f425a32 90 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 91}
92
93/* add */
94void
95OP_1203 ()
96{
4c38885c 97 int64 tmp;
2934d1c9 98#ifdef DEBUG
4c38885c 99 printf(" add\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 100#endif
4f425a32 101 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
4c38885c
MH		 102 if (State.ST)
103 {
104 if (tmp > MAX32)
105 State.a[OP[0]] = MAX32;
106 else if ( tmp < MIN32)
107 State.a[OP[0]] = MIN32;
108 else
4f425a32 109 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 110 }
111 else
4f425a32 112 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 113}
114
115/* add2w */
116void
117OP_1200 ()
118{
119 uint32 tmp;
120 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
121 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
122#ifdef DEBUG
123 printf(" add2w\tr%d,r%d\n",OP[0],OP[1]);
124#endif
125 tmp = tmp1 + tmp2;
126 if ( (tmp < tmp1) || (tmp < tmp2) )
127 State.C = 1;
128 else
129 State.C = 0;
130 State.regs[OP[0]] = tmp >> 16;
131 State.regs[OP[0]+1] = tmp & 0xFFFF;
132}
133
134/* add3 */
135void
136OP_1000000 ()
137{
138 uint16 tmp = State.regs[OP[0]];
139#ifdef DEBUG
140 printf(" add3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
141#endif
142 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
143 if ( tmp > State.regs[OP[0]])
144 State.C = 1;
145 else
146 State.C = 0;
147}
148
149/* addac3 */
150void
151OP_17000200 ()
152{
4c38885c 153 int64 tmp;
2934d1c9 154#ifdef DEBUG
4c38885c 155 printf(" addac3\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 156#endif
4f425a32 157 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 158 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
159 State.regs[OP[0]+1] = tmp & 0xffff;
2934d1c9
MH		 160}
161
162/* addac3 */
163void
164OP_17000202 ()
165{
4c38885c 166 int64 tmp;
2934d1c9 167#ifdef DEBUG
4c38885c 168 printf(" addac3\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 169#endif
4f425a32 170 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 171 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
172 State.regs[OP[0]+1] = tmp & 0xffff;
2934d1c9
MH		 173}
174
175/* addac3s */
176void
177OP_17001200 ()
178{
4c38885c 179 int64 tmp;
2934d1c9 180#ifdef DEBUG
4c38885c 181 printf(" addac3s\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 182#endif
4c38885c 183 State.F1 = State.F0;
4f425a32 184 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 185 if ( tmp > MAX32)
186 {
187 State.regs[OP[0]] = 0x7fff;
188 State.regs[OP[0]+1] = 0xffff;
189 State.F0 = 1;
190 }
191 else if (tmp < MIN32)
192 {
193 State.regs[OP[0]] = 0x8000;
194 State.regs[OP[0]+1] = 0;
195 State.F0 = 1;
196 }
197 else
198 {
199 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
200 State.regs[OP[0]+1] = tmp & 0xffff;
201 State.F0 = 0;
202 }
2934d1c9
MH		 203}
204
205/* addac3s */
206void
207OP_17001202 ()
208{
4c38885c 209 int64 tmp;
2934d1c9 210#ifdef DEBUG
4c38885c 211 printf(" addac3s\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 212#endif
4c38885c 213 State.F1 = State.F0;
4f425a32 214 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 215 if ( tmp > MAX32)
216 {
217 State.regs[OP[0]] = 0x7fff;
218 State.regs[OP[0]+1] = 0xffff;
219 State.F0 = 1;
220 }
221 else if (tmp < MIN32)
222 {
223 State.regs[OP[0]] = 0x8000;
224 State.regs[OP[0]+1] = 0;
225 State.F0 = 1;
226 }
227 else
228 {
229 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
230 State.regs[OP[0]+1] = tmp & 0xffff;
231 State.F0 = 0;
232 }
2934d1c9
MH		 233}
234
235/* addi */
236void
237OP_201 ()
238{
4f425a32
MH		 239 if (OP[1] == 0)
240 OP[1] = 16;
2934d1c9
MH		 241#ifdef DEBUG
242 printf(" addi\tr%d,0x%x\n",OP[0],OP[1]);
243#endif
244 State.regs[OP[0]] += OP[1];
245}
246
247/* and */
248void
249OP_C00 ()
250{
251#ifdef DEBUG
252 printf(" and\tr%d,r%d\n",OP[0],OP[1]);
253#endif
254 State.regs[OP[0]] &= State.regs[OP[1]];
255}
256
257/* and3 */
258void
259OP_6000000 ()
260{
261#ifdef DEBUG
262 printf(" and3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
263#endif
264 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
265}
266
267/* bclri */
268void
269OP_C01 ()
270{
271#ifdef DEBUG
272 printf(" bclri\tr%d,%d\n",OP[0],OP[1]);
273#endif
274 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
275}
276
277/* bl.s */
278void
279OP_4900 ()
280{
281#ifdef DEBUG
282 printf(" bl.s\t0x%x\n",OP[0]);
283#endif
284 State.regs[13] = PC+1;
285 PC += SEXT8 (OP[0]);
286}
287
288/* bl.l */
289void
290OP_24800000 ()
291{
292#ifdef DEBUG
293 printf(" bl.l\t0x%x\n",OP[0]);
294#endif
295 State.regs[13] = PC+1;
296 PC += OP[0];
297}
298
299/* bnoti */
300void
301OP_A01 ()
302{
303#ifdef DEBUG
304 printf(" bnoti\tr%d,%d\n",OP[0],OP[1]);
305#endif
306 State.regs[OP[0]] ^= 0x8000 >> OP[1];
307}
308
309/* bra.s */
310void
311OP_4800 ()
312{
313#ifdef DEBUG
314 printf(" bra.s\t0x%x\n",OP[0]);
315#endif
316 PC += SEXT8 (OP[0]);
317}
318
319/* bra.l */
320void
321OP_24000000 ()
322{
323#ifdef DEBUG
324 printf(" bra.l\t0x%x\n",OP[0]);
325#endif
326 PC += OP[0];
327}
328
329/* brf0f.s */
330void
331OP_4A00 ()
332{
333#ifdef DEBUG
334 printf(" brf0f.s\t0x%x\n",OP[0]);
335#endif
336 if (State.F0 == 0)
337 PC += SEXT8 (OP[0]);
338}
339
340/* brf0f.l */
341void
342OP_25000000 ()
343{
344#ifdef DEBUG
345 printf(" brf0f.l\t0x%x\n",OP[0]);
346#endif
347 if (State.F0 == 0)
348 PC += OP[0];
349}
350
351/* brf0t.s */
352void
353OP_4B00 ()
354{
355#ifdef DEBUG
356 printf(" brf0t.s\t0x%x\n",OP[0]);
357#endif
358 if (State.F0)
359 PC += SEXT8 (OP[0]);
360}
361
362/* brf0t.l */
363void
364OP_25800000 ()
365{
366#ifdef DEBUG
367 printf(" brf0t.l\t0x%x\n",OP[0]);
368#endif
369 if (State.F0)
370 PC += OP[0];
371}
372
373/* bseti */
374void
375OP_801 ()
376{
377#ifdef DEBUG
378 printf(" bseti\tr%d,%d\n",OP[0],OP[1]);
379#endif
380 State.regs[OP[0]] |= 0x8000 >> OP[1];
381}
382
383/* btsti */
384void
385OP_E01 ()
386{
387#ifdef DEBUG
388 printf(" btsti\tr%d,%d\n",OP[0],OP[1]);
389#endif
390 State.F1 = State.F0;
391 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
392}
393
394/* clrac */
395void
396OP_5601 ()
397{
398#ifdef DEBUG
399 printf(" clrac\ta%d\n",OP[0]);
400#endif
401 State.a[OP[0]] = 0;
402}
403
404/* cmp */
405void
406OP_600 ()
407{
408#ifdef DEBUG
409 printf(" cmp\tr%d,r%d\n",OP[0],OP[1]);
410#endif
411 State.F1 = State.F0;
412 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
413}
414
415/* cmp */
416void
417OP_1603 ()
418{
419#ifdef DEBUG
4c38885c 420 printf(" cmp\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 421#endif
4c38885c 422 State.F1 = State.F0;
4f425a32 423 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
2934d1c9
MH		 424}
425
426/* cmpeq */
427void
428OP_400 ()
429{
430#ifdef DEBUG
431 printf(" cmpeq\tr%d,r%d\n",OP[0],OP[1]);
432#endif
433 State.F1 = State.F0;
434 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
435}
436
437/* cmpeq */
438void
439OP_1403 ()
440{
441#ifdef DEBUG
4c38885c 442 printf(" cmpeq\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 443#endif
4c38885c
MH		 444 State.F1 = State.F0;
445 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
2934d1c9
MH		 446}
447
448/* cmpeqi.s */
449void
450OP_401 ()
451{
452#ifdef DEBUG
453 printf(" cmpeqi.s\tr%d,0x%x\n",OP[0],OP[1]);
454#endif
455 State.F1 = State.F0;
456 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
457}
458
459/* cmpeqi.l */
460void
461OP_2000000 ()
462{
463#ifdef DEBUG
464 printf(" cmpeqi.l\tr%d,0x%x\n",OP[0],OP[1]);
465#endif
466 State.F1 = State.F0;
467 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
468}
469
470/* cmpi.s */
471void
472OP_601 ()
473{
474#ifdef DEBUG
475 printf(" cmpi.s\tr%d,0x%x\n",OP[0],OP[1]);
476#endif
477 State.F1 = State.F0;
478 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
479}
480
481/* cmpi.l */
482void
483OP_3000000 ()
484{
485#ifdef DEBUG
486 printf(" cmpi.l\tr%d,0x%x\n",OP[0],OP[1]);
487#endif
488 State.F1 = State.F0;
489 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
490}
491
492/* cmpu */
493void
494OP_4600 ()
495{
496#ifdef DEBUG
497 printf(" cmpu\tr%d,r%d\n",OP[0],OP[1]);
498#endif
499 State.F1 = State.F0;
500 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
501}
502
503/* cmpui */
504void
505OP_23000000 ()
506{
507#ifdef DEBUG
508 printf(" cmpui\tr%d,0x%x\n",OP[0],OP[1]);
509#endif
510 State.F1 = State.F0;
511 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
512}
513
514/* cpfg */
515void
516OP_4E09 ()
517{
518 uint8 *src, *dst;
519#ifdef DEBUG
520 printf(" cpfg\t%x,%x\n",OP[0],OP[1]);
521#endif
522
523 if (OP[0] == 0)
524 dst = &State.F0;
525 else
526 dst = &State.F1;
527
528 if (OP[1] == 0)
529 src = &State.F0;
530 else if (OP[1] == 1)
531 src = &State.F1;
532 else
533 src = &State.C;
534
535 *dst = *src;
536}
537
538/* dbt */
539void
540OP_5F20 ()
541{
4f425a32
MH		 542 printf("***** DBT ***** PC=%x\n",PC);
543 State.exception = SIGTRAP;
2934d1c9
MH		 544}
545
546/* divs */
547void
548OP_14002800 ()
549{
550 uint16 foo, tmp, tmpf;
551#ifdef DEBUG
552 printf(" divs\tr%d,r%d\n",OP[0],OP[1]);
553#endif
554 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
555 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
556 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
557 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
558 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
559}
560
561/* exef0f */
562void
563OP_4E04 ()
564{
565#ifdef DEBUG
566 printf(" exef0f\n");
567#endif
568 State.exe = (State.F0) ? 0 : 1;
569}
570
571/* exef0t */
572void
573OP_4E24 ()
574{
575#ifdef DEBUG
576 printf(" exef0t\n");
577#endif
578 State.exe = State.F0;
579}
580
581/* exef1f */
582void
583OP_4E40 ()
584{
585#ifdef DEBUG
586 printf(" exef1f\n");
587#endif
588 State.exe = (State.F1) ? 0 : 1;
589}
590
591/* exef1t */
592void
593OP_4E42 ()
594{
595#ifdef DEBUG
596 printf(" exef1t\n");
597#endif
598 State.exe = State.F1;
599}
600
601/* exefaf */
602void
603OP_4E00 ()
604{
605#ifdef DEBUG
606 printf(" exefaf\n");
607#endif
608 State.exe = (State.F0 | State.F1) ? 0 : 1;
609}
610
611/* exefat */
612void
613OP_4E02 ()
614{
615#ifdef DEBUG
616 printf(" exefat\n");
617#endif
618 State.exe = (State.F0) ? 0 : (State.F1);
619}
620
621/* exetaf */
622void
623OP_4E20 ()
624{
625#ifdef DEBUG
626 printf(" exetaf\n");
627#endif
628 State.exe = (State.F1) ? 0 : (State.F0);
629}
630
631/* exetat */
632void
633OP_4E22 ()
634{
635#ifdef DEBUG
636 printf(" exetat\n");
637#endif
638 State.exe = (State.F0) ? (State.F1) : 0;
639}
640
641/* exp */
642void
643OP_15002A00 ()
644{
645 uint32 tmp, foo;
646 int i;
647
648#ifdef DEBUG
649 printf(" exp\tr%d,r%d\n",OP[0],OP[1]);
650#endif
4c38885c
MH		 651 if (((int16)State.regs[OP[1]]) >= 0)
652 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 653 else
4c38885c 654 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 655
656 foo = 0x40000000;
4c38885c 657 for (i=1;i<17;i++)
2934d1c9
MH		 658 {
659 if (tmp & foo)
660 {
661 State.regs[OP[0]] = i-1;
662 return;
663 }
4c38885c 664 foo >>= 1;
2934d1c9
MH		 665 }
666 State.regs[OP[0]] = 16;
667}
668
669/* exp */
670void
671OP_15002A02 ()
672{
4c38885c
MH		 673 int64 tmp, foo;
674 int i;
2934d1c9 675#ifdef DEBUG
4c38885c 676 printf(" exp\tr%d,a%d\n",OP[0],OP[1]);
2934d1c9 677#endif
4f425a32 678 if (SEXT40(State.a[OP[1]]) >= 0)
4c38885c
MH		 679 tmp = State.a[OP[1]];
680 else
681 tmp = ~(State.a[OP[1]]);
682
683 foo = 0x4000000000LL;
684 for (i=1;i<25;i++)
685 {
686 if (tmp & foo)
687 {
688 State.regs[OP[0]] = i-9;
689 return;
690 }
691 foo >>= 1;
692 }
693 State.regs[OP[0]] = 16;
2934d1c9
MH		 694}
695
696/* jl */
697void
698OP_4D00 ()
699{
700#ifdef DEBUG
701 printf(" jl\t%x\n",OP[0]);
702#endif
703 State.regs[13] = PC+1;
704 PC = State.regs[OP[0]];
705}
706
707/* jmp */
708void
709OP_4C00 ()
710{
711#ifdef DEBUG
712 printf(" jmp\tr%d\n",OP[0]);
713#endif
714 PC = State.regs[OP[0]];
715}
716
717/* ld */
718void
719OP_30000000 ()
720{
721#ifdef DEBUG
722 printf(" ld\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
723#endif
724 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
725}
726
727/* ld */
728void
729OP_6401 ()
730{
731#ifdef DEBUG
732 printf(" ld\tr%d,@r%d-\n",OP[0],OP[1]);
733#endif
4c38885c 734 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 735 INC_ADDR(State.regs[OP[1]],-2);
2934d1c9
MH		 736}
737
738/* ld */
739void
740OP_6001 ()
741{
742#ifdef DEBUG
743 printf(" ld\tr%d,@r%d+\n",OP[0],OP[1]);
744#endif
4c38885c 745 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 746 INC_ADDR(State.regs[OP[1]],2);
2934d1c9
MH		 747}
748
749/* ld */
750void
751OP_6000 ()
752{
753#ifdef DEBUG
754 printf(" ld\tr%d,@r%d\n",OP[0],OP[1]);
755#endif
756 State.regs[OP[0]] = RW (State.regs[OP[1]]);
757}
758
759/* ld2w */
760void
761OP_31000000 ()
762{
763#ifdef DEBUG
764 printf(" ld2w\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
765#endif
766 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
767 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
768}
769
770/* ld2w */
771void
772OP_6601 ()
773{
774#ifdef DEBUG
775 printf(" ld2w\tr%d,@r%d-\n",OP[0],OP[1]);
776#endif
4c38885c
MH		 777 State.regs[OP[0]] = RW (State.regs[OP[1]]);
778 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 779 INC_ADDR(State.regs[OP[1]],-4);
2934d1c9
MH		 780}
781
782/* ld2w */
783void
784OP_6201 ()
785{
786#ifdef DEBUG
787 printf(" ld2w\tr%d,@r%d+\n",OP[0],OP[1]);
788#endif
4c38885c
MH		 789 State.regs[OP[0]] = RW (State.regs[OP[1]]);
790 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 791 INC_ADDR(State.regs[OP[1]],4);
2934d1c9
MH		 792}
793
794/* ld2w */
795void
796OP_6200 ()
797{
798#ifdef DEBUG
799 printf(" ld2w\tr%d,@r%d\n",OP[0],OP[1]);
800#endif
4c38885c
MH		 801 State.regs[OP[0]] = RW (State.regs[OP[1]]);
802 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
2934d1c9
MH		 803}
804
805/* ldb */
806void
807OP_38000000 ()
808{
809#ifdef DEBUG
810 printf(" ldb\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
811#endif
812 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
813 SEXT8 (State.regs[OP[0]]);
814}
815
816/* ldb */
817void
818OP_7000 ()
819{
820#ifdef DEBUG
821 printf(" ldb\tr%d,@r%d\n",OP[0],OP[1]);
822#endif
823 State.regs[OP[0]] = RB (State.regs[OP[1]]);
824 SEXT8 (State.regs[OP[0]]);
825}
826
827/* ldi.s */
828void
829OP_4001 ()
830{
831#ifdef DEBUG
832 printf(" ldi.s\tr%d,%x\n",OP[0],SEXT4(OP[1]));
833#endif
834 State.regs[OP[0]] = SEXT4(OP[1]);
835}
836
837/* ldi.l */
838void
839OP_20000000 ()
840{
841#ifdef DEBUG
842 printf(" ldi.l\tr%d,%d\t;0x%x\n",OP[0],OP[1],OP[1]);
843#endif
844 State.regs[OP[0]] = OP[1];
845}
846
847/* ldub */
848void
849OP_39000000 ()
850{
851#ifdef DEBUG
852 printf(" ldub\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
853#endif
854 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
855}
856
857/* ldub */
858void
859OP_7200 ()
860{
861#ifdef DEBUG
862 printf(" ldub\tr%d,@r%d\n",OP[0],OP[1]);
863#endif
864 State.regs[OP[0]] = RB (State.regs[OP[1]]);
865}
866
867/* mac */
868void
869OP_2A00 ()
870{
4c38885c 871 int64 tmp;
2934d1c9 872#ifdef DEBUG
4c38885c 873 printf(" mac\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 874#endif
4f425a32 875 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 876
877 if (State.FX)
4f425a32 878 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 879
880 if (State.ST && tmp > MAX32)
881 tmp = MAX32;
882
4f425a32 883 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 884 if (State.ST)
885 {
886 if (tmp > MAX32)
887 State.a[OP[0]] = MAX32;
888 else if (tmp < MIN32)
889 State.a[OP[0]] = MIN32;
890 else
4f425a32 891 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 892 }
893 else
4f425a32 894 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 895}
896
897/* macsu */
898void
899OP_1A00 ()
900{
4f425a32 901 int64 tmp;
2934d1c9 902#ifdef DEBUG
4f425a32 903 printf(" macsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 904#endif
4f425a32
MH		 905 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
906 if (State.FX)
907 tmp = SEXT40( (tmp << 1) & MASK40);
908
909 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
2934d1c9
MH		 910}
911
912/* macu */
913void
914OP_3A00 ()
915{
4f425a32 916 int64 tmp;
2934d1c9 917#ifdef DEBUG
4f425a32 918 printf(" macu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 919#endif
4f425a32
MH		 920 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
921 if (State.FX)
922 tmp = SEXT40( (tmp << 1) & MASK40);
923 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
2934d1c9
MH		 924}
925
926/* max */
927void
928OP_2600 ()
929{
930#ifdef DEBUG
931 printf(" max\tr%d,r%d\n",OP[0],OP[1]);
932#endif
933 State.F1 = State.F0;
934 if (State.regs[OP[1]] > State.regs[OP[0]])
935 {
936 State.regs[OP[0]] = State.regs[OP[1]];
937 State.F0 = 1;
938 }
939 else
940 State.F0 = 0;
941}
942
943/* max */
944void
945OP_3600 ()
946{
4f425a32 947 int64 tmp;
2934d1c9 948#ifdef DEBUG
4f425a32 949 printf(" max\ta%d,r%d\n",OP[0],OP[1]);
2934d1c9 950#endif
4f425a32
MH		 951 State.F1 = State.F0;
952 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
953 if (tmp > SEXT40(State.a[OP[0]]))
954 {
955 State.a[OP[0]] = tmp & MASK40;
956 State.F0 = 1;
957 }
958 else
959 State.F0 = 0;
2934d1c9
MH		 960}
961
962/* max */
963void
964OP_3602 ()
965{
966#ifdef DEBUG
4f425a32 967 printf(" max\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 968#endif
4f425a32
MH		 969 State.F1 = State.F0;
970 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
971 {
972 State.a[OP[0]] = State.a[OP[1]];
973 State.F0 = 1;
974 }
975 else
976 State.F0 = 0;
2934d1c9
MH		 977}
978
4f425a32 979
2934d1c9
MH		 980/* min */
981void
982OP_2601 ()
983{
984#ifdef DEBUG
985 printf(" min\tr%d,r%d\n",OP[0],OP[1]);
986#endif
987 State.F1 = State.F0;
988 if (State.regs[OP[1]] < State.regs[OP[0]])
989 {
990 State.regs[OP[0]] = State.regs[OP[1]];
991 State.F0 = 1;
992 }
993 else
994 State.F0 = 0;
995}
996
997/* min */
998void
999OP_3601 ()
1000{
4f425a32 1001 int64 tmp;
2934d1c9 1002#ifdef DEBUG
4f425a32 1003 printf(" min\ta%d,r%d\n",OP[0],OP[1]);
2934d1c9 1004#endif
4f425a32
MH		 1005 State.F1 = State.F0;
1006 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1007 if (tmp < SEXT40(State.a[OP[0]]))
1008 {
1009 State.a[OP[0]] = tmp & MASK40;
1010 State.F0 = 1;
1011 }
1012 else
1013 State.F0 = 0;
2934d1c9
MH		 1014}
1015
1016/* min */
1017void
1018OP_3603 ()
1019{
1020#ifdef DEBUG
4f425a32 1021 printf(" min\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 1022#endif
4f425a32
MH		 1023 State.F1 = State.F0;
1024 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1025 {
1026 State.a[OP[0]] = State.a[OP[1]];
1027 State.F0 = 1;
1028 }
1029 else
1030 State.F0 = 0;
2934d1c9
MH		 1031}
1032
1033/* msb */
1034void
1035OP_2800 ()
1036{
4f425a32 1037 int64 tmp;
2934d1c9 1038#ifdef DEBUG
4f425a32 1039 printf(" msb\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1040#endif
4f425a32
MH		 1041 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1042
1043 if (State.FX)
1044 tmp = SEXT40 ((tmp << 1) & MASK40);
1045
1046 if (State.ST && tmp > MAX32)
1047 tmp = MAX32;
1048
1049 tmp = SEXT40(State.a[OP[0]]) - tmp;
1050 if (State.ST)
1051 {
1052 if (tmp > MAX32)
1053 State.a[OP[0]] = MAX32;
1054 else if (tmp < MIN32)
1055 State.a[OP[0]] = MIN32;
1056 else
1057 State.a[OP[0]] = tmp & MASK40;
1058 }
1059 else
1060 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1061}
1062
1063/* msbsu */
1064void
1065OP_1800 ()
1066{
4f425a32 1067 int64 tmp;
2934d1c9 1068#ifdef DEBUG
4f425a32 1069 printf(" msbsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1070#endif
4f425a32
MH		 1071 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1072 if (State.FX)
1073 tmp = SEXT40( (tmp << 1) & MASK40);
1074
1075 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
2934d1c9
MH		 1076}
1077
1078/* msbu */
1079void
1080OP_3800 ()
1081{
4f425a32 1082 int64 tmp;
2934d1c9 1083#ifdef DEBUG
4f425a32 1084 printf(" msbu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1085#endif
4f425a32
MH		 1086 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1087 if (State.FX)
1088 tmp = SEXT40( (tmp << 1) & MASK40);
1089
1090 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
2934d1c9
MH		 1091}
1092
1093/* mul */
1094void
1095OP_2E00 ()
1096{
1097#ifdef DEBUG
1098 printf(" mul\tr%d,r%d\n",OP[0],OP[1]);
1099#endif
1100 State.regs[OP[0]] *= State.regs[OP[1]];
1101}
1102
1103/* mulx */
1104void
1105OP_2C00 ()
1106{
4f425a32 1107 int64 tmp;
2934d1c9 1108#ifdef DEBUG
4f425a32 1109 printf(" mulx\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1110#endif
4f425a32
MH		 1111 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1112
1113 if (State.FX)
1114 tmp = SEXT40 ((tmp << 1) & MASK40);
1115
1116 if (State.ST && tmp > MAX32)
1117 State.a[OP[0]] = MAX32;
1118 else
1119 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1120}
1121
1122/* mulxsu */
1123void
1124OP_1C00 ()
1125{
4f425a32 1126 int64 tmp;
2934d1c9 1127#ifdef DEBUG
4f425a32 1128 printf(" mulxsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1129#endif
4f425a32
MH		 1130 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1131
1132 if (State.FX)
1133 tmp <<= 1;
1134
1135 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1136}
1137
1138/* mulxu */
1139void
1140OP_3C00 ()
1141{
4f425a32 1142 int64 tmp;
2934d1c9 1143#ifdef DEBUG
4f425a32 1144 printf(" mulxu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
2934d1c9 1145#endif
4f425a32
MH		 1146 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1147
1148 if (State.FX)
1149 tmp <<= 1;
1150
1151 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1152}
1153
1154/* mv */
1155void
1156OP_4000 ()
1157{
1158#ifdef DEBUG
1159 printf(" mv\tr%d,r%d\n",OP[0],OP[1]);
1160#endif
1161 State.regs[OP[0]] = State.regs[OP[1]];
1162}
1163
1164/* mv2w */
1165void
1166OP_5000 ()
1167{
1168#ifdef DEBUG
1169 printf(" mv2w\tr%d,r%d\n",OP[0],OP[1]);
1170#endif
1171 State.regs[OP[0]] = State.regs[OP[1]];
1172 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1173}
1174
1175/* mv2wfac */
1176void
1177OP_3E00 ()
1178{
1179#ifdef DEBUG
1180 printf(" mv2wfac\tr%d,a%d\n",OP[0],OP[1]);
1181#endif
1182 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1183 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1184}
1185
1186/* mv2wtac */
1187void
1188OP_3E01 ()
1189{
1190#ifdef DEBUG
1191 printf(" mv2wtac\tr%d,a%d\n",OP[0],OP[1]);
1192#endif
4f425a32 1193 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
2934d1c9
MH		 1194}
1195
1196/* mvac */
1197void
1198OP_3E03 ()
1199{
1200#ifdef DEBUG
1201 printf(" mvac\ta%d,a%d\n",OP[0],OP[1]);
1202#endif
1203 State.a[OP[0]] = State.a[OP[1]];
1204}
1205
1206/* mvb */
1207void
1208OP_5400 ()
1209{
1210#ifdef DEBUG
1211 printf(" mvb\tr%d,r%d\n",OP[0],OP[1]);
1212#endif
1213 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1214}
1215
1216/* mvf0f */
1217void
1218OP_4400 ()
1219{
1220#ifdef DEBUG
1221 printf(" mvf0f\tr%d,r%d\n",OP[0],OP[1]);
1222#endif
1223 if (State.F0 == 0)
1224 State.regs[OP[0]] = State.regs[OP[1]];
1225}
1226
1227/* mvf0t */
1228void
1229OP_4401 ()
1230{
1231#ifdef DEBUG
1232 printf(" mvf0t\tr%d,r%d\n",OP[0],OP[1]);
1233#endif
1234 if (State.F0)
1235 State.regs[OP[0]] = State.regs[OP[1]];
1236}
1237
1238/* mvfacg */
1239void
1240OP_1E04 ()
1241{
1242#ifdef DEBUG
1243 printf(" mvfacg\tr%d,a%d\n",OP[0],OP[1]);
1244#endif
1245 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1246}
1247
1248/* mvfachi */
1249void
1250OP_1E00 ()
1251{
1252#ifdef DEBUG
1253 printf(" mvfachi\tr%d,a%d\n",OP[0],OP[1]);
1254#endif
1255 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1256}
1257
1258/* mvfaclo */
1259void
1260OP_1E02 ()
1261{
1262#ifdef DEBUG
1263 printf(" mvfaclo\tr%d,a%d\n",OP[0],OP[1]);
1264#endif
1265 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1266}
1267
1268/* mvfc */
1269void
1270OP_5200 ()
1271{
1272#ifdef DEBUG
1273 printf(" mvfc\tr%d,cr%d\n",OP[0],OP[1]);
1274#endif
1275 if (OP[1] == 0)
1276 {
1277 /* PSW is treated specially */
1278 PSW = 0;
1279 if (State.SM) PSW |= 0x8000;
1280 if (State.EA) PSW |= 0x2000;
1281 if (State.DB) PSW |= 0x1000;
1282 if (State.IE) PSW |= 0x400;
1283 if (State.RP) PSW |= 0x200;
1284 if (State.MD) PSW |= 0x100;
1285 if (State.FX) PSW |= 0x80;
1286 if (State.ST) PSW |= 0x40;
1287 if (State.F0) PSW |= 8;
1288 if (State.F1) PSW |= 4;
1289 if (State.C) PSW |= 1;
1290 }
1291 State.regs[OP[0]] = State.cregs[OP[1]];
1292}
1293
1294/* mvtacg */
1295void
1296OP_1E41 ()
1297{
1298#ifdef DEBUG
1299 printf(" mvtacg\tr%d,a%d\n",OP[0],OP[1]);
1300#endif
1301 State.a[OP[1]] &= MASK32;
1302 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1303}
1304
1305/* mvtachi */
1306void
1307OP_1E01 ()
1308{
1309 uint16 tmp;
1310#ifdef DEBUG
1311 printf(" mvtachi\tr%d,a%d\n",OP[0],OP[1]);
1312#endif
1313 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1314 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
2934d1c9
MH		 1315}
1316
1317/* mvtaclo */
1318void
1319OP_1E21 ()
1320{
1321#ifdef DEBUG
1322 printf(" mvtaclo\tr%d,a%d\n",OP[0],OP[1]);
1323#endif
4f425a32 1324 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
2934d1c9
MH		 1325}
1326
1327/* mvtc */
1328void
1329OP_5600 ()
1330{
1331#ifdef DEBUG
1332 printf(" mvtc\tr%d,cr%d\n",OP[0],OP[1]);
1333#endif
1334 State.cregs[OP[1]] = State.regs[OP[0]];
1335 if (OP[1] == 0)
1336 {
1337 /* PSW is treated specially */
1338 State.SM = (PSW & 0x8000) ? 1 : 0;
1339 State.EA = (PSW & 0x2000) ? 1 : 0;
1340 State.DB = (PSW & 0x1000) ? 1 : 0;
1341 State.IE = (PSW & 0x400) ? 1 : 0;
1342 State.RP = (PSW & 0x200) ? 1 : 0;
1343 State.MD = (PSW & 0x100) ? 1 : 0;
1344 State.FX = (PSW & 0x80) ? 1 : 0;
1345 State.ST = (PSW & 0x40) ? 1 : 0;
1346 State.F0 = (PSW & 8) ? 1 : 0;
1347 State.F1 = (PSW & 4) ? 1 : 0;
1348 State.C = PSW & 1;
1349 if (State.ST && !State.FX)
1350 {
1351 fprintf (stderr,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC<<2);
4f425a32 1352 State.exception = SIGILL;
2934d1c9
MH		 1353 }
1354 }
1355}
1356
1357/* mvub */
1358void
1359OP_5401 ()
1360{
1361#ifdef DEBUG
1362 printf(" mvub\tr%d,r%d\n",OP[0],OP[1]);
1363#endif
1364 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1365}
1366
1367/* neg */
1368void
1369OP_4605 ()
1370{
1371#ifdef DEBUG
1372 printf(" neg\tr%d\n",OP[0]);
1373#endif
1374 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1375}
1376
1377/* neg */
1378void
1379OP_5605 ()
1380{
1381 int64 tmp;
1382#ifdef DEBUG
1383 printf(" neg\ta%d\n",OP[0]);
1384#endif
4f425a32 1385 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1386 if (State.ST)
1387 {
4c38885c 1388 if ( tmp > MAX32)
2934d1c9 1389 State.a[OP[0]] = MAX32;
4c38885c 1390 else if (tmp < MIN32)
2934d1c9
MH		 1391 State.a[OP[0]] = MIN32;
1392 else
4f425a32 1393 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1394 }
1395 else
4f425a32 1396 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1397}
1398
1399
1400/* nop */
1401void
1402OP_5E00 ()
1403{
1404}
1405
1406/* not */
1407void
1408OP_4603 ()
1409{
1410#ifdef DEBUG
1411 printf(" not\tr%d\n",OP[0]);
1412#endif
1413 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1414}
1415
1416/* or */
1417void
1418OP_800 ()
1419{
1420#ifdef DEBUG
1421 printf(" or\tr%d,r%d\n",OP[0],OP[1]);
1422#endif
1423 State.regs[OP[0]] |= State.regs[OP[1]];
1424}
1425
1426/* or3 */
1427void
1428OP_4000000 ()
1429{
1430#ifdef DEBUG
1431 printf(" or3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
1432#endif
1433 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1434}
1435
1436/* rac */
1437void
1438OP_5201 ()
1439{
1440 int64 tmp;
1441 int shift = SEXT3 (OP[2]);
1442#ifdef DEBUG
1443 printf(" rac\tr%d,a%d,%d\n",OP[0],OP[1],shift);
1444#endif
166acb9f
MH		 1445 if (OP[1] != 0)
1446 {
1447 fprintf (stderr,"ERROR at PC 0x%x: instruction only valid for A0\n",PC<<2);
1448 State.exception = SIGILL;
1449 }
1450
2934d1c9
MH		 1451 State.F1 = State.F0;
1452 if (shift >=0)
1453 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1454 else
1455 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f
MH		 1456 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1457 printf("tmp=0x%llx\n",tmp);
1458 /*
4c38885c 1459 if (tmp > MAX32)
2934d1c9
MH		 1460 {
1461 State.regs[OP[0]] = 0x7fff;
1462 State.regs[OP[0]+1] = 0xffff;
1463 State.F0 = 1;
1464 }
4c38885c 1465 else if (tmp < MIN32)
2934d1c9
MH		 1466 {
1467 State.regs[OP[0]] = 0x8000;
1468 State.regs[OP[0]+1] = 0;
1469 State.F0 = 1;
1470 }
1471 else
166acb9f 1472 */
2934d1c9
MH		 1473 {
1474 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1475 State.regs[OP[0]+1] = tmp & 0xffff;
1476 State.F0 = 0;
1477 }
1478}
1479
1480/* rachi */
1481void
1482OP_4201 ()
1483{
4c38885c
MH		 1484 int64 tmp;
1485 int shift = SEXT3 (OP[2]);
2934d1c9 1486#ifdef DEBUG
4c38885c 1487 printf(" rachi\tr%d,a%d,%d\n",OP[0],OP[1],shift);
2934d1c9 1488#endif
4c38885c
MH		 1489 State.F1 = State.F0;
1490 if (shift >=0)
166acb9f 1491 tmp = SEXT44 (State.a[1]) << shift;
4c38885c 1492 else
166acb9f 1493 tmp = SEXT44 (State.a[1]) >> -shift;
4c38885c 1494 tmp += 0x8000;
166acb9f
MH		 1495 printf("tmp=0x%llx\n",tmp);
1496 /*
4c38885c
MH		 1497 if (tmp > MAX32)
1498 {
1499 State.regs[OP[0]] = 0x7fff;
1500 State.F0 = 1;
1501 }
1502 else if (tmp < 0xfff80000000LL)
1503 {
1504 State.regs[OP[0]] = 0x8000;
1505 State.F0 = 1;
1506 }
1507 else
166acb9f 1508 */
4c38885c
MH		 1509 {
1510 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1511 State.F0 = 0;
1512 }
2934d1c9
MH		 1513}
1514
1515/* rep */
1516void
1517OP_27000000 ()
1518{
1519#ifdef DEBUG
1520 printf(" rep\tr%d,0x%x\n",OP[0],OP[1]);
1521#endif
1522 RPT_S = PC + 1;
1523 RPT_E = PC + OP[1];
1524 RPT_C = State.regs[OP[0]];
1525 State.RP = 1;
1526 if (RPT_C == 0)
1527 {
1528 fprintf (stderr, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1529 State.exception = SIGILL;
2934d1c9 1530 }
4c38885c
MH		 1531 if (OP[1] < 4)
1532 {
1533 fprintf (stderr, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1534 State.exception = SIGILL;
4c38885c 1535 }
2934d1c9
MH		 1536}
1537
1538/* repi */
1539void
1540OP_2F000000 ()
1541{
1542#ifdef DEBUG
1543 printf(" repi\t%d,0x%x\n",OP[0],OP[1]);
1544#endif
1545 RPT_S = PC + 1;
1546 RPT_E = PC + OP[1];
1547 RPT_C = OP[0];
1548 State.RP = 1;
1549 if (RPT_C == 0)
1550 {
4c38885c 1551 fprintf (stderr, "ERROR: repi with count=0 is illegal.\n");
4f425a32 1552 State.exception = SIGILL;
4c38885c
MH		 1553 }
1554 if (OP[1] < 4)
1555 {
1556 fprintf (stderr, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 1557 State.exception = SIGILL;
2934d1c9
MH		 1558 }
1559}
1560
1561/* rtd */
1562void
1563OP_5F60 ()
1564{
4c38885c 1565 printf(" rtd - NOT IMPLEMENTED\n");
2934d1c9
MH		 1566}
1567
1568/* rte */
1569void
1570OP_5F40 ()
1571{
1572#ifdef DEBUG
4c38885c 1573 printf(" rte\n");
2934d1c9 1574#endif
4c38885c
MH		 1575 PC = BPC;
1576 PSW = BPSW;
2934d1c9
MH		 1577}
1578
1579/* sadd */
1580void
1581OP_1223 ()
1582{
4c38885c 1583 int64 tmp;
2934d1c9 1584#ifdef DEBUG
4c38885c 1585 printf(" sadd\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 1586#endif
4f425a32 1587 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 1588 if (State.ST)
1589 {
1590 if (tmp > MAX32)
1591 State.a[OP[0]] = MAX32;
1592 else if (tmp < MIN32)
1593 State.a[OP[0]] = MIN32;
1594 else
4f425a32 1595 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1596 }
1597 else
4f425a32 1598 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1599}
1600
1601/* setf0f */
1602void
1603OP_4611 ()
1604{
1605#ifdef DEBUG
4c38885c 1606 printf(" setf0f\tr%d\n",OP[0]);
2934d1c9 1607#endif
4c38885c 1608 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
2934d1c9
MH		 1609}
1610
1611/* setf0t */
1612void
1613OP_4613 ()
1614{
1615#ifdef DEBUG
4c38885c 1616 printf(" setf0t\tr%d\n",OP[0]);
2934d1c9 1617#endif
4c38885c 1618 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
2934d1c9
MH		 1619}
1620
1621/* sleep */
1622void
1623OP_5FC0 ()
1624{
1625#ifdef DEBUG
4c38885c 1626 printf(" sleep\n");
2934d1c9 1627#endif
4c38885c 1628 State.IE = 1;
2934d1c9
MH		 1629}
1630
1631/* sll */
1632void
1633OP_2200 ()
1634{
1635#ifdef DEBUG
1636 printf(" sll\tr%d,r%d\n",OP[0],OP[1]);
1637#endif
1638 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
1639}
1640
1641/* sll */
1642void
1643OP_3200 ()
1644{
4c38885c 1645 int64 tmp;
2934d1c9 1646#ifdef DEBUG
4c38885c 1647 printf(" sll\ta%d,r%d\n",OP[0],OP[1]);
2934d1c9 1648#endif
4c38885c
MH		 1649 if (State.regs[OP[1]] & 31 <= 16)
1650 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
1651
1652 if (State.ST)
1653 {
1654 if (tmp > MAX32)
1655 State.a[OP[0]] = MAX32;
1656 else if (tmp < 0xffffff80000000LL)
1657 State.a[OP[0]] = MIN32;
1658 else
1659 State.a[OP[0]] = tmp & MASK40;
1660 }
1661 else
1662 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1663}
1664
1665/* slli */
1666void
1667OP_2201 ()
1668{
1669#ifdef DEBUG
1670 printf(" slli\tr%d,%d\n",OP[0],OP[1]);
1671#endif
1672 State.regs[OP[0]] <<= OP[1];
1673}
1674
1675/* slli */
1676void
1677OP_3201 ()
1678{
4c38885c 1679 int64 tmp;
4f425a32
MH		 1680
1681 if (OP[1] == 0)
1682 OP[1] = 16;
2934d1c9 1683#ifdef DEBUG
4c38885c 1684 printf(" slli\ta%d,%d\n",OP[0],OP[1]);
2934d1c9 1685#endif
4f425a32
MH		 1686
1687 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 1688
1689 if (State.ST)
1690 {
1691 if (tmp > MAX32)
1692 State.a[OP[0]] = MAX32;
1693 else if (tmp < 0xffffff80000000LL)
1694 State.a[OP[0]] = MIN32;
1695 else
1696 State.a[OP[0]] = tmp & MASK40;
1697 }
1698 else
1699 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1700}
1701
1702/* slx */
1703void
1704OP_460B ()
1705{
1706 uint16 tmp;
1707#ifdef DEBUG
1708 printf(" slx\tr%d\n",OP[0]);
1709#endif
1710 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
1711}
1712
1713/* sra */
1714void
1715OP_2400 ()
1716{
1717#ifdef DEBUG
1718 printf(" sra\tr%d,r%d\n",OP[0],OP[1]);
1719#endif
1720 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
1721}
1722
1723/* sra */
1724void
1725OP_3400 ()
1726{
1727#ifdef DEBUG
4c38885c 1728 printf(" sra\ta%d,r%d\n",OP[0],OP[1]);
2934d1c9 1729#endif
4c38885c
MH		 1730 if (State.regs[OP[1]] & 31 <= 16)
1731 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2934d1c9
MH		 1732}
1733
1734/* srai */
1735void
1736OP_2401 ()
1737{
1738#ifdef DEBUG
1739 printf(" srai\tr%d,%d\n",OP[0],OP[1]);
1740#endif
1741 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
1742}
1743
1744/* srai */
1745void
1746OP_3401 ()
1747{
4f425a32
MH		 1748 if (OP[1] == 0)
1749 OP[1] = 16;
2934d1c9 1750#ifdef DEBUG
4c38885c 1751 printf(" srai\ta%d,%d\n",OP[0],OP[1]);
2934d1c9 1752#endif
4c38885c 1753 State.a[OP[0]] >>= OP[1];
2934d1c9
MH		 1754}
1755
1756/* srl */
1757void
1758OP_2000 ()
1759{
1760#ifdef DEBUG
1761 printf(" srl\tr%d,r%d\n",OP[0],OP[1]);
1762#endif
1763 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
1764}
1765
1766/* srl */
1767void
1768OP_3000 ()
1769{
1770#ifdef DEBUG
4c38885c 1771 printf(" srl\ta%d,r%d\n",OP[0],OP[1]);
2934d1c9 1772#endif
4c38885c
MH		 1773 if (State.regs[OP[1]] & 31 <= 16)
1774 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2934d1c9
MH		 1775}
1776
1777/* srli */
1778void
1779OP_2001 ()
1780{
1781#ifdef DEBUG
1782printf(" srli\tr%d,%d\n",OP[0],OP[1]);
1783#endif
1784 State.regs[OP[0]] >>= OP[1];
1785}
1786
1787/* srli */
1788void
1789OP_3001 ()
1790{
4f425a32
MH		 1791 if (OP[1] == 0)
1792 OP[1] = 16;
2934d1c9 1793#ifdef DEBUG
4c38885c 1794 printf(" srli\ta%d,%d\n",OP[0],OP[1]);
2934d1c9 1795#endif
4c38885c 1796 State.a[OP[0]] >>= OP[1];
2934d1c9
MH		 1797}
1798
1799/* srx */
1800void
1801OP_4609 ()
1802{
1803 uint16 tmp;
1804#ifdef DEBUG
1805 printf(" srx\tr%d\n",OP[0]);
1806#endif
1807 tmp = State.F0 << 15;
1808 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
1809}
1810
1811/* st */
1812void
1813OP_34000000 ()
1814{
1815#ifdef DEBUG
1816 printf(" st\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
1817#endif
1818 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
1819}
1820
1821/* st */
1822void
1823OP_6800 ()
1824{
1825#ifdef DEBUG
1826 printf(" st\tr%d,@r%d\n",OP[0],OP[1]);
1827#endif
1828 SW (State.regs[OP[1]], State.regs[OP[0]]);
1829}
1830
1831/* st */
1832void
1833OP_6C1F ()
1834{
1835#ifdef DEBUG
4c38885c 1836 printf(" st\tr%d,@-r%d\n",OP[0],OP[1]);
2934d1c9 1837#endif
4c38885c
MH		 1838 if ( OP[1] != 15 )
1839 {
1840 fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 1841 State.exception = SIGILL;
1842 return;
4c38885c
MH		 1843 }
1844 State.regs[OP[1]] -= 2;
1845 SW (State.regs[OP[1]], State.regs[OP[0]]);
2934d1c9
MH		 1846}
1847
1848/* st */
1849void
1850OP_6801 ()
1851{
1852#ifdef DEBUG
4c38885c 1853 printf(" st\tr%d,@r%d+\n",OP[0],OP[1]);
2934d1c9 1854#endif
4c38885c 1855 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 1856 INC_ADDR (State.regs[OP[1]],2);
2934d1c9
MH		 1857}
1858
1859/* st */
1860void
1861OP_6C01 ()
1862{
1863#ifdef DEBUG
4c38885c 1864 printf(" st\tr%d,@r%d-\n",OP[0],OP[1]);
2934d1c9 1865#endif
4c38885c 1866 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 1867 INC_ADDR (State.regs[OP[1]],-2);
2934d1c9
MH		 1868}
1869
1870/* st2w */
1871void
1872OP_35000000 ()
1873{
1874#ifdef DEBUG
4c38885c 1875 printf(" st2w\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
2934d1c9 1876#endif
4f425a32
MH		 1877 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
1878 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2934d1c9
MH		 1879}
1880
1881/* st2w */
1882void
1883OP_6A00 ()
1884{
1885#ifdef DEBUG
4c38885c 1886 printf(" st2w\tr%d,@r%d\n",OP[0],OP[1]);
2934d1c9 1887#endif
4c38885c
MH		 1888 SW (State.regs[OP[1]], State.regs[OP[0]]);
1889 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2934d1c9
MH		 1890}
1891
1892/* st2w */
1893void
1894OP_6E1F ()
1895{
1896#ifdef DEBUG
4c38885c 1897 printf(" st2w\tr%d,@-r%d\n",OP[0],OP[1]);
2934d1c9 1898#endif
4c38885c
MH		 1899 if ( OP[1] != 15 )
1900 {
1901 fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 1902 State.exception = SIGILL;
1903 return;
4c38885c
MH		 1904 }
1905 State.regs[OP[1]] -= 4;
1906 SW (State.regs[OP[1]], State.regs[OP[0]]);
1907 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2934d1c9
MH		 1908}
1909
1910/* st2w */
1911void
1912OP_6A01 ()
1913{
1914#ifdef DEBUG
4c38885c 1915 printf(" st2w\tr%d,r%d+\n",OP[0],OP[1]);
2934d1c9 1916#endif
4c38885c
MH		 1917 SW (State.regs[OP[1]], State.regs[OP[0]]);
1918 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 1919 INC_ADDR (State.regs[OP[1]],4);
2934d1c9
MH		 1920}
1921
1922/* st2w */
1923void
1924OP_6E01 ()
1925{
1926#ifdef DEBUG
4c38885c 1927 printf(" st2w\tr%d,r%d-\n",OP[0],OP[1]);
2934d1c9 1928#endif
4c38885c
MH		 1929 SW (State.regs[OP[1]], State.regs[OP[0]]);
1930 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 1931 INC_ADDR (State.regs[OP[1]],-4);
2934d1c9
MH		 1932}
1933
1934/* stb */
1935void
1936OP_3C000000 ()
1937{
1938#ifdef DEBUG
4c38885c 1939 printf(" stb\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
2934d1c9 1940#endif
4f425a32 1941 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2934d1c9
MH		 1942}
1943
1944/* stb */
1945void
1946OP_7800 ()
1947{
1948#ifdef DEBUG
4c38885c 1949 printf(" stb\tr%d,@r%d\n",OP[0],OP[1]);
2934d1c9 1950#endif
4c38885c 1951 SB (State.regs[OP[1]], State.regs[OP[0]]);
2934d1c9
MH		 1952}
1953
1954/* stop */
1955void
1956OP_5FE0 ()
1957{
1958#ifdef DEBUG
1959 printf(" stop\n");
1960#endif
4f425a32 1961 State.exception = SIGQUIT;
2934d1c9
MH		 1962}
1963
1964/* sub */
1965void
1966OP_0 ()
4c38885c
MH		 1967{
1968 int32 tmp;
1969#ifdef DEBUG
1970 printf(" sub\tr%d,r%d\n",OP[0],OP[1]);
1971#endif
1972 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
1973 State.C = (tmp & 0xffff0000) ? 1 : 0;
1974 State.regs[OP[0]] = tmp & 0xffff;
1975}
1976
1977/* sub */
1978void
1979OP_1001 ()
1980{
4f425a32 1981 int64 tmp;
4c38885c
MH		 1982#ifdef DEBUG
1983 printf(" sub\ta%d,r%d\n",OP[0],OP[1]);
1984#endif
4f425a32
MH		 1985 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
1986 if (State.ST)
1987 {
1988 if ( tmp > MAX32)
1989 State.a[OP[0]] = MAX32;
1990 else if ( tmp < MIN32)
1991 State.a[OP[0]] = MIN32;
1992 else
1993 State.a[OP[0]] = tmp & MASK40;
1994 }
1995 else
1996 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1997}
1998
1999/* sub */
2000
2001void
2002OP_1003 ()
2934d1c9 2003{
4f425a32 2004 int64 tmp;
2934d1c9 2005#ifdef DEBUG
4c38885c 2006 printf(" sub\ta%d,a%d\n",OP[0],OP[1]);
2934d1c9 2007#endif
4f425a32
MH		 2008 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2009 if (State.ST)
2010 {
2011 if (tmp > MAX32)
2012 State.a[OP[0]] = MAX32;
2013 else if ( tmp < MIN32)
2014 State.a[OP[0]] = MIN32;
2015 else
2016 State.a[OP[0]] = tmp & MASK40;
2017 }
2018 else
2019 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 2020}
2021
2022/* sub2w */
2023void
2024OP_1000 ()
2025{
4c38885c
MH		 2026 int64 tmp;
2027 int32 a,b;
2934d1c9 2028#ifdef DEBUG
4c38885c 2029 printf(" sub2w\tr%d,r%d\n",OP[0],OP[1]);
2934d1c9 2030#endif
4c38885c
MH		 2031
2032 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2033 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2034 tmp = a-b;
2035 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2036 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2037 State.regs[OP[0]+1] = tmp & 0xffff;
2934d1c9
MH		 2038}
2039
2040/* subac3 */
2041void
2042OP_17000000 ()
2043{
4f425a32 2044 int64 tmp;
2934d1c9 2045#ifdef DEBUG
4f425a32 2046 printf(" subac3\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 2047#endif
4f425a32
MH		 2048 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2049 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2050 State.regs[OP[0]+1] = tmp & 0xffff;
2934d1c9
MH		 2051}
2052
2053/* subac3 */
2054void
2055OP_17000002 ()
2056{
4f425a32 2057 int64 tmp;
2934d1c9 2058#ifdef DEBUG
4f425a32 2059 printf(" subac3\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 2060#endif
4f425a32
MH		 2061 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2062 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2063 State.regs[OP[0]+1] = tmp & 0xffff;
2934d1c9
MH		 2064}
2065
2066/* subac3s */
2067void
2068OP_17001000 ()
2069{
4f425a32 2070 int64 tmp;
2934d1c9 2071#ifdef DEBUG
4f425a32 2072 printf(" subac3s\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 2073#endif
4f425a32
MH		 2074 State.F1 = State.F0;
2075 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2076 if ( tmp > MAX32)
2077 {
2078 State.regs[OP[0]] = 0x7fff;
2079 State.regs[OP[0]+1] = 0xffff;
2080 State.F0 = 1;
2081 }
2082 else if (tmp < MIN32)
2083 {
2084 State.regs[OP[0]] = 0x8000;
2085 State.regs[OP[0]+1] = 0;
2086 State.F0 = 1;
2087 }
2088 else
2089 {
2090 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2091 State.regs[OP[0]+1] = tmp & 0xffff;
2092 State.F0 = 0;
2093 }
2934d1c9
MH		 2094}
2095
2096/* subac3s */
2097void
2098OP_17001002 ()
2099{
4f425a32 2100 int64 tmp;
2934d1c9 2101#ifdef DEBUG
4f425a32 2102 printf(" subac3s\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2934d1c9 2103#endif
4f425a32
MH		 2104 State.F1 = State.F0;
2105 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2106 if ( tmp > MAX32)
2107 {
2108 State.regs[OP[0]] = 0x7fff;
2109 State.regs[OP[0]+1] = 0xffff;
2110 State.F0 = 1;
2111 }
2112 else if (tmp < MIN32)
2113 {
2114 State.regs[OP[0]] = 0x8000;
2115 State.regs[OP[0]+1] = 0;
2116 State.F0 = 1;
2117 }
2118 else
2119 {
2120 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2121 State.regs[OP[0]+1] = tmp & 0xffff;
2122 State.F0 = 0;
2123 }
2934d1c9
MH		 2124}
2125
2126/* subi */
2127void
2128OP_1 ()
2129{
4c38885c 2130 int32 tmp;
4f425a32
MH		 2131 if (OP[1] == 0)
2132 OP[1] = 16;
2934d1c9 2133#ifdef DEBUG
4c38885c 2134 printf(" subi\tr%d,%d\n",OP[0],OP[1]);
2934d1c9 2135#endif
4c38885c
MH		 2136 tmp = (int16)State.regs[OP[0]] - OP[1];
2137 State.C = (tmp & 0xffff0000) ? 1 : 0;
2138 State.regs[OP[0]] = tmp & 0xffff;
2934d1c9
MH		 2139}
2140
2141/* trap */
2142void
2143OP_5F00 ()
2144{
2145#ifdef DEBUG
2146 printf(" trap\t%d\n",OP[0]);
2147#endif
2148
4f425a32 2149 /* for now, trap is used for simulating IO */
2934d1c9
MH		 2150
2151 if (OP[0] == 0)
2152 {
2153 char *fstr = State.regs[2] + State.imem;
2154 printf (fstr,State.regs[3],State.regs[4],State.regs[5]);
2155 }
2156 else if (OP[0] == 1 )
2157 {
2158 char *fstr = State.regs[2] + State.imem;
2159 puts (fstr);
2160 }
2161}
2162
2163/* tst0i */
2164void
2165OP_7000000 ()
2166{
2167#ifdef DEBUG
4c38885c 2168 printf(" tst0i\tr%d,0x%x\n",OP[0],OP[1]);
2934d1c9 2169#endif
4c38885c 2170 State.F1 = State.F0;
4f425a32 2171 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2934d1c9
MH		 2172}
2173
2174/* tst1i */
2175void
2176OP_F000000 ()
2177{
2178#ifdef DEBUG
4c38885c 2179 printf(" tst1i\tr%d,0x%x\n",OP[0],OP[1]);
2934d1c9 2180#endif
4c38885c 2181 State.F1 = State.F0;
4f425a32 2182 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2934d1c9
MH		 2183}
2184
2185/* wait */
2186void
2187OP_5F80 ()
2188{
2189#ifdef DEBUG
4c38885c 2190 printf(" wait\n");
2934d1c9 2191#endif
4c38885c 2192 State.IE = 1;
2934d1c9
MH		 2193}
2194
2195/* xor */
2196void
2197OP_A00 ()
2198{
2199#ifdef DEBUG
4c38885c 2200 printf(" xor\tr%d,r%d\n",OP[0],OP[1]);
2934d1c9 2201#endif
4c38885c 2202 State.regs[OP[0]] ^= State.regs[OP[1]];
2934d1c9
MH		 2203}
2204
2205/* xor3 */
2206void
2207OP_5000000 ()
2208{
2209#ifdef DEBUG
4c38885c 2210 printf(" xor3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
2934d1c9 2211#endif
4c38885c 2212 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
2934d1c9
MH		 2213}
2214
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