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import gdb-1999-11-16 snapshot
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
c906108c
SS		 1#include "config.h"
2
3#include <signal.h>
4#include <errno.h>
5#include <sys/types.h>
6#include <sys/stat.h>
7#ifdef HAVE_UNISTD_H
8#include <unistd.h>
9#endif
10
11#include "d10v_sim.h"
12#include "simops.h"
13#include "targ-vals.h"
14
15extern char *strrchr ();
16
17enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
30 OP_FLAG_OUTPUT,
31 OP_CONSTANT16,
32 OP_CONSTANT8,
33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
cff3e48b 37 OP_MEMREF3,
c906108c
SS		 38 OP_POSTDEC,
39 OP_POSTINC,
40 OP_PREDEC,
41 OP_R0,
42 OP_R1,
43 OP_R2,
44};
45
46
47enum {
48 PSW_MASK = (PSW_SM_BIT
49 | PSW_EA_BIT
50 | PSW_DB_BIT
c906108c
SS		 51 | PSW_IE_BIT
52 | PSW_RP_BIT
53 | PSW_MD_BIT
54 | PSW_FX_BIT
55 | PSW_ST_BIT
56 | PSW_F0_BIT
57 | PSW_F1_BIT
58 | PSW_C_BIT),
4ce44c66
JM		 59 /* The following bits in the PSW _can't_ be set by instructions such
60 as mvtc. */
61 PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
c906108c
SS		 62};
63
64reg_t
4ce44c66 65move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
c906108c
SS		 66{
67 /* A MASK bit is set when the corresponding bit in the CR should
68 be left alone */
69 /* This assumes that (VAL & MASK) == 0 */
70 switch (cr)
71 {
72 case PSW_CR:
4ce44c66
JM		 73 if (psw_hw_p)
74 val &= PSW_HW_MASK;
75 else
76 val &= PSW_MASK;
c906108c
SS		 77 if ((mask & PSW_SM_BIT) == 0)
78 {
4ce44c66
JM		 79 int new_psw_sm = (val & PSW_SM_BIT) != 0;
80 /* save old SP */
81 SET_HELD_SP (PSW_SM, GPR (SP_IDX));
82 if (PSW_SM != new_psw_sm)
83 /* restore new SP */
84 SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
c906108c
SS		 85 }
86 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
87 {
88 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
89 {
90 (*d10v_callback->printf_filtered)
91 (d10v_callback,
92 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
93 PC<<2);
94 State.exception = SIGILL;
95 }
96 }
97 /* keep an up-to-date psw around for tracing */
98 State.trace.psw = (State.trace.psw & mask) | val;
99 break;
100 case BPSW_CR:
101 case DPSW_CR:
4ce44c66
JM		 102 /* Just like PSW, mask things like DM out. */
103 if (psw_hw_p)
104 val &= PSW_HW_MASK;
105 else
106 val &= PSW_MASK;
c906108c
SS		 107 break;
108 case MOD_S_CR:
109 case MOD_E_CR:
110 val &= ~1;
111 break;
112 default:
113 break;
114 }
115 /* only issue an update if the register is being changed */
116 if ((State.cregs[cr] & ~mask) != val)
117 SLOT_PEND_MASK (State.cregs[cr], mask, val);
118 return val;
119}
120
121#ifdef DEBUG
122static void trace_input_func PARAMS ((char *name,
123 enum op_types in1,
124 enum op_types in2,
125 enum op_types in3));
126
127#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
128
129#ifndef SIZE_INSTRUCTION
130#define SIZE_INSTRUCTION 8
131#endif
132
133#ifndef SIZE_OPERANDS
134#define SIZE_OPERANDS 18
135#endif
136
137#ifndef SIZE_VALUES
138#define SIZE_VALUES 13
139#endif
140
141#ifndef SIZE_LOCATION
142#define SIZE_LOCATION 20
143#endif
144
145#ifndef SIZE_PC
146#define SIZE_PC 6
147#endif
148
149#ifndef SIZE_LINE_NUMBER
150#define SIZE_LINE_NUMBER 4
151#endif
152
153static void
154trace_input_func (name, in1, in2, in3)
155 char *name;
156 enum op_types in1;
157 enum op_types in2;
158 enum op_types in3;
159{
160 char *comma;
161 enum op_types in[3];
162 int i;
163 char buf[1024];
164 char *p;
165 long tmp;
166 char *type;
167 const char *filename;
168 const char *functionname;
169 unsigned int linenumber;
170 bfd_vma byte_pc;
171
172 if ((d10v_debug & DEBUG_TRACE) == 0)
173 return;
174
175 switch (State.ins_type)
176 {
177 default:
178 case INS_UNKNOWN: type = " ?"; break;
179 case INS_LEFT: type = " L"; break;
180 case INS_RIGHT: type = " R"; break;
181 case INS_LEFT_PARALLEL: type = "*L"; break;
182 case INS_RIGHT_PARALLEL: type = "*R"; break;
183 case INS_LEFT_COND_TEST: type = "?L"; break;
184 case INS_RIGHT_COND_TEST: type = "?R"; break;
185 case INS_LEFT_COND_EXE: type = "&L"; break;
186 case INS_RIGHT_COND_EXE: type = "&R"; break;
187 case INS_LONG: type = " B"; break;
188 }
189
190 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
191 (*d10v_callback->printf_filtered) (d10v_callback,
192 "0x%.*x %s: %-*s ",
193 SIZE_PC, (unsigned)PC,
194 type,
195 SIZE_INSTRUCTION, name);
196
197 else
198 {
199 buf[0] = '\0';
200 byte_pc = decode_pc ();
201 if (text && byte_pc >= text_start && byte_pc < text_end)
202 {
203 filename = (const char *)0;
204 functionname = (const char *)0;
205 linenumber = 0;
206 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
207 &filename, &functionname, &linenumber))
208 {
209 p = buf;
210 if (linenumber)
211 {
212 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
213 p += strlen (p);
214 }
215 else
216 {
217 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
218 p += SIZE_LINE_NUMBER+2;
219 }
220
221 if (functionname)
222 {
223 sprintf (p, "%s ", functionname);
224 p += strlen (p);
225 }
226 else if (filename)
227 {
228 char *q = strrchr (filename, '/');
229 sprintf (p, "%s ", (q) ? q+1 : filename);
230 p += strlen (p);
231 }
232
233 if (*p == ' ')
234 *p = '\0';
235 }
236 }
237
238 (*d10v_callback->printf_filtered) (d10v_callback,
239 "0x%.*x %s: %-*.*s %-*s ",
240 SIZE_PC, (unsigned)PC,
241 type,
242 SIZE_LOCATION, SIZE_LOCATION, buf,
243 SIZE_INSTRUCTION, name);
244 }
245
246 in[0] = in1;
247 in[1] = in2;
248 in[2] = in3;
249 comma = "";
250 p = buf;
251 for (i = 0; i < 3; i++)
252 {
253 switch (in[i])
254 {
255 case OP_VOID:
256 case OP_R0:
257 case OP_R1:
258 case OP_R2:
259 break;
260
261 case OP_REG:
262 case OP_REG_OUTPUT:
263 case OP_DREG:
264 case OP_DREG_OUTPUT:
265 sprintf (p, "%sr%d", comma, OP[i]);
266 p += strlen (p);
267 comma = ",";
268 break;
269
270 case OP_CR:
271 case OP_CR_OUTPUT:
272 case OP_CR_REVERSE:
273 sprintf (p, "%scr%d", comma, OP[i]);
274 p += strlen (p);
275 comma = ",";
276 break;
277
278 case OP_ACCUM:
279 case OP_ACCUM_OUTPUT:
280 case OP_ACCUM_REVERSE:
281 sprintf (p, "%sa%d", comma, OP[i]);
282 p += strlen (p);
283 comma = ",";
284 break;
285
286 case OP_CONSTANT16:
287 sprintf (p, "%s%d", comma, OP[i]);
288 p += strlen (p);
289 comma = ",";
290 break;
291
292 case OP_CONSTANT8:
293 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
294 p += strlen (p);
295 comma = ",";
296 break;
297
298 case OP_CONSTANT4:
299 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
300 p += strlen (p);
301 comma = ",";
302 break;
303
304 case OP_CONSTANT3:
305 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
306 p += strlen (p);
307 comma = ",";
308 break;
309
310 case OP_MEMREF:
311 sprintf (p, "%s@r%d", comma, OP[i]);
312 p += strlen (p);
313 comma = ",";
314 break;
315
316 case OP_MEMREF2:
317 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
318 p += strlen (p);
319 comma = ",";
320 break;
321
cff3e48b
JM		 322 case OP_MEMREF3:
323 sprintf (p, "%s@%d", comma, OP[i]);
324 p += strlen (p);
325 comma = ",";
326 break;
327
c906108c
SS		 328 case OP_POSTINC:
329 sprintf (p, "%s@r%d+", comma, OP[i]);
330 p += strlen (p);
331 comma = ",";
332 break;
333
334 case OP_POSTDEC:
335 sprintf (p, "%s@r%d-", comma, OP[i]);
336 p += strlen (p);
337 comma = ",";
338 break;
339
340 case OP_PREDEC:
341 sprintf (p, "%s@-r%d", comma, OP[i]);
342 p += strlen (p);
343 comma = ",";
344 break;
345
346 case OP_FLAG:
347 case OP_FLAG_OUTPUT:
348 if (OP[i] == 0)
349 sprintf (p, "%sf0", comma);
350
351 else if (OP[i] == 1)
352 sprintf (p, "%sf1", comma);
353
354 else
355 sprintf (p, "%sc", comma);
356
357 p += strlen (p);
358 comma = ",";
359 break;
360 }
361 }
362
363 if ((d10v_debug & DEBUG_VALUES) == 0)
364 {
365 *p++ = '\n';
366 *p = '\0';
367 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
368 }
369 else
370 {
371 *p = '\0';
372 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
373
374 p = buf;
375 for (i = 0; i < 3; i++)
376 {
377 buf[0] = '\0';
378 switch (in[i])
379 {
380 case OP_VOID:
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
382 break;
383
384 case OP_REG_OUTPUT:
385 case OP_DREG_OUTPUT:
386 case OP_CR_OUTPUT:
387 case OP_ACCUM_OUTPUT:
388 case OP_FLAG_OUTPUT:
389 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
390 break;
391
392 case OP_REG:
393 case OP_MEMREF:
394 case OP_POSTDEC:
395 case OP_POSTINC:
396 case OP_PREDEC:
397 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
398 (uint16) GPR (OP[i]));
399 break;
400
cff3e48b
JM		 401 case OP_MEMREF3:
402 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
403 break;
404
c906108c
SS		 405 case OP_DREG:
406 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
407 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
408 break;
409
410 case OP_CR:
411 case OP_CR_REVERSE:
412 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
413 (uint16) CREG (OP[i]));
414 break;
415
416 case OP_ACCUM:
417 case OP_ACCUM_REVERSE:
418 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
419 ((int)(ACC (OP[i]) >> 32) & 0xff),
420 ((unsigned long) ACC (OP[i])) & 0xffffffff);
421 break;
422
423 case OP_CONSTANT16:
424 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
425 (uint16)OP[i]);
426 break;
427
428 case OP_CONSTANT4:
429 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
430 (uint16)SEXT4(OP[i]));
431 break;
432
433 case OP_CONSTANT8:
434 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
435 (uint16)SEXT8(OP[i]));
436 break;
437
438 case OP_CONSTANT3:
439 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
440 (uint16)SEXT3(OP[i]));
441 break;
442
443 case OP_FLAG:
444 if (OP[i] == 0)
445 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
446 PSW_F0 != 0);
447
448 else if (OP[i] == 1)
449 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
450 PSW_F1 != 0);
451
452 else
453 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
454 PSW_C != 0);
455
456 break;
457
458 case OP_MEMREF2:
459 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
460 (uint16)OP[i]);
461 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
462 (uint16)GPR (OP[i + 1]));
463 i++;
464 break;
465
466 case OP_R0:
467 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
468 (uint16) GPR (0));
469 break;
470
471 case OP_R1:
472 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
473 (uint16) GPR (1));
474 break;
475
476 case OP_R2:
477 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
478 (uint16) GPR (2));
479 break;
480
481 }
482 }
483 }
484
485 (*d10v_callback->flush_stdout) (d10v_callback);
486}
487
488static void
489do_trace_output_flush (void)
490{
491 (*d10v_callback->flush_stdout) (d10v_callback);
492}
493
494static void
495do_trace_output_finish (void)
496{
497 (*d10v_callback->printf_filtered) (d10v_callback,
498 " F0=%d F1=%d C=%d\n",
499 (State.trace.psw & PSW_F0_BIT) != 0,
500 (State.trace.psw & PSW_F1_BIT) != 0,
501 (State.trace.psw & PSW_C_BIT) != 0);
502 (*d10v_callback->flush_stdout) (d10v_callback);
503}
504
505static void
506trace_output_40 (uint64 val)
507{
508 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
509 {
510 (*d10v_callback->printf_filtered) (d10v_callback,
511 " :: %*s0x%.2x%.8lx",
512 SIZE_VALUES - 12,
513 "",
514 ((int)(val >> 32) & 0xff),
515 ((unsigned long) val) & 0xffffffff);
516 do_trace_output_finish ();
517 }
518}
519
520static void
521trace_output_32 (uint32 val)
522{
523 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
524 {
525 (*d10v_callback->printf_filtered) (d10v_callback,
526 " :: %*s0x%.8x",
527 SIZE_VALUES - 10,
528 "",
529 (int) val);
530 do_trace_output_finish ();
531 }
532}
533
534static void
535trace_output_16 (uint16 val)
536{
537 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
538 {
539 (*d10v_callback->printf_filtered) (d10v_callback,
540 " :: %*s0x%.4x",
541 SIZE_VALUES - 6,
542 "",
543 (int) val);
544 do_trace_output_finish ();
545 }
546}
547
548static void
549trace_output_void ()
550{
551 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
552 {
553 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
554 do_trace_output_flush ();
555 }
556}
557
558static void
559trace_output_flag ()
560{
561 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
562 {
563 (*d10v_callback->printf_filtered) (d10v_callback,
564 " :: %*s",
565 SIZE_VALUES,
566 "");
567 do_trace_output_finish ();
568 }
569}
570
571
572
573
574#else
575#define trace_input(NAME, IN1, IN2, IN3)
576#define trace_output(RESULT)
577#endif
578
579/* abs */
580void
581OP_4607 ()
582{
583 int16 tmp;
584 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
585 SET_PSW_F1 (PSW_F0);
586 tmp = GPR(OP[0]);
587 if (tmp < 0)
588 {
589 tmp = - tmp;
590 SET_PSW_F0 (1);
591 }
592 else
593 SET_PSW_F0 (0);
594 SET_GPR (OP[0], tmp);
595 trace_output_16 (tmp);
596}
597
598/* abs */
599void
600OP_5607 ()
601{
602 int64 tmp;
603 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
604 SET_PSW_F1 (PSW_F0);
605
606 tmp = SEXT40 (ACC (OP[0]));
607 if (tmp < 0 )
608 {
609 tmp = - tmp;
610 if (PSW_ST)
611 {
612 if (tmp > SEXT40(MAX32))
613 tmp = (MAX32);
614 else if (tmp < SEXT40(MIN32))
615 tmp = (MIN32);
616 else
617 tmp = (tmp & MASK40);
618 }
619 else
620 tmp = (tmp & MASK40);
621 SET_PSW_F0 (1);
622 }
623 else
624 {
625 tmp = (tmp & MASK40);
626 SET_PSW_F0 (0);
627 }
628 SET_ACC (OP[0], tmp);
629 trace_output_40 (tmp);
630}
631
632/* add */
633void
634OP_200 ()
635{
636 uint16 a = GPR (OP[0]);
637 uint16 b = GPR (OP[1]);
638 uint16 tmp = (a + b);
639 trace_input ("add", OP_REG, OP_REG, OP_VOID);
640 SET_PSW_C (a > tmp);
641 SET_GPR (OP[0], tmp);
642 trace_output_16 (tmp);
643}
644
645/* add */
646void
647OP_1201 ()
648{
649 int64 tmp;
650 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
651
652 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
653 if (PSW_ST)
654 {
655 if (tmp > SEXT40(MAX32))
656 tmp = (MAX32);
657 else if (tmp < SEXT40(MIN32))
658 tmp = (MIN32);
659 else
660 tmp = (tmp & MASK40);
661 }
662 else
663 tmp = (tmp & MASK40);
664 SET_ACC (OP[0], tmp);
665 trace_output_40 (tmp);
666}
667
668/* add */
669void
670OP_1203 ()
671{
672 int64 tmp;
673 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
674
675 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
676 if (PSW_ST)
677 {
678 if (tmp > SEXT40(MAX32))
679 tmp = (MAX32);
680 else if (tmp < SEXT40(MIN32))
681 tmp = (MIN32);
682 else
683 tmp = (tmp & MASK40);
684 }
685 else
686 tmp = (tmp & MASK40);
687 SET_ACC (OP[0], tmp);
688 trace_output_40 (tmp);
689}
690
691/* add2w */
692void
693OP_1200 ()
694{
695 uint32 tmp;
696 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
697 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
698 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
699 tmp = a + b;
700 SET_PSW_C (tmp < a);
701 SET_GPR (OP[0] + 0, (tmp >> 16));
702 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
703 trace_output_32 (tmp);
704}
705
706/* add3 */
707void
708OP_1000000 ()
709{
710 uint16 a = GPR (OP[1]);
711 uint16 b = OP[2];
712 uint16 tmp = (a + b);
713 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
714 SET_PSW_C (tmp < a);
715 SET_GPR (OP[0], tmp);
716 trace_output_16 (tmp);
717}
718
719/* addac3 */
720void
721OP_17000200 ()
722{
723 int64 tmp;
724 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
725
726 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
727 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
728 SET_GPR (OP[0] + 1, (tmp & 0xffff));
729 trace_output_32 (tmp);
730}
731
732/* addac3 */
733void
734OP_17000202 ()
735{
736 int64 tmp;
737 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
738
739 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
740 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
741 SET_GPR (OP[0] + 1, tmp & 0xffff);
742 trace_output_32 (tmp);
743}
744
745/* addac3s */
746void
747OP_17001200 ()
748{
749 int64 tmp;
750 SET_PSW_F1 (PSW_F0);
751
752 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
753 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
754 if (tmp > SEXT40(MAX32))
755 {
756 tmp = (MAX32);
757 SET_PSW_F0 (1);
758 }
759 else if (tmp < SEXT40(MIN32))
760 {
761 tmp = (MIN32);
762 SET_PSW_F0 (1);
763 }
764 else
765 {
766 SET_PSW_F0 (0);
767 }
768 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
769 SET_GPR (OP[0] + 1, (tmp & 0xffff));
770 trace_output_32 (tmp);
771}
772
773/* addac3s */
774void
775OP_17001202 ()
776{
777 int64 tmp;
778 SET_PSW_F1 (PSW_F0);
779
780 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
781 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
782 if (tmp > SEXT40(MAX32))
783 {
784 tmp = (MAX32);
785 SET_PSW_F0 (1);
786 }
787 else if (tmp < SEXT40(MIN32))
788 {
789 tmp = (MIN32);
790 SET_PSW_F0 (1);
791 }
792 else
793 {
794 SET_PSW_F0 (0);
795 }
796 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
797 SET_GPR (OP[0] + 1, (tmp & 0xffff));
798 trace_output_32 (tmp);
799}
800
801/* addi */
802void
803OP_201 ()
804{
805 uint16 a = GPR (OP[0]);
806 uint16 b;
807 uint16 tmp;
808 if (OP[1] == 0)
809 OP[1] = 16;
810 b = OP[1];
811 tmp = (a + b);
812 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
813 SET_PSW_C (tmp < a);
814 SET_GPR (OP[0], tmp);
815 trace_output_16 (tmp);
816}
817
818/* and */
819void
820OP_C00 ()
821{
822 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
823 trace_input ("and", OP_REG, OP_REG, OP_VOID);
824 SET_GPR (OP[0], tmp);
825 trace_output_16 (tmp);
826}
827
828/* and3 */
829void
830OP_6000000 ()
831{
832 uint16 tmp = GPR (OP[1]) & OP[2];
833 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
834 SET_GPR (OP[0], tmp);
835 trace_output_16 (tmp);
836}
837
838/* bclri */
839void
840OP_C01 ()
841{
842 int16 tmp;
843 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
844 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
845 SET_GPR (OP[0], tmp);
846 trace_output_16 (tmp);
847}
848
849/* bl.s */
850void
851OP_4900 ()
852{
853 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
854 SET_GPR (13, PC + 1);
855 JMP( PC + SEXT8 (OP[0]));
856 trace_output_void ();
857}
858
859/* bl.l */
860void
861OP_24800000 ()
862{
863 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
864 SET_GPR (13, (PC + 1));
865 JMP (PC + OP[0]);
866 trace_output_void ();
867}
868
869/* bnoti */
870void
871OP_A01 ()
872{
873 int16 tmp;
874 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
875 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
876 SET_GPR (OP[0], tmp);
877 trace_output_16 (tmp);
878}
879
880/* bra.s */
881void
882OP_4800 ()
883{
884 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
885 JMP (PC + SEXT8 (OP[0]));
886 trace_output_void ();
887}
888
889/* bra.l */
890void
891OP_24000000 ()
892{
893 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
894 JMP (PC + OP[0]);
895 trace_output_void ();
896}
897
898/* brf0f.s */
899void
900OP_4A00 ()
901{
902 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
903 if (!PSW_F0)
904 JMP (PC + SEXT8 (OP[0]));
905 trace_output_flag ();
906}
907
908/* brf0f.l */
909void
910OP_25000000 ()
911{
912 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
913 if (!PSW_F0)
914 JMP (PC + OP[0]);
915 trace_output_flag ();
916}
917
918/* brf0t.s */
919void
920OP_4B00 ()
921{
922 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
923 if (PSW_F0)
924 JMP (PC + SEXT8 (OP[0]));
925 trace_output_flag ();
926}
927
928/* brf0t.l */
929void
930OP_25800000 ()
931{
932 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
933 if (PSW_F0)
934 JMP (PC + OP[0]);
935 trace_output_flag ();
936}
937
938/* bseti */
939void
940OP_801 ()
941{
942 int16 tmp;
943 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
944 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
945 SET_GPR (OP[0], tmp);
946 trace_output_16 (tmp);
947}
948
949/* btsti */
950void
951OP_E01 ()
952{
953 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
954 SET_PSW_F1 (PSW_F0);
955 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
956 trace_output_flag ();
957}
958
959/* clrac */
960void
961OP_5601 ()
962{
963 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
964 SET_ACC (OP[0], 0);
965 trace_output_40 (0);
966}
967
968/* cmp */
969void
970OP_600 ()
971{
972 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
973 SET_PSW_F1 (PSW_F0);
974 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
975 trace_output_flag ();
976}
977
978/* cmp */
979void
980OP_1603 ()
981{
982 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
983 SET_PSW_F1 (PSW_F0);
984 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
985 trace_output_flag ();
986}
987
988/* cmpeq */
989void
990OP_400 ()
991{
992 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
993 SET_PSW_F1 (PSW_F0);
994 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
995 trace_output_flag ();
996}
997
998/* cmpeq */
999void
1000OP_1403 ()
1001{
1002 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1003 SET_PSW_F1 (PSW_F0);
1004 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1005 trace_output_flag ();
1006}
1007
1008/* cmpeqi.s */
1009void
1010OP_401 ()
1011{
1012 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1013 SET_PSW_F1 (PSW_F0);
1014 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1015 trace_output_flag ();
1016}
1017
1018/* cmpeqi.l */
1019void
1020OP_2000000 ()
1021{
1022 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1023 SET_PSW_F1 (PSW_F0);
1024 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1025 trace_output_flag ();
1026}
1027
1028/* cmpi.s */
1029void
1030OP_601 ()
1031{
1032 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1033 SET_PSW_F1 (PSW_F0);
1034 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1035 trace_output_flag ();
1036}
1037
1038/* cmpi.l */
1039void
1040OP_3000000 ()
1041{
1042 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1043 SET_PSW_F1 (PSW_F0);
1044 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1045 trace_output_flag ();
1046}
1047
1048/* cmpu */
1049void
1050OP_4600 ()
1051{
1052 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1053 SET_PSW_F1 (PSW_F0);
1054 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1055 trace_output_flag ();
1056}
1057
1058/* cmpui */
1059void
1060OP_23000000 ()
1061{
1062 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1063 SET_PSW_F1 (PSW_F0);
1064 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1065 trace_output_flag ();
1066}
1067
1068/* cpfg */
1069void
1070OP_4E09 ()
1071{
1072 uint8 val;
1073
1074 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1075
1076 if (OP[1] == 0)
1077 val = PSW_F0;
1078 else if (OP[1] == 1)
1079 val = PSW_F1;
1080 else
1081 val = PSW_C;
1082 if (OP[0] == 0)
1083 SET_PSW_F0 (val);
1084 else
1085 SET_PSW_F1 (val);
1086
1087 trace_output_flag ();
1088}
1089
1090/* dbt */
1091void
1092OP_5F20 ()
1093{
1094 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1095
1096 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1097 The conditional below is for either of the instruction pairs
1098 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1099 where the dbt instruction should be interpreted.
1100
1101 The module `sim-break' provides a more effective mechanism for
1102 detecting GDB planted breakpoints. The code below may,
1103 eventually, be changed to use that mechanism. */
1104
1105 if (State.ins_type == INS_LEFT
1106 || State.ins_type == INS_RIGHT)
1107 {
1108 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1109 SET_DPC (PC + 1);
1110 SET_DPSW (PSW);
4ce44c66 1111 SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
c906108c
SS		 1112 JMP (DBT_VECTOR_START);
1113 trace_output_void ();
1114 }
1115 else
1116 {
1117 State.exception = SIGTRAP;
1118 }
1119}
1120
1121/* divs */
1122void
1123OP_14002800 ()
1124{
1125 uint16 foo, tmp, tmpf;
1126 uint16 hi;
1127 uint16 lo;
1128
1129 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1130 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1131 tmp = (int16)foo - (int16)(GPR (OP[1]));
1132 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1133 hi = ((tmpf == 1) ? tmp : foo);
1134 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1135 SET_GPR (OP[0] + 0, hi);
1136 SET_GPR (OP[0] + 1, lo);
1137 trace_output_32 (((uint32) hi << 16) | lo);
1138}
1139
1140/* exef0f */
1141void
1142OP_4E04 ()
1143{
1144 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1145 State.exe = (PSW_F0 == 0);
1146 trace_output_flag ();
1147}
1148
1149/* exef0t */
1150void
1151OP_4E24 ()
1152{
1153 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1154 State.exe = (PSW_F0 != 0);
1155 trace_output_flag ();
1156}
1157
1158/* exef1f */
1159void
1160OP_4E40 ()
1161{
1162 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1163 State.exe = (PSW_F1 == 0);
1164 trace_output_flag ();
1165}
1166
1167/* exef1t */
1168void
1169OP_4E42 ()
1170{
1171 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1172 State.exe = (PSW_F1 != 0);
1173 trace_output_flag ();
1174}
1175
1176/* exefaf */
1177void
1178OP_4E00 ()
1179{
1180 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1181 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1182 trace_output_flag ();
1183}
1184
1185/* exefat */
1186void
1187OP_4E02 ()
1188{
1189 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1190 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1191 trace_output_flag ();
1192}
1193
1194/* exetaf */
1195void
1196OP_4E20 ()
1197{
1198 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1199 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1200 trace_output_flag ();
1201}
1202
1203/* exetat */
1204void
1205OP_4E22 ()
1206{
1207 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1208 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1209 trace_output_flag ();
1210}
1211
1212/* exp */
1213void
1214OP_15002A00 ()
1215{
1216 uint32 tmp, foo;
1217 int i;
1218
1219 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1220 if (((int16)GPR (OP[1])) >= 0)
1221 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1222 else
1223 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1224
1225 foo = 0x40000000;
1226 for (i=1;i<17;i++)
1227 {
1228 if (tmp & foo)
1229 {
1230 SET_GPR (OP[0], (i - 1));
1231 trace_output_16 (i - 1);
1232 return;
1233 }
1234 foo >>= 1;
1235 }
1236 SET_GPR (OP[0], 16);
1237 trace_output_16 (16);
1238}
1239
1240/* exp */
1241void
1242OP_15002A02 ()
1243{
1244 int64 tmp, foo;
1245 int i;
1246
1247 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1248 tmp = SEXT40(ACC (OP[1]));
1249 if (tmp < 0)
1250 tmp = ~tmp & MASK40;
1251
1252 foo = 0x4000000000LL;
1253 for (i=1;i<25;i++)
1254 {
1255 if (tmp & foo)
1256 {
1257 SET_GPR (OP[0], i - 9);
1258 trace_output_16 (i - 9);
1259 return;
1260 }
1261 foo >>= 1;
1262 }
1263 SET_GPR (OP[0], 16);
1264 trace_output_16 (16);
1265}
1266
1267/* jl */
1268void
1269OP_4D00 ()
1270{
1271 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1272 SET_GPR (13, PC + 1);
1273 JMP (GPR (OP[0]));
1274 trace_output_void ();
1275}
1276
1277/* jmp */
1278void
1279OP_4C00 ()
1280{
1281 trace_input ("jmp", OP_REG,
1282 (OP[0] == 13) ? OP_R0 : OP_VOID,
1283 (OP[0] == 13) ? OP_R1 : OP_VOID);
1284
1285 JMP (GPR (OP[0]));
1286 trace_output_void ();
1287}
1288
1289/* ld */
1290void
1291OP_30000000 ()
1292{
1293 uint16 tmp;
1294 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1295 tmp = RW (OP[1] + GPR (OP[2]));
1296 SET_GPR (OP[0], tmp);
1297 trace_output_16 (tmp);
1298}
1299
1300/* ld */
1301void
1302OP_6401 ()
1303{
1304 uint16 tmp;
1305 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1306 tmp = RW (GPR (OP[1]));
1307 SET_GPR (OP[0], tmp);
1308 if (OP[0] != OP[1])
1309 INC_ADDR (OP[1], -2);
1310 trace_output_16 (tmp);
1311}
1312
1313/* ld */
1314void
1315OP_6001 ()
1316{
1317 uint16 tmp;
1318 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1319 tmp = RW (GPR (OP[1]));
1320 SET_GPR (OP[0], tmp);
1321 if (OP[0] != OP[1])
1322 INC_ADDR (OP[1], 2);
1323 trace_output_16 (tmp);
1324}
1325
1326/* ld */
1327void
1328OP_6000 ()
1329{
1330 uint16 tmp;
1331 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1332 tmp = RW (GPR (OP[1]));
1333 SET_GPR (OP[0], tmp);
1334 trace_output_16 (tmp);
1335}
1336
cff3e48b
JM		 1337/* ld */
1338void
1339OP_32010000 ()
1340{
1341 uint16 tmp;
1342
1343 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1344 tmp = RW (OP[1]);
1345 SET_GPR (OP[0], tmp);
1346 trace_output_16 (tmp);
1347}
1348
c906108c
SS		 1349/* ld2w */
1350void
1351OP_31000000 ()
1352{
1353 int32 tmp;
1354 uint16 addr = GPR (OP[2]);
1355 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1356 tmp = RLW (OP[1] + addr);
1357 SET_GPR32 (OP[0], tmp);
1358 trace_output_32 (tmp);
1359}
1360
1361/* ld2w */
1362void
1363OP_6601 ()
1364{
1365 uint16 addr = GPR (OP[1]);
1366 int32 tmp;
1367 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1368 tmp = RLW (addr);
1369 SET_GPR32 (OP[0], tmp);
d4f3574e 1370 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
7a292a7a 1371 INC_ADDR (OP[1], -4);
c906108c
SS		 1372 trace_output_32 (tmp);
1373}
1374
1375/* ld2w */
1376void
1377OP_6201 ()
1378{
1379 int32 tmp;
1380 uint16 addr = GPR (OP[1]);
1381 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1382 tmp = RLW (addr);
1383 SET_GPR32 (OP[0], tmp);
d4f3574e 1384 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
7a292a7a 1385 INC_ADDR (OP[1], 4);
c906108c
SS		 1386 trace_output_32 (tmp);
1387}
1388
1389/* ld2w */
1390void
1391OP_6200 ()
1392{
1393 uint16 addr = GPR (OP[1]);
1394 int32 tmp;
1395 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1396 tmp = RLW (addr + 0);
1397 SET_GPR32 (OP[0], tmp);
1398 trace_output_32 (tmp);
1399}
1400
cff3e48b
JM		 1401/* ld2w */
1402void
1403OP_33010000 ()
1404{
1405 int32 tmp;
1406
1407 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1408 tmp = RLW (OP[1]);
1409 SET_GPR32 (OP[0], tmp);
1410 trace_output_32 (tmp);
1411}
1412
c906108c
SS		 1413/* ldb */
1414void
1415OP_38000000 ()
1416{
1417 int16 tmp;
1418 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1419 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1420 SET_GPR (OP[0], tmp);
1421 trace_output_16 (tmp);
1422}
1423
1424/* ldb */
1425void
1426OP_7000 ()
1427{
1428 int16 tmp;
1429 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1430 tmp = SEXT8 (RB (GPR (OP[1])));
1431 SET_GPR (OP[0], tmp);
1432 trace_output_16 (tmp);
1433}
1434
1435/* ldi.s */
1436void
1437OP_4001 ()
1438{
1439 int16 tmp;
1440 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1441 tmp = SEXT4 (OP[1]);
1442 SET_GPR (OP[0], tmp);
1443 trace_output_16 (tmp);
1444}
1445
1446/* ldi.l */
1447void
1448OP_20000000 ()
1449{
1450 int16 tmp;
1451 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1452 tmp = OP[1];
1453 SET_GPR (OP[0], tmp);
1454 trace_output_16 (tmp);
1455}
1456
1457/* ldub */
1458void
1459OP_39000000 ()
1460{
1461 int16 tmp;
1462 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1463 tmp = RB (OP[1] + GPR (OP[2]));
1464 SET_GPR (OP[0], tmp);
1465 trace_output_16 (tmp);
1466}
1467
1468/* ldub */
1469void
1470OP_7200 ()
1471{
1472 int16 tmp;
1473 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1474 tmp = RB (GPR (OP[1]));
1475 SET_GPR (OP[0], tmp);
1476 trace_output_16 (tmp);
1477}
1478
1479/* mac */
1480void
1481OP_2A00 ()
1482{
1483 int64 tmp;
1484
1485 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1486 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1487
1488 if (PSW_FX)
1489 tmp = SEXT40( (tmp << 1) & MASK40);
1490
1491 if (PSW_ST && tmp > SEXT40(MAX32))
1492 tmp = (MAX32);
1493
1494 tmp += SEXT40 (ACC (OP[0]));
1495 if (PSW_ST)
1496 {
1497 if (tmp > SEXT40(MAX32))
1498 tmp = (MAX32);
1499 else if (tmp < SEXT40(MIN32))
1500 tmp = (MIN32);
1501 else
1502 tmp = (tmp & MASK40);
1503 }
1504 else
1505 tmp = (tmp & MASK40);
1506 SET_ACC (OP[0], tmp);
1507 trace_output_40 (tmp);
1508}
1509
1510/* macsu */
1511void
1512OP_1A00 ()
1513{
1514 int64 tmp;
1515
1516 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1517 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1518 if (PSW_FX)
1519 tmp = SEXT40 ((tmp << 1) & MASK40);
1520 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1521 SET_ACC (OP[0], tmp);
1522 trace_output_40 (tmp);
1523}
1524
1525/* macu */
1526void
1527OP_3A00 ()
1528{
1529 uint64 tmp;
1530 uint32 src1;
1531 uint32 src2;
1532
1533 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1534 src1 = (uint16) GPR (OP[1]);
1535 src2 = (uint16) GPR (OP[2]);
1536 tmp = src1 * src2;
1537 if (PSW_FX)
1538 tmp = (tmp << 1);
1539 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1540 SET_ACC (OP[0], tmp);
1541 trace_output_40 (tmp);
1542}
1543
1544/* max */
1545void
1546OP_2600 ()
1547{
1548 int16 tmp;
1549 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1550 SET_PSW_F1 (PSW_F0);
1551 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1552 {
1553 tmp = GPR (OP[1]);
1554 SET_PSW_F0 (1);
1555 }
1556 else
1557 {
1558 tmp = GPR (OP[0]);
1559 SET_PSW_F0 (0);
1560 }
1561 SET_GPR (OP[0], tmp);
1562 trace_output_16 (tmp);
1563}
1564
1565/* max */
1566void
1567OP_3600 ()
1568{
1569 int64 tmp;
1570
1571 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1572 SET_PSW_F1 (PSW_F0);
1573 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1574 if (tmp > SEXT40 (ACC (OP[0])))
1575 {
1576 tmp = (tmp & MASK40);
1577 SET_PSW_F0 (1);
1578 }
1579 else
1580 {
1581 tmp = ACC (OP[0]);
1582 SET_PSW_F0 (0);
1583 }
1584 SET_ACC (OP[0], tmp);
1585 trace_output_40 (tmp);
1586}
1587
1588/* max */
1589void
1590OP_3602 ()
1591{
1592 int64 tmp;
1593 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1594 SET_PSW_F1 (PSW_F0);
1595 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1596 {
1597 tmp = ACC (OP[1]);
1598 SET_PSW_F0 (1);
1599 }
1600 else
1601 {
1602 tmp = ACC (OP[0]);
1603 SET_PSW_F0 (0);
1604 }
1605 SET_ACC (OP[0], tmp);
1606 trace_output_40 (tmp);
1607}
1608
1609
1610/* min */
1611void
1612OP_2601 ()
1613{
1614 int16 tmp;
1615 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1616 SET_PSW_F1 (PSW_F0);
1617 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1618 {
1619 tmp = GPR (OP[1]);
1620 SET_PSW_F0 (1);
1621 }
1622 else
1623 {
1624 tmp = GPR (OP[0]);
1625 SET_PSW_F0 (0);
1626 }
1627 SET_GPR (OP[0], tmp);
1628 trace_output_16 (tmp);
1629}
1630
1631/* min */
1632void
1633OP_3601 ()
1634{
1635 int64 tmp;
1636
1637 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1638 SET_PSW_F1 (PSW_F0);
1639 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1640 if (tmp < SEXT40(ACC (OP[0])))
1641 {
1642 tmp = (tmp & MASK40);
1643 SET_PSW_F0 (1);
1644 }
1645 else
1646 {
1647 tmp = ACC (OP[0]);
1648 SET_PSW_F0 (0);
1649 }
1650 SET_ACC (OP[0], tmp);
1651 trace_output_40 (tmp);
1652}
1653
1654/* min */
1655void
1656OP_3603 ()
1657{
1658 int64 tmp;
1659 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1660 SET_PSW_F1 (PSW_F0);
1661 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1662 {
1663 tmp = ACC (OP[1]);
1664 SET_PSW_F0 (1);
1665 }
1666 else
1667 {
1668 tmp = ACC (OP[0]);
1669 SET_PSW_F0 (0);
1670 }
1671 SET_ACC (OP[0], tmp);
1672 trace_output_40 (tmp);
1673}
1674
1675/* msb */
1676void
1677OP_2800 ()
1678{
1679 int64 tmp;
1680
1681 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1682 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1683
1684 if (PSW_FX)
1685 tmp = SEXT40 ((tmp << 1) & MASK40);
1686
1687 if (PSW_ST && tmp > SEXT40(MAX32))
1688 tmp = (MAX32);
1689
1690 tmp = SEXT40(ACC (OP[0])) - tmp;
1691 if (PSW_ST)
1692 {
1693 if (tmp > SEXT40(MAX32))
1694 tmp = (MAX32);
1695 else if (tmp < SEXT40(MIN32))
1696 tmp = (MIN32);
1697 else
1698 tmp = (tmp & MASK40);
1699 }
1700 else
1701 {
1702 tmp = (tmp & MASK40);
1703 }
1704 SET_ACC (OP[0], tmp);
1705 trace_output_40 (tmp);
1706}
1707
1708/* msbsu */
1709void
1710OP_1800 ()
1711{
1712 int64 tmp;
1713
1714 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1715 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1716 if (PSW_FX)
1717 tmp = SEXT40( (tmp << 1) & MASK40);
1718 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1719 SET_ACC (OP[0], tmp);
1720 trace_output_40 (tmp);
1721}
1722
1723/* msbu */
1724void
1725OP_3800 ()
1726{
1727 uint64 tmp;
1728 uint32 src1;
1729 uint32 src2;
1730
1731 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1732 src1 = (uint16) GPR (OP[1]);
1733 src2 = (uint16) GPR (OP[2]);
1734 tmp = src1 * src2;
1735 if (PSW_FX)
1736 tmp = (tmp << 1);
1737 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1738 SET_ACC (OP[0], tmp);
1739 trace_output_40 (tmp);
1740}
1741
1742/* mul */
1743void
1744OP_2E00 ()
1745{
1746 int16 tmp;
1747 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1748 tmp = GPR (OP[0]) * GPR (OP[1]);
1749 SET_GPR (OP[0], tmp);
1750 trace_output_16 (tmp);
1751}
1752
1753/* mulx */
1754void
1755OP_2C00 ()
1756{
1757 int64 tmp;
1758
1759 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1760 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1761
1762 if (PSW_FX)
1763 tmp = SEXT40 ((tmp << 1) & MASK40);
1764
1765 if (PSW_ST && tmp > SEXT40(MAX32))
1766 tmp = (MAX32);
1767 else
1768 tmp = (tmp & MASK40);
1769 SET_ACC (OP[0], tmp);
1770 trace_output_40 (tmp);
1771}
1772
1773/* mulxsu */
1774void
1775OP_1C00 ()
1776{
1777 int64 tmp;
1778
1779 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1780 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1781
1782 if (PSW_FX)
1783 tmp <<= 1;
1784 tmp = (tmp & MASK40);
1785 SET_ACC (OP[0], tmp);
1786 trace_output_40 (tmp);
1787}
1788
1789/* mulxu */
1790void
1791OP_3C00 ()
1792{
1793 uint64 tmp;
1794 uint32 src1;
1795 uint32 src2;
1796
1797 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1798 src1 = (uint16) GPR (OP[1]);
1799 src2 = (uint16) GPR (OP[2]);
1800 tmp = src1 * src2;
1801 if (PSW_FX)
1802 tmp <<= 1;
1803 tmp = (tmp & MASK40);
1804 SET_ACC (OP[0], tmp);
1805 trace_output_40 (tmp);
1806}
1807
1808/* mv */
1809void
1810OP_4000 ()
1811{
1812 int16 tmp;
1813 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1814 tmp = GPR (OP[1]);
1815 SET_GPR (OP[0], tmp);
1816 trace_output_16 (tmp);
1817}
1818
1819/* mv2w */
1820void
1821OP_5000 ()
1822{
1823 int32 tmp;
1824 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1825 tmp = GPR32 (OP[1]);
1826 SET_GPR32 (OP[0], tmp);
1827 trace_output_32 (tmp);
1828}
1829
1830/* mv2wfac */
1831void
1832OP_3E00 ()
1833{
1834 int32 tmp;
1835 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1836 tmp = ACC (OP[1]);
1837 SET_GPR32 (OP[0], tmp);
1838 trace_output_32 (tmp);
1839}
1840
1841/* mv2wtac */
1842void
1843OP_3E01 ()
1844{
1845 int64 tmp;
1846 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1847 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1848 SET_ACC (OP[1], tmp);
1849 trace_output_40 (tmp);
1850}
1851
1852/* mvac */
1853void
1854OP_3E03 ()
1855{
1856 int64 tmp;
1857 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1858 tmp = ACC (OP[1]);
1859 SET_ACC (OP[0], tmp);
1860 trace_output_40 (tmp);
1861}
1862
1863/* mvb */
1864void
1865OP_5400 ()
1866{
1867 int16 tmp;
1868 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1869 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1870 SET_GPR (OP[0], tmp);
1871 trace_output_16 (tmp);
1872}
1873
1874/* mvf0f */
1875void
1876OP_4400 ()
1877{
1878 int16 tmp;
1879 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1880 if (PSW_F0 == 0)
1881 {
1882 tmp = GPR (OP[1]);
1883 SET_GPR (OP[0], tmp);
1884 }
1885 else
1886 tmp = GPR (OP[0]);
1887 trace_output_16 (tmp);
1888}
1889
1890/* mvf0t */
1891void
1892OP_4401 ()
1893{
1894 int16 tmp;
1895 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1896 if (PSW_F0)
1897 {
1898 tmp = GPR (OP[1]);
1899 SET_GPR (OP[0], tmp);
1900 }
1901 else
1902 tmp = GPR (OP[0]);
1903 trace_output_16 (tmp);
1904}
1905
1906/* mvfacg */
1907void
1908OP_1E04 ()
1909{
1910 int16 tmp;
1911 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1912 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1913 SET_GPR (OP[0], tmp);
1914 trace_output_16 (tmp);
1915}
1916
1917/* mvfachi */
1918void
1919OP_1E00 ()
1920{
1921 int16 tmp;
1922 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1923 tmp = (ACC (OP[1]) >> 16);
1924 SET_GPR (OP[0], tmp);
1925 trace_output_16 (tmp);
1926}
1927
1928/* mvfaclo */
1929void
1930OP_1E02 ()
1931{
1932 int16 tmp;
1933 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1934 tmp = ACC (OP[1]);
1935 SET_GPR (OP[0], tmp);
1936 trace_output_16 (tmp);
1937}
1938
1939/* mvfc */
1940void
1941OP_5200 ()
1942{
1943 int16 tmp;
1944 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1945 tmp = CREG (OP[1]);
1946 SET_GPR (OP[0], tmp);
1947 trace_output_16 (tmp);
1948}
1949
1950/* mvtacg */
1951void
1952OP_1E41 ()
1953{
1954 int64 tmp;
1955 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1956 tmp = ((ACC (OP[1]) & MASK32)
1957 | ((int64)(GPR (OP[0]) & 0xff) << 32));
1958 SET_ACC (OP[1], tmp);
1959 trace_output_40 (tmp);
1960}
1961
1962/* mvtachi */
1963void
1964OP_1E01 ()
1965{
1966 uint64 tmp;
1967 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1968 tmp = ACC (OP[1]) & 0xffff;
1969 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
1970 SET_ACC (OP[1], tmp);
1971 trace_output_40 (tmp);
1972}
1973
1974/* mvtaclo */
1975void
1976OP_1E21 ()
1977{
1978 int64 tmp;
1979 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1980 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
1981 SET_ACC (OP[1], tmp);
1982 trace_output_40 (tmp);
1983}
1984
1985/* mvtc */
1986void
1987OP_5600 ()
1988{
1989 int16 tmp;
1990 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1991 tmp = GPR (OP[0]);
1992 tmp = SET_CREG (OP[1], tmp);
1993 trace_output_16 (tmp);
1994}
1995
1996/* mvub */
1997void
1998OP_5401 ()
1999{
2000 int16 tmp;
2001 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2002 tmp = (GPR (OP[1]) & 0xff);
2003 SET_GPR (OP[0], tmp);
2004 trace_output_16 (tmp);
2005}
2006
2007/* neg */
2008void
2009OP_4605 ()
2010{
2011 int16 tmp;
2012 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2013 tmp = - GPR (OP[0]);
2014 SET_GPR (OP[0], tmp);
2015 trace_output_16 (tmp);
2016}
2017
2018/* neg */
2019void
2020OP_5605 ()
2021{
2022 int64 tmp;
2023
2024 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2025 tmp = -SEXT40(ACC (OP[0]));
2026 if (PSW_ST)
2027 {
2028 if (tmp > SEXT40(MAX32))
2029 tmp = (MAX32);
2030 else if (tmp < SEXT40(MIN32))
2031 tmp = (MIN32);
2032 else
2033 tmp = (tmp & MASK40);
2034 }
2035 else
2036 tmp = (tmp & MASK40);
2037 SET_ACC (OP[0], tmp);
2038 trace_output_40 (tmp);
2039}
2040
2041
2042/* nop */
2043void
2044OP_5E00 ()
2045{
2046 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2047
2048 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2049 switch (State.ins_type)
2050 {
2051 default:
2052 ins_type_counters[ (int)INS_UNKNOWN ]++;
2053 break;
2054
2055 case INS_LEFT_PARALLEL:
2056 /* Don't count a parallel op that includes a NOP as a true parallel op */
2057 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2058 ins_type_counters[ (int)INS_RIGHT ]++;
2059 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2060 break;
2061
2062 case INS_LEFT:
2063 case INS_LEFT_COND_EXE:
2064 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2065 break;
2066
2067 case INS_RIGHT_PARALLEL:
2068 /* Don't count a parallel op that includes a NOP as a true parallel op */
2069 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2070 ins_type_counters[ (int)INS_LEFT ]++;
2071 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2072 break;
2073
2074 case INS_RIGHT:
2075 case INS_RIGHT_COND_EXE:
2076 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2077 break;
2078 }
2079
2080 trace_output_void ();
2081}
2082
2083/* not */
2084void
2085OP_4603 ()
2086{
2087 int16 tmp;
2088 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2089 tmp = ~GPR (OP[0]);
2090 SET_GPR (OP[0], tmp);
2091 trace_output_16 (tmp);
2092}
2093
2094/* or */
2095void
2096OP_800 ()
2097{
2098 int16 tmp;
2099 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2100 tmp = (GPR (OP[0]) | GPR (OP[1]));
2101 SET_GPR (OP[0], tmp);
2102 trace_output_16 (tmp);
2103}
2104
2105/* or3 */
2106void
2107OP_4000000 ()
2108{
2109 int16 tmp;
2110 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2111 tmp = (GPR (OP[1]) | OP[2]);
2112 SET_GPR (OP[0], tmp);
2113 trace_output_16 (tmp);
2114}
2115
2116/* rac */
2117void
2118OP_5201 ()
2119{
2120 int64 tmp;
2121 int shift = SEXT3 (OP[2]);
2122
2123 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2124 if (OP[1] != 0)
2125 {
2126 (*d10v_callback->printf_filtered) (d10v_callback,
2127 "ERROR at PC 0x%x: instruction only valid for A0\n",
2128 PC<<2);
2129 State.exception = SIGILL;
2130 }
2131
2132 SET_PSW_F1 (PSW_F0);
2133 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2134 if (shift >=0)
2135 tmp <<= shift;
2136 else
2137 tmp >>= -shift;
2138 tmp += 0x8000;
2139 tmp >>= 16; /* look at bits 0:43 */
2140 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2141 {
2142 tmp = 0x7fffffff;
2143 SET_PSW_F0 (1);
2144 }
2145 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2146 {
2147 tmp = 0x80000000;
2148 SET_PSW_F0 (1);
2149 }
2150 else
2151 {
2152 SET_PSW_F0 (0);
2153 }
2154 SET_GPR32 (OP[0], tmp);
2155 trace_output_32 (tmp);
2156}
2157
2158/* rachi */
2159void
2160OP_4201 ()
2161{
2162 signed64 tmp;
2163 int shift = SEXT3 (OP[2]);
2164
2165 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2166 SET_PSW_F1 (PSW_F0);
2167 if (shift >=0)
2168 tmp = SEXT40 (ACC (OP[1])) << shift;
2169 else
2170 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2171 tmp += 0x8000;
2172
2173 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2174 {
2175 tmp = 0x7fff;
2176 SET_PSW_F0 (1);
2177 }
2178 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2179 {
2180 tmp = 0x8000;
2181 SET_PSW_F0 (1);
2182 }
2183 else
2184 {
2185 tmp = (tmp >> 16);
2186 SET_PSW_F0 (0);
2187 }
2188 SET_GPR (OP[0], tmp);
2189 trace_output_16 (tmp);
2190}
2191
2192/* rep */
2193void
2194OP_27000000 ()
2195{
2196 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2197 SET_RPT_S (PC + 1);
2198 SET_RPT_E (PC + OP[1]);
2199 SET_RPT_C (GPR (OP[0]));
2200 SET_PSW_RP (1);
2201 if (GPR (OP[0]) == 0)
2202 {
2203 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2204 State.exception = SIGILL;
2205 }
2206 if (OP[1] < 4)
2207 {
2208 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2209 State.exception = SIGILL;
2210 }
2211 trace_output_void ();
2212}
2213
2214/* repi */
2215void
2216OP_2F000000 ()
2217{
2218 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2219 SET_RPT_S (PC + 1);
2220 SET_RPT_E (PC + OP[1]);
2221 SET_RPT_C (OP[0]);
2222 SET_PSW_RP (1);
2223 if (OP[0] == 0)
2224 {
2225 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2226 State.exception = SIGILL;
2227 }
2228 if (OP[1] < 4)
2229 {
2230 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2231 State.exception = SIGILL;
2232 }
2233 trace_output_void ();
2234}
2235
2236/* rtd */
2237void
2238OP_5F60 ()
2239{
2240 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2241 SET_CREG (PSW_CR, DPSW);
2242 JMP(DPC);
2243 trace_output_void ();
2244}
2245
2246/* rte */
2247void
2248OP_5F40 ()
2249{
2250 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2251 SET_CREG (PSW_CR, BPSW);
2252 JMP(BPC);
2253 trace_output_void ();
2254}
2255
cff3e48b
JM		 2256/* sac */
2257void OP_5209 ()
2258{
2259 int64 tmp;
2260
2261 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2262
2263 tmp = SEXT40(ACC (OP[1]));
2264
2265 SET_PSW_F1 (PSW_F0);
2266
2267 if (tmp > SEXT40(MAX32))
2268 {
2269 tmp = (MAX32);
2270 SET_PSW_F0 (1);
2271 }
2272 else if (tmp < SEXT40(MIN32))
2273 {
2274 tmp = 0x80000000;
2275 SET_PSW_F0 (1);
2276 }
2277 else
2278 {
2279 tmp = (tmp & MASK32);
2280 SET_PSW_F0 (0);
2281 }
2282
2283 SET_GPR32 (OP[0], tmp);
2284
2285 trace_output_40 (tmp);
2286}
2287
cff3e48b
JM		 2288/* sachi */
2289void
2290OP_4209 ()
2291{
2292 int64 tmp;
2293
2294 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2295
2296 tmp = SEXT40(ACC (OP[1]));
2297
2298 SET_PSW_F1 (PSW_F0);
2299
2300 if (tmp > SEXT40(MAX32))
2301 {
2302 tmp = 0x7fff;
2303 SET_PSW_F0 (1);
2304 }
2305 else if (tmp < SEXT40(MIN32))
2306 {
2307 tmp = 0x8000;
2308 SET_PSW_F0 (1);
2309 }
2310 else
2311 {
2312 tmp >>= 16;
2313 SET_PSW_F0 (0);
2314 }
2315
2316 SET_GPR (OP[0], tmp);
2317
2318 trace_output_16 (OP[0]);
2319}
2320
c906108c
SS		 2321/* sadd */
2322void
2323OP_1223 ()
2324{
2325 int64 tmp;
2326
2327 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2328 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2329 if (PSW_ST)
2330 {
2331 if (tmp > SEXT40(MAX32))
2332 tmp = (MAX32);
2333 else if (tmp < SEXT40(MIN32))
2334 tmp = (MIN32);
2335 else
2336 tmp = (tmp & MASK40);
2337 }
2338 else
2339 tmp = (tmp & MASK40);
2340 SET_ACC (OP[0], tmp);
2341 trace_output_40 (tmp);
2342}
2343
2344/* setf0f */
2345void
2346OP_4611 ()
2347{
2348 int16 tmp;
2349 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2350 tmp = ((PSW_F0 == 0) ? 1 : 0);
2351 SET_GPR (OP[0], tmp);
2352 trace_output_16 (tmp);
2353}
2354
2355/* setf0t */
2356void
2357OP_4613 ()
2358{
2359 int16 tmp;
2360 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2361 tmp = ((PSW_F0 == 1) ? 1 : 0);
2362 SET_GPR (OP[0], tmp);
2363 trace_output_16 (tmp);
2364}
2365
cff3e48b
JM		 2366/* slae */
2367void
2368OP_3220 ()
2369{
2370 int64 tmp;
2371 int16 reg;
2372
2373 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2374
5c44784c 2375 reg = SEXT16 (GPR (OP[1]));
cff3e48b
JM		 2376
2377 if (reg >= 17 || reg <= -17)
2378 {
2379 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2380 State.exception = SIGILL;
2381 return;
2382 }
2383
2384 tmp = SEXT40 (ACC (OP[0]));
2385
2386 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2387 {
5c44784c 2388 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
cff3e48b
JM		 2389 State.exception = SIGILL;
2390 return;
2391 }
2392
2393 if (reg >= 0 && reg <= 16)
2394 {
2395 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2396 if (PSW_ST)
2397 {
2398 if (tmp > SEXT40(MAX32))
2399 tmp = (MAX32);
2400 else if (tmp < SEXT40(MIN32))
2401 tmp = (MIN32);
2402 else
2403 tmp = (tmp & MASK40);
2404 }
2405 else
2406 tmp = (tmp & MASK40);
2407 }
2408 else
2409 {
2410 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2411 }
2412
2413 SET_ACC(OP[0], tmp);
2414
2415 trace_output_40(tmp);
2416}
2417
c906108c
SS		 2418/* sleep */
2419void
2420OP_5FC0 ()
2421{
2422 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2423 SET_PSW_IE (1);
2424 trace_output_void ();
2425}
2426
2427/* sll */
2428void
2429OP_2200 ()
2430{
2431 int16 tmp;
2432 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2433 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2434 SET_GPR (OP[0], tmp);
2435 trace_output_16 (tmp);
2436}
2437
2438/* sll */
2439void
2440OP_3200 ()
2441{
2442 int64 tmp;
2443 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2444 if ((GPR (OP[1]) & 31) <= 16)
2445 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2446 else
2447 {
2448 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2449 State.exception = SIGILL;
2450 return;
2451 }
2452
2453 if (PSW_ST)
2454 {
2455 if (tmp > SEXT40(MAX32))
2456 tmp = (MAX32);
2457 else if (tmp < SEXT40(MIN32))
2458 tmp = (MIN32);
2459 else
2460 tmp = (tmp & MASK40);
2461 }
2462 else
2463 tmp = (tmp & MASK40);
2464 SET_ACC (OP[0], tmp);
2465 trace_output_40 (tmp);
2466}
2467
2468/* slli */
2469void
2470OP_2201 ()
2471{
2472 int16 tmp;
2473 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2474 tmp = (GPR (OP[0]) << OP[1]);
2475 SET_GPR (OP[0], tmp);
2476 trace_output_16 (tmp);
2477}
2478
2479/* slli */
2480void
2481OP_3201 ()
2482{
2483 int64 tmp;
2484
2485 if (OP[1] == 0)
2486 OP[1] = 16;
2487
2488 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2489 tmp = SEXT40(ACC (OP[0])) << OP[1];
2490
2491 if (PSW_ST)
2492 {
2493 if (tmp > SEXT40(MAX32))
2494 tmp = (MAX32);
2495 else if (tmp < SEXT40(MIN32))
2496 tmp = (MIN32);
2497 else
2498 tmp = (tmp & MASK40);
2499 }
2500 else
2501 tmp = (tmp & MASK40);
2502 SET_ACC (OP[0], tmp);
2503 trace_output_40 (tmp);
2504}
2505
2506/* slx */
2507void
2508OP_460B ()
2509{
2510 int16 tmp;
2511 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2512 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2513 SET_GPR (OP[0], tmp);
2514 trace_output_16 (tmp);
2515}
2516
2517/* sra */
2518void
2519OP_2400 ()
2520{
2521 int16 tmp;
2522 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2523 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2524 SET_GPR (OP[0], tmp);
2525 trace_output_16 (tmp);
2526}
2527
2528/* sra */
2529void
2530OP_3400 ()
2531{
2532 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2533 if ((GPR (OP[1]) & 31) <= 16)
2534 {
2535 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2536 SET_ACC (OP[0], tmp);
2537 trace_output_40 (tmp);
2538 }
2539 else
2540 {
2541 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2542 State.exception = SIGILL;
2543 return;
2544 }
2545}
2546
2547/* srai */
2548void
2549OP_2401 ()
2550{
2551 int16 tmp;
2552 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2553 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2554 SET_GPR (OP[0], tmp);
2555 trace_output_16 (tmp);
2556}
2557
2558/* srai */
2559void
2560OP_3401 ()
2561{
2562 int64 tmp;
2563 if (OP[1] == 0)
2564 OP[1] = 16;
2565
2566 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2567 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2568 SET_ACC (OP[0], tmp);
2569 trace_output_40 (tmp);
2570}
2571
2572/* srl */
2573void
2574OP_2000 ()
2575{
2576 int16 tmp;
2577 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2578 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2579 SET_GPR (OP[0], tmp);
2580 trace_output_16 (tmp);
2581}
2582
2583/* srl */
2584void
2585OP_3000 ()
2586{
2587 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2588 if ((GPR (OP[1]) & 31) <= 16)
2589 {
2590 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2591 SET_ACC (OP[0], tmp);
2592 trace_output_40 (tmp);
2593 }
2594 else
2595 {
2596 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2597 State.exception = SIGILL;
2598 return;
2599 }
2600
2601}
2602
2603/* srli */
2604void
2605OP_2001 ()
2606{
2607 int16 tmp;
2608 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2609 tmp = (GPR (OP[0]) >> OP[1]);
2610 SET_GPR (OP[0], tmp);
2611 trace_output_16 (tmp);
2612}
2613
2614/* srli */
2615void
2616OP_3001 ()
2617{
2618 int64 tmp;
2619 if (OP[1] == 0)
2620 OP[1] = 16;
2621
2622 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2623 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2624 SET_ACC (OP[0], tmp);
2625 trace_output_40 (tmp);
2626}
2627
2628/* srx */
2629void
2630OP_4609 ()
2631{
2632 uint16 tmp;
2633 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2634 tmp = PSW_F0 << 15;
2635 tmp = ((GPR (OP[0]) >> 1) | tmp);
2636 SET_GPR (OP[0], tmp);
2637 trace_output_16 (tmp);
2638}
2639
2640/* st */
2641void
2642OP_34000000 ()
2643{
2644 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2645 SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
2646 trace_output_void ();
2647}
2648
2649/* st */
2650void
2651OP_6800 ()
2652{
2653 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2654 SW (GPR (OP[1]), GPR (OP[0]));
2655 trace_output_void ();
2656}
2657
2658/* st */
2659void
2660OP_6C1F ()
2661{
2662 uint16 addr = GPR (OP[1]) - 2;
2663 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2664 if (OP[1] != 15)
2665 {
2666 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2667 State.exception = SIGILL;
2668 return;
2669 }
2670 SW (addr, GPR (OP[0]));
2671 SET_GPR (OP[1], addr);
2672 trace_output_void ();
2673}
2674
2675/* st */
2676void
2677OP_6801 ()
2678{
2679 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2680 SW (GPR (OP[1]), GPR (OP[0]));
2681 INC_ADDR (OP[1], 2);
2682 trace_output_void ();
2683}
2684
2685/* st */
2686void
2687OP_6C01 ()
2688{
2689 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2690 if ( OP[1] == 15 )
2691 {
2692 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2693 State.exception = SIGILL;
2694 return;
2695 }
2696 SW (GPR (OP[1]), GPR (OP[0]));
2697 INC_ADDR (OP[1], -2);
2698 trace_output_void ();
2699}
2700
cff3e48b
JM		 2701/* st */
2702void
2703OP_36010000 ()
2704{
2705 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2706 SW (OP[1], GPR (OP[0]));
2707 trace_output_void ();
2708}
2709
c906108c
SS		 2710/* st2w */
2711void
2712OP_35000000 ()
2713{
2714 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2715 SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
2716 SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
2717 trace_output_void ();
2718}
2719
2720/* st2w */
2721void
2722OP_6A00 ()
2723{
2724 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2725 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2726 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2727 trace_output_void ();
2728}
2729
2730/* st2w */
2731void
2732OP_6E1F ()
2733{
2734 uint16 addr = GPR (OP[1]) - 4;
2735 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2736 if ( OP[1] != 15 )
2737 {
2738 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2739 State.exception = SIGILL;
2740 return;
2741 }
2742 SW (addr + 0, GPR (OP[0] + 0));
2743 SW (addr + 2, GPR (OP[0] + 1));
2744 SET_GPR (OP[1], addr);
2745 trace_output_void ();
2746}
2747
2748/* st2w */
2749void
2750OP_6A01 ()
2751{
2752 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2753 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2754 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2755 INC_ADDR (OP[1], 4);
2756 trace_output_void ();
2757}
2758
2759/* st2w */
2760void
2761OP_6E01 ()
2762{
2763 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2764 if ( OP[1] == 15 )
2765 {
2766 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2767 State.exception = SIGILL;
2768 return;
2769 }
2770 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2771 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2772 INC_ADDR (OP[1], -4);
2773 trace_output_void ();
2774}
2775
cff3e48b
JM		 2776/* st2w */
2777void
2778OP_37010000 ()
2779{
2780 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2781 SW (OP [1] + 0, GPR (OP[0] + 0));
2782 SW (OP [1] + 2, GPR (OP[0] + 1));
2783 trace_output_void ();
2784}
2785
c906108c
SS		 2786/* stb */
2787void
2788OP_3C000000 ()
2789{
2790 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2791 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2792 trace_output_void ();
2793}
2794
2795/* stb */
2796void
2797OP_7800 ()
2798{
2799 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2800 SB (GPR (OP[1]), GPR (OP[0]));
2801 trace_output_void ();
2802}
2803
2804/* stop */
2805void
2806OP_5FE0 ()
2807{
2808 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2809 State.exception = SIG_D10V_STOP;
2810 trace_output_void ();
2811}
2812
2813/* sub */
2814void
2815OP_0 ()
2816{
2817 uint16 a = GPR (OP[0]);
2818 uint16 b = GPR (OP[1]);
2819 uint16 tmp = (a - b);
2820 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2821 /* see ../common/sim-alu.h for a more extensive discussion on how to
2822 compute the carry/overflow bits. */
2823 SET_PSW_C (a >= b);
2824 SET_GPR (OP[0], tmp);
2825 trace_output_16 (tmp);
2826}
2827
2828/* sub */
2829void
2830OP_1001 ()
2831{
2832 int64 tmp;
2833
2834 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2835 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2836 if (PSW_ST)
2837 {
2838 if (tmp > SEXT40(MAX32))
2839 tmp = (MAX32);
2840 else if (tmp < SEXT40(MIN32))
2841 tmp = (MIN32);
2842 else
2843 tmp = (tmp & MASK40);
2844 }
2845 else
2846 tmp = (tmp & MASK40);
2847 SET_ACC (OP[0], tmp);
2848
2849 trace_output_40 (tmp);
2850}
2851
2852/* sub */
2853
2854void
2855OP_1003 ()
2856{
2857 int64 tmp;
2858
2859 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2860 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
2861 if (PSW_ST)
2862 {
2863 if (tmp > SEXT40(MAX32))
2864 tmp = (MAX32);
2865 else if (tmp < SEXT40(MIN32))
2866 tmp = (MIN32);
2867 else
2868 tmp = (tmp & MASK40);
2869 }
2870 else
2871 tmp = (tmp & MASK40);
2872 SET_ACC (OP[0], tmp);
2873
2874 trace_output_40 (tmp);
2875}
2876
2877/* sub2w */
2878void
2879OP_1000 ()
2880{
2881 uint32 tmp, a, b;
2882
2883 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2884 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
2885 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
2886 /* see ../common/sim-alu.h for a more extensive discussion on how to
2887 compute the carry/overflow bits */
2888 tmp = a - b;
2889 SET_PSW_C (a >= b);
2890 SET_GPR32 (OP[0], tmp);
2891 trace_output_32 (tmp);
2892}
2893
2894/* subac3 */
2895void
2896OP_17000000 ()
2897{
2898 int64 tmp;
2899
2900 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2901 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
2902 SET_GPR32 (OP[0], tmp);
2903 trace_output_32 (tmp);
2904}
2905
2906/* subac3 */
2907void
2908OP_17000002 ()
2909{
2910 int64 tmp;
2911
2912 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2913 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
2914 SET_GPR32 (OP[0], tmp);
2915 trace_output_32 (tmp);
2916}
2917
2918/* subac3s */
2919void
2920OP_17001000 ()
2921{
2922 int64 tmp;
2923
2924 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2925 SET_PSW_F1 (PSW_F0);
2926 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
2927 if (tmp > SEXT40(MAX32))
2928 {
2929 tmp = (MAX32);
2930 SET_PSW_F0 (1);
2931 }
2932 else if (tmp < SEXT40(MIN32))
2933 {
2934 tmp = (MIN32);
2935 SET_PSW_F0 (1);
2936 }
2937 else
2938 {
2939 SET_PSW_F0 (0);
2940 }
2941 SET_GPR32 (OP[0], tmp);
2942 trace_output_32 (tmp);
2943}
2944
2945/* subac3s */
2946void
2947OP_17001002 ()
2948{
2949 int64 tmp;
2950
2951 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2952 SET_PSW_F1 (PSW_F0);
2953 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
2954 if (tmp > SEXT40(MAX32))
2955 {
2956 tmp = (MAX32);
2957 SET_PSW_F0 (1);
2958 }
2959 else if (tmp < SEXT40(MIN32))
2960 {
2961 tmp = (MIN32);
2962 SET_PSW_F0 (1);
2963 }
2964 else
2965 {
2966 SET_PSW_F0 (0);
2967 }
2968 SET_GPR32 (OP[0], tmp);
2969 trace_output_32 (tmp);
2970}
2971
2972/* subi */
2973void
2974OP_1 ()
2975{
2976 unsigned tmp;
2977 if (OP[1] == 0)
2978 OP[1] = 16;
2979
2980 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2981 /* see ../common/sim-alu.h for a more extensive discussion on how to
2982 compute the carry/overflow bits. */
2983 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2984 tmp = ((unsigned)(unsigned16) GPR (OP[0])
2985 + (unsigned)(unsigned16) ( - OP[1]));
2986 SET_PSW_C (tmp >= (1 << 16));
2987 SET_GPR (OP[0], tmp);
2988 trace_output_16 (tmp);
2989}
2990
2991/* trap */
2992void
2993OP_5F00 ()
2994{
2995 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2996 trace_output_void ();
2997
2998 switch (OP[0])
2999 {
3000 default:
3001#if (DEBUG & DEBUG_TRAP) == 0
3002 {
3003 uint16 vec = OP[0] + TRAP_VECTOR_START;
3004 SET_BPC (PC + 1);
3005 SET_BPSW (PSW);
3006 SET_PSW (PSW & PSW_SM_BIT);
3007 JMP (vec);
3008 break;
3009 }
3010#else /* if debugging use trap to print registers */
3011 {
3012 int i;
3013 static int first_time = 1;
3014
3015 if (first_time)
3016 {
3017 first_time = 0;
3018 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
3019 for (i = 0; i < 16; i++)
3020 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
3021 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
3022 }
3023
3024 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3025
3026 for (i = 0; i < 16; i++)
3027 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3028
3029 for (i = 0; i < 2; i++)
3030 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3031 ((int)(ACC (i) >> 32) & 0xff),
3032 ((unsigned long) ACC (i)) & 0xffffffff);
3033
3034 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
3035 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3036 (*d10v_callback->flush_stdout) (d10v_callback);
3037 break;
3038 }
3039#endif
3040 case 15: /* new system call trap */
3041 /* Trap 15 is used for simulating low-level I/O */
3042 {
3043 unsigned32 result = 0;
3044 errno = 0;
3045
3046/* Registers passed to trap 0 */
3047
3048#define FUNC GPR (4) /* function number */
3049#define PARM1 GPR (0) /* optional parm 1 */
3050#define PARM2 GPR (1) /* optional parm 2 */
3051#define PARM3 GPR (2) /* optional parm 3 */
3052#define PARM4 GPR (3) /* optional parm 3 */
3053
3054/* Registers set by trap 0 */
3055
3056#define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3057#define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3058#define RETERR(X) SET_GPR (4, (X)) /* return error code */
3059
3060/* Turn a pointer in a register into a pointer into real memory. */
3061
3062#define MEMPTR(x) ((char *)(dmem_addr(x)))
3063
3064 switch (FUNC)
3065 {
3066#if !defined(__GO32__) && !defined(_WIN32)
3067 case TARGET_SYS_fork:
3068 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3069 RETVAL (fork ());
3070 trace_output_16 (result);
3071 break;
3072
3073#define getpid() 47
3074 case TARGET_SYS_getpid:
3075 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3076 RETVAL (getpid ());
3077 trace_output_16 (result);
3078 break;
3079
3080 case TARGET_SYS_kill:
3081 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3082 if (PARM1 == getpid ())
3083 {
3084 trace_output_void ();
3085 State.exception = PARM2;
3086 }
3087 else
3088 {
3089 int os_sig = -1;
3090 switch (PARM2)
3091 {
3092#ifdef SIGHUP
3093 case 1: os_sig = SIGHUP; break;
3094#endif
3095#ifdef SIGINT
3096 case 2: os_sig = SIGINT; break;
3097#endif
3098#ifdef SIGQUIT
3099 case 3: os_sig = SIGQUIT; break;
3100#endif
3101#ifdef SIGILL
3102 case 4: os_sig = SIGILL; break;
3103#endif
3104#ifdef SIGTRAP
3105 case 5: os_sig = SIGTRAP; break;
3106#endif
3107#ifdef SIGABRT
3108 case 6: os_sig = SIGABRT; break;
3109#elif defined(SIGIOT)
3110 case 6: os_sig = SIGIOT; break;
3111#endif
3112#ifdef SIGEMT
3113 case 7: os_sig = SIGEMT; break;
3114#endif
3115#ifdef SIGFPE
3116 case 8: os_sig = SIGFPE; break;
3117#endif
3118#ifdef SIGKILL
3119 case 9: os_sig = SIGKILL; break;
3120#endif
3121#ifdef SIGBUS
3122 case 10: os_sig = SIGBUS; break;
3123#endif
3124#ifdef SIGSEGV
3125 case 11: os_sig = SIGSEGV; break;
3126#endif
3127#ifdef SIGSYS
3128 case 12: os_sig = SIGSYS; break;
3129#endif
3130#ifdef SIGPIPE
3131 case 13: os_sig = SIGPIPE; break;
3132#endif
3133#ifdef SIGALRM
3134 case 14: os_sig = SIGALRM; break;
3135#endif
3136#ifdef SIGTERM
3137 case 15: os_sig = SIGTERM; break;
3138#endif
3139#ifdef SIGURG
3140 case 16: os_sig = SIGURG; break;
3141#endif
3142#ifdef SIGSTOP
3143 case 17: os_sig = SIGSTOP; break;
3144#endif
3145#ifdef SIGTSTP
3146 case 18: os_sig = SIGTSTP; break;
3147#endif
3148#ifdef SIGCONT
3149 case 19: os_sig = SIGCONT; break;
3150#endif
3151#ifdef SIGCHLD
3152 case 20: os_sig = SIGCHLD; break;
3153#elif defined(SIGCLD)
3154 case 20: os_sig = SIGCLD; break;
3155#endif
3156#ifdef SIGTTIN
3157 case 21: os_sig = SIGTTIN; break;
3158#endif
3159#ifdef SIGTTOU
3160 case 22: os_sig = SIGTTOU; break;
3161#endif
3162#ifdef SIGIO
3163 case 23: os_sig = SIGIO; break;
3164#elif defined (SIGPOLL)
3165 case 23: os_sig = SIGPOLL; break;
3166#endif
3167#ifdef SIGXCPU
3168 case 24: os_sig = SIGXCPU; break;
3169#endif
3170#ifdef SIGXFSZ
3171 case 25: os_sig = SIGXFSZ; break;
3172#endif
3173#ifdef SIGVTALRM
3174 case 26: os_sig = SIGVTALRM; break;
3175#endif
3176#ifdef SIGPROF
3177 case 27: os_sig = SIGPROF; break;
3178#endif
3179#ifdef SIGWINCH
3180 case 28: os_sig = SIGWINCH; break;
3181#endif
3182#ifdef SIGLOST
3183 case 29: os_sig = SIGLOST; break;
3184#endif
3185#ifdef SIGUSR1
3186 case 30: os_sig = SIGUSR1; break;
3187#endif
3188#ifdef SIGUSR2
3189 case 31: os_sig = SIGUSR2; break;
3190#endif
3191 }
3192
3193 if (os_sig == -1)
3194 {
3195 trace_output_void ();
3196 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3197 (*d10v_callback->flush_stdout) (d10v_callback);
3198 State.exception = SIGILL;
3199 }
3200 else
3201 {
3202 RETVAL (kill (PARM1, PARM2));
3203 trace_output_16 (result);
3204 }
3205 }
3206 break;
3207
3208 case TARGET_SYS_execve:
3209 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3210 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3211 (char **)MEMPTR (PARM3)));
3212 trace_output_16 (result);
3213 break;
3214
3215#ifdef TARGET_SYS_execv
3216 case TARGET_SYS_execv:
3217 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3218 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3219 trace_output_16 (result);
3220 break;
3221#endif
3222
3223 case TARGET_SYS_pipe:
3224 {
3225 reg_t buf;
3226 int host_fd[2];
3227
3228 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3229 buf = PARM1;
3230 RETVAL (pipe (host_fd));
3231 SW (buf, host_fd[0]);
3232 buf += sizeof(uint16);
3233 SW (buf, host_fd[1]);
3234 trace_output_16 (result);
3235 }
3236 break;
3237
3238#if 0
3239#ifdef TARGET_SYS_wait
3240 case TARGET_SYS_wait:
3241 {
3242 int status;
3243 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3244 RETVAL (wait (&status));
3245 if (PARM1)
3246 SW (PARM1, status);
3247 trace_output_16 (result);
3248 }
3249 break;
3250#endif
3251#endif
3252#else
3253 case TARGET_SYS_getpid:
3254 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3255 RETVAL (1);
3256 trace_output_16 (result);
3257 break;
3258
3259 case TARGET_SYS_kill:
3260 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3261 trace_output_void ();
3262 State.exception = PARM2;
3263 break;
3264#endif
3265
3266 case TARGET_SYS_read:
3267 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3268 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3269 PARM3));
3270 trace_output_16 (result);
3271 break;
3272
3273 case TARGET_SYS_write:
3274 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3275 if (PARM1 == 1)
3276 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3277 MEMPTR (PARM2), PARM3));
3278 else
3279 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3280 MEMPTR (PARM2), PARM3));
3281 trace_output_16 (result);
3282 break;
3283
3284 case TARGET_SYS_lseek:
3285 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3286 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3287 ((((unsigned long) PARM2) << 16)
3288 || (unsigned long) PARM3),
3289 PARM4));
3290 trace_output_32 (result);
3291 break;
3292
3293 case TARGET_SYS_close:
3294 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3295 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3296 trace_output_16 (result);
3297 break;
3298
3299 case TARGET_SYS_open:
3300 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3301 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3302 trace_output_16 (result);
3303 break;
3304
3305 case TARGET_SYS_exit:
3306 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3307 State.exception = SIG_D10V_EXIT;
3308 trace_output_void ();
3309 break;
3310
7a292a7a 3311#ifdef TARGET_SYS_stat
c906108c
SS		 3312 case TARGET_SYS_stat:
3313 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3314 /* stat system call */
3315 {
3316 struct stat host_stat;
3317 reg_t buf;
3318
3319 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3320
3321 buf = PARM2;
3322
3323 /* The hard-coded offsets and sizes were determined by using
3324 * the D10V compiler on a test program that used struct stat.
3325 */
3326 SW (buf, host_stat.st_dev);
3327 SW (buf+2, host_stat.st_ino);
3328 SW (buf+4, host_stat.st_mode);
3329 SW (buf+6, host_stat.st_nlink);
3330 SW (buf+8, host_stat.st_uid);
3331 SW (buf+10, host_stat.st_gid);
3332 SW (buf+12, host_stat.st_rdev);
3333 SLW (buf+16, host_stat.st_size);
3334 SLW (buf+20, host_stat.st_atime);
3335 SLW (buf+28, host_stat.st_mtime);
3336 SLW (buf+36, host_stat.st_ctime);
3337 }
3338 trace_output_16 (result);
3339 break;
7a292a7a 3340#endif
c906108c
SS		 3341
3342 case TARGET_SYS_chown:
3343 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3344 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3345 trace_output_16 (result);
3346 break;
3347
3348 case TARGET_SYS_chmod:
3349 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3350 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3351 trace_output_16 (result);
3352 break;
3353
3354#if 0
3355#ifdef TARGET_SYS_utime
3356 case TARGET_SYS_utime:
3357 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3358 /* Cast the second argument to void *, to avoid type mismatch
3359 if a prototype is present. */
3360 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3361 trace_output_16 (result);
3362 break;
3363#endif
3364#endif
3365
3366#if 0
3367#ifdef TARGET_SYS_time
3368 case TARGET_SYS_time:
3369 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3370 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3371 trace_output_32 (result);
3372 break;
3373#endif
3374#endif
3375
3376 default:
3377 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3378 }
3379 if ((uint16) result == (uint16) -1)
3380 RETERR (d10v_callback->get_errno(d10v_callback));
3381 else
3382 RETERR (0);
3383 break;
3384 }
3385 }
3386}
3387
3388/* tst0i */
3389void
3390OP_7000000 ()
3391{
3392 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3393 SET_PSW_F1 (PSW_F0);;
3394 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3395 trace_output_flag ();
3396}
3397
3398/* tst1i */
3399void
3400OP_F000000 ()
3401{
3402 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3403 SET_PSW_F1 (PSW_F0);
3404 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3405 trace_output_flag ();
3406}
3407
3408/* wait */
3409void
3410OP_5F80 ()
3411{
3412 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3413 SET_PSW_IE (1);
3414 trace_output_void ();
3415}
3416
3417/* xor */
3418void
3419OP_A00 ()
3420{
3421 int16 tmp;
3422 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3423 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3424 SET_GPR (OP[0], tmp);
3425 trace_output_16 (tmp);
3426}
3427
3428/* xor3 */
3429void
3430OP_5000000 ()
3431{
3432 int16 tmp;
3433 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3434 tmp = (GPR (OP[1]) ^ OP[2]);
3435 SET_GPR (OP[0], tmp);
3436 trace_output_16 (tmp);
3437}
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