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Better error messages when a program stops due to signal; support d10v getpid/kill
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
4f425a32 1#include <signal.h>
63a91cfb
MM		 2#include <errno.h>
3#include <sys/types.h>
4#include <sys/stat.h>
5#include <unistd.h>
6
2934d1c9
MH		 7#include "d10v_sim.h"
8#include "simops.h"
8719be26 9#include "sys/syscall.h"
a49a15ad 10#include "bfd.h"
2934d1c9 11
87178dbd
MM		 12enum op_types {
13 OP_VOID,
14 OP_REG,
15 OP_REG_OUTPUT,
16 OP_DREG,
17 OP_DREG_OUTPUT,
18 OP_ACCUM,
19 OP_ACCUM_OUTPUT,
20 OP_ACCUM_REVERSE,
21 OP_CR,
22 OP_CR_OUTPUT,
23 OP_CR_REVERSE,
24 OP_FLAG,
60fc5b72 25 OP_FLAG_OUTPUT,
87178dbd 26 OP_CONSTANT16,
a18cb100 27 OP_CONSTANT8,
87178dbd
MM		 28 OP_CONSTANT3,
29 OP_CONSTANT4,
30 OP_MEMREF,
31 OP_MEMREF2,
32 OP_POSTDEC,
33 OP_POSTINC,
a18cb100
MM		 34 OP_PREDEC,
35 OP_R2,
8918b3a7
MM		 36 OP_R3,
37 OP_R4,
38 OP_R2R3
87178dbd
MM		 39};
40
7eebfc62 41#ifdef DEBUG
a49a15ad
MM		 42static void trace_input_func PARAMS ((char *name,
43 enum op_types in1,
44 enum op_types in2,
45 enum op_types in3));
87178dbd 46
a49a15ad
MM		 47#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
48
49static void trace_output_func PARAMS ((enum op_types result));
50
51#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
52
53static int init_text_p = 0;
54static asection *text;
55static bfd_vma text_start;
56static bfd_vma text_end;
0535fa1a 57extern bfd *exec_bfd;
87178dbd
MM		 58
59#ifndef SIZE_INSTRUCTION
a49a15ad 60#define SIZE_INSTRUCTION 8
87178dbd
MM		 61#endif
62
63#ifndef SIZE_OPERANDS
a49a15ad 64#define SIZE_OPERANDS 18
87178dbd
MM		 65#endif
66
67#ifndef SIZE_VALUES
68#define SIZE_VALUES 13
69#endif
70
a49a15ad
MM		 71#ifndef SIZE_LOCATION
72#define SIZE_LOCATION 20
73#endif
74
891513ee
MM		 75#ifndef SIZE_PC
76#define SIZE_PC 6
77#endif
78
79#ifndef SIZE_LINE_NUMBER
80#define SIZE_LINE_NUMBER 4
81#endif
82
87178dbd 83static void
a49a15ad 84trace_input_func (name, in1, in2, in3)
87178dbd
MM		 85 char *name;
86 enum op_types in1;
87 enum op_types in2;
88 enum op_types in3;
89{
90 char *comma;
91 enum op_types in[3];
92 int i;
a49a15ad 93 char buf[1024];
87178dbd
MM		 94 char *p;
95 long tmp;
96 char *type;
a49a15ad
MM		 97 asection *s;
98 const char *filename;
99 const char *functionname;
100 unsigned int linenumber;
101 bfd_vma byte_pc;
87178dbd 102
7eebfc62
MM		 103 if ((d10v_debug & DEBUG_TRACE) == 0)
104 return;
105
87178dbd
MM		 106 switch (State.ins_type)
107 {
108 default:
109 case INS_UNKNOWN: type = " ?"; break;
110 case INS_LEFT: type = " L"; break;
111 case INS_RIGHT: type = " R"; break;
112 case INS_LEFT_PARALLEL: type = "*L"; break;
113 case INS_RIGHT_PARALLEL: type = "*R"; break;
114 case INS_LONG: type = " B"; break;
115 }
116
a49a15ad
MM		 117 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
118 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 119 "0x%.*x %s: %-*s ",
891513ee
MM		 120 SIZE_PC, (unsigned)PC,
121 type,
a49a15ad
MM		 122 SIZE_INSTRUCTION, name);
123
124 else
125 {
a49a15ad
MM		 126 if (!init_text_p)
127 {
128 init_text_p = 1;
0535fa1a
MM		 129 for (s = exec_bfd->sections; s; s = s->next)
130 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
a49a15ad
MM		 131 {
132 text = s;
0535fa1a
MM		 133 text_start = bfd_get_section_vma (exec_bfd, s);
134 text_end = text_start + bfd_section_size (exec_bfd, s);
a49a15ad
MM		 135 break;
136 }
137 }
138
891513ee 139 buf[0] = '\0';
a49a15ad
MM		 140 byte_pc = (bfd_vma)PC << 2;
141 if (text && byte_pc >= text_start && byte_pc < text_end)
142 {
143 filename = (const char *)0;
144 functionname = (const char *)0;
145 linenumber = 0;
0535fa1a 146 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
a49a15ad
MM		 147 &filename, &functionname, &linenumber))
148 {
149 p = buf;
150 if (linenumber)
151 {
891513ee 152 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
a49a15ad
MM		 153 p += strlen (p);
154 }
891513ee
MM		 155 else
156 {
157 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
158 p += SIZE_LINE_NUMBER+2;
159 }
a49a15ad
MM		 160
161 if (functionname)
162 {
163 sprintf (p, "%s ", functionname);
164 p += strlen (p);
165 }
166 else if (filename)
167 {
168 char *q = (char *) strrchr (filename, '/');
169 sprintf (p, "%s ", (q) ? q+1 : filename);
170 p += strlen (p);
171 }
172
173 if (*p == ' ')
174 *p = '\0';
175 }
176 }
177
178 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 179 "0x%.*x %s: %-*.*s %-*s ",
891513ee
MM		 180 SIZE_PC, (unsigned)PC,
181 type,
a49a15ad
MM		 182 SIZE_LOCATION, SIZE_LOCATION, buf,
183 SIZE_INSTRUCTION, name);
184 }
87178dbd
MM		 185
186 in[0] = in1;
187 in[1] = in2;
188 in[2] = in3;
189 comma = "";
190 p = buf;
191 for (i = 0; i < 3; i++)
192 {
193 switch (in[i])
194 {
195 case OP_VOID:
a18cb100
MM		 196 case OP_R2:
197 case OP_R3:
8918b3a7 198 case OP_R4:
87178dbd
MM		 199 break;
200
201 case OP_REG:
202 case OP_REG_OUTPUT:
203 case OP_DREG:
204 case OP_DREG_OUTPUT:
205 sprintf (p, "%sr%d", comma, OP[i]);
206 p += strlen (p);
207 comma = ",";
208 break;
209
210 case OP_CR:
211 case OP_CR_OUTPUT:
212 case OP_CR_REVERSE:
213 sprintf (p, "%scr%d", comma, OP[i]);
214 p += strlen (p);
215 comma = ",";
216 break;
217
218 case OP_ACCUM:
219 case OP_ACCUM_OUTPUT:
220 case OP_ACCUM_REVERSE:
221 sprintf (p, "%sa%d", comma, OP[i]);
222 p += strlen (p);
223 comma = ",";
224 break;
225
226 case OP_CONSTANT16:
227 sprintf (p, "%s%d", comma, OP[i]);
228 p += strlen (p);
229 comma = ",";
230 break;
231
a18cb100
MM		 232 case OP_CONSTANT8:
233 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
234 p += strlen (p);
235 comma = ",";
236 break;
237
87178dbd
MM		 238 case OP_CONSTANT4:
239 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
240 p += strlen (p);
241 comma = ",";
242 break;
243
244 case OP_CONSTANT3:
245 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
246 p += strlen (p);
247 comma = ",";
248 break;
249
250 case OP_MEMREF:
251 sprintf (p, "%s@r%d", comma, OP[i]);
252 p += strlen (p);
253 comma = ",";
254 break;
255
256 case OP_MEMREF2:
257 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
258 p += strlen (p);
259 comma = ",";
260 break;
261
262 case OP_POSTINC:
263 sprintf (p, "%s@r%d+", comma, OP[i]);
264 p += strlen (p);
265 comma = ",";
266 break;
267
268 case OP_POSTDEC:
269 sprintf (p, "%s@r%d-", comma, OP[i]);
270 p += strlen (p);
271 comma = ",";
272 break;
273
274 case OP_PREDEC:
275 sprintf (p, "%s@-r%d", comma, OP[i]);
276 p += strlen (p);
277 comma = ",";
278 break;
279
280 case OP_FLAG:
60fc5b72 281 case OP_FLAG_OUTPUT:
87178dbd
MM		 282 if (OP[i] == 0)
283 sprintf (p, "%sf0", comma);
284
285 else if (OP[i] == 1)
286 sprintf (p, "%sf1", comma);
287
288 else
60fc5b72 289 sprintf (p, "%sc", comma);
87178dbd
MM		 290
291 p += strlen (p);
292 comma = ",";
293 break;
294 }
295 }
296
7eebfc62
MM		 297 if ((d10v_debug & DEBUG_VALUES) == 0)
298 {
299 *p++ = '\n';
300 *p = '\0';
301 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
302 }
303 else
304 {
305 *p = '\0';
306 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 307
7eebfc62
MM		 308 p = buf;
309 for (i = 0; i < 3; i++)
310 {
311 buf[0] = '\0';
312 switch (in[i])
313 {
314 case OP_VOID:
315 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
316 break;
317
318 case OP_REG_OUTPUT:
319 case OP_DREG_OUTPUT:
320 case OP_CR_OUTPUT:
321 case OP_ACCUM_OUTPUT:
60fc5b72 322 case OP_FLAG_OUTPUT:
7eebfc62
MM		 323 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
324 break;
325
326 case OP_REG:
327 case OP_MEMREF:
328 case OP_POSTDEC:
329 case OP_POSTINC:
330 case OP_PREDEC:
331 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
332 (uint16)State.regs[OP[i]]);
333 break;
334
335 case OP_DREG:
336 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
337 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
338 break;
339
340 case OP_CR:
341 case OP_CR_REVERSE:
342 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
343 (uint16)State.cregs[OP[i]]);
344 break;
345
346 case OP_ACCUM:
347 case OP_ACCUM_REVERSE:
348 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
349 ((int)(State.a[OP[i]] >> 32) & 0xff),
350 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
351 break;
352
353 case OP_CONSTANT16:
354 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
355 (uint16)OP[i]);
356 break;
357
358 case OP_CONSTANT4:
359 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
360 (uint16)SEXT4(OP[i]));
361 break;
362
a18cb100
MM		 363 case OP_CONSTANT8:
364 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
365 (uint16)SEXT8(OP[i]));
366 break;
367
7eebfc62
MM		 368 case OP_CONSTANT3:
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
370 (uint16)SEXT3(OP[i]));
371 break;
372
373 case OP_FLAG:
374 if (OP[i] == 0)
375 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
376 State.F0 != 0);
377
378 else if (OP[i] == 1)
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
380 State.F1 != 0);
381
382 else
383 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
384 State.C != 0);
385
386 break;
387
388 case OP_MEMREF2:
389 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
390 (uint16)OP[i]);
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
392 (uint16)State.regs[OP[++i]]);
393 break;
a18cb100
MM		 394
395 case OP_R2:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
397 (uint16)State.regs[2]);
398 break;
399
400 case OP_R3:
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16)State.regs[3]);
403 break;
8918b3a7
MM		 404
405 case OP_R4:
406 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
407 (uint16)State.regs[4]);
408 break;
7eebfc62
MM		 409 }
410 }
411 }
412}
87178dbd 413
7eebfc62 414static void
a49a15ad 415trace_output_func (result)
7eebfc62
MM		 416 enum op_types result;
417{
418 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 419 {
7eebfc62 420 long tmp;
87178dbd 421
7eebfc62
MM		 422 switch (result)
423 {
424 default:
425 putchar ('\n');
87178dbd
MM		 426 break;
427
428 case OP_REG:
7eebfc62
MM		 429 case OP_REG_OUTPUT:
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
431 (uint16)State.regs[OP[0]],
432 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 433 break;
434
435 case OP_DREG:
7eebfc62
MM		 436 case OP_DREG_OUTPUT:
437 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
439 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 440 break;
441
442 case OP_CR:
7eebfc62
MM		 443 case OP_CR_OUTPUT:
444 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
445 (uint16)State.cregs[OP[0]],
446 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 447 break;
448
7eebfc62
MM		 449 case OP_CR_REVERSE:
450 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
451 (uint16)State.cregs[OP[1]],
452 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 453 break;
454
7eebfc62
MM		 455 case OP_ACCUM:
456 case OP_ACCUM_OUTPUT:
069398aa 457 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 458 ((int)(State.a[OP[0]] >> 32) & 0xff),
459 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
460 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 461 break;
462
7eebfc62 463 case OP_ACCUM_REVERSE:
069398aa 464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 465 ((int)(State.a[OP[1]] >> 32) & 0xff),
466 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
467 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 468 break;
469
470 case OP_FLAG:
60fc5b72 471 case OP_FLAG_OUTPUT:
7eebfc62
MM		 472 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
473 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd 474 break;
8918b3a7
MM		 475
476 case OP_R2:
477 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
478 (uint16)State.regs[2],
479 State.F0 != 0, State.F1 != 0, State.C != 0);
480 break;
481
482 case OP_R2R3:
483 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
484 (uint16)State.regs[2], (uint16)State.regs[3],
485 State.F0 != 0, State.F1 != 0, State.C != 0);
486 break;
87178dbd
MM		 487 }
488 }
87178dbd
MM		 489}
490
491#else
492#define trace_input(NAME, IN1, IN2, IN3)
493#define trace_output(RESULT)
494#endif
2934d1c9
MH		 495
496/* abs */
497void
498OP_4607 ()
499{
87178dbd 500 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 501 State.F1 = State.F0;
502 if ((int16)(State.regs[OP[0]]) < 0)
503 {
504 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
505 State.F0 = 1;
506 }
507 else
508 State.F0 = 0;
87178dbd 509 trace_output (OP_REG);
2934d1c9
MH		 510}
511
512/* abs */
513void
514OP_5607 ()
515{
516 int64 tmp;
517
87178dbd 518 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 519 State.F1 = State.F0;
520 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
521
4c38885c 522 if (State.a[OP[0]] < 0 )
2934d1c9 523 {
4c38885c 524 tmp = -State.a[OP[0]];
2934d1c9
MH		 525 if (State.ST)
526 {
4c38885c 527 if (tmp > MAX32)
2934d1c9 528 State.a[OP[0]] = MAX32;
4c38885c 529 else if (tmp < MIN32)
2934d1c9
MH		 530 State.a[OP[0]] = MIN32;
531 else
4f425a32 532 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 533 }
534 else
4f425a32 535 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 536 State.F0 = 1;
537 }
538 else
539 State.F0 = 0;
87178dbd 540 trace_output (OP_ACCUM);
2934d1c9
MH		 541}
542
543/* add */
544void
545OP_200 ()
546{
547 uint16 tmp = State.regs[OP[0]];
87178dbd 548 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 549 State.regs[OP[0]] += State.regs[OP[1]];
550 if ( tmp > State.regs[OP[0]])
551 State.C = 1;
552 else
553 State.C = 0;
87178dbd 554 trace_output (OP_REG);
2934d1c9
MH		 555}
556
557/* add */
558void
559OP_1201 ()
560{
4c38885c 561 int64 tmp;
4f425a32 562 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 563
564 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 565 if (State.ST)
566 {
567 if ( tmp > MAX32)
568 State.a[OP[0]] = MAX32;
569 else if ( tmp < MIN32)
570 State.a[OP[0]] = MIN32;
571 else
4f425a32 572 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 573 }
574 else
4f425a32 575 State.a[OP[0]] = tmp & MASK40;
87178dbd 576 trace_output (OP_ACCUM);
2934d1c9
MH		 577}
578
579/* add */
580void
581OP_1203 ()
582{
4c38885c 583 int64 tmp;
4f425a32 584 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 585
586 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 587 if (State.ST)
588 {
589 if (tmp > MAX32)
590 State.a[OP[0]] = MAX32;
591 else if ( tmp < MIN32)
592 State.a[OP[0]] = MIN32;
593 else
4f425a32 594 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 595 }
596 else
4f425a32 597 State.a[OP[0]] = tmp & MASK40;
87178dbd 598 trace_output (OP_ACCUM);
2934d1c9
MH		 599}
600
601/* add2w */
602void
603OP_1200 ()
604{
605 uint32 tmp;
606 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
607 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 608
609 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
2934d1c9
MH		 610 tmp = tmp1 + tmp2;
611 if ( (tmp < tmp1) || (tmp < tmp2) )
612 State.C = 1;
613 else
614 State.C = 0;
615 State.regs[OP[0]] = tmp >> 16;
616 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 617 trace_output (OP_DREG);
2934d1c9
MH		 618}
619
620/* add3 */
621void
622OP_1000000 ()
623{
624 uint16 tmp = State.regs[OP[0]];
2934d1c9 625 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
87178dbd
MM		 626
627 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9
MH		 628 if ( tmp > State.regs[OP[0]])
629 State.C = 1;
630 else
631 State.C = 0;
87178dbd 632 trace_output (OP_REG);
2934d1c9
MH		 633}
634
635/* addac3 */
636void
637OP_17000200 ()
638{
4c38885c 639 int64 tmp;
4f425a32 640 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 641
642 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 643 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
644 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 645 trace_output (OP_DREG);
2934d1c9
MH		 646}
647
648/* addac3 */
649void
650OP_17000202 ()
651{
4c38885c 652 int64 tmp;
4f425a32 653 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 654
655 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 656 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
657 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 658 trace_output (OP_DREG);
2934d1c9
MH		 659}
660
661/* addac3s */
662void
663OP_17001200 ()
664{
4c38885c 665 int64 tmp;
4c38885c 666 State.F1 = State.F0;
87178dbd
MM		 667
668 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 669 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 670 if ( tmp > MAX32)
671 {
672 State.regs[OP[0]] = 0x7fff;
673 State.regs[OP[0]+1] = 0xffff;
674 State.F0 = 1;
675 }
676 else if (tmp < MIN32)
677 {
678 State.regs[OP[0]] = 0x8000;
679 State.regs[OP[0]+1] = 0;
680 State.F0 = 1;
681 }
682 else
683 {
684 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
685 State.regs[OP[0]+1] = tmp & 0xffff;
686 State.F0 = 0;
687 }
87178dbd 688 trace_output (OP_DREG);
2934d1c9
MH		 689}
690
691/* addac3s */
692void
693OP_17001202 ()
694{
4c38885c 695 int64 tmp;
4c38885c 696 State.F1 = State.F0;
87178dbd
MM		 697
698 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 699 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 700 if ( tmp > MAX32)
701 {
702 State.regs[OP[0]] = 0x7fff;
703 State.regs[OP[0]+1] = 0xffff;
704 State.F0 = 1;
705 }
706 else if (tmp < MIN32)
707 {
708 State.regs[OP[0]] = 0x8000;
709 State.regs[OP[0]+1] = 0;
710 State.F0 = 1;
711 }
712 else
713 {
714 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
715 State.regs[OP[0]+1] = tmp & 0xffff;
716 State.F0 = 0;
717 }
87178dbd 718 trace_output (OP_DREG);
2934d1c9
MH		 719}
720
721/* addi */
722void
723OP_201 ()
724{
2254cd90 725 uint tmp = State.regs[OP[0]];
4f425a32
MH		 726 if (OP[1] == 0)
727 OP[1] = 16;
87178dbd 728 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 729 State.regs[OP[0]] += OP[1];
2254cd90
MM		 730 if (tmp > State.regs[OP[0]])
731 State.C = 1;
732 else
733 State.C = 0;
87178dbd 734 trace_output (OP_REG);
2934d1c9
MH		 735}
736
737/* and */
738void
739OP_C00 ()
740{
87178dbd 741 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 742 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 743 trace_output (OP_REG);
2934d1c9
MH		 744}
745
746/* and3 */
747void
748OP_6000000 ()
749{
87178dbd 750 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 751 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 752 trace_output (OP_REG);
2934d1c9
MH		 753}
754
755/* bclri */
756void
757OP_C01 ()
758{
87178dbd 759 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 760 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 761 trace_output (OP_REG);
2934d1c9
MH		 762}
763
764/* bl.s */
765void
766OP_4900 ()
767{
a18cb100 768 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
2934d1c9
MH		 769 State.regs[13] = PC+1;
770 PC += SEXT8 (OP[0]);
87178dbd 771 trace_output (OP_VOID);
2934d1c9
MH		 772}
773
774/* bl.l */
775void
776OP_24800000 ()
777{
a18cb100 778 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
2934d1c9
MH		 779 State.regs[13] = PC+1;
780 PC += OP[0];
87178dbd 781 trace_output (OP_VOID);
2934d1c9
MH		 782}
783
784/* bnoti */
785void
786OP_A01 ()
787{
87178dbd 788 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 789 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 790 trace_output (OP_REG);
2934d1c9
MH		 791}
792
793/* bra.s */
794void
795OP_4800 ()
796{
a18cb100 797 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 798 PC += SEXT8 (OP[0]);
87178dbd 799 trace_output (OP_VOID);
2934d1c9
MH		 800}
801
802/* bra.l */
803void
804OP_24000000 ()
805{
87178dbd 806 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 807 PC += OP[0];
87178dbd 808 trace_output (OP_VOID);
2934d1c9
MH		 809}
810
811/* brf0f.s */
812void
813OP_4A00 ()
814{
a18cb100 815 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9
MH		 816 if (State.F0 == 0)
817 PC += SEXT8 (OP[0]);
87178dbd 818 trace_output (OP_FLAG);
2934d1c9
MH		 819}
820
821/* brf0f.l */
822void
823OP_25000000 ()
824{
87178dbd 825 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 826 if (State.F0 == 0)
827 PC += OP[0];
87178dbd 828 trace_output (OP_FLAG);
2934d1c9
MH		 829}
830
831/* brf0t.s */
832void
833OP_4B00 ()
834{
a18cb100 835 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9
MH		 836 if (State.F0)
837 PC += SEXT8 (OP[0]);
87178dbd 838 trace_output (OP_FLAG);
2934d1c9
MH		 839}
840
841/* brf0t.l */
842void
843OP_25800000 ()
844{
87178dbd 845 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 846 if (State.F0)
847 PC += OP[0];
87178dbd 848 trace_output (OP_FLAG);
2934d1c9
MH		 849}
850
851/* bseti */
852void
853OP_801 ()
854{
87178dbd 855 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 856 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 857 trace_output (OP_REG);
2934d1c9
MH		 858}
859
860/* btsti */
861void
862OP_E01 ()
863{
87178dbd 864 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 865 State.F1 = State.F0;
866 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 867 trace_output (OP_FLAG);
2934d1c9
MH		 868}
869
870/* clrac */
871void
872OP_5601 ()
873{
87178dbd 874 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 875 State.a[OP[0]] = 0;
87178dbd 876 trace_output (OP_ACCUM);
2934d1c9
MH		 877}
878
879/* cmp */
880void
881OP_600 ()
882{
87178dbd 883 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 884 State.F1 = State.F0;
885 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 886 trace_output (OP_FLAG);
2934d1c9
MH		 887}
888
889/* cmp */
890void
891OP_1603 ()
892{
87178dbd 893 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 894 State.F1 = State.F0;
4f425a32 895 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 896 trace_output (OP_FLAG);
2934d1c9
MH		 897}
898
899/* cmpeq */
900void
901OP_400 ()
902{
87178dbd 903 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 904 State.F1 = State.F0;
905 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 906 trace_output (OP_FLAG);
2934d1c9
MH		 907}
908
909/* cmpeq */
910void
911OP_1403 ()
912{
87178dbd 913 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 914 State.F1 = State.F0;
915 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
87178dbd 916 trace_output (OP_FLAG);
2934d1c9
MH		 917}
918
919/* cmpeqi.s */
920void
921OP_401 ()
922{
c12f5c67 923 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 924 State.F1 = State.F0;
c12f5c67 925 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
87178dbd 926 trace_output (OP_FLAG);
2934d1c9
MH		 927}
928
929/* cmpeqi.l */
930void
931OP_2000000 ()
932{
87178dbd 933 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 934 State.F1 = State.F0;
c12f5c67 935 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
87178dbd 936 trace_output (OP_FLAG);
2934d1c9
MH		 937}
938
939/* cmpi.s */
940void
941OP_601 ()
942{
87178dbd 943 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 944 State.F1 = State.F0;
c12f5c67 945 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
87178dbd 946 trace_output (OP_FLAG);
2934d1c9
MH		 947}
948
949/* cmpi.l */
950void
951OP_3000000 ()
952{
87178dbd 953 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 954 State.F1 = State.F0;
955 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 956 trace_output (OP_FLAG);
2934d1c9
MH		 957}
958
959/* cmpu */
960void
961OP_4600 ()
962{
87178dbd 963 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 964 State.F1 = State.F0;
965 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 966 trace_output (OP_FLAG);
2934d1c9
MH		 967}
968
969/* cmpui */
970void
971OP_23000000 ()
972{
87178dbd 973 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 974 State.F1 = State.F0;
c12f5c67 975 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
87178dbd 976 trace_output (OP_FLAG);
2934d1c9
MH		 977}
978
979/* cpfg */
980void
981OP_4E09 ()
982{
983 uint8 *src, *dst;
2934d1c9 984
60fc5b72 985 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 986 if (OP[0] == 0)
987 dst = &State.F0;
988 else
989 dst = &State.F1;
990
991 if (OP[1] == 0)
992 src = &State.F0;
993 else if (OP[1] == 1)
994 src = &State.F1;
995 else
996 src = &State.C;
997
998 *dst = *src;
87178dbd 999 trace_output (OP_FLAG);
2934d1c9
MH		 1000}
1001
1002/* dbt */
1003void
1004OP_5F20 ()
1005{
a49a15ad 1006 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
4f425a32 1007 State.exception = SIGTRAP;
2934d1c9
MH		 1008}
1009
1010/* divs */
1011void
1012OP_14002800 ()
1013{
1014 uint16 foo, tmp, tmpf;
87178dbd
MM		 1015
1016 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 1017 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1018 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1019 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1020 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1021 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 1022 trace_output (OP_DREG);
2934d1c9
MH		 1023}
1024
1025/* exef0f */
1026void
1027OP_4E04 ()
1028{
87178dbd 1029 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1030 State.exe = (State.F0 == 0);
87178dbd 1031 trace_output (OP_FLAG);
2934d1c9
MH		 1032}
1033
1034/* exef0t */
1035void
1036OP_4E24 ()
1037{
87178dbd 1038 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1039 State.exe = (State.F0 != 0);
87178dbd 1040 trace_output (OP_FLAG);
2934d1c9
MH		 1041}
1042
1043/* exef1f */
1044void
1045OP_4E40 ()
1046{
87178dbd 1047 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1048 State.exe = (State.F1 == 0);
87178dbd 1049 trace_output (OP_FLAG);
2934d1c9
MH		 1050}
1051
1052/* exef1t */
1053void
1054OP_4E42 ()
1055{
87178dbd 1056 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1057 State.exe = (State.F1 != 0);
87178dbd 1058 trace_output (OP_FLAG);
2934d1c9
MH		 1059}
1060
1061/* exefaf */
1062void
1063OP_4E00 ()
1064{
87178dbd 1065 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1066 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 1067 trace_output (OP_FLAG);
2934d1c9
MH		 1068}
1069
1070/* exefat */
1071void
1072OP_4E02 ()
1073{
87178dbd 1074 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1075 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 1076 trace_output (OP_FLAG);
2934d1c9
MH		 1077}
1078
1079/* exetaf */
1080void
1081OP_4E20 ()
1082{
87178dbd 1083 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1084 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 1085 trace_output (OP_FLAG);
2934d1c9
MH		 1086}
1087
1088/* exetat */
1089void
1090OP_4E22 ()
1091{
87178dbd 1092 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1093 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 1094 trace_output (OP_FLAG);
2934d1c9
MH		 1095}
1096
1097/* exp */
1098void
1099OP_15002A00 ()
1100{
1101 uint32 tmp, foo;
1102 int i;
1103
87178dbd 1104 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 1105 if (((int16)State.regs[OP[1]]) >= 0)
1106 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 1107 else
4c38885c 1108 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 1109
1110 foo = 0x40000000;
4c38885c 1111 for (i=1;i<17;i++)
2934d1c9
MH		 1112 {
1113 if (tmp & foo)
1114 {
1115 State.regs[OP[0]] = i-1;
87178dbd 1116 trace_output (OP_REG);
2934d1c9
MH		 1117 return;
1118 }
4c38885c 1119 foo >>= 1;
2934d1c9
MH		 1120 }
1121 State.regs[OP[0]] = 16;
87178dbd 1122 trace_output (OP_REG);
2934d1c9
MH		 1123}
1124
1125/* exp */
1126void
1127OP_15002A02 ()
1128{
4c38885c
MH		 1129 int64 tmp, foo;
1130 int i;
87178dbd
MM		 1131
1132 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
4f425a32 1133 if (SEXT40(State.a[OP[1]]) >= 0)
4c38885c
MH		 1134 tmp = State.a[OP[1]];
1135 else
1136 tmp = ~(State.a[OP[1]]);
1137
1138 foo = 0x4000000000LL;
1139 for (i=1;i<25;i++)
1140 {
1141 if (tmp & foo)
1142 {
1143 State.regs[OP[0]] = i-9;
87178dbd 1144 trace_output (OP_REG);
4c38885c
MH		 1145 return;
1146 }
1147 foo >>= 1;
1148 }
1149 State.regs[OP[0]] = 16;
87178dbd 1150 trace_output (OP_REG);
2934d1c9
MH		 1151}
1152
1153/* jl */
1154void
1155OP_4D00 ()
1156{
a18cb100 1157 trace_input ("jl", OP_REG, OP_R2, OP_R3);
2934d1c9
MH		 1158 State.regs[13] = PC+1;
1159 PC = State.regs[OP[0]];
87178dbd 1160 trace_output (OP_VOID);
2934d1c9
MH		 1161}
1162
1163/* jmp */
1164void
1165OP_4C00 ()
1166{
a18cb100
MM		 1167 trace_input ("jmp", OP_REG,
1168 (OP[0] == 13) ? OP_R2 : OP_VOID,
1169 (OP[0] == 13) ? OP_R3 : OP_VOID);
1170
2934d1c9 1171 PC = State.regs[OP[0]];
87178dbd 1172 trace_output (OP_VOID);
2934d1c9
MH		 1173}
1174
1175/* ld */
1176void
1177OP_30000000 ()
1178{
87178dbd 1179 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1180 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1181 trace_output (OP_REG);
2934d1c9
MH		 1182}
1183
1184/* ld */
1185void
1186OP_6401 ()
1187{
87178dbd 1188 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1189 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1190 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1191 trace_output (OP_REG);
2934d1c9
MH		 1192}
1193
1194/* ld */
1195void
1196OP_6001 ()
1197{
87178dbd 1198 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1199 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1200 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1201 trace_output (OP_REG);
2934d1c9
MH		 1202}
1203
1204/* ld */
1205void
1206OP_6000 ()
1207{
87178dbd 1208 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1209 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1210 trace_output (OP_REG);
2934d1c9
MH		 1211}
1212
1213/* ld2w */
1214void
1215OP_31000000 ()
1216{
8918b3a7 1217 uint16 addr = State.regs[OP[2]];
308f64d3 1218 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
8918b3a7
MM		 1219 State.regs[OP[0]] = RW (OP[1] + addr);
1220 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
87178dbd 1221 trace_output (OP_DREG);
2934d1c9
MH		 1222}
1223
1224/* ld2w */
1225void
1226OP_6601 ()
1227{
8918b3a7 1228 uint16 addr = State.regs[OP[1]];
87178dbd 1229 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
8918b3a7
MM		 1230 State.regs[OP[0]] = RW (addr);
1231 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1232 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1233 trace_output (OP_DREG);
2934d1c9
MH		 1234}
1235
1236/* ld2w */
1237void
1238OP_6201 ()
1239{
8918b3a7 1240 uint16 addr = State.regs[OP[1]];
87178dbd 1241 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
8918b3a7
MM		 1242 State.regs[OP[0]] = RW (addr);
1243 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1244 INC_ADDR(State.regs[OP[1]],4);
8918b3a7 1245 trace_output (OP_DREG);
2934d1c9
MH		 1246}
1247
1248/* ld2w */
1249void
1250OP_6200 ()
1251{
8918b3a7 1252 uint16 addr = State.regs[OP[1]];
addb61a5 1253 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
8918b3a7
MM		 1254 State.regs[OP[0]] = RW (addr);
1255 State.regs[OP[0]+1] = RW (addr+2);
1256 trace_output (OP_DREG);
2934d1c9
MH		 1257}
1258
1259/* ldb */
1260void
1261OP_38000000 ()
1262{
87178dbd 1263 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9
MH		 1264 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1265 SEXT8 (State.regs[OP[0]]);
87178dbd 1266 trace_output (OP_REG);
2934d1c9
MH		 1267}
1268
1269/* ldb */
1270void
1271OP_7000 ()
1272{
87178dbd 1273 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9
MH		 1274 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1275 SEXT8 (State.regs[OP[0]]);
87178dbd 1276 trace_output (OP_REG);
2934d1c9
MH		 1277}
1278
1279/* ldi.s */
1280void
1281OP_4001 ()
1282{
87178dbd 1283 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1284 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1285 trace_output (OP_REG);
2934d1c9
MH		 1286}
1287
1288/* ldi.l */
1289void
1290OP_20000000 ()
1291{
87178dbd 1292 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1293 State.regs[OP[0]] = OP[1];
87178dbd 1294 trace_output (OP_REG);
2934d1c9
MH		 1295}
1296
1297/* ldub */
1298void
1299OP_39000000 ()
1300{
87178dbd 1301 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1302 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1303 trace_output (OP_REG);
2934d1c9
MH		 1304}
1305
1306/* ldub */
1307void
1308OP_7200 ()
1309{
87178dbd 1310 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1311 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1312 trace_output (OP_REG);
2934d1c9
MH		 1313}
1314
1315/* mac */
1316void
1317OP_2A00 ()
1318{
4c38885c 1319 int64 tmp;
87178dbd
MM		 1320
1321 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1322 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1323
1324 if (State.FX)
4f425a32 1325 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1326
1327 if (State.ST && tmp > MAX32)
1328 tmp = MAX32;
1329
4f425a32 1330 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1331 if (State.ST)
1332 {
1333 if (tmp > MAX32)
1334 State.a[OP[0]] = MAX32;
1335 else if (tmp < MIN32)
1336 State.a[OP[0]] = MIN32;
1337 else
4f425a32 1338 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1339 }
1340 else
4f425a32 1341 State.a[OP[0]] = tmp & MASK40;
87178dbd 1342 trace_output (OP_ACCUM);
2934d1c9
MH		 1343}
1344
1345/* macsu */
1346void
1347OP_1A00 ()
1348{
4f425a32 1349 int64 tmp;
87178dbd
MM		 1350
1351 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1352 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1353 if (State.FX)
1354 tmp = SEXT40( (tmp << 1) & MASK40);
1355
1356 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1357 trace_output (OP_ACCUM);
2934d1c9
MH		 1358}
1359
1360/* macu */
1361void
1362OP_3A00 ()
1363{
4f425a32 1364 int64 tmp;
87178dbd
MM		 1365
1366 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1367 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1368 if (State.FX)
1369 tmp = SEXT40( (tmp << 1) & MASK40);
1370 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1371 trace_output (OP_ACCUM);
2934d1c9
MH		 1372}
1373
1374/* max */
1375void
1376OP_2600 ()
1377{
87178dbd 1378 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1379 State.F1 = State.F0;
ea2155e8 1380 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1381 {
1382 State.regs[OP[0]] = State.regs[OP[1]];
1383 State.F0 = 1;
1384 }
1385 else
1386 State.F0 = 0;
87178dbd 1387 trace_output (OP_REG);
2934d1c9
MH		 1388}
1389
1390/* max */
1391void
1392OP_3600 ()
1393{
4f425a32 1394 int64 tmp;
87178dbd
MM		 1395
1396 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1397 State.F1 = State.F0;
1398 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1399 if (tmp > SEXT40(State.a[OP[0]]))
1400 {
1401 State.a[OP[0]] = tmp & MASK40;
1402 State.F0 = 1;
1403 }
1404 else
1405 State.F0 = 0;
87178dbd 1406 trace_output (OP_ACCUM);
2934d1c9
MH		 1407}
1408
1409/* max */
1410void
1411OP_3602 ()
1412{
87178dbd 1413 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1414 State.F1 = State.F0;
1415 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1416 {
1417 State.a[OP[0]] = State.a[OP[1]];
1418 State.F0 = 1;
1419 }
1420 else
1421 State.F0 = 0;
87178dbd 1422 trace_output (OP_ACCUM);
2934d1c9
MH		 1423}
1424
4f425a32 1425
2934d1c9
MH		 1426/* min */
1427void
1428OP_2601 ()
1429{
87178dbd 1430 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1431 State.F1 = State.F0;
ea2155e8 1432 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1433 {
1434 State.regs[OP[0]] = State.regs[OP[1]];
1435 State.F0 = 1;
1436 }
1437 else
1438 State.F0 = 0;
87178dbd 1439 trace_output (OP_REG);
2934d1c9
MH		 1440}
1441
1442/* min */
1443void
1444OP_3601 ()
1445{
4f425a32 1446 int64 tmp;
87178dbd
MM		 1447
1448 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1449 State.F1 = State.F0;
1450 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1451 if (tmp < SEXT40(State.a[OP[0]]))
1452 {
1453 State.a[OP[0]] = tmp & MASK40;
1454 State.F0 = 1;
1455 }
1456 else
1457 State.F0 = 0;
87178dbd 1458 trace_output (OP_ACCUM);
2934d1c9
MH		 1459}
1460
1461/* min */
1462void
1463OP_3603 ()
1464{
87178dbd 1465 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1466 State.F1 = State.F0;
1467 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1468 {
1469 State.a[OP[0]] = State.a[OP[1]];
1470 State.F0 = 1;
1471 }
1472 else
1473 State.F0 = 0;
87178dbd 1474 trace_output (OP_ACCUM);
2934d1c9
MH		 1475}
1476
1477/* msb */
1478void
1479OP_2800 ()
1480{
4f425a32 1481 int64 tmp;
87178dbd
MM		 1482
1483 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1484 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1485
1486 if (State.FX)
1487 tmp = SEXT40 ((tmp << 1) & MASK40);
1488
1489 if (State.ST && tmp > MAX32)
1490 tmp = MAX32;
1491
1492 tmp = SEXT40(State.a[OP[0]]) - tmp;
1493 if (State.ST)
1494 {
1495 if (tmp > MAX32)
1496 State.a[OP[0]] = MAX32;
1497 else if (tmp < MIN32)
1498 State.a[OP[0]] = MIN32;
1499 else
1500 State.a[OP[0]] = tmp & MASK40;
1501 }
1502 else
1503 State.a[OP[0]] = tmp & MASK40;
87178dbd 1504 trace_output (OP_ACCUM);
2934d1c9
MH		 1505}
1506
1507/* msbsu */
1508void
1509OP_1800 ()
1510{
4f425a32 1511 int64 tmp;
87178dbd
MM		 1512
1513 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1514 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1515 if (State.FX)
1516 tmp = SEXT40( (tmp << 1) & MASK40);
1517
1518 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1519 trace_output (OP_ACCUM);
2934d1c9
MH		 1520}
1521
1522/* msbu */
1523void
1524OP_3800 ()
1525{
4f425a32 1526 int64 tmp;
87178dbd
MM		 1527
1528 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1529 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1530 if (State.FX)
1531 tmp = SEXT40( (tmp << 1) & MASK40);
1532
1533 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1534 trace_output (OP_ACCUM);
2934d1c9
MH		 1535}
1536
1537/* mul */
1538void
1539OP_2E00 ()
1540{
87178dbd 1541 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1542 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1543 trace_output (OP_REG);
2934d1c9
MH		 1544}
1545
1546/* mulx */
1547void
1548OP_2C00 ()
1549{
4f425a32 1550 int64 tmp;
87178dbd
MM		 1551
1552 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1553 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1554
1555 if (State.FX)
1556 tmp = SEXT40 ((tmp << 1) & MASK40);
1557
1558 if (State.ST && tmp > MAX32)
1559 State.a[OP[0]] = MAX32;
1560 else
1561 State.a[OP[0]] = tmp & MASK40;
87178dbd 1562 trace_output (OP_ACCUM);
2934d1c9
MH		 1563}
1564
1565/* mulxsu */
1566void
1567OP_1C00 ()
1568{
4f425a32 1569 int64 tmp;
87178dbd
MM		 1570
1571 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1572 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1573
1574 if (State.FX)
1575 tmp <<= 1;
1576
1577 State.a[OP[0]] = tmp & MASK40;
87178dbd 1578 trace_output (OP_ACCUM);
2934d1c9
MH		 1579}
1580
1581/* mulxu */
1582void
1583OP_3C00 ()
1584{
4f425a32 1585 int64 tmp;
87178dbd
MM		 1586
1587 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1588 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1589
1590 if (State.FX)
1591 tmp <<= 1;
1592
1593 State.a[OP[0]] = tmp & MASK40;
87178dbd 1594 trace_output (OP_ACCUM);
2934d1c9
MH		 1595}
1596
1597/* mv */
1598void
1599OP_4000 ()
1600{
87178dbd 1601 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1602 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1603 trace_output (OP_REG);
2934d1c9
MH		 1604}
1605
1606/* mv2w */
1607void
1608OP_5000 ()
1609{
87178dbd 1610 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1611 State.regs[OP[0]] = State.regs[OP[1]];
1612 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1613 trace_output (OP_DREG);
2934d1c9
MH		 1614}
1615
1616/* mv2wfac */
1617void
1618OP_3E00 ()
1619{
87178dbd 1620 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1621 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1622 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1623 trace_output (OP_DREG);
2934d1c9
MH		 1624}
1625
1626/* mv2wtac */
1627void
1628OP_3E01 ()
1629{
87178dbd 1630 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
4f425a32 1631 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
87178dbd 1632 trace_output (OP_ACCUM);
2934d1c9
MH		 1633}
1634
1635/* mvac */
1636void
1637OP_3E03 ()
1638{
87178dbd 1639 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1640 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1641 trace_output (OP_ACCUM);
2934d1c9
MH		 1642}
1643
1644/* mvb */
1645void
1646OP_5400 ()
1647{
87178dbd 1648 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1649 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1650 trace_output (OP_REG);
2934d1c9
MH		 1651}
1652
1653/* mvf0f */
1654void
1655OP_4400 ()
1656{
87178dbd 1657 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1658 if (State.F0 == 0)
1659 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1660 trace_output (OP_REG);
2934d1c9
MH		 1661}
1662
1663/* mvf0t */
1664void
1665OP_4401 ()
1666{
87178dbd 1667 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1668 if (State.F0)
1669 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1670 trace_output (OP_REG);
2934d1c9
MH		 1671}
1672
1673/* mvfacg */
1674void
1675OP_1E04 ()
1676{
87178dbd 1677 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1678 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1679 trace_output (OP_ACCUM);
2934d1c9
MH		 1680}
1681
1682/* mvfachi */
1683void
1684OP_1E00 ()
1685{
87178dbd 1686 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1687 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1688 trace_output (OP_REG);
2934d1c9
MH		 1689}
1690
1691/* mvfaclo */
1692void
1693OP_1E02 ()
1694{
87178dbd 1695 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1696 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1697 trace_output (OP_REG);
2934d1c9
MH		 1698}
1699
1700/* mvfc */
1701void
1702OP_5200 ()
1703{
87178dbd 1704 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2934d1c9
MH		 1705 if (OP[1] == 0)
1706 {
1707 /* PSW is treated specially */
1708 PSW = 0;
1709 if (State.SM) PSW |= 0x8000;
1710 if (State.EA) PSW |= 0x2000;
1711 if (State.DB) PSW |= 0x1000;
1712 if (State.IE) PSW |= 0x400;
1713 if (State.RP) PSW |= 0x200;
1714 if (State.MD) PSW |= 0x100;
1715 if (State.FX) PSW |= 0x80;
1716 if (State.ST) PSW |= 0x40;
1717 if (State.F0) PSW |= 8;
1718 if (State.F1) PSW |= 4;
1719 if (State.C) PSW |= 1;
1720 }
1721 State.regs[OP[0]] = State.cregs[OP[1]];
87178dbd 1722 trace_output (OP_REG);
2934d1c9
MH		 1723}
1724
1725/* mvtacg */
1726void
1727OP_1E41 ()
1728{
87178dbd 1729 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1730 State.a[OP[1]] &= MASK32;
1731 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1732 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1733}
1734
1735/* mvtachi */
1736void
1737OP_1E01 ()
1738{
1739 uint16 tmp;
87178dbd
MM		 1740
1741 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1742 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1743 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1744 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1745}
1746
1747/* mvtaclo */
1748void
1749OP_1E21 ()
1750{
87178dbd 1751 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1752 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1753 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1754}
1755
1756/* mvtc */
1757void
1758OP_5600 ()
1759{
87178dbd 1760 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2934d1c9
MH		 1761 State.cregs[OP[1]] = State.regs[OP[0]];
1762 if (OP[1] == 0)
1763 {
1764 /* PSW is treated specially */
1765 State.SM = (PSW & 0x8000) ? 1 : 0;
1766 State.EA = (PSW & 0x2000) ? 1 : 0;
1767 State.DB = (PSW & 0x1000) ? 1 : 0;
1768 State.IE = (PSW & 0x400) ? 1 : 0;
1769 State.RP = (PSW & 0x200) ? 1 : 0;
1770 State.MD = (PSW & 0x100) ? 1 : 0;
1771 State.FX = (PSW & 0x80) ? 1 : 0;
1772 State.ST = (PSW & 0x40) ? 1 : 0;
1773 State.F0 = (PSW & 8) ? 1 : 0;
1774 State.F1 = (PSW & 4) ? 1 : 0;
1775 State.C = PSW & 1;
1776 if (State.ST && !State.FX)
1777 {
7eebfc62
MM		 1778 (*d10v_callback->printf_filtered) (d10v_callback,
1779 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1780 PC<<2);
4f425a32 1781 State.exception = SIGILL;
2934d1c9
MH		 1782 }
1783 }
87178dbd 1784 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1785}
1786
1787/* mvub */
1788void
1789OP_5401 ()
1790{
87178dbd 1791 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1792 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1793 trace_output (OP_REG);
2934d1c9
MH		 1794}
1795
1796/* neg */
1797void
1798OP_4605 ()
1799{
87178dbd 1800 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1801 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1802 trace_output (OP_REG);
2934d1c9
MH		 1803}
1804
1805/* neg */
1806void
1807OP_5605 ()
1808{
1809 int64 tmp;
87178dbd
MM		 1810
1811 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1812 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1813 if (State.ST)
1814 {
4c38885c 1815 if ( tmp > MAX32)
2934d1c9 1816 State.a[OP[0]] = MAX32;
4c38885c 1817 else if (tmp < MIN32)
2934d1c9
MH		 1818 State.a[OP[0]] = MIN32;
1819 else
4f425a32 1820 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1821 }
1822 else
4f425a32 1823 State.a[OP[0]] = tmp & MASK40;
87178dbd 1824 trace_output (OP_ACCUM);
2934d1c9
MH		 1825}
1826
1827
1828/* nop */
1829void
1830OP_5E00 ()
1831{
87178dbd
MM		 1832 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1833 trace_output (OP_VOID);
7eebfc62
MM		 1834
1835 if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
1836 left_nops++;
1837 else
1838 right_nops++;
2934d1c9
MH		 1839}
1840
1841/* not */
1842void
1843OP_4603 ()
1844{
87178dbd 1845 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1846 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1847 trace_output (OP_REG);
2934d1c9
MH		 1848}
1849
1850/* or */
1851void
1852OP_800 ()
1853{
87178dbd 1854 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1855 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1856 trace_output (OP_REG);
2934d1c9
MH		 1857}
1858
1859/* or3 */
1860void
1861OP_4000000 ()
1862{
87178dbd 1863 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1864 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1865 trace_output (OP_REG);
2934d1c9
MH		 1866}
1867
1868/* rac */
1869void
1870OP_5201 ()
1871{
1872 int64 tmp;
1873 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1874
1875 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1876 if (OP[1] != 0)
1877 {
7eebfc62
MM		 1878 (*d10v_callback->printf_filtered) (d10v_callback,
1879 "ERROR at PC 0x%x: instruction only valid for A0\n",
1880 PC<<2);
166acb9f
MH		 1881 State.exception = SIGILL;
1882 }
1883
2934d1c9
MH		 1884 State.F1 = State.F0;
1885 if (shift >=0)
1886 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1887 else
1888 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f 1889 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
4c38885c 1890 if (tmp > MAX32)
2934d1c9
MH		 1891 {
1892 State.regs[OP[0]] = 0x7fff;
1893 State.regs[OP[0]+1] = 0xffff;
1894 State.F0 = 1;
1895 }
4c38885c 1896 else if (tmp < MIN32)
2934d1c9
MH		 1897 {
1898 State.regs[OP[0]] = 0x8000;
1899 State.regs[OP[0]+1] = 0;
1900 State.F0 = 1;
1901 }
1902 else
1903 {
1904 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1905 State.regs[OP[0]+1] = tmp & 0xffff;
1906 State.F0 = 0;
1907 }
87178dbd 1908 trace_output (OP_DREG);
2934d1c9
MH		 1909}
1910
1911/* rachi */
1912void
1913OP_4201 ()
1914{
4c38885c
MH		 1915 int64 tmp;
1916 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1917
1918 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1919 State.F1 = State.F0;
1920 if (shift >=0)
166acb9f 1921 tmp = SEXT44 (State.a[1]) << shift;
4c38885c 1922 else
166acb9f 1923 tmp = SEXT44 (State.a[1]) >> -shift;
4c38885c 1924 tmp += 0x8000;
63a91cfb 1925
4c38885c
MH		 1926 if (tmp > MAX32)
1927 {
1928 State.regs[OP[0]] = 0x7fff;
1929 State.F0 = 1;
1930 }
1931 else if (tmp < 0xfff80000000LL)
1932 {
1933 State.regs[OP[0]] = 0x8000;
1934 State.F0 = 1;
1935 }
1936 else
1937 {
1938 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1939 State.F0 = 0;
1940 }
87178dbd 1941 trace_output (OP_REG);
2934d1c9
MH		 1942}
1943
1944/* rep */
1945void
1946OP_27000000 ()
1947{
87178dbd 1948 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1949 RPT_S = PC + 1;
1950 RPT_E = PC + OP[1];
1951 RPT_C = State.regs[OP[0]];
1952 State.RP = 1;
1953 if (RPT_C == 0)
1954 {
7eebfc62 1955 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1956 State.exception = SIGILL;
2934d1c9 1957 }
4c38885c
MH		 1958 if (OP[1] < 4)
1959 {
7eebfc62 1960 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1961 State.exception = SIGILL;
4c38885c 1962 }
87178dbd 1963 trace_output (OP_VOID);
2934d1c9
MH		 1964}
1965
1966/* repi */
1967void
1968OP_2F000000 ()
1969{
87178dbd 1970 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1971 RPT_S = PC + 1;
1972 RPT_E = PC + OP[1];
1973 RPT_C = OP[0];
1974 State.RP = 1;
1975 if (RPT_C == 0)
1976 {
7eebfc62 1977 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 1978 State.exception = SIGILL;
4c38885c
MH		 1979 }
1980 if (OP[1] < 4)
1981 {
7eebfc62 1982 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 1983 State.exception = SIGILL;
2934d1c9 1984 }
87178dbd 1985 trace_output (OP_VOID);
2934d1c9
MH		 1986}
1987
1988/* rtd */
1989void
1990OP_5F60 ()
1991{
7eebfc62 1992 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 1993 State.exception = SIGILL;
2934d1c9
MH		 1994}
1995
1996/* rte */
1997void
1998OP_5F40 ()
1999{
87178dbd 2000 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
4c38885c
MH		 2001 PC = BPC;
2002 PSW = BPSW;
87178dbd 2003 trace_output (OP_VOID);
2934d1c9
MH		 2004}
2005
2006/* sadd */
2007void
2008OP_1223 ()
2009{
4c38885c 2010 int64 tmp;
87178dbd
MM		 2011
2012 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 2013 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 2014 if (State.ST)
2015 {
2016 if (tmp > MAX32)
2017 State.a[OP[0]] = MAX32;
2018 else if (tmp < MIN32)
2019 State.a[OP[0]] = MIN32;
2020 else
4f425a32 2021 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 2022 }
2023 else
4f425a32 2024 State.a[OP[0]] = tmp & MASK40;
87178dbd 2025 trace_output (OP_ACCUM);
2934d1c9
MH		 2026}
2027
2028/* setf0f */
2029void
2030OP_4611 ()
2031{
87178dbd 2032 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2033 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 2034 trace_output (OP_REG);
2934d1c9
MH		 2035}
2036
2037/* setf0t */
2038void
2039OP_4613 ()
2040{
87178dbd 2041 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2042 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 2043 trace_output (OP_REG);
2934d1c9
MH		 2044}
2045
2046/* sleep */
2047void
2048OP_5FC0 ()
2049{
87178dbd 2050 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2051 State.IE = 1;
87178dbd 2052 trace_output (OP_VOID);
2934d1c9
MH		 2053}
2054
2055/* sll */
2056void
2057OP_2200 ()
2058{
87178dbd 2059 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 2060 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 2061 trace_output (OP_REG);
2934d1c9
MH		 2062}
2063
2064/* sll */
2065void
2066OP_3200 ()
2067{
4c38885c 2068 int64 tmp;
87178dbd 2069 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2070 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2071 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 2072 else
2073 {
2074 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2075 State.exception = SIGILL;
2076 return;
2077 }
4c38885c
MH		 2078
2079 if (State.ST)
2080 {
2081 if (tmp > MAX32)
2082 State.a[OP[0]] = MAX32;
2083 else if (tmp < 0xffffff80000000LL)
2084 State.a[OP[0]] = MIN32;
2085 else
2086 State.a[OP[0]] = tmp & MASK40;
2087 }
2088 else
2089 State.a[OP[0]] = tmp & MASK40;
87178dbd 2090 trace_output (OP_ACCUM);
2934d1c9
MH		 2091}
2092
2093/* slli */
2094void
2095OP_2201 ()
2096{
87178dbd 2097 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2098 State.regs[OP[0]] <<= OP[1];
87178dbd 2099 trace_output (OP_REG);
2934d1c9
MH		 2100}
2101
2102/* slli */
2103void
2104OP_3201 ()
2105{
4c38885c 2106 int64 tmp;
4f425a32
MH		 2107
2108 if (OP[1] == 0)
2109 OP[1] = 16;
4f425a32 2110
87178dbd 2111 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 2112 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 2113
2114 if (State.ST)
2115 {
2116 if (tmp > MAX32)
2117 State.a[OP[0]] = MAX32;
2118 else if (tmp < 0xffffff80000000LL)
2119 State.a[OP[0]] = MIN32;
2120 else
2121 State.a[OP[0]] = tmp & MASK40;
2122 }
2123 else
2124 State.a[OP[0]] = tmp & MASK40;
87178dbd 2125 trace_output (OP_ACCUM);
2934d1c9
MH		 2126}
2127
2128/* slx */
2129void
2130OP_460B ()
2131{
2132 uint16 tmp;
87178dbd
MM		 2133
2134 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 2135 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 2136 trace_output (OP_REG);
2934d1c9
MH		 2137}
2138
2139/* sra */
2140void
2141OP_2400 ()
2142{
87178dbd 2143 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 2144 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2145 trace_output (OP_REG);
2934d1c9
MH		 2146}
2147
2148/* sra */
2149void
2150OP_3400 ()
2151{
87178dbd 2152 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2153 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2154 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2155 else
2156 {
2157 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2158 State.exception = SIGILL;
2159 return;
2160 }
2161
87178dbd 2162 trace_output (OP_ACCUM);
2934d1c9
MH		 2163}
2164
2165/* srai */
2166void
2167OP_2401 ()
2168{
87178dbd 2169 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2170 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2171 trace_output (OP_REG);
2934d1c9
MH		 2172}
2173
2174/* srai */
2175void
2176OP_3401 ()
2177{
4f425a32
MH		 2178 if (OP[1] == 0)
2179 OP[1] = 16;
87178dbd
MM		 2180
2181 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2182 State.a[OP[0]] >>= OP[1];
2183 trace_output (OP_ACCUM);
2934d1c9
MH		 2184}
2185
2186/* srl */
2187void
2188OP_2000 ()
2189{
87178dbd 2190 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2191 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2192 trace_output (OP_REG);
2934d1c9
MH		 2193}
2194
2195/* srl */
2196void
2197OP_3000 ()
2198{
87178dbd 2199 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2200 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2201 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2202 else
2203 {
2204 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2205 State.exception = SIGILL;
2206 return;
2207 }
2208
87178dbd 2209 trace_output (OP_ACCUM);
2934d1c9
MH		 2210}
2211
2212/* srli */
2213void
2214OP_2001 ()
2215{
87178dbd 2216 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2217 State.regs[OP[0]] >>= OP[1];
87178dbd 2218 trace_output (OP_REG);
2934d1c9
MH		 2219}
2220
2221/* srli */
2222void
2223OP_3001 ()
2224{
4f425a32
MH		 2225 if (OP[1] == 0)
2226 OP[1] = 16;
87178dbd
MM		 2227
2228 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2229 State.a[OP[0]] >>= OP[1];
2230 trace_output (OP_ACCUM);
2934d1c9
MH		 2231}
2232
2233/* srx */
2234void
2235OP_4609 ()
2236{
2237 uint16 tmp;
87178dbd
MM		 2238
2239 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2240 tmp = State.F0 << 15;
2241 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2242 trace_output (OP_REG);
2934d1c9
MH		 2243}
2244
2245/* st */
2246void
2247OP_34000000 ()
2248{
87178dbd 2249 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2250 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2251 trace_output (OP_VOID);
2934d1c9
MH		 2252}
2253
2254/* st */
2255void
2256OP_6800 ()
2257{
87178dbd 2258 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2259 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2260 trace_output (OP_VOID);
2934d1c9
MH		 2261}
2262
2263/* st */
2264void
2265OP_6C1F ()
2266{
87178dbd 2267 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2268 if ( OP[1] != 15 )
2269 {
7eebfc62 2270 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2271 State.exception = SIGILL;
2272 return;
4c38885c
MH		 2273 }
2274 State.regs[OP[1]] -= 2;
2275 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2276 trace_output (OP_VOID);
2934d1c9
MH		 2277}
2278
2279/* st */
2280void
2281OP_6801 ()
2282{
87178dbd 2283 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2284 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2285 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2286 trace_output (OP_VOID);
2934d1c9
MH		 2287}
2288
2289/* st */
2290void
2291OP_6C01 ()
2292{
87178dbd 2293 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
4c38885c 2294 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2295 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2296 trace_output (OP_VOID);
2934d1c9
MH		 2297}
2298
2299/* st2w */
2300void
2301OP_35000000 ()
2302{
87178dbd 2303 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2304 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2305 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2306 trace_output (OP_VOID);
2934d1c9
MH		 2307}
2308
2309/* st2w */
2310void
2311OP_6A00 ()
2312{
a18cb100 2313 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2314 SW (State.regs[OP[1]], State.regs[OP[0]]);
2315 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2316 trace_output (OP_VOID);
2934d1c9
MH		 2317}
2318
2319/* st2w */
2320void
2321OP_6E1F ()
2322{
a18cb100 2323 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2324 if ( OP[1] != 15 )
2325 {
7eebfc62 2326 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2327 State.exception = SIGILL;
2328 return;
4c38885c
MH		 2329 }
2330 State.regs[OP[1]] -= 4;
2331 SW (State.regs[OP[1]], State.regs[OP[0]]);
2332 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2333 trace_output (OP_VOID);
2934d1c9
MH		 2334}
2335
2336/* st2w */
2337void
2338OP_6A01 ()
2339{
a18cb100 2340 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
4c38885c
MH		 2341 SW (State.regs[OP[1]], State.regs[OP[0]]);
2342 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2343 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2344 trace_output (OP_VOID);
2934d1c9
MH		 2345}
2346
2347/* st2w */
2348void
2349OP_6E01 ()
2350{
a18cb100 2351 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2352 SW (State.regs[OP[1]], State.regs[OP[0]]);
2353 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2354 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2355 trace_output (OP_VOID);
2934d1c9
MH		 2356}
2357
2358/* stb */
2359void
2360OP_3C000000 ()
2361{
87178dbd 2362 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2363 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2364 trace_output (OP_VOID);
2934d1c9
MH		 2365}
2366
2367/* stb */
2368void
2369OP_7800 ()
2370{
87178dbd 2371 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2372 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2373 trace_output (OP_VOID);
2934d1c9
MH		 2374}
2375
2376/* stop */
2377void
2378OP_5FE0 ()
2379{
87178dbd 2380 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
a49a15ad 2381 State.exception = SIG_D10V_STOP;
87178dbd 2382 trace_output (OP_VOID);
2934d1c9
MH		 2383}
2384
2385/* sub */
2386void
2387OP_0 ()
4c38885c
MH		 2388{
2389 int32 tmp;
87178dbd
MM		 2390
2391 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
4c38885c
MH		 2392 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2393 State.C = (tmp & 0xffff0000) ? 1 : 0;
2394 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2395 trace_output (OP_REG);
4c38885c
MH		 2396}
2397
2398/* sub */
2399void
2400OP_1001 ()
2401{
4f425a32 2402 int64 tmp;
87178dbd
MM		 2403
2404 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2405 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2406 if (State.ST)
2407 {
2408 if ( tmp > MAX32)
2409 State.a[OP[0]] = MAX32;
2410 else if ( tmp < MIN32)
2411 State.a[OP[0]] = MIN32;
2412 else
2413 State.a[OP[0]] = tmp & MASK40;
2414 }
2415 else
2416 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2417
2418 trace_output (OP_ACCUM);
4c38885c
MH		 2419}
2420
2421/* sub */
2422
2423void
2424OP_1003 ()
2934d1c9 2425{
4f425a32 2426 int64 tmp;
87178dbd
MM		 2427
2428 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2429 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2430 if (State.ST)
2431 {
2432 if (tmp > MAX32)
2433 State.a[OP[0]] = MAX32;
2434 else if ( tmp < MIN32)
2435 State.a[OP[0]] = MIN32;
2436 else
2437 State.a[OP[0]] = tmp & MASK40;
2438 }
2439 else
2440 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2441
2442 trace_output (OP_ACCUM);
2934d1c9
MH		 2443}
2444
2445/* sub2w */
2446void
2447OP_1000 ()
2448{
4c38885c
MH		 2449 int64 tmp;
2450 int32 a,b;
4c38885c 2451
87178dbd 2452 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
4c38885c
MH		 2453 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2454 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2455 tmp = a-b;
2456 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2457 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2458 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2459 trace_output (OP_DREG);
2934d1c9
MH		 2460}
2461
2462/* subac3 */
2463void
2464OP_17000000 ()
2465{
4f425a32 2466 int64 tmp;
87178dbd
MM		 2467
2468 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2469 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2470 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2471 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2472 trace_output (OP_DREG);
2934d1c9
MH		 2473}
2474
2475/* subac3 */
2476void
2477OP_17000002 ()
2478{
4f425a32 2479 int64 tmp;
87178dbd
MM		 2480
2481 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2482 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2483 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2484 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2485 trace_output (OP_DREG);
2934d1c9
MH		 2486}
2487
2488/* subac3s */
2489void
2490OP_17001000 ()
2491{
4f425a32 2492 int64 tmp;
87178dbd
MM		 2493
2494 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2495 State.F1 = State.F0;
2496 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2497 if ( tmp > MAX32)
2498 {
2499 State.regs[OP[0]] = 0x7fff;
2500 State.regs[OP[0]+1] = 0xffff;
2501 State.F0 = 1;
2502 }
2503 else if (tmp < MIN32)
2504 {
2505 State.regs[OP[0]] = 0x8000;
2506 State.regs[OP[0]+1] = 0;
2507 State.F0 = 1;
2508 }
2509 else
2510 {
2511 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2512 State.regs[OP[0]+1] = tmp & 0xffff;
2513 State.F0 = 0;
2514 }
87178dbd 2515 trace_output (OP_DREG);
2934d1c9
MH		 2516}
2517
2518/* subac3s */
2519void
2520OP_17001002 ()
2521{
4f425a32 2522 int64 tmp;
87178dbd
MM		 2523
2524 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2525 State.F1 = State.F0;
2526 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2527 if ( tmp > MAX32)
2528 {
2529 State.regs[OP[0]] = 0x7fff;
2530 State.regs[OP[0]+1] = 0xffff;
2531 State.F0 = 1;
2532 }
2533 else if (tmp < MIN32)
2534 {
2535 State.regs[OP[0]] = 0x8000;
2536 State.regs[OP[0]+1] = 0;
2537 State.F0 = 1;
2538 }
2539 else
2540 {
2541 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2542 State.regs[OP[0]+1] = tmp & 0xffff;
2543 State.F0 = 0;
2544 }
87178dbd 2545 trace_output (OP_DREG);
2934d1c9
MH		 2546}
2547
2548/* subi */
2549void
2550OP_1 ()
2551{
4c38885c 2552 int32 tmp;
4f425a32
MH		 2553 if (OP[1] == 0)
2554 OP[1] = 16;
87178dbd
MM		 2555
2556 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c
MH		 2557 tmp = (int16)State.regs[OP[0]] - OP[1];
2558 State.C = (tmp & 0xffff0000) ? 1 : 0;
2559 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2560 trace_output (OP_REG);
2934d1c9
MH		 2561}
2562
2563/* trap */
2564void
2565OP_5F00 ()
2566{
a5719092 2567 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2568 trace_output (OP_VOID);
8918b3a7 2569
63a91cfb 2570 switch (OP[0])
2934d1c9 2571 {
63a91cfb 2572 default:
19d44375 2573#if 0
7eebfc62 2574 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
63a91cfb 2575 State.exception = SIGILL;
19d44375
MM		 2576#else
2577 /* Use any other traps for batch debugging. */
2578 {
2579 int i;
2580 static int first_time = 1;
2581
2582 if (first_time)
2583 {
2584 first_time = 0;
2585 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2586 for (i = 0; i < 16; i++)
2587 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2588 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2589 }
2590
2591 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2592
2593 for (i = 0; i < 16; i++)
2594 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2595
2596 for (i = 0; i < 2; i++)
2597 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2598 ((int)(State.a[OP[i]] >> 32) & 0xff),
2599 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
2600
2601 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2602 State.F0 != 0, State.F1 != 0, State.C != 0);
2603 break;
2604#endif
63a91cfb
MM		 2605
2606 case 0:
2607 /* Trap 0 is used for simulating low-level I/O */
2608 {
2609 int save_errno = errno;
2610 errno = 0;
2611
2612/* Registers passed to trap 0 */
2613
65c0d7de
MA		 2614#define FUNC State.regs[6] /* function number */
2615#define PARM1 State.regs[2] /* optional parm 1 */
2616#define PARM2 State.regs[3] /* optional parm 2 */
2617#define PARM3 State.regs[4] /* optional parm 3 */
2618#define PARM4 State.regs[5] /* optional parm 3 */
63a91cfb
MM		 2619
2620/* Registers set by trap 0 */
2621
65c0d7de
MA		 2622#define RETVAL State.regs[2] /* return value */
2623#define RETVAL_HIGH State.regs[2] /* return value */
2624#define RETVAL_LOW State.regs[3] /* return value */
2625#define RETERR State.regs[4] /* return error code */
63a91cfb
MM		 2626
2627/* Turn a pointer in a register into a pointer into real memory. */
2628
2629#define MEMPTR(x) ((char *)((x) + State.imem))
2630
2631 switch (FUNC)
2632 {
2633#if !defined(__GO32__) && !defined(_WIN32)
63a91cfb
MM		 2634 case SYS_fork:
2635 RETVAL = fork ();
8918b3a7
MM		 2636 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2637 trace_output (OP_R2);
63a91cfb 2638 break;
8918b3a7 2639
57bc1a72
MM		 2640 case SYS_getpid:
2641 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2642 RETVAL = getpid ();
2643 trace_output (OP_R2);
2644 break;
2645
2646 case SYS_kill:
2647 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2648 if (PARM1 == getpid ())
2649 {
2650 trace_output (OP_VOID);
2651 State.exception = PARM2;
2652 }
2653 else
2654 {
2655 int os_sig = -1;
2656 switch (PARM2)
2657 {
2658#ifdef SIGHUP
2659 case 1: os_sig = SIGHUP; break;
2660#endif
2661#ifdef SIGINT
2662 case 2: os_sig = SIGINT; break;
2663#endif
2664#ifdef SIGQUIT
2665 case 3: os_sig = SIGQUIT; break;
2666#endif
2667#ifdef SIGILL
2668 case 4: os_sig = SIGILL; break;
2669#endif
2670#ifdef SIGTRAP
2671 case 5: os_sig = SIGTRAP; break;
2672#endif
2673#ifdef SIGABRT
2674 case 6: os_sig = SIGABRT; break;
2675#elif defined(SIGIOT)
2676 case 6: os_sig = SIGIOT; break;
2677#endif
2678#ifdef SIGEMT
2679 case 7: os_sig = SIGEMT; break;
2680#endif
2681#ifdef SIGFPE
2682 case 8: os_sig = SIGFPE; break;
2683#endif
2684#ifdef SIGKILL
2685 case 9: os_sig = SIGKILL; break;
2686#endif
2687#ifdef SIGBUS
2688 case 10: os_sig = SIGBUS; break;
2689#endif
2690#ifdef SIGSEGV
2691 case 11: os_sig = SIGSEGV; break;
2692#endif
2693#ifdef SIGSYS
2694 case 12: os_sig = SIGSYS; break;
2695#endif
2696#ifdef SIGPIPE
2697 case 13: os_sig = SIGPIPE; break;
2698#endif
2699#ifdef SIGALRM
2700 case 14: os_sig = SIGALRM; break;
2701#endif
2702#ifdef SIGTERM
2703 case 15: os_sig = SIGTERM; break;
2704#endif
2705#ifdef SIGURG
2706 case 16: os_sig = SIGURG; break;
2707#endif
2708#ifdef SIGSTOP
2709 case 17: os_sig = SIGSTOP; break;
2710#endif
2711#ifdef SIGTSTP
2712 case 18: os_sig = SIGTSTP; break;
2713#endif
2714#ifdef SIGCONT
2715 case 19: os_sig = SIGCONT; break;
2716#endif
2717#ifdef SIGCHLD
2718 case 20: os_sig = SIGCHLD; break;
2719#elif defined(SIGCLD)
2720 case 20: os_sig = SIGCLD; break;
2721#endif
2722#ifdef SIGTTIN
2723 case 21: os_sig = SIGTTIN; break;
2724#endif
2725#ifdef SIGTTOU
2726 case 22: os_sig = SIGTTOU; break;
2727#endif
2728#ifdef SIGIO
2729 case 23: os_sig = SIGIO; break;
2730#elif defined (SIGPOLL)
2731 case 23: os_sig = SIGPOLL; break;
2732#endif
2733#ifdef SIGXCPU
2734 case 24: os_sig = SIGXCPU; break;
2735#endif
2736#ifdef SIGXFSZ
2737 case 25: os_sig = SIGXFSZ; break;
2738#endif
2739#ifdef SIGVTALRM
2740 case 26: os_sig = SIGVTALRM; break;
2741#endif
2742#ifdef SIGPROF
2743 case 27: os_sig = SIGPROF; break;
2744#endif
2745#ifdef SIGWINCH
2746 case 28: os_sig = SIGWINCH; break;
2747#endif
2748#ifdef SIGLOST
2749 case 29: os_sig = SIGLOST; break;
2750#endif
2751#ifdef SIGUSR1
2752 case 30: os_sig = SIGUSR1; break;
2753#endif
2754#ifdef SIGUSR2
2755 case 31: os_sig = SIGUSR2; break;
2756#endif
2757 }
2758
2759 if (os_sig == -1)
2760 {
2761 trace_output (OP_VOID);
2762 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
2763 State.exception = SIGILL;
2764 }
2765 else
2766 {
2767 RETVAL = kill (PARM1, PARM2);
2768 trace_output (OP_R2);
2769 }
2770 }
2771 break;
2772
63a91cfb
MM		 2773 case SYS_execve:
2774 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2775 (char **)MEMPTR (PARM3));
8918b3a7
MM		 2776 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2777 trace_output (OP_R2);
63a91cfb 2778 break;
8918b3a7 2779
63a91cfb
MM		 2780 case SYS_execv:
2781 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
8918b3a7
MM		 2782 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2783 trace_output (OP_R2);
63a91cfb 2784 break;
8918b3a7 2785
63a91cfb
MM		 2786 case SYS_pipe:
2787 {
2788 reg_t buf;
2789 int host_fd[2];
2790
2791 buf = PARM1;
2792 RETVAL = pipe (host_fd);
2793 SW (buf, host_fd[0]);
2794 buf += sizeof(uint16);
2795 SW (buf, host_fd[1]);
8918b3a7
MM		 2796 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2797 trace_output (OP_R2);
63a91cfb
MM		 2798 }
2799 break;
8918b3a7 2800
63a91cfb
MM		 2801 case SYS_wait:
2802 {
2803 int status;
2804
2805 RETVAL = wait (&status);
8918b3a7
MM		 2806 if (PARM1)
2807 SW (PARM1, status);
2808 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2809 trace_output (OP_R2);
63a91cfb
MM		 2810 }
2811 break;
57bc1a72
MM		 2812#else
2813 case SYS_getpid:
2814 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2815 RETVAL = 1;
2816 trace_output (OP_R2);
2817 break;
2818
2819 case SYS_kill:
2820 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2821 trace_output (OP_VOID);
2822 State.exception = PARM2;
2823 break;
63a91cfb 2824#endif
8918b3a7 2825
63a91cfb
MM		 2826 case SYS_read:
2827 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2828 PARM3);
8918b3a7
MM		 2829 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2830 trace_output (OP_R2);
63a91cfb 2831 break;
8918b3a7 2832
63a91cfb
MM		 2833 case SYS_write:
2834 if (PARM1 == 1)
2835 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2836 MEMPTR (PARM2), PARM3);
2837 else
2838 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2839 MEMPTR (PARM2), PARM3);
8918b3a7
MM		 2840 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2841 trace_output (OP_R2);
63a91cfb 2842 break;
8918b3a7 2843
63a91cfb 2844 case SYS_lseek:
65c0d7de
MA		 2845 {
2846 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2847 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2848 PARM4);
2849 RETVAL_HIGH = ret >> 16;
2850 RETVAL_LOW = ret & 0xffff;
2851 }
8918b3a7
MM		 2852 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2853 trace_output (OP_R2R3);
63a91cfb 2854 break;
8918b3a7 2855
63a91cfb
MM		 2856 case SYS_close:
2857 RETVAL = d10v_callback->close (d10v_callback, PARM1);
8918b3a7
MM		 2858 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2859 trace_output (OP_R2);
63a91cfb 2860 break;
8918b3a7 2861
63a91cfb
MM		 2862 case SYS_open:
2863 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2864 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2865 trace_output (OP_R2);
2866 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2867 trace_output (OP_R2);
63a91cfb 2868 break;
8918b3a7 2869
63a91cfb 2870 case SYS_exit:
a49a15ad 2871 State.exception = SIG_D10V_EXIT;
8918b3a7
MM		 2872 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2873 trace_output (OP_VOID);
63a91cfb 2874 break;
63a91cfb 2875
8719be26 2876 case SYS_stat:
63a91cfb
MM		 2877 /* stat system call */
2878 {
2879 struct stat host_stat;
2880 reg_t buf;
2881
2882 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2883
2884 buf = PARM2;
2885
2886 /* The hard-coded offsets and sizes were determined by using
2887 * the D10V compiler on a test program that used struct stat.
2888 */
2889 SW (buf, host_stat.st_dev);
2890 SW (buf+2, host_stat.st_ino);
2891 SW (buf+4, host_stat.st_mode);
2892 SW (buf+6, host_stat.st_nlink);
2893 SW (buf+8, host_stat.st_uid);
2894 SW (buf+10, host_stat.st_gid);
2895 SW (buf+12, host_stat.st_rdev);
2896 SLW (buf+16, host_stat.st_size);
2897 SLW (buf+20, host_stat.st_atime);
2898 SLW (buf+28, host_stat.st_mtime);
2899 SLW (buf+36, host_stat.st_ctime);
2900 }
8918b3a7
MM		 2901 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2902 trace_output (OP_R2);
63a91cfb 2903 break;
63a91cfb 2904
63a91cfb
MM		 2905 case SYS_chown:
2906 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
8918b3a7
MM		 2907 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2908 trace_output (OP_R2);
63a91cfb 2909 break;
8918b3a7 2910
63a91cfb
MM		 2911 case SYS_chmod:
2912 RETVAL = chmod (MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2913 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2914 trace_output (OP_R2);
63a91cfb 2915 break;
8918b3a7 2916
63a91cfb
MM		 2917 case SYS_utime:
2918 /* Cast the second argument to void *, to avoid type mismatch
2919 if a prototype is present. */
2920 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
8918b3a7
MM		 2921 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2922 trace_output (OP_R2);
2923 break;
2924
2925 case SYS_time:
2926 {
2927 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2928 RETVAL_HIGH = ret >> 16;
2929 RETVAL_LOW = ret & 0xffff;
2930 }
2931 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2932 trace_output (OP_R2R3);
63a91cfb 2933 break;
8918b3a7 2934
63a91cfb
MM		 2935 default:
2936 abort ();
2937 }
65c0d7de 2938 RETERR = d10v_callback->get_errno(d10v_callback);
63a91cfb
MM		 2939 break;
2940 }
2941
2942 case 1:
2943 /* Trap 1 prints a string */
2944 {
2945 char *fstr = State.regs[2] + State.imem;
2946 fputs (fstr, stdout);
2947 break;
2948 }
2949
2950 case 2:
2951 /* Trap 2 calls printf */
2952 {
2953 char *fstr = State.regs[2] + State.imem;
7eebfc62
MM		 2954 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2955 (int16)State.regs[3],
2956 (int16)State.regs[4],
2957 (int16)State.regs[5]);
63a91cfb
MM		 2958 break;
2959 }
2960
2961 case 3:
2962 /* Trap 3 writes a character */
2963 putchar (State.regs[2]);
2964 break;
19d44375 2965 }
2934d1c9
MH		 2966 }
2967}
2968
2969/* tst0i */
2970void
2971OP_7000000 ()
2972{
87178dbd 2973 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2974 State.F1 = State.F0;
4f425a32 2975 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 2976 trace_output (OP_FLAG);
2934d1c9
MH		 2977}
2978
2979/* tst1i */
2980void
2981OP_F000000 ()
2982{
87178dbd 2983 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2984 State.F1 = State.F0;
4f425a32 2985 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 2986 trace_output (OP_FLAG);
2934d1c9
MH		 2987}
2988
2989/* wait */
2990void
2991OP_5F80 ()
2992{
87178dbd 2993 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2994 State.IE = 1;
87178dbd 2995 trace_output (OP_VOID);
2934d1c9
MH		 2996}
2997
2998/* xor */
2999void
3000OP_A00 ()
3001{
87178dbd 3002 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 3003 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 3004 trace_output (OP_REG);
2934d1c9
MH		 3005}
3006
3007/* xor3 */
3008void
3009OP_5000000 ()
3010{
87178dbd 3011 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 3012 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 3013 trace_output (OP_REG);
2934d1c9
MH		 3014}
3015
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