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import gdb-1999-11-01 snapshot
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
c906108c
SS		 1#include "config.h"
2
3#include <signal.h>
4#include <errno.h>
5#include <sys/types.h>
6#include <sys/stat.h>
7#ifdef HAVE_UNISTD_H
8#include <unistd.h>
9#endif
10
11#include "d10v_sim.h"
12#include "simops.h"
13#include "targ-vals.h"
14
15extern char *strrchr ();
16
17enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
30 OP_FLAG_OUTPUT,
31 OP_CONSTANT16,
32 OP_CONSTANT8,
33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
cff3e48b 37 OP_MEMREF3,
c906108c
SS		 38 OP_POSTDEC,
39 OP_POSTINC,
40 OP_PREDEC,
41 OP_R0,
42 OP_R1,
43 OP_R2,
44};
45
46
47enum {
48 PSW_MASK = (PSW_SM_BIT
49 | PSW_EA_BIT
50 | PSW_DB_BIT
c906108c
SS		 51 | PSW_IE_BIT
52 | PSW_RP_BIT
53 | PSW_MD_BIT
54 | PSW_FX_BIT
55 | PSW_ST_BIT
56 | PSW_F0_BIT
57 | PSW_F1_BIT
58 | PSW_C_BIT),
59};
60
61reg_t
62move_to_cr (int cr, reg_t mask, reg_t val)
63{
64 /* A MASK bit is set when the corresponding bit in the CR should
65 be left alone */
66 /* This assumes that (VAL & MASK) == 0 */
67 switch (cr)
68 {
69 case PSW_CR:
70 val &= PSW_MASK;
71 if ((mask & PSW_SM_BIT) == 0)
72 {
73 int new_sm = (val & PSW_SM_BIT) != 0;
74 SET_HELD_SP (PSW_SM, GPR (SP_IDX)); /* save old SP */
75 if (PSW_SM != new_sm)
76 SET_GPR (SP_IDX, HELD_SP (new_sm)); /* restore new SP */
77 }
78 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
79 {
80 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
81 {
82 (*d10v_callback->printf_filtered)
83 (d10v_callback,
84 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
85 PC<<2);
86 State.exception = SIGILL;
87 }
88 }
89 /* keep an up-to-date psw around for tracing */
90 State.trace.psw = (State.trace.psw & mask) | val;
91 break;
92 case BPSW_CR:
93 case DPSW_CR:
94 val &= PSW_MASK;
95 break;
96 case MOD_S_CR:
97 case MOD_E_CR:
98 val &= ~1;
99 break;
100 default:
101 break;
102 }
103 /* only issue an update if the register is being changed */
104 if ((State.cregs[cr] & ~mask) != val)
105 SLOT_PEND_MASK (State.cregs[cr], mask, val);
106 return val;
107}
108
109#ifdef DEBUG
110static void trace_input_func PARAMS ((char *name,
111 enum op_types in1,
112 enum op_types in2,
113 enum op_types in3));
114
115#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
116
117#ifndef SIZE_INSTRUCTION
118#define SIZE_INSTRUCTION 8
119#endif
120
121#ifndef SIZE_OPERANDS
122#define SIZE_OPERANDS 18
123#endif
124
125#ifndef SIZE_VALUES
126#define SIZE_VALUES 13
127#endif
128
129#ifndef SIZE_LOCATION
130#define SIZE_LOCATION 20
131#endif
132
133#ifndef SIZE_PC
134#define SIZE_PC 6
135#endif
136
137#ifndef SIZE_LINE_NUMBER
138#define SIZE_LINE_NUMBER 4
139#endif
140
141static void
142trace_input_func (name, in1, in2, in3)
143 char *name;
144 enum op_types in1;
145 enum op_types in2;
146 enum op_types in3;
147{
148 char *comma;
149 enum op_types in[3];
150 int i;
151 char buf[1024];
152 char *p;
153 long tmp;
154 char *type;
155 const char *filename;
156 const char *functionname;
157 unsigned int linenumber;
158 bfd_vma byte_pc;
159
160 if ((d10v_debug & DEBUG_TRACE) == 0)
161 return;
162
163 switch (State.ins_type)
164 {
165 default:
166 case INS_UNKNOWN: type = " ?"; break;
167 case INS_LEFT: type = " L"; break;
168 case INS_RIGHT: type = " R"; break;
169 case INS_LEFT_PARALLEL: type = "*L"; break;
170 case INS_RIGHT_PARALLEL: type = "*R"; break;
171 case INS_LEFT_COND_TEST: type = "?L"; break;
172 case INS_RIGHT_COND_TEST: type = "?R"; break;
173 case INS_LEFT_COND_EXE: type = "&L"; break;
174 case INS_RIGHT_COND_EXE: type = "&R"; break;
175 case INS_LONG: type = " B"; break;
176 }
177
178 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
179 (*d10v_callback->printf_filtered) (d10v_callback,
180 "0x%.*x %s: %-*s ",
181 SIZE_PC, (unsigned)PC,
182 type,
183 SIZE_INSTRUCTION, name);
184
185 else
186 {
187 buf[0] = '\0';
188 byte_pc = decode_pc ();
189 if (text && byte_pc >= text_start && byte_pc < text_end)
190 {
191 filename = (const char *)0;
192 functionname = (const char *)0;
193 linenumber = 0;
194 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
195 &filename, &functionname, &linenumber))
196 {
197 p = buf;
198 if (linenumber)
199 {
200 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
201 p += strlen (p);
202 }
203 else
204 {
205 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
206 p += SIZE_LINE_NUMBER+2;
207 }
208
209 if (functionname)
210 {
211 sprintf (p, "%s ", functionname);
212 p += strlen (p);
213 }
214 else if (filename)
215 {
216 char *q = strrchr (filename, '/');
217 sprintf (p, "%s ", (q) ? q+1 : filename);
218 p += strlen (p);
219 }
220
221 if (*p == ' ')
222 *p = '\0';
223 }
224 }
225
226 (*d10v_callback->printf_filtered) (d10v_callback,
227 "0x%.*x %s: %-*.*s %-*s ",
228 SIZE_PC, (unsigned)PC,
229 type,
230 SIZE_LOCATION, SIZE_LOCATION, buf,
231 SIZE_INSTRUCTION, name);
232 }
233
234 in[0] = in1;
235 in[1] = in2;
236 in[2] = in3;
237 comma = "";
238 p = buf;
239 for (i = 0; i < 3; i++)
240 {
241 switch (in[i])
242 {
243 case OP_VOID:
244 case OP_R0:
245 case OP_R1:
246 case OP_R2:
247 break;
248
249 case OP_REG:
250 case OP_REG_OUTPUT:
251 case OP_DREG:
252 case OP_DREG_OUTPUT:
253 sprintf (p, "%sr%d", comma, OP[i]);
254 p += strlen (p);
255 comma = ",";
256 break;
257
258 case OP_CR:
259 case OP_CR_OUTPUT:
260 case OP_CR_REVERSE:
261 sprintf (p, "%scr%d", comma, OP[i]);
262 p += strlen (p);
263 comma = ",";
264 break;
265
266 case OP_ACCUM:
267 case OP_ACCUM_OUTPUT:
268 case OP_ACCUM_REVERSE:
269 sprintf (p, "%sa%d", comma, OP[i]);
270 p += strlen (p);
271 comma = ",";
272 break;
273
274 case OP_CONSTANT16:
275 sprintf (p, "%s%d", comma, OP[i]);
276 p += strlen (p);
277 comma = ",";
278 break;
279
280 case OP_CONSTANT8:
281 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
282 p += strlen (p);
283 comma = ",";
284 break;
285
286 case OP_CONSTANT4:
287 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
288 p += strlen (p);
289 comma = ",";
290 break;
291
292 case OP_CONSTANT3:
293 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
294 p += strlen (p);
295 comma = ",";
296 break;
297
298 case OP_MEMREF:
299 sprintf (p, "%s@r%d", comma, OP[i]);
300 p += strlen (p);
301 comma = ",";
302 break;
303
304 case OP_MEMREF2:
305 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
306 p += strlen (p);
307 comma = ",";
308 break;
309
cff3e48b
JM		 310 case OP_MEMREF3:
311 sprintf (p, "%s@%d", comma, OP[i]);
312 p += strlen (p);
313 comma = ",";
314 break;
315
c906108c
SS		 316 case OP_POSTINC:
317 sprintf (p, "%s@r%d+", comma, OP[i]);
318 p += strlen (p);
319 comma = ",";
320 break;
321
322 case OP_POSTDEC:
323 sprintf (p, "%s@r%d-", comma, OP[i]);
324 p += strlen (p);
325 comma = ",";
326 break;
327
328 case OP_PREDEC:
329 sprintf (p, "%s@-r%d", comma, OP[i]);
330 p += strlen (p);
331 comma = ",";
332 break;
333
334 case OP_FLAG:
335 case OP_FLAG_OUTPUT:
336 if (OP[i] == 0)
337 sprintf (p, "%sf0", comma);
338
339 else if (OP[i] == 1)
340 sprintf (p, "%sf1", comma);
341
342 else
343 sprintf (p, "%sc", comma);
344
345 p += strlen (p);
346 comma = ",";
347 break;
348 }
349 }
350
351 if ((d10v_debug & DEBUG_VALUES) == 0)
352 {
353 *p++ = '\n';
354 *p = '\0';
355 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
356 }
357 else
358 {
359 *p = '\0';
360 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
361
362 p = buf;
363 for (i = 0; i < 3; i++)
364 {
365 buf[0] = '\0';
366 switch (in[i])
367 {
368 case OP_VOID:
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
370 break;
371
372 case OP_REG_OUTPUT:
373 case OP_DREG_OUTPUT:
374 case OP_CR_OUTPUT:
375 case OP_ACCUM_OUTPUT:
376 case OP_FLAG_OUTPUT:
377 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
378 break;
379
380 case OP_REG:
381 case OP_MEMREF:
382 case OP_POSTDEC:
383 case OP_POSTINC:
384 case OP_PREDEC:
385 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
386 (uint16) GPR (OP[i]));
387 break;
388
cff3e48b
JM		 389 case OP_MEMREF3:
390 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
391 break;
392
c906108c
SS		 393 case OP_DREG:
394 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
395 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
396 break;
397
398 case OP_CR:
399 case OP_CR_REVERSE:
400 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
401 (uint16) CREG (OP[i]));
402 break;
403
404 case OP_ACCUM:
405 case OP_ACCUM_REVERSE:
406 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
407 ((int)(ACC (OP[i]) >> 32) & 0xff),
408 ((unsigned long) ACC (OP[i])) & 0xffffffff);
409 break;
410
411 case OP_CONSTANT16:
412 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
413 (uint16)OP[i]);
414 break;
415
416 case OP_CONSTANT4:
417 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
418 (uint16)SEXT4(OP[i]));
419 break;
420
421 case OP_CONSTANT8:
422 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
423 (uint16)SEXT8(OP[i]));
424 break;
425
426 case OP_CONSTANT3:
427 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
428 (uint16)SEXT3(OP[i]));
429 break;
430
431 case OP_FLAG:
432 if (OP[i] == 0)
433 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
434 PSW_F0 != 0);
435
436 else if (OP[i] == 1)
437 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
438 PSW_F1 != 0);
439
440 else
441 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
442 PSW_C != 0);
443
444 break;
445
446 case OP_MEMREF2:
447 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
448 (uint16)OP[i]);
449 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
450 (uint16)GPR (OP[i + 1]));
451 i++;
452 break;
453
454 case OP_R0:
455 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
456 (uint16) GPR (0));
457 break;
458
459 case OP_R1:
460 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
461 (uint16) GPR (1));
462 break;
463
464 case OP_R2:
465 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
466 (uint16) GPR (2));
467 break;
468
469 }
470 }
471 }
472
473 (*d10v_callback->flush_stdout) (d10v_callback);
474}
475
476static void
477do_trace_output_flush (void)
478{
479 (*d10v_callback->flush_stdout) (d10v_callback);
480}
481
482static void
483do_trace_output_finish (void)
484{
485 (*d10v_callback->printf_filtered) (d10v_callback,
486 " F0=%d F1=%d C=%d\n",
487 (State.trace.psw & PSW_F0_BIT) != 0,
488 (State.trace.psw & PSW_F1_BIT) != 0,
489 (State.trace.psw & PSW_C_BIT) != 0);
490 (*d10v_callback->flush_stdout) (d10v_callback);
491}
492
493static void
494trace_output_40 (uint64 val)
495{
496 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
497 {
498 (*d10v_callback->printf_filtered) (d10v_callback,
499 " :: %*s0x%.2x%.8lx",
500 SIZE_VALUES - 12,
501 "",
502 ((int)(val >> 32) & 0xff),
503 ((unsigned long) val) & 0xffffffff);
504 do_trace_output_finish ();
505 }
506}
507
508static void
509trace_output_32 (uint32 val)
510{
511 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
512 {
513 (*d10v_callback->printf_filtered) (d10v_callback,
514 " :: %*s0x%.8x",
515 SIZE_VALUES - 10,
516 "",
517 (int) val);
518 do_trace_output_finish ();
519 }
520}
521
522static void
523trace_output_16 (uint16 val)
524{
525 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
526 {
527 (*d10v_callback->printf_filtered) (d10v_callback,
528 " :: %*s0x%.4x",
529 SIZE_VALUES - 6,
530 "",
531 (int) val);
532 do_trace_output_finish ();
533 }
534}
535
536static void
537trace_output_void ()
538{
539 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
540 {
541 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
542 do_trace_output_flush ();
543 }
544}
545
546static void
547trace_output_flag ()
548{
549 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
550 {
551 (*d10v_callback->printf_filtered) (d10v_callback,
552 " :: %*s",
553 SIZE_VALUES,
554 "");
555 do_trace_output_finish ();
556 }
557}
558
559
560
561
562#else
563#define trace_input(NAME, IN1, IN2, IN3)
564#define trace_output(RESULT)
565#endif
566
567/* abs */
568void
569OP_4607 ()
570{
571 int16 tmp;
572 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
573 SET_PSW_F1 (PSW_F0);
574 tmp = GPR(OP[0]);
575 if (tmp < 0)
576 {
577 tmp = - tmp;
578 SET_PSW_F0 (1);
579 }
580 else
581 SET_PSW_F0 (0);
582 SET_GPR (OP[0], tmp);
583 trace_output_16 (tmp);
584}
585
586/* abs */
587void
588OP_5607 ()
589{
590 int64 tmp;
591 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
592 SET_PSW_F1 (PSW_F0);
593
594 tmp = SEXT40 (ACC (OP[0]));
595 if (tmp < 0 )
596 {
597 tmp = - tmp;
598 if (PSW_ST)
599 {
600 if (tmp > SEXT40(MAX32))
601 tmp = (MAX32);
602 else if (tmp < SEXT40(MIN32))
603 tmp = (MIN32);
604 else
605 tmp = (tmp & MASK40);
606 }
607 else
608 tmp = (tmp & MASK40);
609 SET_PSW_F0 (1);
610 }
611 else
612 {
613 tmp = (tmp & MASK40);
614 SET_PSW_F0 (0);
615 }
616 SET_ACC (OP[0], tmp);
617 trace_output_40 (tmp);
618}
619
620/* add */
621void
622OP_200 ()
623{
624 uint16 a = GPR (OP[0]);
625 uint16 b = GPR (OP[1]);
626 uint16 tmp = (a + b);
627 trace_input ("add", OP_REG, OP_REG, OP_VOID);
628 SET_PSW_C (a > tmp);
629 SET_GPR (OP[0], tmp);
630 trace_output_16 (tmp);
631}
632
633/* add */
634void
635OP_1201 ()
636{
637 int64 tmp;
638 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
639
640 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
641 if (PSW_ST)
642 {
643 if (tmp > SEXT40(MAX32))
644 tmp = (MAX32);
645 else if (tmp < SEXT40(MIN32))
646 tmp = (MIN32);
647 else
648 tmp = (tmp & MASK40);
649 }
650 else
651 tmp = (tmp & MASK40);
652 SET_ACC (OP[0], tmp);
653 trace_output_40 (tmp);
654}
655
656/* add */
657void
658OP_1203 ()
659{
660 int64 tmp;
661 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
662
663 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
664 if (PSW_ST)
665 {
666 if (tmp > SEXT40(MAX32))
667 tmp = (MAX32);
668 else if (tmp < SEXT40(MIN32))
669 tmp = (MIN32);
670 else
671 tmp = (tmp & MASK40);
672 }
673 else
674 tmp = (tmp & MASK40);
675 SET_ACC (OP[0], tmp);
676 trace_output_40 (tmp);
677}
678
679/* add2w */
680void
681OP_1200 ()
682{
683 uint32 tmp;
684 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
685 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
686 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
687 tmp = a + b;
688 SET_PSW_C (tmp < a);
689 SET_GPR (OP[0] + 0, (tmp >> 16));
690 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
691 trace_output_32 (tmp);
692}
693
694/* add3 */
695void
696OP_1000000 ()
697{
698 uint16 a = GPR (OP[1]);
699 uint16 b = OP[2];
700 uint16 tmp = (a + b);
701 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
702 SET_PSW_C (tmp < a);
703 SET_GPR (OP[0], tmp);
704 trace_output_16 (tmp);
705}
706
707/* addac3 */
708void
709OP_17000200 ()
710{
711 int64 tmp;
712 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
713
714 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
715 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
716 SET_GPR (OP[0] + 1, (tmp & 0xffff));
717 trace_output_32 (tmp);
718}
719
720/* addac3 */
721void
722OP_17000202 ()
723{
724 int64 tmp;
725 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
726
727 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
728 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
729 SET_GPR (OP[0] + 1, tmp & 0xffff);
730 trace_output_32 (tmp);
731}
732
733/* addac3s */
734void
735OP_17001200 ()
736{
737 int64 tmp;
738 SET_PSW_F1 (PSW_F0);
739
740 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
741 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
742 if (tmp > SEXT40(MAX32))
743 {
744 tmp = (MAX32);
745 SET_PSW_F0 (1);
746 }
747 else if (tmp < SEXT40(MIN32))
748 {
749 tmp = (MIN32);
750 SET_PSW_F0 (1);
751 }
752 else
753 {
754 SET_PSW_F0 (0);
755 }
756 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
757 SET_GPR (OP[0] + 1, (tmp & 0xffff));
758 trace_output_32 (tmp);
759}
760
761/* addac3s */
762void
763OP_17001202 ()
764{
765 int64 tmp;
766 SET_PSW_F1 (PSW_F0);
767
768 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
769 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
770 if (tmp > SEXT40(MAX32))
771 {
772 tmp = (MAX32);
773 SET_PSW_F0 (1);
774 }
775 else if (tmp < SEXT40(MIN32))
776 {
777 tmp = (MIN32);
778 SET_PSW_F0 (1);
779 }
780 else
781 {
782 SET_PSW_F0 (0);
783 }
784 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
785 SET_GPR (OP[0] + 1, (tmp & 0xffff));
786 trace_output_32 (tmp);
787}
788
789/* addi */
790void
791OP_201 ()
792{
793 uint16 a = GPR (OP[0]);
794 uint16 b;
795 uint16 tmp;
796 if (OP[1] == 0)
797 OP[1] = 16;
798 b = OP[1];
799 tmp = (a + b);
800 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
801 SET_PSW_C (tmp < a);
802 SET_GPR (OP[0], tmp);
803 trace_output_16 (tmp);
804}
805
806/* and */
807void
808OP_C00 ()
809{
810 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
811 trace_input ("and", OP_REG, OP_REG, OP_VOID);
812 SET_GPR (OP[0], tmp);
813 trace_output_16 (tmp);
814}
815
816/* and3 */
817void
818OP_6000000 ()
819{
820 uint16 tmp = GPR (OP[1]) & OP[2];
821 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
822 SET_GPR (OP[0], tmp);
823 trace_output_16 (tmp);
824}
825
826/* bclri */
827void
828OP_C01 ()
829{
830 int16 tmp;
831 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
832 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
833 SET_GPR (OP[0], tmp);
834 trace_output_16 (tmp);
835}
836
837/* bl.s */
838void
839OP_4900 ()
840{
841 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
842 SET_GPR (13, PC + 1);
843 JMP( PC + SEXT8 (OP[0]));
844 trace_output_void ();
845}
846
847/* bl.l */
848void
849OP_24800000 ()
850{
851 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
852 SET_GPR (13, (PC + 1));
853 JMP (PC + OP[0]);
854 trace_output_void ();
855}
856
857/* bnoti */
858void
859OP_A01 ()
860{
861 int16 tmp;
862 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
863 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
864 SET_GPR (OP[0], tmp);
865 trace_output_16 (tmp);
866}
867
868/* bra.s */
869void
870OP_4800 ()
871{
872 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
873 JMP (PC + SEXT8 (OP[0]));
874 trace_output_void ();
875}
876
877/* bra.l */
878void
879OP_24000000 ()
880{
881 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
882 JMP (PC + OP[0]);
883 trace_output_void ();
884}
885
886/* brf0f.s */
887void
888OP_4A00 ()
889{
890 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
891 if (!PSW_F0)
892 JMP (PC + SEXT8 (OP[0]));
893 trace_output_flag ();
894}
895
896/* brf0f.l */
897void
898OP_25000000 ()
899{
900 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
901 if (!PSW_F0)
902 JMP (PC + OP[0]);
903 trace_output_flag ();
904}
905
906/* brf0t.s */
907void
908OP_4B00 ()
909{
910 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
911 if (PSW_F0)
912 JMP (PC + SEXT8 (OP[0]));
913 trace_output_flag ();
914}
915
916/* brf0t.l */
917void
918OP_25800000 ()
919{
920 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
921 if (PSW_F0)
922 JMP (PC + OP[0]);
923 trace_output_flag ();
924}
925
926/* bseti */
927void
928OP_801 ()
929{
930 int16 tmp;
931 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
932 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
933 SET_GPR (OP[0], tmp);
934 trace_output_16 (tmp);
935}
936
937/* btsti */
938void
939OP_E01 ()
940{
941 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
942 SET_PSW_F1 (PSW_F0);
943 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
944 trace_output_flag ();
945}
946
947/* clrac */
948void
949OP_5601 ()
950{
951 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
952 SET_ACC (OP[0], 0);
953 trace_output_40 (0);
954}
955
956/* cmp */
957void
958OP_600 ()
959{
960 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
961 SET_PSW_F1 (PSW_F0);
962 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
963 trace_output_flag ();
964}
965
966/* cmp */
967void
968OP_1603 ()
969{
970 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
971 SET_PSW_F1 (PSW_F0);
972 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
973 trace_output_flag ();
974}
975
976/* cmpeq */
977void
978OP_400 ()
979{
980 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
981 SET_PSW_F1 (PSW_F0);
982 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
983 trace_output_flag ();
984}
985
986/* cmpeq */
987void
988OP_1403 ()
989{
990 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
991 SET_PSW_F1 (PSW_F0);
992 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
993 trace_output_flag ();
994}
995
996/* cmpeqi.s */
997void
998OP_401 ()
999{
1000 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1001 SET_PSW_F1 (PSW_F0);
1002 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1003 trace_output_flag ();
1004}
1005
1006/* cmpeqi.l */
1007void
1008OP_2000000 ()
1009{
1010 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1011 SET_PSW_F1 (PSW_F0);
1012 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1013 trace_output_flag ();
1014}
1015
1016/* cmpi.s */
1017void
1018OP_601 ()
1019{
1020 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1021 SET_PSW_F1 (PSW_F0);
1022 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1023 trace_output_flag ();
1024}
1025
1026/* cmpi.l */
1027void
1028OP_3000000 ()
1029{
1030 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1031 SET_PSW_F1 (PSW_F0);
1032 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1033 trace_output_flag ();
1034}
1035
1036/* cmpu */
1037void
1038OP_4600 ()
1039{
1040 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1041 SET_PSW_F1 (PSW_F0);
1042 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1043 trace_output_flag ();
1044}
1045
1046/* cmpui */
1047void
1048OP_23000000 ()
1049{
1050 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1051 SET_PSW_F1 (PSW_F0);
1052 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1053 trace_output_flag ();
1054}
1055
1056/* cpfg */
1057void
1058OP_4E09 ()
1059{
1060 uint8 val;
1061
1062 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1063
1064 if (OP[1] == 0)
1065 val = PSW_F0;
1066 else if (OP[1] == 1)
1067 val = PSW_F1;
1068 else
1069 val = PSW_C;
1070 if (OP[0] == 0)
1071 SET_PSW_F0 (val);
1072 else
1073 SET_PSW_F1 (val);
1074
1075 trace_output_flag ();
1076}
1077
1078/* dbt */
1079void
1080OP_5F20 ()
1081{
1082 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1083
1084 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1085 The conditional below is for either of the instruction pairs
1086 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1087 where the dbt instruction should be interpreted.
1088
1089 The module `sim-break' provides a more effective mechanism for
1090 detecting GDB planted breakpoints. The code below may,
1091 eventually, be changed to use that mechanism. */
1092
1093 if (State.ins_type == INS_LEFT
1094 || State.ins_type == INS_RIGHT)
1095 {
1096 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1097 SET_DPC (PC + 1);
1098 SET_DPSW (PSW);
c2c6d25f 1099 SET_PSW (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT));
c906108c
SS		 1100 JMP (DBT_VECTOR_START);
1101 trace_output_void ();
1102 }
1103 else
1104 {
1105 State.exception = SIGTRAP;
1106 }
1107}
1108
1109/* divs */
1110void
1111OP_14002800 ()
1112{
1113 uint16 foo, tmp, tmpf;
1114 uint16 hi;
1115 uint16 lo;
1116
1117 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1118 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1119 tmp = (int16)foo - (int16)(GPR (OP[1]));
1120 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1121 hi = ((tmpf == 1) ? tmp : foo);
1122 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1123 SET_GPR (OP[0] + 0, hi);
1124 SET_GPR (OP[0] + 1, lo);
1125 trace_output_32 (((uint32) hi << 16) | lo);
1126}
1127
1128/* exef0f */
1129void
1130OP_4E04 ()
1131{
1132 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1133 State.exe = (PSW_F0 == 0);
1134 trace_output_flag ();
1135}
1136
1137/* exef0t */
1138void
1139OP_4E24 ()
1140{
1141 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1142 State.exe = (PSW_F0 != 0);
1143 trace_output_flag ();
1144}
1145
1146/* exef1f */
1147void
1148OP_4E40 ()
1149{
1150 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1151 State.exe = (PSW_F1 == 0);
1152 trace_output_flag ();
1153}
1154
1155/* exef1t */
1156void
1157OP_4E42 ()
1158{
1159 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1160 State.exe = (PSW_F1 != 0);
1161 trace_output_flag ();
1162}
1163
1164/* exefaf */
1165void
1166OP_4E00 ()
1167{
1168 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1169 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1170 trace_output_flag ();
1171}
1172
1173/* exefat */
1174void
1175OP_4E02 ()
1176{
1177 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1178 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1179 trace_output_flag ();
1180}
1181
1182/* exetaf */
1183void
1184OP_4E20 ()
1185{
1186 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1187 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1188 trace_output_flag ();
1189}
1190
1191/* exetat */
1192void
1193OP_4E22 ()
1194{
1195 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1196 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1197 trace_output_flag ();
1198}
1199
1200/* exp */
1201void
1202OP_15002A00 ()
1203{
1204 uint32 tmp, foo;
1205 int i;
1206
1207 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1208 if (((int16)GPR (OP[1])) >= 0)
1209 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1210 else
1211 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1212
1213 foo = 0x40000000;
1214 for (i=1;i<17;i++)
1215 {
1216 if (tmp & foo)
1217 {
1218 SET_GPR (OP[0], (i - 1));
1219 trace_output_16 (i - 1);
1220 return;
1221 }
1222 foo >>= 1;
1223 }
1224 SET_GPR (OP[0], 16);
1225 trace_output_16 (16);
1226}
1227
1228/* exp */
1229void
1230OP_15002A02 ()
1231{
1232 int64 tmp, foo;
1233 int i;
1234
1235 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1236 tmp = SEXT40(ACC (OP[1]));
1237 if (tmp < 0)
1238 tmp = ~tmp & MASK40;
1239
1240 foo = 0x4000000000LL;
1241 for (i=1;i<25;i++)
1242 {
1243 if (tmp & foo)
1244 {
1245 SET_GPR (OP[0], i - 9);
1246 trace_output_16 (i - 9);
1247 return;
1248 }
1249 foo >>= 1;
1250 }
1251 SET_GPR (OP[0], 16);
1252 trace_output_16 (16);
1253}
1254
1255/* jl */
1256void
1257OP_4D00 ()
1258{
1259 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1260 SET_GPR (13, PC + 1);
1261 JMP (GPR (OP[0]));
1262 trace_output_void ();
1263}
1264
1265/* jmp */
1266void
1267OP_4C00 ()
1268{
1269 trace_input ("jmp", OP_REG,
1270 (OP[0] == 13) ? OP_R0 : OP_VOID,
1271 (OP[0] == 13) ? OP_R1 : OP_VOID);
1272
1273 JMP (GPR (OP[0]));
1274 trace_output_void ();
1275}
1276
1277/* ld */
1278void
1279OP_30000000 ()
1280{
1281 uint16 tmp;
1282 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1283 tmp = RW (OP[1] + GPR (OP[2]));
1284 SET_GPR (OP[0], tmp);
1285 trace_output_16 (tmp);
1286}
1287
1288/* ld */
1289void
1290OP_6401 ()
1291{
1292 uint16 tmp;
1293 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1294 tmp = RW (GPR (OP[1]));
1295 SET_GPR (OP[0], tmp);
1296 if (OP[0] != OP[1])
1297 INC_ADDR (OP[1], -2);
1298 trace_output_16 (tmp);
1299}
1300
1301/* ld */
1302void
1303OP_6001 ()
1304{
1305 uint16 tmp;
1306 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1307 tmp = RW (GPR (OP[1]));
1308 SET_GPR (OP[0], tmp);
1309 if (OP[0] != OP[1])
1310 INC_ADDR (OP[1], 2);
1311 trace_output_16 (tmp);
1312}
1313
1314/* ld */
1315void
1316OP_6000 ()
1317{
1318 uint16 tmp;
1319 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1320 tmp = RW (GPR (OP[1]));
1321 SET_GPR (OP[0], tmp);
1322 trace_output_16 (tmp);
1323}
1324
cff3e48b
JM		 1325/* ld */
1326void
1327OP_32010000 ()
1328{
1329 uint16 tmp;
1330
1331 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1332 tmp = RW (OP[1]);
1333 SET_GPR (OP[0], tmp);
1334 trace_output_16 (tmp);
1335}
1336
c906108c
SS		 1337/* ld2w */
1338void
1339OP_31000000 ()
1340{
1341 int32 tmp;
1342 uint16 addr = GPR (OP[2]);
1343 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1344 tmp = RLW (OP[1] + addr);
1345 SET_GPR32 (OP[0], tmp);
1346 trace_output_32 (tmp);
1347}
1348
1349/* ld2w */
1350void
1351OP_6601 ()
1352{
1353 uint16 addr = GPR (OP[1]);
1354 int32 tmp;
1355 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1356 tmp = RLW (addr);
1357 SET_GPR32 (OP[0], tmp);
d4f3574e 1358 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
7a292a7a 1359 INC_ADDR (OP[1], -4);
c906108c
SS		 1360 trace_output_32 (tmp);
1361}
1362
1363/* ld2w */
1364void
1365OP_6201 ()
1366{
1367 int32 tmp;
1368 uint16 addr = GPR (OP[1]);
1369 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1370 tmp = RLW (addr);
1371 SET_GPR32 (OP[0], tmp);
d4f3574e 1372 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
7a292a7a 1373 INC_ADDR (OP[1], 4);
c906108c
SS		 1374 trace_output_32 (tmp);
1375}
1376
1377/* ld2w */
1378void
1379OP_6200 ()
1380{
1381 uint16 addr = GPR (OP[1]);
1382 int32 tmp;
1383 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1384 tmp = RLW (addr + 0);
1385 SET_GPR32 (OP[0], tmp);
1386 trace_output_32 (tmp);
1387}
1388
cff3e48b
JM		 1389/* ld2w */
1390void
1391OP_33010000 ()
1392{
1393 int32 tmp;
1394
1395 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1396 tmp = RLW (OP[1]);
1397 SET_GPR32 (OP[0], tmp);
1398 trace_output_32 (tmp);
1399}
1400
c906108c
SS		 1401/* ldb */
1402void
1403OP_38000000 ()
1404{
1405 int16 tmp;
1406 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1407 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1408 SET_GPR (OP[0], tmp);
1409 trace_output_16 (tmp);
1410}
1411
1412/* ldb */
1413void
1414OP_7000 ()
1415{
1416 int16 tmp;
1417 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1418 tmp = SEXT8 (RB (GPR (OP[1])));
1419 SET_GPR (OP[0], tmp);
1420 trace_output_16 (tmp);
1421}
1422
1423/* ldi.s */
1424void
1425OP_4001 ()
1426{
1427 int16 tmp;
1428 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1429 tmp = SEXT4 (OP[1]);
1430 SET_GPR (OP[0], tmp);
1431 trace_output_16 (tmp);
1432}
1433
1434/* ldi.l */
1435void
1436OP_20000000 ()
1437{
1438 int16 tmp;
1439 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1440 tmp = OP[1];
1441 SET_GPR (OP[0], tmp);
1442 trace_output_16 (tmp);
1443}
1444
1445/* ldub */
1446void
1447OP_39000000 ()
1448{
1449 int16 tmp;
1450 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1451 tmp = RB (OP[1] + GPR (OP[2]));
1452 SET_GPR (OP[0], tmp);
1453 trace_output_16 (tmp);
1454}
1455
1456/* ldub */
1457void
1458OP_7200 ()
1459{
1460 int16 tmp;
1461 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1462 tmp = RB (GPR (OP[1]));
1463 SET_GPR (OP[0], tmp);
1464 trace_output_16 (tmp);
1465}
1466
1467/* mac */
1468void
1469OP_2A00 ()
1470{
1471 int64 tmp;
1472
1473 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1474 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1475
1476 if (PSW_FX)
1477 tmp = SEXT40( (tmp << 1) & MASK40);
1478
1479 if (PSW_ST && tmp > SEXT40(MAX32))
1480 tmp = (MAX32);
1481
1482 tmp += SEXT40 (ACC (OP[0]));
1483 if (PSW_ST)
1484 {
1485 if (tmp > SEXT40(MAX32))
1486 tmp = (MAX32);
1487 else if (tmp < SEXT40(MIN32))
1488 tmp = (MIN32);
1489 else
1490 tmp = (tmp & MASK40);
1491 }
1492 else
1493 tmp = (tmp & MASK40);
1494 SET_ACC (OP[0], tmp);
1495 trace_output_40 (tmp);
1496}
1497
1498/* macsu */
1499void
1500OP_1A00 ()
1501{
1502 int64 tmp;
1503
1504 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1505 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1506 if (PSW_FX)
1507 tmp = SEXT40 ((tmp << 1) & MASK40);
1508 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1509 SET_ACC (OP[0], tmp);
1510 trace_output_40 (tmp);
1511}
1512
1513/* macu */
1514void
1515OP_3A00 ()
1516{
1517 uint64 tmp;
1518 uint32 src1;
1519 uint32 src2;
1520
1521 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1522 src1 = (uint16) GPR (OP[1]);
1523 src2 = (uint16) GPR (OP[2]);
1524 tmp = src1 * src2;
1525 if (PSW_FX)
1526 tmp = (tmp << 1);
1527 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1528 SET_ACC (OP[0], tmp);
1529 trace_output_40 (tmp);
1530}
1531
1532/* max */
1533void
1534OP_2600 ()
1535{
1536 int16 tmp;
1537 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1538 SET_PSW_F1 (PSW_F0);
1539 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1540 {
1541 tmp = GPR (OP[1]);
1542 SET_PSW_F0 (1);
1543 }
1544 else
1545 {
1546 tmp = GPR (OP[0]);
1547 SET_PSW_F0 (0);
1548 }
1549 SET_GPR (OP[0], tmp);
1550 trace_output_16 (tmp);
1551}
1552
1553/* max */
1554void
1555OP_3600 ()
1556{
1557 int64 tmp;
1558
1559 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1560 SET_PSW_F1 (PSW_F0);
1561 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1562 if (tmp > SEXT40 (ACC (OP[0])))
1563 {
1564 tmp = (tmp & MASK40);
1565 SET_PSW_F0 (1);
1566 }
1567 else
1568 {
1569 tmp = ACC (OP[0]);
1570 SET_PSW_F0 (0);
1571 }
1572 SET_ACC (OP[0], tmp);
1573 trace_output_40 (tmp);
1574}
1575
1576/* max */
1577void
1578OP_3602 ()
1579{
1580 int64 tmp;
1581 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1582 SET_PSW_F1 (PSW_F0);
1583 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1584 {
1585 tmp = ACC (OP[1]);
1586 SET_PSW_F0 (1);
1587 }
1588 else
1589 {
1590 tmp = ACC (OP[0]);
1591 SET_PSW_F0 (0);
1592 }
1593 SET_ACC (OP[0], tmp);
1594 trace_output_40 (tmp);
1595}
1596
1597
1598/* min */
1599void
1600OP_2601 ()
1601{
1602 int16 tmp;
1603 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1604 SET_PSW_F1 (PSW_F0);
1605 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1606 {
1607 tmp = GPR (OP[1]);
1608 SET_PSW_F0 (1);
1609 }
1610 else
1611 {
1612 tmp = GPR (OP[0]);
1613 SET_PSW_F0 (0);
1614 }
1615 SET_GPR (OP[0], tmp);
1616 trace_output_16 (tmp);
1617}
1618
1619/* min */
1620void
1621OP_3601 ()
1622{
1623 int64 tmp;
1624
1625 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1626 SET_PSW_F1 (PSW_F0);
1627 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1628 if (tmp < SEXT40(ACC (OP[0])))
1629 {
1630 tmp = (tmp & MASK40);
1631 SET_PSW_F0 (1);
1632 }
1633 else
1634 {
1635 tmp = ACC (OP[0]);
1636 SET_PSW_F0 (0);
1637 }
1638 SET_ACC (OP[0], tmp);
1639 trace_output_40 (tmp);
1640}
1641
1642/* min */
1643void
1644OP_3603 ()
1645{
1646 int64 tmp;
1647 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1648 SET_PSW_F1 (PSW_F0);
1649 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1650 {
1651 tmp = ACC (OP[1]);
1652 SET_PSW_F0 (1);
1653 }
1654 else
1655 {
1656 tmp = ACC (OP[0]);
1657 SET_PSW_F0 (0);
1658 }
1659 SET_ACC (OP[0], tmp);
1660 trace_output_40 (tmp);
1661}
1662
1663/* msb */
1664void
1665OP_2800 ()
1666{
1667 int64 tmp;
1668
1669 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1670 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1671
1672 if (PSW_FX)
1673 tmp = SEXT40 ((tmp << 1) & MASK40);
1674
1675 if (PSW_ST && tmp > SEXT40(MAX32))
1676 tmp = (MAX32);
1677
1678 tmp = SEXT40(ACC (OP[0])) - tmp;
1679 if (PSW_ST)
1680 {
1681 if (tmp > SEXT40(MAX32))
1682 tmp = (MAX32);
1683 else if (tmp < SEXT40(MIN32))
1684 tmp = (MIN32);
1685 else
1686 tmp = (tmp & MASK40);
1687 }
1688 else
1689 {
1690 tmp = (tmp & MASK40);
1691 }
1692 SET_ACC (OP[0], tmp);
1693 trace_output_40 (tmp);
1694}
1695
1696/* msbsu */
1697void
1698OP_1800 ()
1699{
1700 int64 tmp;
1701
1702 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1703 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1704 if (PSW_FX)
1705 tmp = SEXT40( (tmp << 1) & MASK40);
1706 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1707 SET_ACC (OP[0], tmp);
1708 trace_output_40 (tmp);
1709}
1710
1711/* msbu */
1712void
1713OP_3800 ()
1714{
1715 uint64 tmp;
1716 uint32 src1;
1717 uint32 src2;
1718
1719 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1720 src1 = (uint16) GPR (OP[1]);
1721 src2 = (uint16) GPR (OP[2]);
1722 tmp = src1 * src2;
1723 if (PSW_FX)
1724 tmp = (tmp << 1);
1725 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1726 SET_ACC (OP[0], tmp);
1727 trace_output_40 (tmp);
1728}
1729
1730/* mul */
1731void
1732OP_2E00 ()
1733{
1734 int16 tmp;
1735 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1736 tmp = GPR (OP[0]) * GPR (OP[1]);
1737 SET_GPR (OP[0], tmp);
1738 trace_output_16 (tmp);
1739}
1740
1741/* mulx */
1742void
1743OP_2C00 ()
1744{
1745 int64 tmp;
1746
1747 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1748 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1749
1750 if (PSW_FX)
1751 tmp = SEXT40 ((tmp << 1) & MASK40);
1752
1753 if (PSW_ST && tmp > SEXT40(MAX32))
1754 tmp = (MAX32);
1755 else
1756 tmp = (tmp & MASK40);
1757 SET_ACC (OP[0], tmp);
1758 trace_output_40 (tmp);
1759}
1760
1761/* mulxsu */
1762void
1763OP_1C00 ()
1764{
1765 int64 tmp;
1766
1767 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1768 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1769
1770 if (PSW_FX)
1771 tmp <<= 1;
1772 tmp = (tmp & MASK40);
1773 SET_ACC (OP[0], tmp);
1774 trace_output_40 (tmp);
1775}
1776
1777/* mulxu */
1778void
1779OP_3C00 ()
1780{
1781 uint64 tmp;
1782 uint32 src1;
1783 uint32 src2;
1784
1785 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1786 src1 = (uint16) GPR (OP[1]);
1787 src2 = (uint16) GPR (OP[2]);
1788 tmp = src1 * src2;
1789 if (PSW_FX)
1790 tmp <<= 1;
1791 tmp = (tmp & MASK40);
1792 SET_ACC (OP[0], tmp);
1793 trace_output_40 (tmp);
1794}
1795
1796/* mv */
1797void
1798OP_4000 ()
1799{
1800 int16 tmp;
1801 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1802 tmp = GPR (OP[1]);
1803 SET_GPR (OP[0], tmp);
1804 trace_output_16 (tmp);
1805}
1806
1807/* mv2w */
1808void
1809OP_5000 ()
1810{
1811 int32 tmp;
1812 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1813 tmp = GPR32 (OP[1]);
1814 SET_GPR32 (OP[0], tmp);
1815 trace_output_32 (tmp);
1816}
1817
1818/* mv2wfac */
1819void
1820OP_3E00 ()
1821{
1822 int32 tmp;
1823 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1824 tmp = ACC (OP[1]);
1825 SET_GPR32 (OP[0], tmp);
1826 trace_output_32 (tmp);
1827}
1828
1829/* mv2wtac */
1830void
1831OP_3E01 ()
1832{
1833 int64 tmp;
1834 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1835 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1836 SET_ACC (OP[1], tmp);
1837 trace_output_40 (tmp);
1838}
1839
1840/* mvac */
1841void
1842OP_3E03 ()
1843{
1844 int64 tmp;
1845 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1846 tmp = ACC (OP[1]);
1847 SET_ACC (OP[0], tmp);
1848 trace_output_40 (tmp);
1849}
1850
1851/* mvb */
1852void
1853OP_5400 ()
1854{
1855 int16 tmp;
1856 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1857 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1858 SET_GPR (OP[0], tmp);
1859 trace_output_16 (tmp);
1860}
1861
1862/* mvf0f */
1863void
1864OP_4400 ()
1865{
1866 int16 tmp;
1867 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1868 if (PSW_F0 == 0)
1869 {
1870 tmp = GPR (OP[1]);
1871 SET_GPR (OP[0], tmp);
1872 }
1873 else
1874 tmp = GPR (OP[0]);
1875 trace_output_16 (tmp);
1876}
1877
1878/* mvf0t */
1879void
1880OP_4401 ()
1881{
1882 int16 tmp;
1883 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1884 if (PSW_F0)
1885 {
1886 tmp = GPR (OP[1]);
1887 SET_GPR (OP[0], tmp);
1888 }
1889 else
1890 tmp = GPR (OP[0]);
1891 trace_output_16 (tmp);
1892}
1893
1894/* mvfacg */
1895void
1896OP_1E04 ()
1897{
1898 int16 tmp;
1899 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1900 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1901 SET_GPR (OP[0], tmp);
1902 trace_output_16 (tmp);
1903}
1904
1905/* mvfachi */
1906void
1907OP_1E00 ()
1908{
1909 int16 tmp;
1910 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1911 tmp = (ACC (OP[1]) >> 16);
1912 SET_GPR (OP[0], tmp);
1913 trace_output_16 (tmp);
1914}
1915
1916/* mvfaclo */
1917void
1918OP_1E02 ()
1919{
1920 int16 tmp;
1921 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1922 tmp = ACC (OP[1]);
1923 SET_GPR (OP[0], tmp);
1924 trace_output_16 (tmp);
1925}
1926
1927/* mvfc */
1928void
1929OP_5200 ()
1930{
1931 int16 tmp;
1932 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1933 tmp = CREG (OP[1]);
1934 SET_GPR (OP[0], tmp);
1935 trace_output_16 (tmp);
1936}
1937
1938/* mvtacg */
1939void
1940OP_1E41 ()
1941{
1942 int64 tmp;
1943 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1944 tmp = ((ACC (OP[1]) & MASK32)
1945 | ((int64)(GPR (OP[0]) & 0xff) << 32));
1946 SET_ACC (OP[1], tmp);
1947 trace_output_40 (tmp);
1948}
1949
1950/* mvtachi */
1951void
1952OP_1E01 ()
1953{
1954 uint64 tmp;
1955 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1956 tmp = ACC (OP[1]) & 0xffff;
1957 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
1958 SET_ACC (OP[1], tmp);
1959 trace_output_40 (tmp);
1960}
1961
1962/* mvtaclo */
1963void
1964OP_1E21 ()
1965{
1966 int64 tmp;
1967 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1968 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
1969 SET_ACC (OP[1], tmp);
1970 trace_output_40 (tmp);
1971}
1972
1973/* mvtc */
1974void
1975OP_5600 ()
1976{
1977 int16 tmp;
1978 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1979 tmp = GPR (OP[0]);
1980 tmp = SET_CREG (OP[1], tmp);
1981 trace_output_16 (tmp);
1982}
1983
1984/* mvub */
1985void
1986OP_5401 ()
1987{
1988 int16 tmp;
1989 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1990 tmp = (GPR (OP[1]) & 0xff);
1991 SET_GPR (OP[0], tmp);
1992 trace_output_16 (tmp);
1993}
1994
1995/* neg */
1996void
1997OP_4605 ()
1998{
1999 int16 tmp;
2000 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2001 tmp = - GPR (OP[0]);
2002 SET_GPR (OP[0], tmp);
2003 trace_output_16 (tmp);
2004}
2005
2006/* neg */
2007void
2008OP_5605 ()
2009{
2010 int64 tmp;
2011
2012 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2013 tmp = -SEXT40(ACC (OP[0]));
2014 if (PSW_ST)
2015 {
2016 if (tmp > SEXT40(MAX32))
2017 tmp = (MAX32);
2018 else if (tmp < SEXT40(MIN32))
2019 tmp = (MIN32);
2020 else
2021 tmp = (tmp & MASK40);
2022 }
2023 else
2024 tmp = (tmp & MASK40);
2025 SET_ACC (OP[0], tmp);
2026 trace_output_40 (tmp);
2027}
2028
2029
2030/* nop */
2031void
2032OP_5E00 ()
2033{
2034 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2035
2036 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2037 switch (State.ins_type)
2038 {
2039 default:
2040 ins_type_counters[ (int)INS_UNKNOWN ]++;
2041 break;
2042
2043 case INS_LEFT_PARALLEL:
2044 /* Don't count a parallel op that includes a NOP as a true parallel op */
2045 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2046 ins_type_counters[ (int)INS_RIGHT ]++;
2047 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2048 break;
2049
2050 case INS_LEFT:
2051 case INS_LEFT_COND_EXE:
2052 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2053 break;
2054
2055 case INS_RIGHT_PARALLEL:
2056 /* Don't count a parallel op that includes a NOP as a true parallel op */
2057 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2058 ins_type_counters[ (int)INS_LEFT ]++;
2059 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2060 break;
2061
2062 case INS_RIGHT:
2063 case INS_RIGHT_COND_EXE:
2064 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2065 break;
2066 }
2067
2068 trace_output_void ();
2069}
2070
2071/* not */
2072void
2073OP_4603 ()
2074{
2075 int16 tmp;
2076 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2077 tmp = ~GPR (OP[0]);
2078 SET_GPR (OP[0], tmp);
2079 trace_output_16 (tmp);
2080}
2081
2082/* or */
2083void
2084OP_800 ()
2085{
2086 int16 tmp;
2087 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2088 tmp = (GPR (OP[0]) | GPR (OP[1]));
2089 SET_GPR (OP[0], tmp);
2090 trace_output_16 (tmp);
2091}
2092
2093/* or3 */
2094void
2095OP_4000000 ()
2096{
2097 int16 tmp;
2098 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2099 tmp = (GPR (OP[1]) | OP[2]);
2100 SET_GPR (OP[0], tmp);
2101 trace_output_16 (tmp);
2102}
2103
2104/* rac */
2105void
2106OP_5201 ()
2107{
2108 int64 tmp;
2109 int shift = SEXT3 (OP[2]);
2110
2111 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2112 if (OP[1] != 0)
2113 {
2114 (*d10v_callback->printf_filtered) (d10v_callback,
2115 "ERROR at PC 0x%x: instruction only valid for A0\n",
2116 PC<<2);
2117 State.exception = SIGILL;
2118 }
2119
2120 SET_PSW_F1 (PSW_F0);
2121 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2122 if (shift >=0)
2123 tmp <<= shift;
2124 else
2125 tmp >>= -shift;
2126 tmp += 0x8000;
2127 tmp >>= 16; /* look at bits 0:43 */
2128 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2129 {
2130 tmp = 0x7fffffff;
2131 SET_PSW_F0 (1);
2132 }
2133 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2134 {
2135 tmp = 0x80000000;
2136 SET_PSW_F0 (1);
2137 }
2138 else
2139 {
2140 SET_PSW_F0 (0);
2141 }
2142 SET_GPR32 (OP[0], tmp);
2143 trace_output_32 (tmp);
2144}
2145
2146/* rachi */
2147void
2148OP_4201 ()
2149{
2150 signed64 tmp;
2151 int shift = SEXT3 (OP[2]);
2152
2153 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2154 SET_PSW_F1 (PSW_F0);
2155 if (shift >=0)
2156 tmp = SEXT40 (ACC (OP[1])) << shift;
2157 else
2158 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2159 tmp += 0x8000;
2160
2161 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2162 {
2163 tmp = 0x7fff;
2164 SET_PSW_F0 (1);
2165 }
2166 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2167 {
2168 tmp = 0x8000;
2169 SET_PSW_F0 (1);
2170 }
2171 else
2172 {
2173 tmp = (tmp >> 16);
2174 SET_PSW_F0 (0);
2175 }
2176 SET_GPR (OP[0], tmp);
2177 trace_output_16 (tmp);
2178}
2179
2180/* rep */
2181void
2182OP_27000000 ()
2183{
2184 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2185 SET_RPT_S (PC + 1);
2186 SET_RPT_E (PC + OP[1]);
2187 SET_RPT_C (GPR (OP[0]));
2188 SET_PSW_RP (1);
2189 if (GPR (OP[0]) == 0)
2190 {
2191 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2192 State.exception = SIGILL;
2193 }
2194 if (OP[1] < 4)
2195 {
2196 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2197 State.exception = SIGILL;
2198 }
2199 trace_output_void ();
2200}
2201
2202/* repi */
2203void
2204OP_2F000000 ()
2205{
2206 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2207 SET_RPT_S (PC + 1);
2208 SET_RPT_E (PC + OP[1]);
2209 SET_RPT_C (OP[0]);
2210 SET_PSW_RP (1);
2211 if (OP[0] == 0)
2212 {
2213 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2214 State.exception = SIGILL;
2215 }
2216 if (OP[1] < 4)
2217 {
2218 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2219 State.exception = SIGILL;
2220 }
2221 trace_output_void ();
2222}
2223
2224/* rtd */
2225void
2226OP_5F60 ()
2227{
2228 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2229 SET_CREG (PSW_CR, DPSW);
2230 JMP(DPC);
2231 trace_output_void ();
2232}
2233
2234/* rte */
2235void
2236OP_5F40 ()
2237{
2238 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2239 SET_CREG (PSW_CR, BPSW);
2240 JMP(BPC);
2241 trace_output_void ();
2242}
2243
cff3e48b
JM		 2244/* sac */
2245void OP_5209 ()
2246{
2247 int64 tmp;
2248
2249 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2250
2251 tmp = SEXT40(ACC (OP[1]));
2252
2253 SET_PSW_F1 (PSW_F0);
2254
2255 if (tmp > SEXT40(MAX32))
2256 {
2257 tmp = (MAX32);
2258 SET_PSW_F0 (1);
2259 }
2260 else if (tmp < SEXT40(MIN32))
2261 {
2262 tmp = 0x80000000;
2263 SET_PSW_F0 (1);
2264 }
2265 else
2266 {
2267 tmp = (tmp & MASK32);
2268 SET_PSW_F0 (0);
2269 }
2270
2271 SET_GPR32 (OP[0], tmp);
2272
2273 trace_output_40 (tmp);
2274}
2275
cff3e48b
JM		 2276/* sachi */
2277void
2278OP_4209 ()
2279{
2280 int64 tmp;
2281
2282 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2283
2284 tmp = SEXT40(ACC (OP[1]));
2285
2286 SET_PSW_F1 (PSW_F0);
2287
2288 if (tmp > SEXT40(MAX32))
2289 {
2290 tmp = 0x7fff;
2291 SET_PSW_F0 (1);
2292 }
2293 else if (tmp < SEXT40(MIN32))
2294 {
2295 tmp = 0x8000;
2296 SET_PSW_F0 (1);
2297 }
2298 else
2299 {
2300 tmp >>= 16;
2301 SET_PSW_F0 (0);
2302 }
2303
2304 SET_GPR (OP[0], tmp);
2305
2306 trace_output_16 (OP[0]);
2307}
2308
c906108c
SS		 2309/* sadd */
2310void
2311OP_1223 ()
2312{
2313 int64 tmp;
2314
2315 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2316 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2317 if (PSW_ST)
2318 {
2319 if (tmp > SEXT40(MAX32))
2320 tmp = (MAX32);
2321 else if (tmp < SEXT40(MIN32))
2322 tmp = (MIN32);
2323 else
2324 tmp = (tmp & MASK40);
2325 }
2326 else
2327 tmp = (tmp & MASK40);
2328 SET_ACC (OP[0], tmp);
2329 trace_output_40 (tmp);
2330}
2331
2332/* setf0f */
2333void
2334OP_4611 ()
2335{
2336 int16 tmp;
2337 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2338 tmp = ((PSW_F0 == 0) ? 1 : 0);
2339 SET_GPR (OP[0], tmp);
2340 trace_output_16 (tmp);
2341}
2342
2343/* setf0t */
2344void
2345OP_4613 ()
2346{
2347 int16 tmp;
2348 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2349 tmp = ((PSW_F0 == 1) ? 1 : 0);
2350 SET_GPR (OP[0], tmp);
2351 trace_output_16 (tmp);
2352}
2353
cff3e48b
JM		 2354/* slae */
2355void
2356OP_3220 ()
2357{
2358 int64 tmp;
2359 int16 reg;
2360
2361 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2362
5c44784c 2363 reg = SEXT16 (GPR (OP[1]));
cff3e48b
JM		 2364
2365 if (reg >= 17 || reg <= -17)
2366 {
2367 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2368 State.exception = SIGILL;
2369 return;
2370 }
2371
2372 tmp = SEXT40 (ACC (OP[0]));
2373
2374 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2375 {
5c44784c 2376 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
cff3e48b
JM		 2377 State.exception = SIGILL;
2378 return;
2379 }
2380
2381 if (reg >= 0 && reg <= 16)
2382 {
2383 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2384 if (PSW_ST)
2385 {
2386 if (tmp > SEXT40(MAX32))
2387 tmp = (MAX32);
2388 else if (tmp < SEXT40(MIN32))
2389 tmp = (MIN32);
2390 else
2391 tmp = (tmp & MASK40);
2392 }
2393 else
2394 tmp = (tmp & MASK40);
2395 }
2396 else
2397 {
2398 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2399 }
2400
2401 SET_ACC(OP[0], tmp);
2402
2403 trace_output_40(tmp);
2404}
2405
c906108c
SS		 2406/* sleep */
2407void
2408OP_5FC0 ()
2409{
2410 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2411 SET_PSW_IE (1);
2412 trace_output_void ();
2413}
2414
2415/* sll */
2416void
2417OP_2200 ()
2418{
2419 int16 tmp;
2420 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2421 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2422 SET_GPR (OP[0], tmp);
2423 trace_output_16 (tmp);
2424}
2425
2426/* sll */
2427void
2428OP_3200 ()
2429{
2430 int64 tmp;
2431 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2432 if ((GPR (OP[1]) & 31) <= 16)
2433 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2434 else
2435 {
2436 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2437 State.exception = SIGILL;
2438 return;
2439 }
2440
2441 if (PSW_ST)
2442 {
2443 if (tmp > SEXT40(MAX32))
2444 tmp = (MAX32);
2445 else if (tmp < SEXT40(MIN32))
2446 tmp = (MIN32);
2447 else
2448 tmp = (tmp & MASK40);
2449 }
2450 else
2451 tmp = (tmp & MASK40);
2452 SET_ACC (OP[0], tmp);
2453 trace_output_40 (tmp);
2454}
2455
2456/* slli */
2457void
2458OP_2201 ()
2459{
2460 int16 tmp;
2461 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2462 tmp = (GPR (OP[0]) << OP[1]);
2463 SET_GPR (OP[0], tmp);
2464 trace_output_16 (tmp);
2465}
2466
2467/* slli */
2468void
2469OP_3201 ()
2470{
2471 int64 tmp;
2472
2473 if (OP[1] == 0)
2474 OP[1] = 16;
2475
2476 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2477 tmp = SEXT40(ACC (OP[0])) << OP[1];
2478
2479 if (PSW_ST)
2480 {
2481 if (tmp > SEXT40(MAX32))
2482 tmp = (MAX32);
2483 else if (tmp < SEXT40(MIN32))
2484 tmp = (MIN32);
2485 else
2486 tmp = (tmp & MASK40);
2487 }
2488 else
2489 tmp = (tmp & MASK40);
2490 SET_ACC (OP[0], tmp);
2491 trace_output_40 (tmp);
2492}
2493
2494/* slx */
2495void
2496OP_460B ()
2497{
2498 int16 tmp;
2499 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2500 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2501 SET_GPR (OP[0], tmp);
2502 trace_output_16 (tmp);
2503}
2504
2505/* sra */
2506void
2507OP_2400 ()
2508{
2509 int16 tmp;
2510 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2511 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2512 SET_GPR (OP[0], tmp);
2513 trace_output_16 (tmp);
2514}
2515
2516/* sra */
2517void
2518OP_3400 ()
2519{
2520 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2521 if ((GPR (OP[1]) & 31) <= 16)
2522 {
2523 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2524 SET_ACC (OP[0], tmp);
2525 trace_output_40 (tmp);
2526 }
2527 else
2528 {
2529 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2530 State.exception = SIGILL;
2531 return;
2532 }
2533}
2534
2535/* srai */
2536void
2537OP_2401 ()
2538{
2539 int16 tmp;
2540 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2541 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2542 SET_GPR (OP[0], tmp);
2543 trace_output_16 (tmp);
2544}
2545
2546/* srai */
2547void
2548OP_3401 ()
2549{
2550 int64 tmp;
2551 if (OP[1] == 0)
2552 OP[1] = 16;
2553
2554 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2555 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2556 SET_ACC (OP[0], tmp);
2557 trace_output_40 (tmp);
2558}
2559
2560/* srl */
2561void
2562OP_2000 ()
2563{
2564 int16 tmp;
2565 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2566 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2567 SET_GPR (OP[0], tmp);
2568 trace_output_16 (tmp);
2569}
2570
2571/* srl */
2572void
2573OP_3000 ()
2574{
2575 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2576 if ((GPR (OP[1]) & 31) <= 16)
2577 {
2578 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2579 SET_ACC (OP[0], tmp);
2580 trace_output_40 (tmp);
2581 }
2582 else
2583 {
2584 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2585 State.exception = SIGILL;
2586 return;
2587 }
2588
2589}
2590
2591/* srli */
2592void
2593OP_2001 ()
2594{
2595 int16 tmp;
2596 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2597 tmp = (GPR (OP[0]) >> OP[1]);
2598 SET_GPR (OP[0], tmp);
2599 trace_output_16 (tmp);
2600}
2601
2602/* srli */
2603void
2604OP_3001 ()
2605{
2606 int64 tmp;
2607 if (OP[1] == 0)
2608 OP[1] = 16;
2609
2610 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2611 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2612 SET_ACC (OP[0], tmp);
2613 trace_output_40 (tmp);
2614}
2615
2616/* srx */
2617void
2618OP_4609 ()
2619{
2620 uint16 tmp;
2621 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2622 tmp = PSW_F0 << 15;
2623 tmp = ((GPR (OP[0]) >> 1) | tmp);
2624 SET_GPR (OP[0], tmp);
2625 trace_output_16 (tmp);
2626}
2627
2628/* st */
2629void
2630OP_34000000 ()
2631{
2632 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2633 SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
2634 trace_output_void ();
2635}
2636
2637/* st */
2638void
2639OP_6800 ()
2640{
2641 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2642 SW (GPR (OP[1]), GPR (OP[0]));
2643 trace_output_void ();
2644}
2645
2646/* st */
2647void
2648OP_6C1F ()
2649{
2650 uint16 addr = GPR (OP[1]) - 2;
2651 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2652 if (OP[1] != 15)
2653 {
2654 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2655 State.exception = SIGILL;
2656 return;
2657 }
2658 SW (addr, GPR (OP[0]));
2659 SET_GPR (OP[1], addr);
2660 trace_output_void ();
2661}
2662
2663/* st */
2664void
2665OP_6801 ()
2666{
2667 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2668 SW (GPR (OP[1]), GPR (OP[0]));
2669 INC_ADDR (OP[1], 2);
2670 trace_output_void ();
2671}
2672
2673/* st */
2674void
2675OP_6C01 ()
2676{
2677 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2678 if ( OP[1] == 15 )
2679 {
2680 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2681 State.exception = SIGILL;
2682 return;
2683 }
2684 SW (GPR (OP[1]), GPR (OP[0]));
2685 INC_ADDR (OP[1], -2);
2686 trace_output_void ();
2687}
2688
cff3e48b
JM		 2689/* st */
2690void
2691OP_36010000 ()
2692{
2693 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2694 SW (OP[1], GPR (OP[0]));
2695 trace_output_void ();
2696}
2697
c906108c
SS		 2698/* st2w */
2699void
2700OP_35000000 ()
2701{
2702 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2703 SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
2704 SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
2705 trace_output_void ();
2706}
2707
2708/* st2w */
2709void
2710OP_6A00 ()
2711{
2712 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2713 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2714 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2715 trace_output_void ();
2716}
2717
2718/* st2w */
2719void
2720OP_6E1F ()
2721{
2722 uint16 addr = GPR (OP[1]) - 4;
2723 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2724 if ( OP[1] != 15 )
2725 {
2726 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2727 State.exception = SIGILL;
2728 return;
2729 }
2730 SW (addr + 0, GPR (OP[0] + 0));
2731 SW (addr + 2, GPR (OP[0] + 1));
2732 SET_GPR (OP[1], addr);
2733 trace_output_void ();
2734}
2735
2736/* st2w */
2737void
2738OP_6A01 ()
2739{
2740 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2741 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2742 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2743 INC_ADDR (OP[1], 4);
2744 trace_output_void ();
2745}
2746
2747/* st2w */
2748void
2749OP_6E01 ()
2750{
2751 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2752 if ( OP[1] == 15 )
2753 {
2754 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2755 State.exception = SIGILL;
2756 return;
2757 }
2758 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2759 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2760 INC_ADDR (OP[1], -4);
2761 trace_output_void ();
2762}
2763
cff3e48b
JM		 2764/* st2w */
2765void
2766OP_37010000 ()
2767{
2768 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2769 SW (OP [1] + 0, GPR (OP[0] + 0));
2770 SW (OP [1] + 2, GPR (OP[0] + 1));
2771 trace_output_void ();
2772}
2773
c906108c
SS		 2774/* stb */
2775void
2776OP_3C000000 ()
2777{
2778 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2779 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2780 trace_output_void ();
2781}
2782
2783/* stb */
2784void
2785OP_7800 ()
2786{
2787 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2788 SB (GPR (OP[1]), GPR (OP[0]));
2789 trace_output_void ();
2790}
2791
2792/* stop */
2793void
2794OP_5FE0 ()
2795{
2796 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2797 State.exception = SIG_D10V_STOP;
2798 trace_output_void ();
2799}
2800
2801/* sub */
2802void
2803OP_0 ()
2804{
2805 uint16 a = GPR (OP[0]);
2806 uint16 b = GPR (OP[1]);
2807 uint16 tmp = (a - b);
2808 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2809 /* see ../common/sim-alu.h for a more extensive discussion on how to
2810 compute the carry/overflow bits. */
2811 SET_PSW_C (a >= b);
2812 SET_GPR (OP[0], tmp);
2813 trace_output_16 (tmp);
2814}
2815
2816/* sub */
2817void
2818OP_1001 ()
2819{
2820 int64 tmp;
2821
2822 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2823 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2824 if (PSW_ST)
2825 {
2826 if (tmp > SEXT40(MAX32))
2827 tmp = (MAX32);
2828 else if (tmp < SEXT40(MIN32))
2829 tmp = (MIN32);
2830 else
2831 tmp = (tmp & MASK40);
2832 }
2833 else
2834 tmp = (tmp & MASK40);
2835 SET_ACC (OP[0], tmp);
2836
2837 trace_output_40 (tmp);
2838}
2839
2840/* sub */
2841
2842void
2843OP_1003 ()
2844{
2845 int64 tmp;
2846
2847 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2848 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
2849 if (PSW_ST)
2850 {
2851 if (tmp > SEXT40(MAX32))
2852 tmp = (MAX32);
2853 else if (tmp < SEXT40(MIN32))
2854 tmp = (MIN32);
2855 else
2856 tmp = (tmp & MASK40);
2857 }
2858 else
2859 tmp = (tmp & MASK40);
2860 SET_ACC (OP[0], tmp);
2861
2862 trace_output_40 (tmp);
2863}
2864
2865/* sub2w */
2866void
2867OP_1000 ()
2868{
2869 uint32 tmp, a, b;
2870
2871 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2872 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
2873 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
2874 /* see ../common/sim-alu.h for a more extensive discussion on how to
2875 compute the carry/overflow bits */
2876 tmp = a - b;
2877 SET_PSW_C (a >= b);
2878 SET_GPR32 (OP[0], tmp);
2879 trace_output_32 (tmp);
2880}
2881
2882/* subac3 */
2883void
2884OP_17000000 ()
2885{
2886 int64 tmp;
2887
2888 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2889 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
2890 SET_GPR32 (OP[0], tmp);
2891 trace_output_32 (tmp);
2892}
2893
2894/* subac3 */
2895void
2896OP_17000002 ()
2897{
2898 int64 tmp;
2899
2900 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2901 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
2902 SET_GPR32 (OP[0], tmp);
2903 trace_output_32 (tmp);
2904}
2905
2906/* subac3s */
2907void
2908OP_17001000 ()
2909{
2910 int64 tmp;
2911
2912 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2913 SET_PSW_F1 (PSW_F0);
2914 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
2915 if (tmp > SEXT40(MAX32))
2916 {
2917 tmp = (MAX32);
2918 SET_PSW_F0 (1);
2919 }
2920 else if (tmp < SEXT40(MIN32))
2921 {
2922 tmp = (MIN32);
2923 SET_PSW_F0 (1);
2924 }
2925 else
2926 {
2927 SET_PSW_F0 (0);
2928 }
2929 SET_GPR32 (OP[0], tmp);
2930 trace_output_32 (tmp);
2931}
2932
2933/* subac3s */
2934void
2935OP_17001002 ()
2936{
2937 int64 tmp;
2938
2939 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2940 SET_PSW_F1 (PSW_F0);
2941 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
2942 if (tmp > SEXT40(MAX32))
2943 {
2944 tmp = (MAX32);
2945 SET_PSW_F0 (1);
2946 }
2947 else if (tmp < SEXT40(MIN32))
2948 {
2949 tmp = (MIN32);
2950 SET_PSW_F0 (1);
2951 }
2952 else
2953 {
2954 SET_PSW_F0 (0);
2955 }
2956 SET_GPR32 (OP[0], tmp);
2957 trace_output_32 (tmp);
2958}
2959
2960/* subi */
2961void
2962OP_1 ()
2963{
2964 unsigned tmp;
2965 if (OP[1] == 0)
2966 OP[1] = 16;
2967
2968 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2969 /* see ../common/sim-alu.h for a more extensive discussion on how to
2970 compute the carry/overflow bits. */
2971 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2972 tmp = ((unsigned)(unsigned16) GPR (OP[0])
2973 + (unsigned)(unsigned16) ( - OP[1]));
2974 SET_PSW_C (tmp >= (1 << 16));
2975 SET_GPR (OP[0], tmp);
2976 trace_output_16 (tmp);
2977}
2978
2979/* trap */
2980void
2981OP_5F00 ()
2982{
2983 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2984 trace_output_void ();
2985
2986 switch (OP[0])
2987 {
2988 default:
2989#if (DEBUG & DEBUG_TRAP) == 0
2990 {
2991 uint16 vec = OP[0] + TRAP_VECTOR_START;
2992 SET_BPC (PC + 1);
2993 SET_BPSW (PSW);
2994 SET_PSW (PSW & PSW_SM_BIT);
2995 JMP (vec);
2996 break;
2997 }
2998#else /* if debugging use trap to print registers */
2999 {
3000 int i;
3001 static int first_time = 1;
3002
3003 if (first_time)
3004 {
3005 first_time = 0;
3006 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
3007 for (i = 0; i < 16; i++)
3008 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
3009 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
3010 }
3011
3012 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3013
3014 for (i = 0; i < 16; i++)
3015 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3016
3017 for (i = 0; i < 2; i++)
3018 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3019 ((int)(ACC (i) >> 32) & 0xff),
3020 ((unsigned long) ACC (i)) & 0xffffffff);
3021
3022 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
3023 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3024 (*d10v_callback->flush_stdout) (d10v_callback);
3025 break;
3026 }
3027#endif
3028 case 15: /* new system call trap */
3029 /* Trap 15 is used for simulating low-level I/O */
3030 {
3031 unsigned32 result = 0;
3032 errno = 0;
3033
3034/* Registers passed to trap 0 */
3035
3036#define FUNC GPR (4) /* function number */
3037#define PARM1 GPR (0) /* optional parm 1 */
3038#define PARM2 GPR (1) /* optional parm 2 */
3039#define PARM3 GPR (2) /* optional parm 3 */
3040#define PARM4 GPR (3) /* optional parm 3 */
3041
3042/* Registers set by trap 0 */
3043
3044#define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3045#define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3046#define RETERR(X) SET_GPR (4, (X)) /* return error code */
3047
3048/* Turn a pointer in a register into a pointer into real memory. */
3049
3050#define MEMPTR(x) ((char *)(dmem_addr(x)))
3051
3052 switch (FUNC)
3053 {
3054#if !defined(__GO32__) && !defined(_WIN32)
3055 case TARGET_SYS_fork:
3056 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3057 RETVAL (fork ());
3058 trace_output_16 (result);
3059 break;
3060
3061#define getpid() 47
3062 case TARGET_SYS_getpid:
3063 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3064 RETVAL (getpid ());
3065 trace_output_16 (result);
3066 break;
3067
3068 case TARGET_SYS_kill:
3069 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3070 if (PARM1 == getpid ())
3071 {
3072 trace_output_void ();
3073 State.exception = PARM2;
3074 }
3075 else
3076 {
3077 int os_sig = -1;
3078 switch (PARM2)
3079 {
3080#ifdef SIGHUP
3081 case 1: os_sig = SIGHUP; break;
3082#endif
3083#ifdef SIGINT
3084 case 2: os_sig = SIGINT; break;
3085#endif
3086#ifdef SIGQUIT
3087 case 3: os_sig = SIGQUIT; break;
3088#endif
3089#ifdef SIGILL
3090 case 4: os_sig = SIGILL; break;
3091#endif
3092#ifdef SIGTRAP
3093 case 5: os_sig = SIGTRAP; break;
3094#endif
3095#ifdef SIGABRT
3096 case 6: os_sig = SIGABRT; break;
3097#elif defined(SIGIOT)
3098 case 6: os_sig = SIGIOT; break;
3099#endif
3100#ifdef SIGEMT
3101 case 7: os_sig = SIGEMT; break;
3102#endif
3103#ifdef SIGFPE
3104 case 8: os_sig = SIGFPE; break;
3105#endif
3106#ifdef SIGKILL
3107 case 9: os_sig = SIGKILL; break;
3108#endif
3109#ifdef SIGBUS
3110 case 10: os_sig = SIGBUS; break;
3111#endif
3112#ifdef SIGSEGV
3113 case 11: os_sig = SIGSEGV; break;
3114#endif
3115#ifdef SIGSYS
3116 case 12: os_sig = SIGSYS; break;
3117#endif
3118#ifdef SIGPIPE
3119 case 13: os_sig = SIGPIPE; break;
3120#endif
3121#ifdef SIGALRM
3122 case 14: os_sig = SIGALRM; break;
3123#endif
3124#ifdef SIGTERM
3125 case 15: os_sig = SIGTERM; break;
3126#endif
3127#ifdef SIGURG
3128 case 16: os_sig = SIGURG; break;
3129#endif
3130#ifdef SIGSTOP
3131 case 17: os_sig = SIGSTOP; break;
3132#endif
3133#ifdef SIGTSTP
3134 case 18: os_sig = SIGTSTP; break;
3135#endif
3136#ifdef SIGCONT
3137 case 19: os_sig = SIGCONT; break;
3138#endif
3139#ifdef SIGCHLD
3140 case 20: os_sig = SIGCHLD; break;
3141#elif defined(SIGCLD)
3142 case 20: os_sig = SIGCLD; break;
3143#endif
3144#ifdef SIGTTIN
3145 case 21: os_sig = SIGTTIN; break;
3146#endif
3147#ifdef SIGTTOU
3148 case 22: os_sig = SIGTTOU; break;
3149#endif
3150#ifdef SIGIO
3151 case 23: os_sig = SIGIO; break;
3152#elif defined (SIGPOLL)
3153 case 23: os_sig = SIGPOLL; break;
3154#endif
3155#ifdef SIGXCPU
3156 case 24: os_sig = SIGXCPU; break;
3157#endif
3158#ifdef SIGXFSZ
3159 case 25: os_sig = SIGXFSZ; break;
3160#endif
3161#ifdef SIGVTALRM
3162 case 26: os_sig = SIGVTALRM; break;
3163#endif
3164#ifdef SIGPROF
3165 case 27: os_sig = SIGPROF; break;
3166#endif
3167#ifdef SIGWINCH
3168 case 28: os_sig = SIGWINCH; break;
3169#endif
3170#ifdef SIGLOST
3171 case 29: os_sig = SIGLOST; break;
3172#endif
3173#ifdef SIGUSR1
3174 case 30: os_sig = SIGUSR1; break;
3175#endif
3176#ifdef SIGUSR2
3177 case 31: os_sig = SIGUSR2; break;
3178#endif
3179 }
3180
3181 if (os_sig == -1)
3182 {
3183 trace_output_void ();
3184 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3185 (*d10v_callback->flush_stdout) (d10v_callback);
3186 State.exception = SIGILL;
3187 }
3188 else
3189 {
3190 RETVAL (kill (PARM1, PARM2));
3191 trace_output_16 (result);
3192 }
3193 }
3194 break;
3195
3196 case TARGET_SYS_execve:
3197 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3198 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3199 (char **)MEMPTR (PARM3)));
3200 trace_output_16 (result);
3201 break;
3202
3203#ifdef TARGET_SYS_execv
3204 case TARGET_SYS_execv:
3205 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3206 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3207 trace_output_16 (result);
3208 break;
3209#endif
3210
3211 case TARGET_SYS_pipe:
3212 {
3213 reg_t buf;
3214 int host_fd[2];
3215
3216 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3217 buf = PARM1;
3218 RETVAL (pipe (host_fd));
3219 SW (buf, host_fd[0]);
3220 buf += sizeof(uint16);
3221 SW (buf, host_fd[1]);
3222 trace_output_16 (result);
3223 }
3224 break;
3225
3226#if 0
3227#ifdef TARGET_SYS_wait
3228 case TARGET_SYS_wait:
3229 {
3230 int status;
3231 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3232 RETVAL (wait (&status));
3233 if (PARM1)
3234 SW (PARM1, status);
3235 trace_output_16 (result);
3236 }
3237 break;
3238#endif
3239#endif
3240#else
3241 case TARGET_SYS_getpid:
3242 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3243 RETVAL (1);
3244 trace_output_16 (result);
3245 break;
3246
3247 case TARGET_SYS_kill:
3248 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3249 trace_output_void ();
3250 State.exception = PARM2;
3251 break;
3252#endif
3253
3254 case TARGET_SYS_read:
3255 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3256 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3257 PARM3));
3258 trace_output_16 (result);
3259 break;
3260
3261 case TARGET_SYS_write:
3262 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3263 if (PARM1 == 1)
3264 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3265 MEMPTR (PARM2), PARM3));
3266 else
3267 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3268 MEMPTR (PARM2), PARM3));
3269 trace_output_16 (result);
3270 break;
3271
3272 case TARGET_SYS_lseek:
3273 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3274 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3275 ((((unsigned long) PARM2) << 16)
3276 || (unsigned long) PARM3),
3277 PARM4));
3278 trace_output_32 (result);
3279 break;
3280
3281 case TARGET_SYS_close:
3282 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3283 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3284 trace_output_16 (result);
3285 break;
3286
3287 case TARGET_SYS_open:
3288 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3289 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3290 trace_output_16 (result);
3291 break;
3292
3293 case TARGET_SYS_exit:
3294 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3295 State.exception = SIG_D10V_EXIT;
3296 trace_output_void ();
3297 break;
3298
7a292a7a 3299#ifdef TARGET_SYS_stat
c906108c
SS		 3300 case TARGET_SYS_stat:
3301 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3302 /* stat system call */
3303 {
3304 struct stat host_stat;
3305 reg_t buf;
3306
3307 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3308
3309 buf = PARM2;
3310
3311 /* The hard-coded offsets and sizes were determined by using
3312 * the D10V compiler on a test program that used struct stat.
3313 */
3314 SW (buf, host_stat.st_dev);
3315 SW (buf+2, host_stat.st_ino);
3316 SW (buf+4, host_stat.st_mode);
3317 SW (buf+6, host_stat.st_nlink);
3318 SW (buf+8, host_stat.st_uid);
3319 SW (buf+10, host_stat.st_gid);
3320 SW (buf+12, host_stat.st_rdev);
3321 SLW (buf+16, host_stat.st_size);
3322 SLW (buf+20, host_stat.st_atime);
3323 SLW (buf+28, host_stat.st_mtime);
3324 SLW (buf+36, host_stat.st_ctime);
3325 }
3326 trace_output_16 (result);
3327 break;
7a292a7a 3328#endif
c906108c
SS		 3329
3330 case TARGET_SYS_chown:
3331 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3332 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3333 trace_output_16 (result);
3334 break;
3335
3336 case TARGET_SYS_chmod:
3337 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3338 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3339 trace_output_16 (result);
3340 break;
3341
3342#if 0
3343#ifdef TARGET_SYS_utime
3344 case TARGET_SYS_utime:
3345 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3346 /* Cast the second argument to void *, to avoid type mismatch
3347 if a prototype is present. */
3348 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3349 trace_output_16 (result);
3350 break;
3351#endif
3352#endif
3353
3354#if 0
3355#ifdef TARGET_SYS_time
3356 case TARGET_SYS_time:
3357 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3358 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3359 trace_output_32 (result);
3360 break;
3361#endif
3362#endif
3363
3364 default:
3365 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3366 }
3367 if ((uint16) result == (uint16) -1)
3368 RETERR (d10v_callback->get_errno(d10v_callback));
3369 else
3370 RETERR (0);
3371 break;
3372 }
3373 }
3374}
3375
3376/* tst0i */
3377void
3378OP_7000000 ()
3379{
3380 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3381 SET_PSW_F1 (PSW_F0);;
3382 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3383 trace_output_flag ();
3384}
3385
3386/* tst1i */
3387void
3388OP_F000000 ()
3389{
3390 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3391 SET_PSW_F1 (PSW_F0);
3392 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3393 trace_output_flag ();
3394}
3395
3396/* wait */
3397void
3398OP_5F80 ()
3399{
3400 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3401 SET_PSW_IE (1);
3402 trace_output_void ();
3403}
3404
3405/* xor */
3406void
3407OP_A00 ()
3408{
3409 int16 tmp;
3410 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3411 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3412 SET_GPR (OP[0], tmp);
3413 trace_output_16 (tmp);
3414}
3415
3416/* xor3 */
3417void
3418OP_5000000 ()
3419{
3420 int16 tmp;
3421 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3422 tmp = (GPR (OP[1]) ^ OP[2]);
3423 SET_GPR (OP[0], tmp);
3424 trace_output_16 (tmp);
3425}
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