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First round of d10v ABI changes
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
fd435e9f
MM		 1#include "config.h"
2
4f425a32 3#include <signal.h>
63a91cfb
MM		 4#include <errno.h>
5#include <sys/types.h>
6#include <sys/stat.h>
fd435e9f 7#ifdef HAVE_UNISTD_H
63a91cfb 8#include <unistd.h>
fd435e9f 9#endif
63a91cfb 10
2934d1c9
MH		 11#include "d10v_sim.h"
12#include "simops.h"
8719be26 13#include "sys/syscall.h"
2934d1c9 14
c422ecc7
MH		 15extern char *strrchr ();
16
87178dbd
MM		 17enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
60fc5b72 30 OP_FLAG_OUTPUT,
87178dbd 31 OP_CONSTANT16,
a18cb100 32 OP_CONSTANT8,
87178dbd
MM		 33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
a18cb100 39 OP_PREDEC,
8831cb01
MM		 40 OP_R0,
41 OP_R1,
a18cb100 42 OP_R2,
8831cb01 43 OP_R0R1
87178dbd
MM		 44};
45
bc6df23d
AC		 46
47void
48move_to_cr (int cr, reg_t val)
49{
50 switch (cr)
51 {
52 case PSW_CR:
53 State.SM = (val & PSW_SM_BIT) != 0;
54 State.EA = (val & PSW_EA_BIT) != 0;
55 State.DB = (val & PSW_DB_BIT) != 0;
56 State.DM = (val & PSW_DM_BIT) != 0;
57 State.IE = (val & PSW_IE_BIT) != 0;
58 State.RP = (val & PSW_RP_BIT) != 0;
59 State.MD = (val & PSW_MD_BIT) != 0;
60 State.FX = (val & PSW_FX_BIT) != 0;
61 State.ST = (val & PSW_ST_BIT) != 0;
62 State.F0 = (val & PSW_F0_BIT) != 0;
63 State.F1 = (val & PSW_F1_BIT) != 0;
64 State.C = (val & PSW_C_BIT) != 0;
65 if (State.ST && !State.FX)
66 {
67 (*d10v_callback->printf_filtered)
68 (d10v_callback,
69 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
70 PC<<2);
71 State.exception = SIGILL;
72 }
73 State.cregs[PSW_CR] = (val & ~0x4032);
74 break;
75 case BPSW_CR:
76 State.cregs[BPSW_CR] = (val & ~0x4032);
77 break;
78 case MOD_S_CR:
79 case MOD_E_CR:
80 State.cregs[cr] = (val & ~0x1);
81 break;
82 default:
83 State.cregs[cr] = val;
84 break;
85 }
86}
87
88reg_t
89move_from_cr (int cr)
90{
91 reg_t val = 0;
92 switch (cr)
93 {
94 case PSW_CR:
95 if (State.SM) val |= PSW_SM_BIT;
96 if (State.EA) val |= PSW_EA_BIT;
97 if (State.DB) val |= PSW_DB_BIT;
98 if (State.DM) val |= PSW_DM_BIT;
99 if (State.IE) val |= PSW_IE_BIT;
100 if (State.RP) val |= PSW_RP_BIT;
101 if (State.MD) val |= PSW_MD_BIT;
102 if (State.FX) val |= PSW_FX_BIT;
103 if (State.ST) val |= PSW_ST_BIT;
104 if (State.F0) val |= PSW_F0_BIT;
105 if (State.F1) val |= PSW_F1_BIT;
106 if (State.C) val |= PSW_C_BIT;
107 break;
108 default:
109 val = State.cregs[cr];
110 break;
111 }
112 return val;
113}
114
115
7eebfc62 116#ifdef DEBUG
a49a15ad
MM		 117static void trace_input_func PARAMS ((char *name,
118 enum op_types in1,
119 enum op_types in2,
120 enum op_types in3));
87178dbd 121
a49a15ad
MM		 122#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
123
124static void trace_output_func PARAMS ((enum op_types result));
125
126#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
127
87178dbd 128#ifndef SIZE_INSTRUCTION
a49a15ad 129#define SIZE_INSTRUCTION 8
87178dbd
MM		 130#endif
131
132#ifndef SIZE_OPERANDS
a49a15ad 133#define SIZE_OPERANDS 18
87178dbd
MM		 134#endif
135
136#ifndef SIZE_VALUES
137#define SIZE_VALUES 13
138#endif
139
a49a15ad
MM		 140#ifndef SIZE_LOCATION
141#define SIZE_LOCATION 20
142#endif
143
891513ee
MM		 144#ifndef SIZE_PC
145#define SIZE_PC 6
146#endif
147
148#ifndef SIZE_LINE_NUMBER
149#define SIZE_LINE_NUMBER 4
150#endif
151
87178dbd 152static void
a49a15ad 153trace_input_func (name, in1, in2, in3)
87178dbd
MM		 154 char *name;
155 enum op_types in1;
156 enum op_types in2;
157 enum op_types in3;
158{
159 char *comma;
160 enum op_types in[3];
161 int i;
a49a15ad 162 char buf[1024];
87178dbd
MM		 163 char *p;
164 long tmp;
165 char *type;
a49a15ad
MM		 166 const char *filename;
167 const char *functionname;
168 unsigned int linenumber;
169 bfd_vma byte_pc;
87178dbd 170
7eebfc62
MM		 171 if ((d10v_debug & DEBUG_TRACE) == 0)
172 return;
173
87178dbd
MM		 174 switch (State.ins_type)
175 {
176 default:
177 case INS_UNKNOWN: type = " ?"; break;
178 case INS_LEFT: type = " L"; break;
179 case INS_RIGHT: type = " R"; break;
180 case INS_LEFT_PARALLEL: type = "*L"; break;
181 case INS_RIGHT_PARALLEL: type = "*R"; break;
c422ecc7
MH		 182 case INS_LEFT_COND_TEST: type = "?L"; break;
183 case INS_RIGHT_COND_TEST: type = "?R"; break;
184 case INS_LEFT_COND_EXE: type = "&L"; break;
185 case INS_RIGHT_COND_EXE: type = "&R"; break;
87178dbd
MM		 186 case INS_LONG: type = " B"; break;
187 }
188
a49a15ad
MM		 189 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
190 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 191 "0x%.*x %s: %-*s ",
891513ee
MM		 192 SIZE_PC, (unsigned)PC,
193 type,
a49a15ad
MM		 194 SIZE_INSTRUCTION, name);
195
196 else
197 {
891513ee 198 buf[0] = '\0';
b30cdd35 199 byte_pc = decode_pc ();
a49a15ad
MM		 200 if (text && byte_pc >= text_start && byte_pc < text_end)
201 {
202 filename = (const char *)0;
203 functionname = (const char *)0;
204 linenumber = 0;
b83093ff 205 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
a49a15ad
MM		 206 &filename, &functionname, &linenumber))
207 {
208 p = buf;
209 if (linenumber)
210 {
891513ee 211 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
a49a15ad
MM		 212 p += strlen (p);
213 }
891513ee
MM		 214 else
215 {
216 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
217 p += SIZE_LINE_NUMBER+2;
218 }
a49a15ad
MM		 219
220 if (functionname)
221 {
222 sprintf (p, "%s ", functionname);
223 p += strlen (p);
224 }
225 else if (filename)
226 {
c422ecc7 227 char *q = strrchr (filename, '/');
a49a15ad
MM		 228 sprintf (p, "%s ", (q) ? q+1 : filename);
229 p += strlen (p);
230 }
231
232 if (*p == ' ')
233 *p = '\0';
234 }
235 }
236
237 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 238 "0x%.*x %s: %-*.*s %-*s ",
891513ee
MM		 239 SIZE_PC, (unsigned)PC,
240 type,
a49a15ad
MM		 241 SIZE_LOCATION, SIZE_LOCATION, buf,
242 SIZE_INSTRUCTION, name);
243 }
87178dbd
MM		 244
245 in[0] = in1;
246 in[1] = in2;
247 in[2] = in3;
248 comma = "";
249 p = buf;
250 for (i = 0; i < 3; i++)
251 {
252 switch (in[i])
253 {
254 case OP_VOID:
8831cb01
MM		 255 case OP_R0:
256 case OP_R1:
a18cb100 257 case OP_R2:
8831cb01 258 case OP_R0R1:
87178dbd
MM		 259 break;
260
261 case OP_REG:
262 case OP_REG_OUTPUT:
263 case OP_DREG:
264 case OP_DREG_OUTPUT:
265 sprintf (p, "%sr%d", comma, OP[i]);
266 p += strlen (p);
267 comma = ",";
268 break;
269
270 case OP_CR:
271 case OP_CR_OUTPUT:
272 case OP_CR_REVERSE:
273 sprintf (p, "%scr%d", comma, OP[i]);
274 p += strlen (p);
275 comma = ",";
276 break;
277
278 case OP_ACCUM:
279 case OP_ACCUM_OUTPUT:
280 case OP_ACCUM_REVERSE:
281 sprintf (p, "%sa%d", comma, OP[i]);
282 p += strlen (p);
283 comma = ",";
284 break;
285
286 case OP_CONSTANT16:
287 sprintf (p, "%s%d", comma, OP[i]);
288 p += strlen (p);
289 comma = ",";
290 break;
291
a18cb100
MM		 292 case OP_CONSTANT8:
293 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
294 p += strlen (p);
295 comma = ",";
296 break;
297
87178dbd
MM		 298 case OP_CONSTANT4:
299 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
300 p += strlen (p);
301 comma = ",";
302 break;
303
304 case OP_CONSTANT3:
305 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
306 p += strlen (p);
307 comma = ",";
308 break;
309
310 case OP_MEMREF:
311 sprintf (p, "%s@r%d", comma, OP[i]);
312 p += strlen (p);
313 comma = ",";
314 break;
315
316 case OP_MEMREF2:
317 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
318 p += strlen (p);
319 comma = ",";
320 break;
321
322 case OP_POSTINC:
323 sprintf (p, "%s@r%d+", comma, OP[i]);
324 p += strlen (p);
325 comma = ",";
326 break;
327
328 case OP_POSTDEC:
329 sprintf (p, "%s@r%d-", comma, OP[i]);
330 p += strlen (p);
331 comma = ",";
332 break;
333
334 case OP_PREDEC:
335 sprintf (p, "%s@-r%d", comma, OP[i]);
336 p += strlen (p);
337 comma = ",";
338 break;
339
340 case OP_FLAG:
60fc5b72 341 case OP_FLAG_OUTPUT:
87178dbd
MM		 342 if (OP[i] == 0)
343 sprintf (p, "%sf0", comma);
344
345 else if (OP[i] == 1)
346 sprintf (p, "%sf1", comma);
347
348 else
60fc5b72 349 sprintf (p, "%sc", comma);
87178dbd
MM		 350
351 p += strlen (p);
352 comma = ",";
353 break;
354 }
355 }
356
7eebfc62
MM		 357 if ((d10v_debug & DEBUG_VALUES) == 0)
358 {
359 *p++ = '\n';
360 *p = '\0';
361 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
362 }
363 else
364 {
365 *p = '\0';
366 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 367
7eebfc62
MM		 368 p = buf;
369 for (i = 0; i < 3; i++)
370 {
371 buf[0] = '\0';
372 switch (in[i])
373 {
374 case OP_VOID:
375 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
376 break;
377
378 case OP_REG_OUTPUT:
379 case OP_DREG_OUTPUT:
380 case OP_CR_OUTPUT:
381 case OP_ACCUM_OUTPUT:
60fc5b72 382 case OP_FLAG_OUTPUT:
7eebfc62
MM		 383 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
384 break;
385
386 case OP_REG:
387 case OP_MEMREF:
388 case OP_POSTDEC:
389 case OP_POSTINC:
390 case OP_PREDEC:
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
392 (uint16)State.regs[OP[i]]);
393 break;
394
395 case OP_DREG:
396 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
397 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
398 break;
399
400 case OP_CR:
401 case OP_CR_REVERSE:
402 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
403 (uint16)State.cregs[OP[i]]);
404 break;
405
406 case OP_ACCUM:
407 case OP_ACCUM_REVERSE:
408 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
409 ((int)(State.a[OP[i]] >> 32) & 0xff),
410 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
411 break;
412
413 case OP_CONSTANT16:
414 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
415 (uint16)OP[i]);
416 break;
417
418 case OP_CONSTANT4:
419 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
420 (uint16)SEXT4(OP[i]));
421 break;
422
a18cb100
MM		 423 case OP_CONSTANT8:
424 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
425 (uint16)SEXT8(OP[i]));
426 break;
427
7eebfc62
MM		 428 case OP_CONSTANT3:
429 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
430 (uint16)SEXT3(OP[i]));
431 break;
432
433 case OP_FLAG:
434 if (OP[i] == 0)
435 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
436 State.F0 != 0);
437
438 else if (OP[i] == 1)
439 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
440 State.F1 != 0);
441
442 else
443 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
444 State.C != 0);
445
446 break;
447
448 case OP_MEMREF2:
449 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
450 (uint16)OP[i]);
451 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
452 (uint16)State.regs[OP[++i]]);
453 break;
a18cb100 454
8831cb01 455 case OP_R0:
a18cb100 456 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
8831cb01 457 (uint16)State.regs[0]);
a18cb100
MM		 458 break;
459
8831cb01 460 case OP_R1:
a18cb100 461 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
8831cb01 462 (uint16)State.regs[1]);
a18cb100 463 break;
8918b3a7 464
8831cb01 465 case OP_R2:
8918b3a7 466 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
8831cb01 467 (uint16)State.regs[2]);
8918b3a7 468 break;
c422ecc7 469
8831cb01 470 case OP_R0R1:
c422ecc7 471 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
8831cb01 472 (uint16)State.regs[0]);
c422ecc7 473 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
8831cb01 474 (uint16)State.regs[1]);
c422ecc7
MH		 475 i++;
476 break;
7eebfc62
MM		 477 }
478 }
479 }
fd435e9f
MM		 480
481 (*d10v_callback->flush_stdout) (d10v_callback);
7eebfc62 482}
87178dbd 483
7eebfc62 484static void
a49a15ad 485trace_output_func (result)
7eebfc62
MM		 486 enum op_types result;
487{
488 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 489 {
7eebfc62 490 long tmp;
87178dbd 491
7eebfc62
MM		 492 switch (result)
493 {
494 default:
495 putchar ('\n');
87178dbd
MM		 496 break;
497
498 case OP_REG:
7eebfc62
MM		 499 case OP_REG_OUTPUT:
500 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
501 (uint16)State.regs[OP[0]],
502 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 503 break;
504
505 case OP_DREG:
7eebfc62
MM		 506 case OP_DREG_OUTPUT:
507 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
508 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
509 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 510 break;
511
512 case OP_CR:
7eebfc62
MM		 513 case OP_CR_OUTPUT:
514 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
515 (uint16)State.cregs[OP[0]],
516 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 517 break;
518
7eebfc62
MM		 519 case OP_CR_REVERSE:
520 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
521 (uint16)State.cregs[OP[1]],
522 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 523 break;
524
7eebfc62
MM		 525 case OP_ACCUM:
526 case OP_ACCUM_OUTPUT:
069398aa 527 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 528 ((int)(State.a[OP[0]] >> 32) & 0xff),
529 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
530 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 531 break;
532
7eebfc62 533 case OP_ACCUM_REVERSE:
069398aa 534 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 535 ((int)(State.a[OP[1]] >> 32) & 0xff),
536 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
537 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 538 break;
539
540 case OP_FLAG:
60fc5b72 541 case OP_FLAG_OUTPUT:
7eebfc62
MM		 542 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
543 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd 544 break;
8918b3a7 545
8831cb01 546 case OP_R0:
8918b3a7 547 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
8831cb01 548 (uint16)State.regs[0],
8918b3a7
MM		 549 State.F0 != 0, State.F1 != 0, State.C != 0);
550 break;
551
8831cb01 552 case OP_R0R1:
8918b3a7 553 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
8831cb01 554 (uint16)State.regs[0], (uint16)State.regs[1],
8918b3a7
MM		 555 State.F0 != 0, State.F1 != 0, State.C != 0);
556 break;
87178dbd
MM		 557 }
558 }
fd435e9f
MM		 559
560 (*d10v_callback->flush_stdout) (d10v_callback);
87178dbd
MM		 561}
562
563#else
564#define trace_input(NAME, IN1, IN2, IN3)
565#define trace_output(RESULT)
566#endif
2934d1c9
MH		 567
568/* abs */
569void
570OP_4607 ()
571{
87178dbd 572 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 573 State.F1 = State.F0;
574 if ((int16)(State.regs[OP[0]]) < 0)
575 {
576 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
577 State.F0 = 1;
578 }
579 else
580 State.F0 = 0;
87178dbd 581 trace_output (OP_REG);
2934d1c9
MH		 582}
583
584/* abs */
585void
586OP_5607 ()
587{
588 int64 tmp;
589
87178dbd 590 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 591 State.F1 = State.F0;
592 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
593
4c38885c 594 if (State.a[OP[0]] < 0 )
2934d1c9 595 {
4c38885c 596 tmp = -State.a[OP[0]];
2934d1c9
MH		 597 if (State.ST)
598 {
4c38885c 599 if (tmp > MAX32)
2934d1c9 600 State.a[OP[0]] = MAX32;
4c38885c 601 else if (tmp < MIN32)
2934d1c9
MH		 602 State.a[OP[0]] = MIN32;
603 else
4f425a32 604 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 605 }
606 else
4f425a32 607 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 608 State.F0 = 1;
609 }
610 else
611 State.F0 = 0;
87178dbd 612 trace_output (OP_ACCUM);
2934d1c9
MH		 613}
614
615/* add */
616void
617OP_200 ()
618{
619 uint16 tmp = State.regs[OP[0]];
87178dbd 620 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 621 State.regs[OP[0]] += State.regs[OP[1]];
622 if ( tmp > State.regs[OP[0]])
623 State.C = 1;
624 else
625 State.C = 0;
87178dbd 626 trace_output (OP_REG);
2934d1c9
MH		 627}
628
629/* add */
630void
631OP_1201 ()
632{
4c38885c 633 int64 tmp;
4f425a32 634 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 635
636 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 637 if (State.ST)
638 {
639 if ( tmp > MAX32)
640 State.a[OP[0]] = MAX32;
641 else if ( tmp < MIN32)
642 State.a[OP[0]] = MIN32;
643 else
4f425a32 644 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 645 }
646 else
4f425a32 647 State.a[OP[0]] = tmp & MASK40;
87178dbd 648 trace_output (OP_ACCUM);
2934d1c9
MH		 649}
650
651/* add */
652void
653OP_1203 ()
654{
4c38885c 655 int64 tmp;
4f425a32 656 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 657
658 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 659 if (State.ST)
660 {
661 if (tmp > MAX32)
662 State.a[OP[0]] = MAX32;
663 else if ( tmp < MIN32)
664 State.a[OP[0]] = MIN32;
665 else
4f425a32 666 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 667 }
668 else
4f425a32 669 State.a[OP[0]] = tmp & MASK40;
87178dbd 670 trace_output (OP_ACCUM);
2934d1c9
MH		 671}
672
673/* add2w */
674void
675OP_1200 ()
676{
677 uint32 tmp;
f4b022d3
MM		 678 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
679 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 680
681 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
f4b022d3
MM		 682 tmp = a + b;
683 State.C = (tmp < a);
2934d1c9
MH		 684 State.regs[OP[0]] = tmp >> 16;
685 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 686 trace_output (OP_DREG);
2934d1c9
MH		 687}
688
689/* add3 */
690void
691OP_1000000 ()
692{
f4b022d3
MM		 693 uint16 tmp = State.regs[OP[1]];
694 State.regs[OP[0]] = tmp + OP[2];
87178dbd
MM		 695
696 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
f4b022d3 697 State.C = (State.regs[OP[0]] < tmp);
87178dbd 698 trace_output (OP_REG);
2934d1c9
MH		 699}
700
701/* addac3 */
702void
703OP_17000200 ()
704{
4c38885c 705 int64 tmp;
4f425a32 706 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 707
708 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 709 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
710 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 711 trace_output (OP_DREG);
2934d1c9
MH		 712}
713
714/* addac3 */
715void
716OP_17000202 ()
717{
4c38885c 718 int64 tmp;
4f425a32 719 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 720
721 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 722 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
723 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 724 trace_output (OP_DREG);
2934d1c9
MH		 725}
726
727/* addac3s */
728void
729OP_17001200 ()
730{
4c38885c 731 int64 tmp;
4c38885c 732 State.F1 = State.F0;
87178dbd
MM		 733
734 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 735 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 736 if ( tmp > MAX32)
737 {
738 State.regs[OP[0]] = 0x7fff;
739 State.regs[OP[0]+1] = 0xffff;
740 State.F0 = 1;
741 }
742 else if (tmp < MIN32)
743 {
744 State.regs[OP[0]] = 0x8000;
745 State.regs[OP[0]+1] = 0;
746 State.F0 = 1;
747 }
748 else
749 {
750 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
751 State.regs[OP[0]+1] = tmp & 0xffff;
752 State.F0 = 0;
753 }
87178dbd 754 trace_output (OP_DREG);
2934d1c9
MH		 755}
756
757/* addac3s */
758void
759OP_17001202 ()
760{
4c38885c 761 int64 tmp;
4c38885c 762 State.F1 = State.F0;
87178dbd
MM		 763
764 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 765 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 766 if ( tmp > MAX32)
767 {
768 State.regs[OP[0]] = 0x7fff;
769 State.regs[OP[0]+1] = 0xffff;
770 State.F0 = 1;
771 }
772 else if (tmp < MIN32)
773 {
774 State.regs[OP[0]] = 0x8000;
775 State.regs[OP[0]+1] = 0;
776 State.F0 = 1;
777 }
778 else
779 {
780 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
781 State.regs[OP[0]+1] = tmp & 0xffff;
782 State.F0 = 0;
783 }
87178dbd 784 trace_output (OP_DREG);
2934d1c9
MH		 785}
786
787/* addi */
788void
789OP_201 ()
790{
2254cd90 791 uint tmp = State.regs[OP[0]];
4f425a32
MH		 792 if (OP[1] == 0)
793 OP[1] = 16;
f4b022d3 794
87178dbd 795 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 796 State.regs[OP[0]] += OP[1];
f4b022d3 797 State.C = (State.regs[OP[0]] < tmp);
87178dbd 798 trace_output (OP_REG);
2934d1c9
MH		 799}
800
801/* and */
802void
803OP_C00 ()
804{
87178dbd 805 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 806 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 807 trace_output (OP_REG);
2934d1c9
MH		 808}
809
810/* and3 */
811void
812OP_6000000 ()
813{
87178dbd 814 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 815 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 816 trace_output (OP_REG);
2934d1c9
MH		 817}
818
819/* bclri */
820void
821OP_C01 ()
822{
87178dbd 823 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 824 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 825 trace_output (OP_REG);
2934d1c9
MH		 826}
827
828/* bl.s */
829void
830OP_4900 ()
831{
8831cb01 832 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
2934d1c9 833 State.regs[13] = PC+1;
fd435e9f 834 JMP( PC + SEXT8 (OP[0]));
87178dbd 835 trace_output (OP_VOID);
2934d1c9
MH		 836}
837
838/* bl.l */
839void
840OP_24800000 ()
841{
8831cb01 842 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
2934d1c9 843 State.regs[13] = PC+1;
fd435e9f 844 JMP (PC + OP[0]);
87178dbd 845 trace_output (OP_VOID);
2934d1c9
MH		 846}
847
848/* bnoti */
849void
850OP_A01 ()
851{
87178dbd 852 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 853 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 854 trace_output (OP_REG);
2934d1c9
MH		 855}
856
857/* bra.s */
858void
859OP_4800 ()
860{
a18cb100 861 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
fd435e9f 862 JMP (PC + SEXT8 (OP[0]));
87178dbd 863 trace_output (OP_VOID);
2934d1c9
MH		 864}
865
866/* bra.l */
867void
868OP_24000000 ()
869{
87178dbd 870 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
fd435e9f 871 JMP (PC + OP[0]);
87178dbd 872 trace_output (OP_VOID);
2934d1c9
MH		 873}
874
875/* brf0f.s */
876void
877OP_4A00 ()
878{
a18cb100 879 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 880 if (State.F0 == 0)
fd435e9f 881 JMP (PC + SEXT8 (OP[0]));
87178dbd 882 trace_output (OP_FLAG);
2934d1c9
MH		 883}
884
885/* brf0f.l */
886void
887OP_25000000 ()
888{
87178dbd 889 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 890 if (State.F0 == 0)
fd435e9f 891 JMP (PC + OP[0]);
87178dbd 892 trace_output (OP_FLAG);
2934d1c9
MH		 893}
894
895/* brf0t.s */
896void
897OP_4B00 ()
898{
a18cb100 899 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 900 if (State.F0)
fd435e9f 901 JMP (PC + SEXT8 (OP[0]));
87178dbd 902 trace_output (OP_FLAG);
2934d1c9
MH		 903}
904
905/* brf0t.l */
906void
907OP_25800000 ()
908{
87178dbd 909 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 910 if (State.F0)
fd435e9f 911 JMP (PC + OP[0]);
87178dbd 912 trace_output (OP_FLAG);
2934d1c9
MH		 913}
914
915/* bseti */
916void
917OP_801 ()
918{
87178dbd 919 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 920 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 921 trace_output (OP_REG);
2934d1c9
MH		 922}
923
924/* btsti */
925void
926OP_E01 ()
927{
87178dbd 928 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 929 State.F1 = State.F0;
930 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 931 trace_output (OP_FLAG);
2934d1c9
MH		 932}
933
934/* clrac */
935void
936OP_5601 ()
937{
87178dbd 938 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 939 State.a[OP[0]] = 0;
87178dbd 940 trace_output (OP_ACCUM);
2934d1c9
MH		 941}
942
943/* cmp */
944void
945OP_600 ()
946{
87178dbd 947 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 948 State.F1 = State.F0;
949 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 950 trace_output (OP_FLAG);
2934d1c9
MH		 951}
952
953/* cmp */
954void
955OP_1603 ()
956{
87178dbd 957 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 958 State.F1 = State.F0;
4f425a32 959 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 960 trace_output (OP_FLAG);
2934d1c9
MH		 961}
962
963/* cmpeq */
964void
965OP_400 ()
966{
87178dbd 967 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 968 State.F1 = State.F0;
969 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 970 trace_output (OP_FLAG);
2934d1c9
MH		 971}
972
973/* cmpeq */
974void
975OP_1403 ()
976{
87178dbd 977 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 978 State.F1 = State.F0;
fd435e9f 979 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
87178dbd 980 trace_output (OP_FLAG);
2934d1c9
MH		 981}
982
983/* cmpeqi.s */
984void
985OP_401 ()
986{
c12f5c67 987 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 988 State.F1 = State.F0;
c12f5c67 989 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
87178dbd 990 trace_output (OP_FLAG);
2934d1c9
MH		 991}
992
993/* cmpeqi.l */
994void
995OP_2000000 ()
996{
87178dbd 997 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 998 State.F1 = State.F0;
c12f5c67 999 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
87178dbd 1000 trace_output (OP_FLAG);
2934d1c9
MH		 1001}
1002
1003/* cmpi.s */
1004void
1005OP_601 ()
1006{
87178dbd 1007 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 1008 State.F1 = State.F0;
c12f5c67 1009 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
87178dbd 1010 trace_output (OP_FLAG);
2934d1c9
MH		 1011}
1012
1013/* cmpi.l */
1014void
1015OP_3000000 ()
1016{
87178dbd 1017 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1018 State.F1 = State.F0;
1019 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 1020 trace_output (OP_FLAG);
2934d1c9
MH		 1021}
1022
1023/* cmpu */
1024void
1025OP_4600 ()
1026{
87178dbd 1027 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 1028 State.F1 = State.F0;
1029 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 1030 trace_output (OP_FLAG);
2934d1c9
MH		 1031}
1032
1033/* cmpui */
1034void
1035OP_23000000 ()
1036{
87178dbd 1037 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 1038 State.F1 = State.F0;
c12f5c67 1039 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
87178dbd 1040 trace_output (OP_FLAG);
2934d1c9
MH		 1041}
1042
1043/* cpfg */
1044void
1045OP_4E09 ()
1046{
1047 uint8 *src, *dst;
2934d1c9 1048
60fc5b72 1049 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 1050 if (OP[0] == 0)
1051 dst = &State.F0;
1052 else
1053 dst = &State.F1;
1054
1055 if (OP[1] == 0)
1056 src = &State.F0;
1057 else if (OP[1] == 1)
1058 src = &State.F1;
1059 else
1060 src = &State.C;
1061
1062 *dst = *src;
87178dbd 1063 trace_output (OP_FLAG);
2934d1c9
MH		 1064}
1065
1066/* dbt */
1067void
1068OP_5F20 ()
1069{
a49a15ad 1070 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
4f425a32 1071 State.exception = SIGTRAP;
2934d1c9
MH		 1072}
1073
1074/* divs */
1075void
1076OP_14002800 ()
1077{
1078 uint16 foo, tmp, tmpf;
87178dbd
MM		 1079
1080 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 1081 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1082 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1083 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1084 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1085 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 1086 trace_output (OP_DREG);
2934d1c9
MH		 1087}
1088
1089/* exef0f */
1090void
1091OP_4E04 ()
1092{
87178dbd 1093 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1094 State.exe = (State.F0 == 0);
87178dbd 1095 trace_output (OP_FLAG);
2934d1c9
MH		 1096}
1097
1098/* exef0t */
1099void
1100OP_4E24 ()
1101{
87178dbd 1102 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1103 State.exe = (State.F0 != 0);
87178dbd 1104 trace_output (OP_FLAG);
2934d1c9
MH		 1105}
1106
1107/* exef1f */
1108void
1109OP_4E40 ()
1110{
87178dbd 1111 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1112 State.exe = (State.F1 == 0);
87178dbd 1113 trace_output (OP_FLAG);
2934d1c9
MH		 1114}
1115
1116/* exef1t */
1117void
1118OP_4E42 ()
1119{
87178dbd 1120 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1121 State.exe = (State.F1 != 0);
87178dbd 1122 trace_output (OP_FLAG);
2934d1c9
MH		 1123}
1124
1125/* exefaf */
1126void
1127OP_4E00 ()
1128{
87178dbd 1129 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1130 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 1131 trace_output (OP_FLAG);
2934d1c9
MH		 1132}
1133
1134/* exefat */
1135void
1136OP_4E02 ()
1137{
87178dbd 1138 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1139 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 1140 trace_output (OP_FLAG);
2934d1c9
MH		 1141}
1142
1143/* exetaf */
1144void
1145OP_4E20 ()
1146{
87178dbd 1147 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1148 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 1149 trace_output (OP_FLAG);
2934d1c9
MH		 1150}
1151
1152/* exetat */
1153void
1154OP_4E22 ()
1155{
87178dbd 1156 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1157 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 1158 trace_output (OP_FLAG);
2934d1c9
MH		 1159}
1160
1161/* exp */
1162void
1163OP_15002A00 ()
1164{
1165 uint32 tmp, foo;
1166 int i;
1167
87178dbd 1168 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 1169 if (((int16)State.regs[OP[1]]) >= 0)
1170 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 1171 else
4c38885c 1172 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 1173
1174 foo = 0x40000000;
4c38885c 1175 for (i=1;i<17;i++)
2934d1c9
MH		 1176 {
1177 if (tmp & foo)
1178 {
1179 State.regs[OP[0]] = i-1;
87178dbd 1180 trace_output (OP_REG);
2934d1c9
MH		 1181 return;
1182 }
4c38885c 1183 foo >>= 1;
2934d1c9
MH		 1184 }
1185 State.regs[OP[0]] = 16;
87178dbd 1186 trace_output (OP_REG);
2934d1c9
MH		 1187}
1188
1189/* exp */
1190void
1191OP_15002A02 ()
1192{
4c38885c
MH		 1193 int64 tmp, foo;
1194 int i;
87178dbd
MM		 1195
1196 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
fd435e9f
MM		 1197 tmp = SEXT40(State.a[OP[1]]);
1198 if (tmp < 0)
1199 tmp = ~tmp & MASK40;
4c38885c
MH		 1200
1201 foo = 0x4000000000LL;
1202 for (i=1;i<25;i++)
1203 {
1204 if (tmp & foo)
1205 {
1206 State.regs[OP[0]] = i-9;
87178dbd 1207 trace_output (OP_REG);
4c38885c
MH		 1208 return;
1209 }
1210 foo >>= 1;
1211 }
1212 State.regs[OP[0]] = 16;
87178dbd 1213 trace_output (OP_REG);
2934d1c9
MH		 1214}
1215
1216/* jl */
1217void
1218OP_4D00 ()
1219{
8831cb01 1220 trace_input ("jl", OP_REG, OP_R0, OP_R1);
2934d1c9 1221 State.regs[13] = PC+1;
fd435e9f 1222 JMP (State.regs[OP[0]]);
87178dbd 1223 trace_output (OP_VOID);
2934d1c9
MH		 1224}
1225
1226/* jmp */
1227void
1228OP_4C00 ()
1229{
a18cb100 1230 trace_input ("jmp", OP_REG,
8831cb01
MM		 1231 (OP[0] == 13) ? OP_R0 : OP_VOID,
1232 (OP[0] == 13) ? OP_R1 : OP_VOID);
a18cb100 1233
fd435e9f 1234 JMP (State.regs[OP[0]]);
87178dbd 1235 trace_output (OP_VOID);
2934d1c9
MH		 1236}
1237
1238/* ld */
1239void
1240OP_30000000 ()
1241{
87178dbd 1242 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1243 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1244 trace_output (OP_REG);
2934d1c9
MH		 1245}
1246
1247/* ld */
1248void
1249OP_6401 ()
1250{
87178dbd 1251 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1252 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1253 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1254 trace_output (OP_REG);
2934d1c9
MH		 1255}
1256
1257/* ld */
1258void
1259OP_6001 ()
1260{
87178dbd 1261 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1262 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1263 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1264 trace_output (OP_REG);
2934d1c9
MH		 1265}
1266
1267/* ld */
1268void
1269OP_6000 ()
1270{
87178dbd 1271 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1272 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1273 trace_output (OP_REG);
2934d1c9
MH		 1274}
1275
1276/* ld2w */
1277void
1278OP_31000000 ()
1279{
8918b3a7 1280 uint16 addr = State.regs[OP[2]];
308f64d3 1281 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
8918b3a7
MM		 1282 State.regs[OP[0]] = RW (OP[1] + addr);
1283 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
87178dbd 1284 trace_output (OP_DREG);
2934d1c9
MH		 1285}
1286
1287/* ld2w */
1288void
1289OP_6601 ()
1290{
8918b3a7 1291 uint16 addr = State.regs[OP[1]];
87178dbd 1292 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
8918b3a7
MM		 1293 State.regs[OP[0]] = RW (addr);
1294 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1295 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1296 trace_output (OP_DREG);
2934d1c9
MH		 1297}
1298
1299/* ld2w */
1300void
1301OP_6201 ()
1302{
8918b3a7 1303 uint16 addr = State.regs[OP[1]];
87178dbd 1304 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
8918b3a7
MM		 1305 State.regs[OP[0]] = RW (addr);
1306 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1307 INC_ADDR(State.regs[OP[1]],4);
8918b3a7 1308 trace_output (OP_DREG);
2934d1c9
MH		 1309}
1310
1311/* ld2w */
1312void
1313OP_6200 ()
1314{
8918b3a7 1315 uint16 addr = State.regs[OP[1]];
addb61a5 1316 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
8918b3a7
MM		 1317 State.regs[OP[0]] = RW (addr);
1318 State.regs[OP[0]+1] = RW (addr+2);
1319 trace_output (OP_DREG);
2934d1c9
MH		 1320}
1321
1322/* ldb */
1323void
1324OP_38000000 ()
1325{
87178dbd 1326 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
c422ecc7 1327 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
87178dbd 1328 trace_output (OP_REG);
2934d1c9
MH		 1329}
1330
1331/* ldb */
1332void
1333OP_7000 ()
1334{
87178dbd 1335 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
c422ecc7 1336 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
87178dbd 1337 trace_output (OP_REG);
2934d1c9
MH		 1338}
1339
1340/* ldi.s */
1341void
1342OP_4001 ()
1343{
87178dbd 1344 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1345 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1346 trace_output (OP_REG);
2934d1c9
MH		 1347}
1348
1349/* ldi.l */
1350void
1351OP_20000000 ()
1352{
fd435e9f 1353 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1354 State.regs[OP[0]] = OP[1];
87178dbd 1355 trace_output (OP_REG);
2934d1c9
MH		 1356}
1357
1358/* ldub */
1359void
1360OP_39000000 ()
1361{
87178dbd 1362 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1363 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1364 trace_output (OP_REG);
2934d1c9
MH		 1365}
1366
1367/* ldub */
1368void
1369OP_7200 ()
1370{
87178dbd 1371 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1372 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1373 trace_output (OP_REG);
2934d1c9
MH		 1374}
1375
1376/* mac */
1377void
1378OP_2A00 ()
1379{
4c38885c 1380 int64 tmp;
87178dbd
MM		 1381
1382 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1383 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1384
1385 if (State.FX)
4f425a32 1386 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1387
1388 if (State.ST && tmp > MAX32)
1389 tmp = MAX32;
1390
4f425a32 1391 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1392 if (State.ST)
1393 {
1394 if (tmp > MAX32)
1395 State.a[OP[0]] = MAX32;
1396 else if (tmp < MIN32)
1397 State.a[OP[0]] = MIN32;
1398 else
4f425a32 1399 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1400 }
1401 else
4f425a32 1402 State.a[OP[0]] = tmp & MASK40;
87178dbd 1403 trace_output (OP_ACCUM);
2934d1c9
MH		 1404}
1405
1406/* macsu */
1407void
1408OP_1A00 ()
1409{
4f425a32 1410 int64 tmp;
87178dbd
MM		 1411
1412 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1413 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1414 if (State.FX)
1415 tmp = SEXT40( (tmp << 1) & MASK40);
1416
1417 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1418 trace_output (OP_ACCUM);
2934d1c9
MH		 1419}
1420
1421/* macu */
1422void
1423OP_3A00 ()
1424{
ae558075
AC		 1425 uint64 tmp;
1426 uint32 src1;
1427 uint32 src2;
87178dbd
MM		 1428
1429 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
ae558075
AC		 1430 src1 = (uint16) State.regs[OP[1]];
1431 src2 = (uint16) State.regs[OP[2]];
1432 tmp = src1 * src2;
4f425a32 1433 if (State.FX)
ae558075
AC		 1434 tmp = (tmp << 1);
1435 State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
87178dbd 1436 trace_output (OP_ACCUM);
2934d1c9
MH		 1437}
1438
1439/* max */
1440void
1441OP_2600 ()
1442{
87178dbd 1443 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1444 State.F1 = State.F0;
ea2155e8 1445 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1446 {
1447 State.regs[OP[0]] = State.regs[OP[1]];
1448 State.F0 = 1;
1449 }
1450 else
1451 State.F0 = 0;
87178dbd 1452 trace_output (OP_REG);
2934d1c9
MH		 1453}
1454
1455/* max */
1456void
1457OP_3600 ()
1458{
4f425a32 1459 int64 tmp;
87178dbd
MM		 1460
1461 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1462 State.F1 = State.F0;
1463 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1464 if (tmp > SEXT40(State.a[OP[0]]))
1465 {
1466 State.a[OP[0]] = tmp & MASK40;
1467 State.F0 = 1;
1468 }
1469 else
1470 State.F0 = 0;
87178dbd 1471 trace_output (OP_ACCUM);
2934d1c9
MH		 1472}
1473
1474/* max */
1475void
1476OP_3602 ()
1477{
87178dbd 1478 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1479 State.F1 = State.F0;
1480 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1481 {
1482 State.a[OP[0]] = State.a[OP[1]];
1483 State.F0 = 1;
1484 }
1485 else
1486 State.F0 = 0;
87178dbd 1487 trace_output (OP_ACCUM);
2934d1c9
MH		 1488}
1489
4f425a32 1490
2934d1c9
MH		 1491/* min */
1492void
1493OP_2601 ()
1494{
87178dbd 1495 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1496 State.F1 = State.F0;
ea2155e8 1497 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1498 {
1499 State.regs[OP[0]] = State.regs[OP[1]];
1500 State.F0 = 1;
1501 }
1502 else
1503 State.F0 = 0;
87178dbd 1504 trace_output (OP_REG);
2934d1c9
MH		 1505}
1506
1507/* min */
1508void
1509OP_3601 ()
1510{
4f425a32 1511 int64 tmp;
87178dbd
MM		 1512
1513 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1514 State.F1 = State.F0;
1515 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1516 if (tmp < SEXT40(State.a[OP[0]]))
1517 {
1518 State.a[OP[0]] = tmp & MASK40;
1519 State.F0 = 1;
1520 }
1521 else
1522 State.F0 = 0;
87178dbd 1523 trace_output (OP_ACCUM);
2934d1c9
MH		 1524}
1525
1526/* min */
1527void
1528OP_3603 ()
1529{
87178dbd 1530 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1531 State.F1 = State.F0;
1532 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1533 {
1534 State.a[OP[0]] = State.a[OP[1]];
1535 State.F0 = 1;
1536 }
1537 else
1538 State.F0 = 0;
87178dbd 1539 trace_output (OP_ACCUM);
2934d1c9
MH		 1540}
1541
1542/* msb */
1543void
1544OP_2800 ()
1545{
4f425a32 1546 int64 tmp;
87178dbd
MM		 1547
1548 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1549 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1550
1551 if (State.FX)
1552 tmp = SEXT40 ((tmp << 1) & MASK40);
1553
1554 if (State.ST && tmp > MAX32)
1555 tmp = MAX32;
1556
1557 tmp = SEXT40(State.a[OP[0]]) - tmp;
1558 if (State.ST)
1559 {
1560 if (tmp > MAX32)
1561 State.a[OP[0]] = MAX32;
1562 else if (tmp < MIN32)
1563 State.a[OP[0]] = MIN32;
1564 else
1565 State.a[OP[0]] = tmp & MASK40;
1566 }
1567 else
1568 State.a[OP[0]] = tmp & MASK40;
87178dbd 1569 trace_output (OP_ACCUM);
2934d1c9
MH		 1570}
1571
1572/* msbsu */
1573void
1574OP_1800 ()
1575{
4f425a32 1576 int64 tmp;
87178dbd
MM		 1577
1578 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1579 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1580 if (State.FX)
1581 tmp = SEXT40( (tmp << 1) & MASK40);
1582
1583 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1584 trace_output (OP_ACCUM);
2934d1c9
MH		 1585}
1586
1587/* msbu */
1588void
1589OP_3800 ()
1590{
d294a657
AC		 1591 uint64 tmp;
1592 uint32 src1;
1593 uint32 src2;
87178dbd
MM		 1594
1595 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
d294a657
AC		 1596 src1 = (uint16) State.regs[OP[1]];
1597 src2 = (uint16) State.regs[OP[2]];
1598 tmp = src1 * src2;
4f425a32 1599 if (State.FX)
d294a657 1600 tmp = (tmp << 1);
4f425a32 1601
d294a657 1602 State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40;
87178dbd 1603 trace_output (OP_ACCUM);
2934d1c9
MH		 1604}
1605
1606/* mul */
1607void
1608OP_2E00 ()
1609{
87178dbd 1610 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1611 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1612 trace_output (OP_REG);
2934d1c9
MH		 1613}
1614
1615/* mulx */
1616void
1617OP_2C00 ()
1618{
4f425a32 1619 int64 tmp;
87178dbd
MM		 1620
1621 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1622 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1623
1624 if (State.FX)
1625 tmp = SEXT40 ((tmp << 1) & MASK40);
1626
1627 if (State.ST && tmp > MAX32)
1628 State.a[OP[0]] = MAX32;
1629 else
1630 State.a[OP[0]] = tmp & MASK40;
87178dbd 1631 trace_output (OP_ACCUM);
2934d1c9
MH		 1632}
1633
1634/* mulxsu */
1635void
1636OP_1C00 ()
1637{
4f425a32 1638 int64 tmp;
87178dbd
MM		 1639
1640 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1641 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1642
1643 if (State.FX)
1644 tmp <<= 1;
1645
1646 State.a[OP[0]] = tmp & MASK40;
87178dbd 1647 trace_output (OP_ACCUM);
2934d1c9
MH		 1648}
1649
1650/* mulxu */
1651void
1652OP_3C00 ()
1653{
9420287e
AC		 1654 uint64 tmp;
1655 uint32 src1;
1656 uint32 src2;
87178dbd
MM		 1657
1658 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
9420287e
AC		 1659 src1 = (uint16) State.regs[OP[1]];
1660 src2 = (uint16) State.regs[OP[2]];
1661 tmp = src1 * src2;
4f425a32
MH		 1662 if (State.FX)
1663 tmp <<= 1;
1664
1665 State.a[OP[0]] = tmp & MASK40;
87178dbd 1666 trace_output (OP_ACCUM);
2934d1c9
MH		 1667}
1668
1669/* mv */
1670void
1671OP_4000 ()
1672{
87178dbd 1673 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1674 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1675 trace_output (OP_REG);
2934d1c9
MH		 1676}
1677
1678/* mv2w */
1679void
1680OP_5000 ()
1681{
87178dbd 1682 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1683 State.regs[OP[0]] = State.regs[OP[1]];
1684 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1685 trace_output (OP_DREG);
2934d1c9
MH		 1686}
1687
1688/* mv2wfac */
1689void
1690OP_3E00 ()
1691{
87178dbd 1692 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1693 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1694 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1695 trace_output (OP_DREG);
2934d1c9
MH		 1696}
1697
1698/* mv2wtac */
1699void
1700OP_3E01 ()
1701{
fd435e9f 1702 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
4f425a32 1703 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
fd435e9f 1704 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1705}
1706
1707/* mvac */
1708void
1709OP_3E03 ()
1710{
87178dbd 1711 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1712 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1713 trace_output (OP_ACCUM);
2934d1c9
MH		 1714}
1715
1716/* mvb */
1717void
1718OP_5400 ()
1719{
87178dbd 1720 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1721 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1722 trace_output (OP_REG);
2934d1c9
MH		 1723}
1724
1725/* mvf0f */
1726void
1727OP_4400 ()
1728{
87178dbd 1729 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1730 if (State.F0 == 0)
1731 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1732 trace_output (OP_REG);
2934d1c9
MH		 1733}
1734
1735/* mvf0t */
1736void
1737OP_4401 ()
1738{
87178dbd 1739 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1740 if (State.F0)
1741 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1742 trace_output (OP_REG);
2934d1c9
MH		 1743}
1744
1745/* mvfacg */
1746void
1747OP_1E04 ()
1748{
87178dbd 1749 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1750 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1751 trace_output (OP_ACCUM);
2934d1c9
MH		 1752}
1753
1754/* mvfachi */
1755void
1756OP_1E00 ()
1757{
87178dbd 1758 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1759 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1760 trace_output (OP_REG);
2934d1c9
MH		 1761}
1762
1763/* mvfaclo */
1764void
1765OP_1E02 ()
1766{
87178dbd 1767 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1768 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1769 trace_output (OP_REG);
2934d1c9
MH		 1770}
1771
1772/* mvfc */
1773void
1774OP_5200 ()
1775{
87178dbd 1776 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
bc6df23d 1777 State.regs[OP[0]] = move_from_cr (OP[1]);
87178dbd 1778 trace_output (OP_REG);
2934d1c9
MH		 1779}
1780
1781/* mvtacg */
1782void
1783OP_1E41 ()
1784{
87178dbd 1785 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1786 State.a[OP[1]] &= MASK32;
1787 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1788 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1789}
1790
1791/* mvtachi */
1792void
1793OP_1E01 ()
1794{
1795 uint16 tmp;
87178dbd
MM		 1796
1797 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1798 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1799 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1800 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1801}
1802
1803/* mvtaclo */
1804void
1805OP_1E21 ()
1806{
87178dbd 1807 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1808 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1809 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1810}
1811
1812/* mvtc */
1813void
1814OP_5600 ()
1815{
87178dbd 1816 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
bc6df23d 1817 move_to_cr (OP[1], State.regs[OP[0]]);
87178dbd 1818 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1819}
1820
1821/* mvub */
1822void
1823OP_5401 ()
1824{
87178dbd 1825 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1826 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1827 trace_output (OP_REG);
2934d1c9
MH		 1828}
1829
1830/* neg */
1831void
1832OP_4605 ()
1833{
87178dbd 1834 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1835 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1836 trace_output (OP_REG);
2934d1c9
MH		 1837}
1838
1839/* neg */
1840void
1841OP_5605 ()
1842{
1843 int64 tmp;
87178dbd
MM		 1844
1845 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1846 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1847 if (State.ST)
1848 {
4c38885c 1849 if ( tmp > MAX32)
2934d1c9 1850 State.a[OP[0]] = MAX32;
4c38885c 1851 else if (tmp < MIN32)
2934d1c9
MH		 1852 State.a[OP[0]] = MIN32;
1853 else
4f425a32 1854 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1855 }
1856 else
4f425a32 1857 State.a[OP[0]] = tmp & MASK40;
87178dbd 1858 trace_output (OP_ACCUM);
2934d1c9
MH		 1859}
1860
1861
1862/* nop */
1863void
1864OP_5E00 ()
1865{
87178dbd 1866 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
7eebfc62 1867
c422ecc7
MH		 1868 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1869 switch (State.ins_type)
1870 {
1871 default:
1872 ins_type_counters[ (int)INS_UNKNOWN ]++;
1873 break;
1874
1875 case INS_LEFT_PARALLEL:
1876 /* Don't count a parallel op that includes a NOP as a true parallel op */
1877 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1878 ins_type_counters[ (int)INS_RIGHT ]++;
1879 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1880 break;
1881
1882 case INS_LEFT:
1883 case INS_LEFT_COND_EXE:
1884 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1885 break;
1886
1887 case INS_RIGHT_PARALLEL:
1888 /* Don't count a parallel op that includes a NOP as a true parallel op */
1889 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1890 ins_type_counters[ (int)INS_LEFT ]++;
1891 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1892 break;
1893
1894 case INS_RIGHT:
1895 case INS_RIGHT_COND_EXE:
1896 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1897 break;
1898 }
1899
1900 trace_output (OP_VOID);
2934d1c9
MH		 1901}
1902
1903/* not */
1904void
1905OP_4603 ()
1906{
87178dbd 1907 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1908 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1909 trace_output (OP_REG);
2934d1c9
MH		 1910}
1911
1912/* or */
1913void
1914OP_800 ()
1915{
87178dbd 1916 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1917 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1918 trace_output (OP_REG);
2934d1c9
MH		 1919}
1920
1921/* or3 */
1922void
1923OP_4000000 ()
1924{
87178dbd 1925 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1926 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1927 trace_output (OP_REG);
2934d1c9
MH		 1928}
1929
1930/* rac */
1931void
1932OP_5201 ()
1933{
1934 int64 tmp;
1935 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1936
1937 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1938 if (OP[1] != 0)
1939 {
7eebfc62
MM		 1940 (*d10v_callback->printf_filtered) (d10v_callback,
1941 "ERROR at PC 0x%x: instruction only valid for A0\n",
1942 PC<<2);
166acb9f
MH		 1943 State.exception = SIGILL;
1944 }
1945
2934d1c9 1946 State.F1 = State.F0;
aa49c64f 1947 tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff));
2934d1c9 1948 if (shift >=0)
aa49c64f 1949 tmp <<= shift;
2934d1c9 1950 else
aa49c64f
AC		 1951 tmp >>= -shift;
1952 tmp += 0x8000;
1953 tmp >>= 16; /* look at bits 0:43 */
1954 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2934d1c9
MH		 1955 {
1956 State.regs[OP[0]] = 0x7fff;
1957 State.regs[OP[0]+1] = 0xffff;
1958 State.F0 = 1;
1959 }
aa49c64f 1960 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2934d1c9
MH		 1961 {
1962 State.regs[OP[0]] = 0x8000;
1963 State.regs[OP[0]+1] = 0;
1964 State.F0 = 1;
1965 }
1966 else
1967 {
1968 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1969 State.regs[OP[0]+1] = tmp & 0xffff;
1970 State.F0 = 0;
1971 }
87178dbd 1972 trace_output (OP_DREG);
2934d1c9
MH		 1973}
1974
1975/* rachi */
1976void
1977OP_4201 ()
1978{
70ee56c5 1979 signed64 tmp;
4c38885c 1980 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1981
1982 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1983 State.F1 = State.F0;
1984 if (shift >=0)
70ee56c5 1985 tmp = SEXT40 (State.a[OP[1]]) << shift;
4c38885c 1986 else
70ee56c5 1987 tmp = SEXT40 (State.a[OP[1]]) >> -shift;
4c38885c 1988 tmp += 0x8000;
63a91cfb 1989
70ee56c5 1990 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
4c38885c
MH		 1991 {
1992 State.regs[OP[0]] = 0x7fff;
1993 State.F0 = 1;
1994 }
70ee56c5 1995 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
4c38885c
MH		 1996 {
1997 State.regs[OP[0]] = 0x8000;
1998 State.F0 = 1;
1999 }
2000 else
2001 {
2002 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2003 State.F0 = 0;
2004 }
87178dbd 2005 trace_output (OP_REG);
2934d1c9
MH		 2006}
2007
2008/* rep */
2009void
2010OP_27000000 ()
2011{
87178dbd 2012 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 2013 RPT_S = PC + 1;
2014 RPT_E = PC + OP[1];
2015 RPT_C = State.regs[OP[0]];
2016 State.RP = 1;
2017 if (RPT_C == 0)
2018 {
7eebfc62 2019 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 2020 State.exception = SIGILL;
2934d1c9 2021 }
4c38885c
MH		 2022 if (OP[1] < 4)
2023 {
7eebfc62 2024 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 2025 State.exception = SIGILL;
4c38885c 2026 }
87178dbd 2027 trace_output (OP_VOID);
2934d1c9
MH		 2028}
2029
2030/* repi */
2031void
2032OP_2F000000 ()
2033{
87178dbd 2034 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 2035 RPT_S = PC + 1;
2036 RPT_E = PC + OP[1];
2037 RPT_C = OP[0];
2038 State.RP = 1;
2039 if (RPT_C == 0)
2040 {
7eebfc62 2041 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 2042 State.exception = SIGILL;
4c38885c
MH		 2043 }
2044 if (OP[1] < 4)
2045 {
7eebfc62 2046 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 2047 State.exception = SIGILL;
2934d1c9 2048 }
87178dbd 2049 trace_output (OP_VOID);
2934d1c9
MH		 2050}
2051
2052/* rtd */
2053void
2054OP_5F60 ()
2055{
7eebfc62 2056 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 2057 State.exception = SIGILL;
2934d1c9
MH		 2058}
2059
2060/* rte */
2061void
2062OP_5F40 ()
2063{
87178dbd 2064 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
bc6df23d 2065 move_to_cr (PSW_CR, BPSW);
8831cb01 2066 JMP(BPC);
87178dbd 2067 trace_output (OP_VOID);
2934d1c9
MH		 2068}
2069
2070/* sadd */
2071void
2072OP_1223 ()
2073{
4c38885c 2074 int64 tmp;
87178dbd
MM		 2075
2076 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 2077 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 2078 if (State.ST)
2079 {
2080 if (tmp > MAX32)
2081 State.a[OP[0]] = MAX32;
2082 else if (tmp < MIN32)
2083 State.a[OP[0]] = MIN32;
2084 else
4f425a32 2085 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 2086 }
2087 else
4f425a32 2088 State.a[OP[0]] = tmp & MASK40;
87178dbd 2089 trace_output (OP_ACCUM);
2934d1c9
MH		 2090}
2091
2092/* setf0f */
2093void
2094OP_4611 ()
2095{
87178dbd 2096 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2097 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 2098 trace_output (OP_REG);
2934d1c9
MH		 2099}
2100
2101/* setf0t */
2102void
2103OP_4613 ()
2104{
87178dbd 2105 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2106 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 2107 trace_output (OP_REG);
2934d1c9
MH		 2108}
2109
2110/* sleep */
2111void
2112OP_5FC0 ()
2113{
87178dbd 2114 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2115 State.IE = 1;
87178dbd 2116 trace_output (OP_VOID);
2934d1c9
MH		 2117}
2118
2119/* sll */
2120void
2121OP_2200 ()
2122{
87178dbd 2123 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 2124 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 2125 trace_output (OP_REG);
2934d1c9
MH		 2126}
2127
2128/* sll */
2129void
2130OP_3200 ()
2131{
4c38885c 2132 int64 tmp;
87178dbd 2133 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2134 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2135 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 2136 else
2137 {
2138 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2139 State.exception = SIGILL;
2140 return;
2141 }
4c38885c
MH		 2142
2143 if (State.ST)
2144 {
2145 if (tmp > MAX32)
2146 State.a[OP[0]] = MAX32;
2147 else if (tmp < 0xffffff80000000LL)
2148 State.a[OP[0]] = MIN32;
2149 else
2150 State.a[OP[0]] = tmp & MASK40;
2151 }
2152 else
2153 State.a[OP[0]] = tmp & MASK40;
87178dbd 2154 trace_output (OP_ACCUM);
2934d1c9
MH		 2155}
2156
2157/* slli */
2158void
2159OP_2201 ()
2160{
87178dbd 2161 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2162 State.regs[OP[0]] <<= OP[1];
87178dbd 2163 trace_output (OP_REG);
2934d1c9
MH		 2164}
2165
2166/* slli */
2167void
2168OP_3201 ()
2169{
4c38885c 2170 int64 tmp;
4f425a32
MH		 2171
2172 if (OP[1] == 0)
2173 OP[1] = 16;
4f425a32 2174
87178dbd 2175 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 2176 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 2177
2178 if (State.ST)
2179 {
2180 if (tmp > MAX32)
2181 State.a[OP[0]] = MAX32;
2182 else if (tmp < 0xffffff80000000LL)
2183 State.a[OP[0]] = MIN32;
2184 else
2185 State.a[OP[0]] = tmp & MASK40;
2186 }
2187 else
2188 State.a[OP[0]] = tmp & MASK40;
87178dbd 2189 trace_output (OP_ACCUM);
2934d1c9
MH		 2190}
2191
2192/* slx */
2193void
2194OP_460B ()
2195{
87178dbd 2196 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 2197 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 2198 trace_output (OP_REG);
2934d1c9
MH		 2199}
2200
2201/* sra */
2202void
2203OP_2400 ()
2204{
87178dbd 2205 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 2206 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2207 trace_output (OP_REG);
2934d1c9
MH		 2208}
2209
2210/* sra */
2211void
2212OP_3400 ()
2213{
87178dbd 2214 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2215 if ((State.regs[OP[1]] & 31) <= 16)
fd435e9f 2216 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
069398aa
MM		 2217 else
2218 {
2219 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2220 State.exception = SIGILL;
2221 return;
2222 }
2223
87178dbd 2224 trace_output (OP_ACCUM);
2934d1c9
MH		 2225}
2226
2227/* srai */
2228void
2229OP_2401 ()
2230{
87178dbd 2231 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2232 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2233 trace_output (OP_REG);
2934d1c9
MH		 2234}
2235
2236/* srai */
2237void
2238OP_3401 ()
2239{
4f425a32
MH		 2240 if (OP[1] == 0)
2241 OP[1] = 16;
87178dbd
MM		 2242
2243 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
fd435e9f 2244 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
87178dbd 2245 trace_output (OP_ACCUM);
2934d1c9
MH		 2246}
2247
2248/* srl */
2249void
2250OP_2000 ()
2251{
87178dbd 2252 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2253 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2254 trace_output (OP_REG);
2934d1c9
MH		 2255}
2256
2257/* srl */
2258void
2259OP_3000 ()
2260{
87178dbd 2261 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2262 if ((State.regs[OP[1]] & 31) <= 16)
fd435e9f 2263 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
069398aa
MM		 2264 else
2265 {
2266 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2267 State.exception = SIGILL;
2268 return;
2269 }
2270
87178dbd 2271 trace_output (OP_ACCUM);
2934d1c9
MH		 2272}
2273
2274/* srli */
2275void
2276OP_2001 ()
2277{
87178dbd 2278 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2279 State.regs[OP[0]] >>= OP[1];
87178dbd 2280 trace_output (OP_REG);
2934d1c9
MH		 2281}
2282
2283/* srli */
2284void
2285OP_3001 ()
2286{
4f425a32
MH		 2287 if (OP[1] == 0)
2288 OP[1] = 16;
87178dbd
MM		 2289
2290 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
fd435e9f 2291 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
87178dbd 2292 trace_output (OP_ACCUM);
2934d1c9
MH		 2293}
2294
2295/* srx */
2296void
2297OP_4609 ()
2298{
2299 uint16 tmp;
87178dbd
MM		 2300
2301 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2302 tmp = State.F0 << 15;
2303 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2304 trace_output (OP_REG);
2934d1c9
MH		 2305}
2306
2307/* st */
2308void
2309OP_34000000 ()
2310{
87178dbd 2311 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2312 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2313 trace_output (OP_VOID);
2934d1c9
MH		 2314}
2315
2316/* st */
2317void
2318OP_6800 ()
2319{
87178dbd 2320 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2321 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2322 trace_output (OP_VOID);
2934d1c9
MH		 2323}
2324
2325/* st */
2326void
2327OP_6C1F ()
2328{
87178dbd 2329 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2330 if ( OP[1] != 15 )
2331 {
7eebfc62 2332 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2333 State.exception = SIGILL;
2334 return;
4c38885c
MH		 2335 }
2336 State.regs[OP[1]] -= 2;
2337 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2338 trace_output (OP_VOID);
2934d1c9
MH		 2339}
2340
2341/* st */
2342void
2343OP_6801 ()
2344{
87178dbd 2345 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2346 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2347 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2348 trace_output (OP_VOID);
2934d1c9
MH		 2349}
2350
2351/* st */
2352void
2353OP_6C01 ()
2354{
87178dbd 2355 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
fd435e9f
MM		 2356 if ( OP[1] == 15 )
2357 {
2358 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2359 State.exception = SIGILL;
2360 return;
2361 }
4c38885c 2362 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2363 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2364 trace_output (OP_VOID);
2934d1c9
MH		 2365}
2366
2367/* st2w */
2368void
2369OP_35000000 ()
2370{
87178dbd 2371 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2372 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2373 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2374 trace_output (OP_VOID);
2934d1c9
MH		 2375}
2376
2377/* st2w */
2378void
2379OP_6A00 ()
2380{
a18cb100 2381 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2382 SW (State.regs[OP[1]], State.regs[OP[0]]);
2383 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2384 trace_output (OP_VOID);
2934d1c9
MH		 2385}
2386
2387/* st2w */
2388void
2389OP_6E1F ()
2390{
a18cb100 2391 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2392 if ( OP[1] != 15 )
2393 {
7eebfc62 2394 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2395 State.exception = SIGILL;
2396 return;
4c38885c
MH		 2397 }
2398 State.regs[OP[1]] -= 4;
2399 SW (State.regs[OP[1]], State.regs[OP[0]]);
2400 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2401 trace_output (OP_VOID);
2934d1c9
MH		 2402}
2403
2404/* st2w */
2405void
2406OP_6A01 ()
2407{
1155e06e 2408 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2409 SW (State.regs[OP[1]], State.regs[OP[0]]);
2410 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2411 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2412 trace_output (OP_VOID);
2934d1c9
MH		 2413}
2414
2415/* st2w */
2416void
2417OP_6E01 ()
2418{
1155e06e
FF		 2419 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2420 if ( OP[1] == 15 )
2421 {
2422 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2423 State.exception = SIGILL;
2424 return;
2425 }
4c38885c
MH		 2426 SW (State.regs[OP[1]], State.regs[OP[0]]);
2427 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2428 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2429 trace_output (OP_VOID);
2934d1c9
MH		 2430}
2431
2432/* stb */
2433void
2434OP_3C000000 ()
2435{
87178dbd 2436 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2437 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2438 trace_output (OP_VOID);
2934d1c9
MH		 2439}
2440
2441/* stb */
2442void
2443OP_7800 ()
2444{
87178dbd 2445 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2446 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2447 trace_output (OP_VOID);
2934d1c9
MH		 2448}
2449
2450/* stop */
2451void
2452OP_5FE0 ()
2453{
87178dbd 2454 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
a49a15ad 2455 State.exception = SIG_D10V_STOP;
87178dbd 2456 trace_output (OP_VOID);
2934d1c9
MH		 2457}
2458
2459/* sub */
2460void
2461OP_0 ()
4c38885c 2462{
f4b022d3 2463 uint16 tmp;
87178dbd
MM		 2464
2465 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
aa49c64f
AC		 2466 /* see ../common/sim-alu.h for a more extensive discussion on how to
2467 compute the carry/overflow bits. */
f4b022d3 2468 tmp = State.regs[OP[0]] - State.regs[OP[1]];
aa49c64f 2469 State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]);
f4b022d3 2470 State.regs[OP[0]] = tmp;
87178dbd 2471 trace_output (OP_REG);
4c38885c
MH		 2472}
2473
2474/* sub */
2475void
2476OP_1001 ()
2477{
4f425a32 2478 int64 tmp;
87178dbd
MM		 2479
2480 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2481 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2482 if (State.ST)
2483 {
2484 if ( tmp > MAX32)
2485 State.a[OP[0]] = MAX32;
2486 else if ( tmp < MIN32)
2487 State.a[OP[0]] = MIN32;
2488 else
2489 State.a[OP[0]] = tmp & MASK40;
2490 }
2491 else
2492 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2493
2494 trace_output (OP_ACCUM);
4c38885c
MH		 2495}
2496
2497/* sub */
2498
2499void
2500OP_1003 ()
2934d1c9 2501{
4f425a32 2502 int64 tmp;
87178dbd
MM		 2503
2504 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2505 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2506 if (State.ST)
2507 {
2508 if (tmp > MAX32)
2509 State.a[OP[0]] = MAX32;
2510 else if ( tmp < MIN32)
2511 State.a[OP[0]] = MIN32;
2512 else
2513 State.a[OP[0]] = tmp & MASK40;
2514 }
2515 else
2516 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2517
2518 trace_output (OP_ACCUM);
2934d1c9
MH		 2519}
2520
2521/* sub2w */
2522void
2523OP_1000 ()
2524{
f4b022d3 2525 uint32 tmp,a,b;
4c38885c 2526
87178dbd 2527 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
f4b022d3
MM		 2528 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2529 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
70ee56c5
AC		 2530 /* see ../common/sim-alu.h for a more extensive discussion on how to
2531 compute the carry/overflow bits */
2532 tmp = a - b;
51b057f2 2533 State.C = (a >= b);
4c38885c
MH		 2534 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2535 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2536 trace_output (OP_DREG);
2934d1c9
MH		 2537}
2538
2539/* subac3 */
2540void
2541OP_17000000 ()
2542{
4f425a32 2543 int64 tmp;
87178dbd
MM		 2544
2545 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2546 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2547 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2548 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2549 trace_output (OP_DREG);
2934d1c9
MH		 2550}
2551
2552/* subac3 */
2553void
2554OP_17000002 ()
2555{
4f425a32 2556 int64 tmp;
87178dbd
MM		 2557
2558 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2559 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2560 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2561 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2562 trace_output (OP_DREG);
2934d1c9
MH		 2563}
2564
2565/* subac3s */
2566void
2567OP_17001000 ()
2568{
4f425a32 2569 int64 tmp;
87178dbd
MM		 2570
2571 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2572 State.F1 = State.F0;
2573 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2574 if ( tmp > MAX32)
2575 {
2576 State.regs[OP[0]] = 0x7fff;
2577 State.regs[OP[0]+1] = 0xffff;
2578 State.F0 = 1;
2579 }
2580 else if (tmp < MIN32)
2581 {
2582 State.regs[OP[0]] = 0x8000;
2583 State.regs[OP[0]+1] = 0;
2584 State.F0 = 1;
2585 }
2586 else
2587 {
2588 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2589 State.regs[OP[0]+1] = tmp & 0xffff;
2590 State.F0 = 0;
2591 }
87178dbd 2592 trace_output (OP_DREG);
2934d1c9
MH		 2593}
2594
2595/* subac3s */
2596void
2597OP_17001002 ()
2598{
4f425a32 2599 int64 tmp;
87178dbd
MM		 2600
2601 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2602 State.F1 = State.F0;
2603 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2604 if ( tmp > MAX32)
2605 {
2606 State.regs[OP[0]] = 0x7fff;
2607 State.regs[OP[0]+1] = 0xffff;
2608 State.F0 = 1;
2609 }
2610 else if (tmp < MIN32)
2611 {
2612 State.regs[OP[0]] = 0x8000;
2613 State.regs[OP[0]+1] = 0;
2614 State.F0 = 1;
2615 }
2616 else
2617 {
2618 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2619 State.regs[OP[0]+1] = tmp & 0xffff;
2620 State.F0 = 0;
2621 }
87178dbd 2622 trace_output (OP_DREG);
2934d1c9
MH		 2623}
2624
2625/* subi */
2626void
2627OP_1 ()
2628{
70ee56c5 2629 unsigned tmp;
4f425a32
MH		 2630 if (OP[1] == 0)
2631 OP[1] = 16;
87178dbd
MM		 2632
2633 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
70ee56c5 2634 /* see ../common/sim-alu.h for a more extensive discussion on how to
51b057f2
AC		 2635 compute the carry/overflow bits. */
2636 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
70ee56c5
AC		 2637 tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
2638 + (unsigned)(unsigned16) ( - OP[1]));
2639 State.C = (tmp >= (1 << 16));
2640 State.regs[OP[0]] = tmp;
87178dbd 2641 trace_output (OP_REG);
2934d1c9
MH		 2642}
2643
2644/* trap */
2645void
2646OP_5F00 ()
2647{
a5719092 2648 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2649 trace_output (OP_VOID);
8918b3a7 2650
63a91cfb 2651 switch (OP[0])
2934d1c9 2652 {
63a91cfb 2653 default:
19d44375 2654 {
bc6df23d
AC		 2655 uint16 vec = OP[0] + TRAP_VECTOR_START;
2656 BPC = PC + 1;
2657 move_to_cr (BPSW_CR, PSW);
2658 move_to_cr (PSW_CR, PSW & PSW_SM_BIT);
2659 JMP (vec);
87e43259 2660 }
bc6df23d 2661 break;
87e43259
AC		 2662 case 15: /* new system call trap */
2663 /* Trap 15 is used for simulating low-level I/O */
63a91cfb 2664 {
63a91cfb
MM		 2665 errno = 0;
2666
2667/* Registers passed to trap 0 */
2668
8831cb01
MM		 2669#define FUNC State.regs[4] /* function number */
2670#define PARM1 State.regs[0] /* optional parm 1 */
2671#define PARM2 State.regs[1] /* optional parm 2 */
2672#define PARM3 State.regs[2] /* optional parm 3 */
2673#define PARM4 State.regs[3] /* optional parm 3 */
63a91cfb
MM		 2674
2675/* Registers set by trap 0 */
2676
8831cb01
MM		 2677#define RETVAL State.regs[0] /* return value */
2678#define RETVAL_HIGH State.regs[0] /* return value */
2679#define RETVAL_LOW State.regs[1] /* return value */
65c0d7de 2680#define RETERR State.regs[4] /* return error code */
63a91cfb
MM		 2681
2682/* Turn a pointer in a register into a pointer into real memory. */
2683
c422ecc7 2684#define MEMPTR(x) ((char *)(dmem_addr(x)))
63a91cfb
MM		 2685
2686 switch (FUNC)
2687 {
2688#if !defined(__GO32__) && !defined(_WIN32)
63a91cfb
MM		 2689 case SYS_fork:
2690 RETVAL = fork ();
8918b3a7 2691 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
8831cb01 2692 trace_output (OP_R0);
63a91cfb 2693 break;
8918b3a7 2694
57bc1a72
MM		 2695 case SYS_getpid:
2696 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2697 RETVAL = getpid ();
8831cb01 2698 trace_output (OP_R0);
57bc1a72
MM		 2699 break;
2700
2701 case SYS_kill:
2702 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2703 if (PARM1 == getpid ())
2704 {
2705 trace_output (OP_VOID);
2706 State.exception = PARM2;
2707 }
2708 else
2709 {
2710 int os_sig = -1;
2711 switch (PARM2)
2712 {
2713#ifdef SIGHUP
2714 case 1: os_sig = SIGHUP; break;
2715#endif
2716#ifdef SIGINT
2717 case 2: os_sig = SIGINT; break;
2718#endif
2719#ifdef SIGQUIT
2720 case 3: os_sig = SIGQUIT; break;
2721#endif
2722#ifdef SIGILL
2723 case 4: os_sig = SIGILL; break;
2724#endif
2725#ifdef SIGTRAP
2726 case 5: os_sig = SIGTRAP; break;
2727#endif
2728#ifdef SIGABRT
2729 case 6: os_sig = SIGABRT; break;
2730#elif defined(SIGIOT)
2731 case 6: os_sig = SIGIOT; break;
2732#endif
2733#ifdef SIGEMT
2734 case 7: os_sig = SIGEMT; break;
2735#endif
2736#ifdef SIGFPE
2737 case 8: os_sig = SIGFPE; break;
2738#endif
2739#ifdef SIGKILL
2740 case 9: os_sig = SIGKILL; break;
2741#endif
2742#ifdef SIGBUS
2743 case 10: os_sig = SIGBUS; break;
2744#endif
2745#ifdef SIGSEGV
2746 case 11: os_sig = SIGSEGV; break;
2747#endif
2748#ifdef SIGSYS
2749 case 12: os_sig = SIGSYS; break;
2750#endif
2751#ifdef SIGPIPE
2752 case 13: os_sig = SIGPIPE; break;
2753#endif
2754#ifdef SIGALRM
2755 case 14: os_sig = SIGALRM; break;
2756#endif
2757#ifdef SIGTERM
2758 case 15: os_sig = SIGTERM; break;
2759#endif
2760#ifdef SIGURG
2761 case 16: os_sig = SIGURG; break;
2762#endif
2763#ifdef SIGSTOP
2764 case 17: os_sig = SIGSTOP; break;
2765#endif
2766#ifdef SIGTSTP
2767 case 18: os_sig = SIGTSTP; break;
2768#endif
2769#ifdef SIGCONT
2770 case 19: os_sig = SIGCONT; break;
2771#endif
2772#ifdef SIGCHLD
2773 case 20: os_sig = SIGCHLD; break;
2774#elif defined(SIGCLD)
2775 case 20: os_sig = SIGCLD; break;
2776#endif
2777#ifdef SIGTTIN
2778 case 21: os_sig = SIGTTIN; break;
2779#endif
2780#ifdef SIGTTOU
2781 case 22: os_sig = SIGTTOU; break;
2782#endif
2783#ifdef SIGIO
2784 case 23: os_sig = SIGIO; break;
2785#elif defined (SIGPOLL)
2786 case 23: os_sig = SIGPOLL; break;
2787#endif
2788#ifdef SIGXCPU
2789 case 24: os_sig = SIGXCPU; break;
2790#endif
2791#ifdef SIGXFSZ
2792 case 25: os_sig = SIGXFSZ; break;
2793#endif
2794#ifdef SIGVTALRM
2795 case 26: os_sig = SIGVTALRM; break;
2796#endif
2797#ifdef SIGPROF
2798 case 27: os_sig = SIGPROF; break;
2799#endif
2800#ifdef SIGWINCH
2801 case 28: os_sig = SIGWINCH; break;
2802#endif
2803#ifdef SIGLOST
2804 case 29: os_sig = SIGLOST; break;
2805#endif
2806#ifdef SIGUSR1
2807 case 30: os_sig = SIGUSR1; break;
2808#endif
2809#ifdef SIGUSR2
2810 case 31: os_sig = SIGUSR2; break;
2811#endif
2812 }
2813
2814 if (os_sig == -1)
2815 {
2816 trace_output (OP_VOID);
2817 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
fd435e9f 2818 (*d10v_callback->flush_stdout) (d10v_callback);
57bc1a72
MM		 2819 State.exception = SIGILL;
2820 }
2821 else
2822 {
2823 RETVAL = kill (PARM1, PARM2);
8831cb01 2824 trace_output (OP_R0);
57bc1a72
MM		 2825 }
2826 }
2827 break;
2828
63a91cfb
MM		 2829 case SYS_execve:
2830 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2831 (char **)MEMPTR (PARM3));
8831cb01
MM		 2832 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
2833 trace_output (OP_R0);
63a91cfb 2834 break;
8918b3a7 2835
87e43259 2836#ifdef SYS_execv
63a91cfb
MM		 2837 case SYS_execv:
2838 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
8831cb01
MM		 2839 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
2840 trace_output (OP_R0);
63a91cfb 2841 break;
87e43259 2842#endif
8918b3a7 2843
63a91cfb
MM		 2844 case SYS_pipe:
2845 {
2846 reg_t buf;
2847 int host_fd[2];
2848
2849 buf = PARM1;
2850 RETVAL = pipe (host_fd);
2851 SW (buf, host_fd[0]);
2852 buf += sizeof(uint16);
2853 SW (buf, host_fd[1]);
8831cb01
MM		 2854 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
2855 trace_output (OP_R0);
63a91cfb
MM		 2856 }
2857 break;
8918b3a7 2858
87e43259 2859#ifdef SYS_wait
63a91cfb
MM		 2860 case SYS_wait:
2861 {
2862 int status;
2863
2864 RETVAL = wait (&status);
8918b3a7
MM		 2865 if (PARM1)
2866 SW (PARM1, status);
8831cb01
MM		 2867 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
2868 trace_output (OP_R0);
63a91cfb
MM		 2869 }
2870 break;
87e43259 2871#endif
57bc1a72
MM		 2872#else
2873 case SYS_getpid:
2874 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2875 RETVAL = 1;
8831cb01 2876 trace_output (OP_R0);
57bc1a72
MM		 2877 break;
2878
2879 case SYS_kill:
2880 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2881 trace_output (OP_VOID);
2882 State.exception = PARM2;
2883 break;
63a91cfb 2884#endif
8918b3a7 2885
63a91cfb
MM		 2886 case SYS_read:
2887 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2888 PARM3);
8831cb01
MM		 2889 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
2890 trace_output (OP_R0);
63a91cfb 2891 break;
8918b3a7 2892
63a91cfb
MM		 2893 case SYS_write:
2894 if (PARM1 == 1)
2895 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2896 MEMPTR (PARM2), PARM3);
2897 else
2898 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2899 MEMPTR (PARM2), PARM3);
8831cb01
MM		 2900 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
2901 trace_output (OP_R0);
63a91cfb 2902 break;
8918b3a7 2903
63a91cfb 2904 case SYS_lseek:
65c0d7de
MA		 2905 {
2906 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2907 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2908 PARM4);
2909 RETVAL_HIGH = ret >> 16;
2910 RETVAL_LOW = ret & 0xffff;
2911 }
8831cb01
MM		 2912 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
2913 trace_output (OP_R0R1);
63a91cfb 2914 break;
8918b3a7 2915
63a91cfb
MM		 2916 case SYS_close:
2917 RETVAL = d10v_callback->close (d10v_callback, PARM1);
8831cb01
MM		 2918 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
2919 trace_output (OP_R0);
63a91cfb 2920 break;
8918b3a7 2921
63a91cfb
MM		 2922 case SYS_open:
2923 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
8831cb01
MM		 2924 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
2925 trace_output (OP_R0);
2926 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
2927 trace_output (OP_R0);
63a91cfb 2928 break;
8918b3a7 2929
63a91cfb 2930 case SYS_exit:
a49a15ad 2931 State.exception = SIG_D10V_EXIT;
8831cb01 2932 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
8918b3a7 2933 trace_output (OP_VOID);
63a91cfb 2934 break;
63a91cfb 2935
8719be26 2936 case SYS_stat:
63a91cfb
MM		 2937 /* stat system call */
2938 {
2939 struct stat host_stat;
2940 reg_t buf;
2941
2942 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2943
2944 buf = PARM2;
2945
2946 /* The hard-coded offsets and sizes were determined by using
2947 * the D10V compiler on a test program that used struct stat.
2948 */
2949 SW (buf, host_stat.st_dev);
2950 SW (buf+2, host_stat.st_ino);
2951 SW (buf+4, host_stat.st_mode);
2952 SW (buf+6, host_stat.st_nlink);
2953 SW (buf+8, host_stat.st_uid);
2954 SW (buf+10, host_stat.st_gid);
2955 SW (buf+12, host_stat.st_rdev);
2956 SLW (buf+16, host_stat.st_size);
2957 SLW (buf+20, host_stat.st_atime);
2958 SLW (buf+28, host_stat.st_mtime);
2959 SLW (buf+36, host_stat.st_ctime);
2960 }
8831cb01
MM		 2961 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
2962 trace_output (OP_R0);
63a91cfb 2963 break;
63a91cfb 2964
63a91cfb
MM		 2965 case SYS_chown:
2966 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
8831cb01
MM		 2967 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
2968 trace_output (OP_R0);
63a91cfb 2969 break;
8918b3a7 2970
63a91cfb
MM		 2971 case SYS_chmod:
2972 RETVAL = chmod (MEMPTR (PARM1), PARM2);
8831cb01
MM		 2973 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
2974 trace_output (OP_R0);
63a91cfb 2975 break;
8918b3a7 2976
87e43259 2977#ifdef SYS_utime
63a91cfb
MM		 2978 case SYS_utime:
2979 /* Cast the second argument to void *, to avoid type mismatch
2980 if a prototype is present. */
2981 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
8831cb01
MM		 2982 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
2983 trace_output (OP_R0);
8918b3a7 2984 break;
87e43259 2985#endif
8918b3a7 2986
87e43259 2987#ifdef SYS_time
8918b3a7
MM		 2988 case SYS_time:
2989 {
2990 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2991 RETVAL_HIGH = ret >> 16;
2992 RETVAL_LOW = ret & 0xffff;
2993 }
8831cb01
MM		 2994 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
2995 trace_output (OP_R0R1);
63a91cfb 2996 break;
87e43259 2997#endif
8918b3a7 2998
63a91cfb
MM		 2999 default:
3000 abort ();
3001 }
87e43259 3002 RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
63a91cfb
MM		 3003 break;
3004 }
2934d1c9
MH		 3005 }
3006}
3007
3008/* tst0i */
3009void
3010OP_7000000 ()
3011{
87178dbd 3012 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3013 State.F1 = State.F0;
4f425a32 3014 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 3015 trace_output (OP_FLAG);
2934d1c9
MH		 3016}
3017
3018/* tst1i */
3019void
3020OP_F000000 ()
3021{
87178dbd 3022 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3023 State.F1 = State.F0;
4f425a32 3024 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 3025 trace_output (OP_FLAG);
2934d1c9
MH		 3026}
3027
3028/* wait */
3029void
3030OP_5F80 ()
3031{
87178dbd 3032 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 3033 State.IE = 1;
87178dbd 3034 trace_output (OP_VOID);
2934d1c9
MH		 3035}
3036
3037/* xor */
3038void
3039OP_A00 ()
3040{
87178dbd 3041 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 3042 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 3043 trace_output (OP_REG);
2934d1c9
MH		 3044}
3045
3046/* xor3 */
3047void
3048OP_5000000 ()
3049{
87178dbd 3050 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 3051 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 3052 trace_output (OP_REG);
2934d1c9
MH		 3053}
3054
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