]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/frv/frv-sim.h
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Update years in copyright notice for the GDB files.
[thirdparty/binutils-gdb.git] / sim / frv / frv-sim.h
CommitLineData
b34f6357 1/* collection of junk waiting time to sort out
8acc9f48 2 Copyright (C) 1998-2013 Free Software Foundation, Inc.
e930b1f5 3 Contributed by Red Hat
b34f6357
DB		 4
5This file is part of the GNU Simulators.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
4744ac1b
JB		 9the Free Software Foundation; either version 3 of the License, or
10(at your option) any later version.
b34f6357
DB		 11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
4744ac1b
JB		 17You should have received a copy of the GNU General Public License
18along with this program. If not, see <http://www.gnu.org/licenses/>. */
b34f6357
DB		 19
20#ifndef FRV_SIM_H
21#define FRV_SIM_H
22
23#include "sim-options.h"
24
676a64f4
RS		 25/* True if SPR is the number of accumulator or accumulator guard register. */
26#define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535)
b34f6357 27
b34f6357
DB		 28/* Initialization of the frv cpu. */
29void frv_initialize (SIM_CPU *, SIM_DESC);
30void frv_term (SIM_DESC);
31void frv_power_on_reset (SIM_CPU *);
32void frv_hardware_reset (SIM_CPU *);
33void frv_software_reset (SIM_CPU *);
34
35/* The reset register. See FRV LSI section 10.3.1 */
36#define RSTR_ADDRESS 0xfeff0500
37#define RSTR_INITIAL_VALUE 0x00000400
38#define RSTR_HARDWARE_RESET 0x00000200
39#define RSTR_SOFTWARE_RESET 0x00000100
40
41#define GET_RSTR_HR(rstr) (((rstr) >> 1) & 1)
42#define GET_RSTR_SR(rstr) (((rstr) ) & 1)
43
44#define SET_RSTR_H(rstr) ((rstr) |= (1 << 9))
45#define SET_RSTR_S(rstr) ((rstr) |= (1 << 8))
46
47#define CLEAR_RSTR_P(rstr) ((rstr) &= ~(1 << 10))
48#define CLEAR_RSTR_H(rstr) ((rstr) &= ~(1 << 9))
49#define CLEAR_RSTR_S(rstr) ((rstr) &= ~(1 << 8))
50#define CLEAR_RSTR_HR(rstr) ((rstr) &= ~(1 << 1))
51#define CLEAR_RSTR_SR(rstr) ((rstr) &= ~1)
52
53/* Cutomized hardware get/set functions. */
54extern USI frvbf_h_spr_get_handler (SIM_CPU *, UINT);
55extern void frvbf_h_spr_set_handler (SIM_CPU *, UINT, USI);
56extern USI frvbf_h_gr_get_handler (SIM_CPU *, UINT);
57extern void frvbf_h_gr_set_handler (SIM_CPU *, UINT, USI);
58extern UHI frvbf_h_gr_hi_get_handler (SIM_CPU *, UINT);
59extern void frvbf_h_gr_hi_set_handler (SIM_CPU *, UINT, UHI);
60extern UHI frvbf_h_gr_lo_get_handler (SIM_CPU *, UINT);
61extern void frvbf_h_gr_lo_set_handler (SIM_CPU *, UINT, UHI);
62extern DI frvbf_h_gr_double_get_handler (SIM_CPU *, UINT);
63extern void frvbf_h_gr_double_set_handler (SIM_CPU *, UINT, DI);
64extern SF frvbf_h_fr_get_handler (SIM_CPU *, UINT);
65extern void frvbf_h_fr_set_handler (SIM_CPU *, UINT, SF);
66extern DF frvbf_h_fr_double_get_handler (SIM_CPU *, UINT);
67extern void frvbf_h_fr_double_set_handler (SIM_CPU *, UINT, DF);
68extern USI frvbf_h_fr_int_get_handler (SIM_CPU *, UINT);
69extern void frvbf_h_fr_int_set_handler (SIM_CPU *, UINT, USI);
70extern DI frvbf_h_cpr_double_get_handler (SIM_CPU *, UINT);
71extern void frvbf_h_cpr_double_set_handler (SIM_CPU *, UINT, DI);
72extern void frvbf_h_gr_quad_set_handler (SIM_CPU *, UINT, SI *);
73extern void frvbf_h_fr_quad_set_handler (SIM_CPU *, UINT, SI *);
74extern void frvbf_h_cpr_quad_set_handler (SIM_CPU *, UINT, SI *);
75extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI);
76
77extern USI spr_psr_get_handler (SIM_CPU *);
78extern void spr_psr_set_handler (SIM_CPU *, USI);
79extern USI spr_tbr_get_handler (SIM_CPU *);
80extern void spr_tbr_set_handler (SIM_CPU *, USI);
81extern USI spr_bpsr_get_handler (SIM_CPU *);
82extern void spr_bpsr_set_handler (SIM_CPU *, USI);
83extern USI spr_ccr_get_handler (SIM_CPU *);
84extern void spr_ccr_set_handler (SIM_CPU *, USI);
85extern void spr_cccr_set_handler (SIM_CPU *, USI);
86extern USI spr_cccr_get_handler (SIM_CPU *);
87extern USI spr_isr_get_handler (SIM_CPU *);
88extern void spr_isr_set_handler (SIM_CPU *, USI);
89extern USI spr_sr_get_handler (SIM_CPU *, UINT);
90extern void spr_sr_set_handler (SIM_CPU *, UINT, USI);
91
92extern void frvbf_switch_supervisor_user_context (SIM_CPU *);
93
94extern QI frvbf_set_icc_for_shift_left (SIM_CPU *, SI, SI, QI);
95extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
96
e930b1f5 97/* Insn semantics. */
b34f6357
DB		 98extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
99extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
e930b1f5
DB		 100extern SI frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
101extern SI frvbf_iacc_cut (SIM_CPU *, DI, SI);
b34f6357
DB		 102
103extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
104
105extern SI frvbf_scan_result (SIM_CPU *, SI);
106extern SI frvbf_cut (SIM_CPU *, SI, SI, SI);
107extern SI frvbf_media_cut (SIM_CPU *, DI, SI);
108extern SI frvbf_media_cut_ss (SIM_CPU *, DI, SI);
109extern void frvbf_media_cop (SIM_CPU *, int);
110extern UQI frvbf_cr_logic (SIM_CPU *, SI, UQI, UQI);
111
112extern void frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *, int);
113extern int frvbf_write_next_vliw_addr_to_LR;
114
115extern void frvbf_set_ne_index (SIM_CPU *, int);
116extern void frvbf_force_update (SIM_CPU *);
117\f
118#define GETTWI GETTSI
119#define SETTWI SETTSI
120#define LEUINT LEUSI
121\f
122/* Hardware/device support.
123 ??? Will eventually want to move device stuff to config files. */
124
125/* Support for the MCCR register (Cache Control Register) is needed in order
126 for overlays to work correctly with the scache: cached instructions need
127 to be flushed when the instruction space is changed at runtime. */
128
129/* These were just copied from another port and are necessary to build, but
130 but don't appear to be used. */
131#define MCCR_ADDR 0xffffffff
132#define MCCR_CP 0x80
133/* not supported */
134#define MCCR_CM0 2
135#define MCCR_CM1 1
136
137/* sim_core_attach device argument. */
138extern device frv_devices;
139
140/* FIXME: Temporary, until device support ready. */
141struct _device { int foo; };
142
143/* maintain the address of the start of the previous VLIW insn sequence. */
144extern IADDR previous_vliw_pc;
79e59fe6 145extern CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot;
b34f6357
DB		 146
147/* Hardware status. */
148#define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
149#define SET_HSR0(hsr0) SET_H_SPR (H_SPR_HSR0, (hsr0))
150
151#define GET_HSR0_ICE(hsr0) (((hsr0) >> 31) & 1)
152#define SET_HSR0_ICE(hsr0) ((hsr0) |= (1 << 31))
153#define CLEAR_HSR0_ICE(hsr0) ((hsr0) &= ~(1 << 31))
154
155#define GET_HSR0_DCE(hsr0) (((hsr0) >> 30) & 1)
156#define SET_HSR0_DCE(hsr0) ((hsr0) |= (1 << 30))
157#define CLEAR_HSR0_DCE(hsr0) ((hsr0) &= ~(1 << 30))
158
159#define GET_HSR0_CBM(hsr0) (((hsr0) >> 27) & 1)
160#define GET_HSR0_RME(hsr0) (((hsr0) >> 22) & 1)
161#define GET_HSR0_SA(hsr0) (((hsr0) >> 12) & 1)
162#define GET_HSR0_FRN(hsr0) (((hsr0) >> 11) & 1)
163#define GET_HSR0_GRN(hsr0) (((hsr0) >> 10) & 1)
164#define GET_HSR0_FRHE(hsr0) (((hsr0) >> 9) & 1)
165#define GET_HSR0_FRLE(hsr0) (((hsr0) >> 8) & 1)
166#define GET_HSR0_GRHE(hsr0) (((hsr0) >> 7) & 1)
167#define GET_HSR0_GRLE(hsr0) (((hsr0) >> 6) & 1)
168
169#define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
170#define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
e930b1f5
DB		 171#define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >> 1) & 1)
172#define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >> 8) & 7)
173#define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
b34f6357
DB		 174
175void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
176void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
177void frvbf_insn_cache_unlock (SIM_CPU *, SI);
178void frvbf_data_cache_unlock (SIM_CPU *, SI);
179void frvbf_insn_cache_invalidate (SIM_CPU *, SI, int);
180void frvbf_data_cache_invalidate (SIM_CPU *, SI, int);
181void frvbf_data_cache_flush (SIM_CPU *, SI, int);
182
183/* FR-V Interrupt classes.
184 These are declared in order of increasing priority. */
185enum frv_interrupt_class
186{
187 FRV_EXTERNAL_INTERRUPT,
188 FRV_SOFTWARE_INTERRUPT,
189 FRV_PROGRAM_INTERRUPT,
190 FRV_BREAK_INTERRUPT,
191 FRV_RESET_INTERRUPT,
192 NUM_FRV_INTERRUPT_CLASSES
193};
194
195/* FR-V Interrupt kinds.
196 These are declared in order of increasing priority. */
197enum frv_interrupt_kind
198{
199 /* External interrupts */
200 FRV_INTERRUPT_LEVEL_1,
201 FRV_INTERRUPT_LEVEL_2,
202 FRV_INTERRUPT_LEVEL_3,
203 FRV_INTERRUPT_LEVEL_4,
204 FRV_INTERRUPT_LEVEL_5,
205 FRV_INTERRUPT_LEVEL_6,
206 FRV_INTERRUPT_LEVEL_7,
207 FRV_INTERRUPT_LEVEL_8,
208 FRV_INTERRUPT_LEVEL_9,
209 FRV_INTERRUPT_LEVEL_10,
210 FRV_INTERRUPT_LEVEL_11,
211 FRV_INTERRUPT_LEVEL_12,
212 FRV_INTERRUPT_LEVEL_13,
213 FRV_INTERRUPT_LEVEL_14,
214 FRV_INTERRUPT_LEVEL_15,
215 /* Software interrupt */
216 FRV_TRAP_INSTRUCTION,
217 /* Program interrupts */
218 FRV_COMMIT_EXCEPTION,
219 FRV_DIVISION_EXCEPTION,
220 FRV_DATA_STORE_ERROR,
221 FRV_DATA_ACCESS_EXCEPTION,
222 FRV_DATA_ACCESS_MMU_MISS,
223 FRV_DATA_ACCESS_ERROR,
224 FRV_MP_EXCEPTION,
225 FRV_FP_EXCEPTION,
226 FRV_MEM_ADDRESS_NOT_ALIGNED,
227 FRV_REGISTER_EXCEPTION,
228 FRV_MP_DISABLED,
229 FRV_FP_DISABLED,
230 FRV_PRIVILEGED_INSTRUCTION,
231 FRV_ILLEGAL_INSTRUCTION,
232 FRV_INSTRUCTION_ACCESS_EXCEPTION,
233 FRV_INSTRUCTION_ACCESS_ERROR,
234 FRV_INSTRUCTION_ACCESS_MMU_MISS,
235 FRV_COMPOUND_EXCEPTION,
236 /* Break interrupt */
237 FRV_BREAK_EXCEPTION,
238 /* Reset interrupt */
239 FRV_RESET,
240 NUM_FRV_INTERRUPT_KINDS
241};
242
243/* FRV interrupt exception codes */
244enum frv_ec
245{
246 FRV_EC_DATA_STORE_ERROR = 0x00,
247 FRV_EC_INSTRUCTION_ACCESS_MMU_MISS = 0x01,
248 FRV_EC_INSTRUCTION_ACCESS_ERROR = 0x02,
249 FRV_EC_INSTRUCTION_ACCESS_EXCEPTION = 0x03,
250 FRV_EC_PRIVILEGED_INSTRUCTION = 0x04,
251 FRV_EC_ILLEGAL_INSTRUCTION = 0x05,
252 FRV_EC_FP_DISABLED = 0x06,
253 FRV_EC_MP_DISABLED = 0x07,
254 FRV_EC_MEM_ADDRESS_NOT_ALIGNED = 0x0b,
255 FRV_EC_REGISTER_EXCEPTION = 0x0c,
256 FRV_EC_FP_EXCEPTION = 0x0d,
257 FRV_EC_MP_EXCEPTION = 0x0e,
258 FRV_EC_DATA_ACCESS_ERROR = 0x10,
259 FRV_EC_DATA_ACCESS_MMU_MISS = 0x11,
260 FRV_EC_DATA_ACCESS_EXCEPTION = 0x12,
261 FRV_EC_DIVISION_EXCEPTION = 0x13,
262 FRV_EC_COMMIT_EXCEPTION = 0x14,
263 FRV_EC_NOT_EXECUTED = 0x1f,
264 FRV_EC_INTERRUPT_LEVEL_1 = FRV_EC_NOT_EXECUTED,
265 FRV_EC_INTERRUPT_LEVEL_2 = FRV_EC_NOT_EXECUTED,
266 FRV_EC_INTERRUPT_LEVEL_3 = FRV_EC_NOT_EXECUTED,
267 FRV_EC_INTERRUPT_LEVEL_4 = FRV_EC_NOT_EXECUTED,
268 FRV_EC_INTERRUPT_LEVEL_5 = FRV_EC_NOT_EXECUTED,
269 FRV_EC_INTERRUPT_LEVEL_6 = FRV_EC_NOT_EXECUTED,
270 FRV_EC_INTERRUPT_LEVEL_7 = FRV_EC_NOT_EXECUTED,
271 FRV_EC_INTERRUPT_LEVEL_8 = FRV_EC_NOT_EXECUTED,
272 FRV_EC_INTERRUPT_LEVEL_9 = FRV_EC_NOT_EXECUTED,
273 FRV_EC_INTERRUPT_LEVEL_10 = FRV_EC_NOT_EXECUTED,
274 FRV_EC_INTERRUPT_LEVEL_11 = FRV_EC_NOT_EXECUTED,
275 FRV_EC_INTERRUPT_LEVEL_12 = FRV_EC_NOT_EXECUTED,
276 FRV_EC_INTERRUPT_LEVEL_13 = FRV_EC_NOT_EXECUTED,
277 FRV_EC_INTERRUPT_LEVEL_14 = FRV_EC_NOT_EXECUTED,
278 FRV_EC_INTERRUPT_LEVEL_15 = FRV_EC_NOT_EXECUTED,
279 FRV_EC_TRAP_INSTRUCTION = FRV_EC_NOT_EXECUTED,
280 FRV_EC_COMPOUND_EXCEPTION = FRV_EC_NOT_EXECUTED,
281 FRV_EC_BREAK_EXCEPTION = FRV_EC_NOT_EXECUTED,
282 FRV_EC_RESET = FRV_EC_NOT_EXECUTED
283};
284
285/* FR-V Interrupt.
286 This struct contains enough information to describe a particular interrupt
287 occurance. */
288struct frv_interrupt
289{
290 enum frv_interrupt_kind kind;
291 enum frv_ec ec;
292 enum frv_interrupt_class iclass;
293 unsigned char deferred;
294 unsigned char precise;
295 unsigned char handler_offset;
296};
297
298/* FR-V Interrupt table.
299 Describes the interrupts supported by the FR-V. */
300extern struct frv_interrupt frv_interrupt_table[];
301
302/* FR-V Interrupt State.
303 Interrupts are queued during execution of parallel insns and the interupt(s)
304 to be handled determined by analysing the queue after each VLIW insn. */
305#define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now. */
306
307/* register_exception codes */
308enum frv_rec
309{
310 FRV_REC_UNIMPLEMENTED = 0,
311 FRV_REC_UNALIGNED = 1
312};
313
314/* instruction_access_exception codes */
315enum frv_iaec
316{
317 FRV_IAEC_PROTECT_VIOLATION = 1
318};
319
320/* data_access_exception codes */
321enum frv_daec
322{
323 FRV_DAEC_PROTECT_VIOLATION = 1
324};
325
326/* division_exception ISR codes */
327enum frv_dtt
328{
329 FRV_DTT_NO_EXCEPTION = 0,
330 FRV_DTT_DIVISION_BY_ZERO = 1,
331 FRV_DTT_OVERFLOW = 2,
332 FRV_DTT_BOTH = 3
333};
334
335/* data written during an insn causing an interrupt */
336struct frv_data_written
337{
338 USI words[4]; /* Actual data in words */
339 int length; /* length of data written */
340};
341
342/* fp_exception info */
343/* Trap codes for FSR0 and FQ registers. */
344enum frv_fsr_traps
345{
346 FSR_INVALID_OPERATION = 0x20,
347 FSR_OVERFLOW = 0x10,
348 FSR_UNDERFLOW = 0x08,
349 FSR_DIVISION_BY_ZERO = 0x04,
350 FSR_INEXACT = 0x02,
351 FSR_DENORMAL_INPUT = 0x01,
352 FSR_NO_EXCEPTION = 0
353};
354
355/* Floating point trap types for FSR. */
356enum frv_fsr_ftt
357{
358 FTT_NONE = 0,
359 FTT_IEEE_754_EXCEPTION = 1,
360 FTT_UNIMPLEMENTED_FPOP = 3,
361 FTT_SEQUENCE_ERROR = 4,
362 FTT_INVALID_FR = 6,
363 FTT_DENORMAL_INPUT = 7
364};
365
366struct frv_fp_exception_info
367{
368 enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */
369 enum frv_fsr_ftt ftt; /* floating point trap type */
370};
371
372struct frv_interrupt_queue_element
373{
374 enum frv_interrupt_kind kind; /* kind of interrupt */
375 IADDR vpc; /* address of insn causing interrupt */
376 int slot; /* VLIW slot containing the insn. */
377 USI eaddress; /* address of data access */
378 union {
379 enum frv_rec rec; /* register exception code */
380 enum frv_iaec iaec; /* insn access exception code */
381 enum frv_daec daec; /* data access exception code */
382 enum frv_dtt dtt; /* division exception code */
383 struct frv_fp_exception_info fp_info;
384 struct frv_data_written data_written;
385 } u;
386};
387
388struct frv_interrupt_timer
389{
390 int enabled;
391 unsigned value;
392 unsigned current;
393 enum frv_interrupt_kind interrupt;
394};
395
396struct frv_interrupt_state
397{
398 /* The interrupt queue */
399 struct frv_interrupt_queue_element queue[FRV_INTERRUPT_QUEUE_SIZE];
400 int queue_index;
401
402 /* interrupt queue element causing imprecise interrupt. */
403 struct frv_interrupt_queue_element *imprecise_interrupt;
404
405 /* interrupt timer. */
406 struct frv_interrupt_timer timer;
407
408 /* The last data written stored as an array of words. */
409 struct frv_data_written data_written;
410
411 /* The vliw slot of the insn causing the interrupt. */
412 int slot;
413
414 /* target register index for non excepting insns. */
415#define NE_NOFLAG (-1)
416 int ne_index;
417
418 /* Accumulated NE flags for non excepting floating point insns. */
419 SI f_ne_flags[2];
420};
421
422extern struct frv_interrupt_state frv_interrupt_state;
423
424/* Macros to manipulate the PSR. */
425#define GET_PSR() GET_H_SPR (H_SPR_PSR)
426
427#define SET_PSR_ET(psr, et) ( \
428 (psr) = ((psr) & ~0x1) | ((et) & 0x1) \
429)
430
431#define GET_PSR_PS(psr) (((psr) >> 1) & 1)
432
433#define SET_PSR_S(psr, s) ( \
434 (psr) = ((psr) & ~(0x1 << 2)) | (((s) & 0x1) << 2) \
435)
436
437/* Macros to handle the ISR register. */
438#define GET_ISR() GET_H_SPR (H_SPR_ISR)
439#define SET_ISR(isr) SET_H_SPR (H_SPR_ISR, (isr))
440
441#define GET_ISR_EDE(isr) (((isr) >> 5) & 1)
442
443#define GET_ISR_DTT(isr) (((isr) >> 3) & 3)
444#define SET_ISR_DTT(isr, dtt) ( \
445 (isr) = ((isr) & ~(0x3 << 3)) | (((dtt) & 0x3) << 3) \
446)
447
448#define SET_ISR_AEXC(isr) ((isr) |= (1 << 2))
449
450#define GET_ISR_EMAM(isr) ((isr) & 1)
451
452/* Macros to handle exception status registers.
453 Get and set the hardware directly, since we may be getting/setting fields
454 which are not accessible to the user. */
455#define GET_ESR(index) \
456 (CPU (h_spr[H_SPR_ESR0 + (index)]))
457#define SET_ESR(index, esr) \
458 (CPU (h_spr[H_SPR_ESR0 + (index)]) = (esr))
459
460#define SET_ESR_VALID(esr) ((esr) |= 1)
461#define CLEAR_ESR_VALID(esr) ((esr) &= ~1)
462
463#define SET_ESR_EC(esr, ec) ( \
464 (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
465)
466
467#define SET_ESR_REC(esr, rec) ( \
468 (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \
469)
470
471#define SET_ESR_IAEC(esr, iaec) ( \
472 (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \
473)
474
475#define SET_ESR_DAEC(esr, daec) ( \
476 (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \
477)
478
479#define SET_ESR_EAV(esr) ((esr) |= (1 << 11))
480#define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11))
481
482#define GET_ESR_EDV(esr) (((esr) >> 12) & 1)
483#define SET_ESR_EDV(esr) ((esr) |= (1 << 12))
484#define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12))
485
486#define GET_ESR_EDN(esr) ( \
487 ((esr) >> 13) & 0xf \
488)
489#define SET_ESR_EDN(esr, edn) ( \
490 (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \
491)
492
493#define SET_EPCR(index, address) \
494 (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address))
495
496#define SET_EAR(index, address) \
497 (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address))
498
499#define SET_EDR(index, edr) \
500 (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr))
501
502#define GET_ESFR(index) \
503 (CPU (h_spr[H_SPR_ESFR0 + (index)]))
504#define SET_ESFR(index, esfr) \
505 (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr))
506
507#define GET_ESFR_FLAG(findex) ( \
508 (findex) > 31 ? \
509 ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \
510 : \
511 ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \
512)
513#define SET_ESFR_FLAG(findex) ( \
514 (findex) > 31 ? \
515 (CPU (h_spr[H_SPR_ESFR0]) = \
516 (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \
517 ) : \
518 (CPU (h_spr[H_SPR_ESFR1]) = \
519 (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \
520 ) \
521)
522
523/* The FSR registers.
524 Get and set the hardware directly, since we may be getting/setting fields
525 which are not accessible to the user. */
526#define GET_FSR(index) \
527 (CPU (h_spr[H_SPR_FSR0 + (index)]))
528#define SET_FSR(index, fsr) \
529 (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))
530
531#define GET_FSR_TEM(fsr) ( \
532 ((fsr) >> 24) & 0x3f \
533)
534
535#define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
536#define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1)
537
538#define SET_FSR_FTT(fsr, ftt) ( \
539 (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \
540)
541
542#define GET_FSR_AEXC(fsr) ( \
543 ((fsr) >> 10) & 0x3f \
544)
545#define SET_FSR_AEXC(fsr, aexc) ( \
546 (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \
547)
548
549/* SIMD instruction exception codes for FQ. */
550enum frv_sie
551{
552 SIE_NIL = 0,
553 SIE_FRi = 1,
554 SIE_FRi_1 = 2
555};
556
557/* MIV field of FQ. */
558enum frv_miv
559{
560 MIV_FLOAT = 0,
561 MIV_MEDIA = 1
562};
563
564/* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The
565 index here refers to the low order 32 bit element.
566 Get and set the hardware directly, since we may be getting/setting fields
567 which are not accessible to the user. */
568#define GET_FQ(index) \
569 (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]))
570#define SET_FQ(index, fq) \
571 (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq))
572
573#define SET_FQ_MIV(fq, miv) ( \
574 (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \
575)
576
577#define SET_FQ_SIE(fq, sie) ( \
578 (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \
579)
580
581#define SET_FQ_FTT(fq, ftt) ( \
582 (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \
583)
584
585#define SET_FQ_CEXC(fq, cexc) ( \
586 (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \
587)
588
589#define GET_FQ_VALID(fq) ((fq) & 1)
590#define SET_FQ_VALID(fq) ((fq) |= 1)
591
592#define SET_FQ_OPC(index, insn) \
593 (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn))
594
595/* mp_exception support. */
596/* Media trap types for MSR. */
597enum frv_msr_mtt
598{
599 MTT_NONE = 0,
600 MTT_OVERFLOW = 1,
601 MTT_ACC_NOT_ALIGNED = 2,
602 MTT_ACC_NOT_IMPLEMENTED = 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED. */
603 MTT_CR_NOT_ALIGNED = 3,
604 MTT_UNIMPLEMENTED_MPOP = 5,
605 MTT_INVALID_FR = 6
606};
607
608/* Media status registers.
609 Get and set the hardware directly, since we may be getting/setting fields
610 which are not accessible to the user. */
611#define GET_MSR(index) \
612 (CPU (h_spr[H_SPR_MSR0 + (index)]))
613#define SET_MSR(index, msr) \
614 (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr))
615
616#define GET_MSR_AOVF(msr) ((msr) & 1)
617#define SET_MSR_AOVF(msr) ((msr) |= 1)
618
619#define GET_MSR_OVF(msr) ( \
620 ((msr) >> 1) & 0x1 \
621)
622#define SET_MSR_OVF(msr) ( \
623 (msr) |= (1 << 1) \
624)
625#define CLEAR_MSR_OVF(msr) ( \
626 (msr) &= ~(1 << 1) \
627)
628
629#define OR_MSR_SIE(msr, sie) ( \
630 (msr) |= (((sie) & 0xf) << 2) \
631)
632#define CLEAR_MSR_SIE(msr) ( \
633 (msr) &= ~(0xf << 2) \
634)
635
636#define GET_MSR_MTT(msr) ( \
637 ((msr) >> 12) & 0x7 \
638)
639#define SET_MSR_MTT(msr, mtt) ( \
640 (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \
641)
642#define GET_MSR_EMCI(msr) ( \
643 ((msr) >> 24) & 0x1 \
644)
e930b1f5
DB		 645#define GET_MSR_MPEM(msr) ( \
646 ((msr) >> 27) & 0x1 \
647)
b34f6357
DB		 648#define GET_MSR_SRDAV(msr) ( \
649 ((msr) >> 28) & 0x1 \
650)
651#define GET_MSR_RDAV(msr) ( \
652 ((msr) >> 29) & 0x1 \
653)
654#define GET_MSR_RD(msr) ( \
655 ((msr) >> 30) & 0x3 \
656)
657
658void frvbf_media_register_not_aligned (SIM_CPU *);
659void frvbf_media_acc_not_aligned (SIM_CPU *);
660void frvbf_media_cr_not_aligned (SIM_CPU *);
661void frvbf_media_overflow (SIM_CPU *, int);
662
663/* Functions for queuing and processing interrupts. */
664struct frv_interrupt_queue_element *
665frv_queue_break_interrupt (SIM_CPU *);
666
667struct frv_interrupt_queue_element *
668frv_queue_software_interrupt (SIM_CPU *, SI);
669
670struct frv_interrupt_queue_element *
671frv_queue_program_interrupt (SIM_CPU *, enum frv_interrupt_kind);
672
673struct frv_interrupt_queue_element *
674frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind);
675
676struct frv_interrupt_queue_element *
677frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
678
e930b1f5
DB		 679struct frv_interrupt_queue_element *
680frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
681
682struct frv_interrupt_queue_element *
683frv_queue_float_disabled_interrupt (SIM_CPU *);
684
685struct frv_interrupt_queue_element *
686frv_queue_media_disabled_interrupt (SIM_CPU *);
687
b34f6357
DB		 688struct frv_interrupt_queue_element *
689frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
690
691struct frv_interrupt_queue_element *
692frv_queue_register_exception_interrupt (SIM_CPU *, enum frv_rec);
693
694struct frv_interrupt_queue_element *
695frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI);
696
697struct frv_interrupt_queue_element *
698frv_queue_data_access_error_interrupt (SIM_CPU *, USI);
699
700struct frv_interrupt_queue_element *
701frv_queue_instruction_access_error_interrupt (SIM_CPU *);
702
703struct frv_interrupt_queue_element *
704frv_queue_instruction_access_exception_interrupt (SIM_CPU *);
705
706struct frv_interrupt_queue_element *
707frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *);
708
709enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int);
710
711struct frv_interrupt_queue_element *
712frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind);
713
714void
715frv_set_interrupt_queue_slot (SIM_CPU *, struct frv_interrupt_queue_element *);
716
717void frv_set_mp_exception_registers (SIM_CPU *, enum frv_msr_mtt, int);
718void frv_detect_insn_access_interrupts (SIM_CPU *, SCACHE *);
719
720void frv_process_interrupts (SIM_CPU *);
721
722void frv_break_interrupt (SIM_CPU *, struct frv_interrupt *, IADDR);
723void frv_non_operating_interrupt (SIM_CPU *, enum frv_interrupt_kind, IADDR);
724void frv_program_interrupt (
725 SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
726);
727void frv_software_interrupt (
728 SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
729);
730void frv_external_interrupt (
731 SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
732);
733void frv_program_or_software_interrupt (
734 SIM_CPU *, struct frv_interrupt *, IADDR
735);
736void frv_clear_interrupt_classes (
737 enum frv_interrupt_class, enum frv_interrupt_class
738);
739
740void
741frv_save_data_written_for_interrupts (SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *);
742
743/* Special purpose traps. */
744#define TRAP_SYSCALL 0x80
745#define TRAP_BREAKPOINT 0x81
746#define TRAP_REGDUMP1 0x82
747#define TRAP_REGDUMP2 0x83
748
749/* Handle the trap insns */
750void frv_itrap (SIM_CPU *, PCADDR, USI, int);
751void frv_mtrap (SIM_CPU *);
752/* Handle the break insn. */
753void frv_break (SIM_CPU *);
754/* Handle the rett insn. */
755USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
756
757/* Parallel write queue flags. */
758#define FRV_WRITE_QUEUE_FORCE_WRITE 1
759
760#define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element)
761
762/* Functions and macros for handling non-excepting instruction side effects.
763 Get and set the hardware directly, since we may be getting/setting fields
764 which are not accessible to the user. */
765#define GET_NECR() (GET_H_SPR (H_SPR_NECR))
766#define GET_NECR_ELOS(necr) (((necr) >> 6) & 1)
767#define GET_NECR_NEN(necr) (((necr) >> 1) & 0x1f)
768#define GET_NECR_VALID(necr) (((necr) ) & 1)
769
770#define NO_NESR (-1)
771/* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV
772 Architecture volume 1. */
773#define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b
774#define NESR_REGISTER_NOT_ALIGNED 0x1
775#define NESR_UQI_SIZE 0
776#define NESR_QI_SIZE 1
777#define NESR_UHI_SIZE 2
778#define NESR_HI_SIZE 3
779#define NESR_SI_SIZE 4
780#define NESR_DI_SIZE 5
781#define NESR_XI_SIZE 6
782
783#define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index))
784#define SET_NESR(index, value) ( \
785 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, \
786 H_SPR_NESR0 + (index), (value)), \
787 frvbf_force_update (current_cpu) \
788)
789#define GET_NESR_VALID(nesr) ((nesr) & 1)
790#define SET_NESR_VALID(nesr) ((nesr) |= 1)
791
792#define SET_NESR_EAV(nesr) ((nesr) |= (1 << 31))
793
794#define GET_NESR_FR(nesr) (((nesr) >> 30) & 1)
795#define SET_NESR_FR(nesr) ((nesr) |= (1 << 30))
796#define CLEAR_NESR_FR(nesr) ((nesr) &= ~(1 << 30))
797
798#define GET_NESR_DRN(nesr) (((nesr) >> 24) & 0x3f)
799#define SET_NESR_DRN(nesr, drn) ( \
800 (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \
801)
802
803#define SET_NESR_SIZE(nesr, data_size) ( \
804 (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \
805)
806
807#define SET_NESR_NEAN(nesr, index) ( \
808 (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \
809)
810
811#define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1)
812#define SET_NESR_DAEC(nesr, daec) ( \
813 (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \
814)
815
816#define GET_NESR_REC(nesr) (((nesr) >> 6) & 3)
817#define SET_NESR_REC(nesr, rec) ( \
818 (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \
819)
820
821#define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f)
822#define SET_NESR_EC(nesr, ec) ( \
823 (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
824)
825
826#define SET_NEEAR(index, address) ( \
827 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, \
828 H_SPR_NEEAR0 + (index), (address)), \
829 frvbf_force_update (current_cpu) \
830)
831
832#define GET_NE_FLAGS(flags, NE_base) ( \
833 (flags)[0] = GET_H_SPR ((NE_base)), \
834 (flags)[1] = GET_H_SPR ((NE_base) + 1) \
835)
836#define SET_NE_FLAGS(NE_base, flags) ( \
837 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base), \
838 (flags)[0]), \
839 frvbf_force_update (current_cpu), \
840 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1, \
841 (flags)[1]), \
842 frvbf_force_update (current_cpu) \
843)
844
845#define GET_NE_FLAG(flags, index) ( \
846 (index) > 31 ? \
847 ((flags[0] >> ((index) - 32)) & 1) \
848 : \
849 ((flags[1] >> (index)) & 1) \
850)
851#define SET_NE_FLAG(flags, index) ( \
852 (index) > 31 ? \
853 ((flags)[0] |= (1 << ((index) - 32))) \
854 : \
855 ((flags)[1] |= (1 << (index))) \
856)
857#define CLEAR_NE_FLAG(flags, index) ( \
858 (index) > 31 ? \
859 ((flags)[0] &= ~(1 << ((index) - 32))) \
860 : \
861 ((flags)[1] &= ~(1 << (index))) \
862)
863
864BI frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
865void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);
866
867void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
868void frvbf_commit (SIM_CPU *, SI, BI);
869
870void frvbf_fpu_error (CGEN_FPU *, int);
871
872void frv_vliw_setup_insn (SIM_CPU *, const CGEN_INSN *);
873
874extern int insns_in_slot[];
875
876#define COUNT_INSNS_IN_SLOT(slot) \
877{ \
878 if (WITH_PROFILE_MODEL_P) \
879 ++insns_in_slot[slot]; \
880}
881
882#define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
883
884/* Multiple loads and stores. */
885void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
886void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
887void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
888void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
889void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
890void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
891
892/* Memory and cache support. */
893QI frvbf_read_mem_QI (SIM_CPU *, IADDR, SI);
894UQI frvbf_read_mem_UQI (SIM_CPU *, IADDR, SI);
895HI frvbf_read_mem_HI (SIM_CPU *, IADDR, SI);
896UHI frvbf_read_mem_UHI (SIM_CPU *, IADDR, SI);
897SI frvbf_read_mem_SI (SIM_CPU *, IADDR, SI);
898SI frvbf_read_mem_WI (SIM_CPU *, IADDR, SI);
899DI frvbf_read_mem_DI (SIM_CPU *, IADDR, SI);
900DF frvbf_read_mem_DF (SIM_CPU *, IADDR, SI);
901
902USI frvbf_read_imem_USI (SIM_CPU *, PCADDR);
903
904void frvbf_write_mem_QI (SIM_CPU *, IADDR, SI, QI);
905void frvbf_write_mem_UQI (SIM_CPU *, IADDR, SI, UQI);
906void frvbf_write_mem_HI (SIM_CPU *, IADDR, SI, HI);
907void frvbf_write_mem_UHI (SIM_CPU *, IADDR, SI, UHI);
908void frvbf_write_mem_SI (SIM_CPU *, IADDR, SI, SI);
909void frvbf_write_mem_WI (SIM_CPU *, IADDR, SI, SI);
910void frvbf_write_mem_DI (SIM_CPU *, IADDR, SI, DI);
911void frvbf_write_mem_DF (SIM_CPU *, IADDR, SI, DF);
912
913void frvbf_mem_set_QI (SIM_CPU *, IADDR, SI, QI);
914void frvbf_mem_set_HI (SIM_CPU *, IADDR, SI, HI);
915void frvbf_mem_set_SI (SIM_CPU *, IADDR, SI, SI);
916void frvbf_mem_set_DI (SIM_CPU *, IADDR, SI, DI);
917void frvbf_mem_set_DF (SIM_CPU *, IADDR, SI, DF);
918void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
919
920void frv_set_write_queue_slot (SIM_CPU *current_cpu);
921
922/* FRV specific options. */
923extern const OPTION frv_options[];
924
925#endif /* FRV_SIM_H */
A mirror of the official binutils-gdb repository