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[thirdparty/binutils-gdb.git] / sim / frv / profile-fr500.c
CommitLineData
b34f6357
DB		 1/* frv simulator fr500 dependent profiling code.
2
c5a57081
JB		 3 Copyright (C) 1998-2001, 2003, 2007-2012 Free Software Foundation,
4 Inc.
b34f6357
DB		 5 Contributed by Red Hat
6
7This file is part of the GNU simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
4744ac1b
JB		 11the Free Software Foundation; either version 3 of the License, or
12(at your option) any later version.
b34f6357
DB		 13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
4744ac1b
JB		 19You should have received a copy of the GNU General Public License
20along with this program. If not, see <http://www.gnu.org/licenses/>.
b34f6357
DB		 21
22*/
23#define WANT_CPU
24#define WANT_CPU_FRVBF
25
26#include "sim-main.h"
27#include "bfd.h"
28
29#if WITH_PROFILE_MODEL_P
30
31#include "profile.h"
32#include "profile-fr500.h"
33
34/* Initialize cycle counting for an insn.
35 FIRST_P is non-zero if this is the first insn in a set of parallel
36 insns. */
37void
38fr500_model_insn_before (SIM_CPU *cpu, int first_p)
39{
40 if (first_p)
41 {
42 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
43 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
44 ps->cur_gr_complex = ps->prev_gr_complex;
45 d->cur_fpop = d->prev_fpop;
46 d->cur_media = d->prev_media;
47 d->cur_cc_complex = d->prev_cc_complex;
48 }
49}
50
51/* Record the cycles computed for an insn.
52 LAST_P is non-zero if this is the last insn in a set of parallel insns,
53 and we update the total cycle count.
54 CYCLES is the cycle count of the insn. */
55void
56fr500_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
57{
58 if (last_p)
59 {
60 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
61 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
62 ps->prev_gr_complex = ps->cur_gr_complex;
63 d->prev_fpop = d->cur_fpop;
64 d->prev_media = d->cur_media;
65 d->prev_cc_complex = d->cur_cc_complex;
66 }
67}
68
69static void
70set_use_is_fpop (SIM_CPU *cpu, INT fr)
71{
72 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
73 fr500_reset_fr_flags (cpu, (fr));
74 d->cur_fpop |= (((DI)1) << (fr));
75}
76
77static void
78set_use_not_fpop (SIM_CPU *cpu, INT fr)
79{
80 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
81 d->cur_fpop &= ~(((DI)1) << (fr));
82}
83
84static int
85use_is_fpop (SIM_CPU *cpu, INT fr)
86{
87 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
88 return d->prev_fpop & (((DI)1) << (fr));
89}
90
91static void
92set_use_is_media ( SIM_CPU *cpu, INT fr)
93{
94 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
95 fr500_reset_fr_flags (cpu, (fr));
96 d->cur_media |= (((DI)1) << (fr));
97}
98
99static void
100set_use_not_media (SIM_CPU *cpu, INT fr)
101{
102 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
103 d->cur_media &= ~(((DI)1) << (fr));
104}
105
106static int
107use_is_media (SIM_CPU *cpu, INT fr)
108{
109 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
110 return d->prev_media & (((DI)1) << (fr));
111}
112
113static void
114set_use_is_cc_complex (SIM_CPU *cpu, INT cc)
115{
116 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
117 fr500_reset_cc_flags (cpu, cc);
118 d->cur_cc_complex |= (((DI)1) << (cc));
119}
120
121static void
122set_use_not_cc_complex (SIM_CPU *cpu, INT cc)
123{
124 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
125 d->cur_cc_complex &= ~(((DI)1) << (cc));
126}
127
128static int
129use_is_cc_complex (SIM_CPU *cpu, INT cc)
130{
131 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
132 return d->prev_cc_complex & (((DI)1) << (cc));
133}
134
135void
136fr500_reset_fr_flags (SIM_CPU *cpu, INT fr)
137{
138 set_use_not_fpop (cpu, fr);
139 set_use_not_media (cpu, fr);
140}
141
142void
143fr500_reset_cc_flags (SIM_CPU *cpu, INT cc)
144{
145 set_use_not_cc_complex (cpu, cc);
146}
147
148/* Latency of floating point registers may be less than recorded when followed
149 by another floating point insn. */
150static void
151adjust_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
152 int cycles)
153{
154 /* If the registers were previously used in a floating point op,
155 then their latency will be less than previously recorded.
156 See Table 13-13 in the LSI. */
157 if (in_FRi >= 0)
158 if (use_is_fpop (cpu, in_FRi))
159 decrease_FR_busy (cpu, in_FRi, cycles);
160 else
161 enforce_full_fr_latency (cpu, in_FRi);
162
163 if (in_FRj >= 0 && in_FRj != in_FRi)
164 if (use_is_fpop (cpu, in_FRj))
165 decrease_FR_busy (cpu, in_FRj, cycles);
166 else
167 enforce_full_fr_latency (cpu, in_FRj);
168
169 if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
170 if (use_is_fpop (cpu, out_FRk))
171 decrease_FR_busy (cpu, out_FRk, cycles);
172 else
173 enforce_full_fr_latency (cpu, out_FRk);
174}
175
176/* Latency of floating point registers may be less than recorded when followed
177 by another floating point insn. */
178static void
179adjust_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
180 int cycles)
181{
182 /* If the registers were previously used in a floating point op,
183 then their latency will be less than previously recorded.
184 See Table 13-13 in the LSI. */
185 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
186 if (in_FRi >= 0) ++in_FRi;
187 if (in_FRj >= 0) ++in_FRj;
188 if (out_FRk >= 0) ++out_FRk;
189 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
190}
191
192/* Latency of floating point registers is less than recorded when followed
193 by another floating point insn. */
194static void
195restore_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
196 int cycles)
197{
198 /* If the registers were previously used in a floating point op,
199 then their latency will be less than previously recorded.
200 See Table 13-13 in the LSI. */
201 if (in_FRi >= 0 && use_is_fpop (cpu, in_FRi))
202 increase_FR_busy (cpu, in_FRi, cycles);
203 if (in_FRj != in_FRi && use_is_fpop (cpu, in_FRj))
204 increase_FR_busy (cpu, in_FRj, cycles);
205 if (out_FRk != in_FRi && out_FRk != in_FRj && use_is_fpop (cpu, out_FRk))
206 increase_FR_busy (cpu, out_FRk, cycles);
207}
208
209/* Latency of floating point registers is less than recorded when followed
210 by another floating point insn. */
211static void
212restore_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
213 int cycles)
214{
215 /* If the registers were previously used in a floating point op,
216 then their latency will be less than previously recorded.
217 See Table 13-13 in the LSI. */
218 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
219 if (in_FRi >= 0) ++in_FRi;
220 if (in_FRj >= 0) ++in_FRj;
221 if (out_FRk >= 0) ++out_FRk;
222 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
223}
224
225int
226frvbf_model_fr500_u_exec (SIM_CPU *cpu, const IDESC *idesc,
227 int unit_num, int referenced)
228{
229 return idesc->timing->units[unit_num].done;
230}
231
232int
233frvbf_model_fr500_u_integer (SIM_CPU *cpu, const IDESC *idesc,
234 int unit_num, int referenced,
235 INT in_GRi, INT in_GRj, INT out_GRk,
236 INT out_ICCi_1)
237{
238 int cycles;
239
240 if (model_insn == FRV_INSN_MODEL_PASS_1)
241 {
242 /* icc0-icc4 are the upper 4 fields of the CCR. */
243 if (out_ICCi_1 >= 0)
244 out_ICCi_1 += 4;
245
246 /* The entire VLIW insn must wait if there is a dependency on a register
247 which is not ready yet.
248 The latency of the registers may be less than previously recorded,
249 depending on how they were used previously.
250 See Table 13-8 in the LSI. */
251 if (in_GRi != out_GRk && in_GRi >= 0)
252 {
253 if (use_is_gr_complex (cpu, in_GRi))
254 decrease_GR_busy (cpu, in_GRi, 1);
255 }
256 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
257 {
258 if (use_is_gr_complex (cpu, in_GRj))
259 decrease_GR_busy (cpu, in_GRj, 1);
260 }
261 vliw_wait_for_GR (cpu, in_GRi);
262 vliw_wait_for_GR (cpu, in_GRj);
263 vliw_wait_for_GR (cpu, out_GRk);
264 vliw_wait_for_CCR (cpu, out_ICCi_1);
265 handle_resource_wait (cpu);
266 load_wait_for_GR (cpu, in_GRi);
267 load_wait_for_GR (cpu, in_GRj);
268 load_wait_for_GR (cpu, out_GRk);
269 trace_vliw_wait_cycles (cpu);
270 return 0;
271 }
272
273 /* GRk is available immediately to the next VLIW insn as is ICCi_1. */
274 cycles = idesc->timing->units[unit_num].done;
275 return cycles;
276}
277
278int
279frvbf_model_fr500_u_imul (SIM_CPU *cpu, const IDESC *idesc,
280 int unit_num, int referenced,
281 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
282{
283 int cycles;
284 /* icc0-icc4 are the upper 4 fields of the CCR. */
285 if (out_ICCi_1 >= 0)
286 out_ICCi_1 += 4;
287
288 if (model_insn == FRV_INSN_MODEL_PASS_1)
289 {
290 /* The entire VLIW insn must wait if there is a dependency on a register
291 which is not ready yet.
292 The latency of the registers may be less than previously recorded,
293 depending on how they were used previously.
294 See Table 13-8 in the LSI. */
295 if (in_GRi != out_GRk && in_GRi >= 0)
296 {
297 if (use_is_gr_complex (cpu, in_GRi))
298 decrease_GR_busy (cpu, in_GRi, 1);
299 }
300 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
301 {
302 if (use_is_gr_complex (cpu, in_GRj))
303 decrease_GR_busy (cpu, in_GRj, 1);
304 }
305 vliw_wait_for_GR (cpu, in_GRi);
306 vliw_wait_for_GR (cpu, in_GRj);
307 vliw_wait_for_GRdouble (cpu, out_GRk);
308 vliw_wait_for_CCR (cpu, out_ICCi_1);
309 handle_resource_wait (cpu);
310 load_wait_for_GR (cpu, in_GRi);
311 load_wait_for_GR (cpu, in_GRj);
312 load_wait_for_GRdouble (cpu, out_GRk);
313 trace_vliw_wait_cycles (cpu);
314 return 0;
315 }
316
317 /* GRk has a latency of 2 cycles. */
318 cycles = idesc->timing->units[unit_num].done;
319 update_GRdouble_latency (cpu, out_GRk, cycles + 2);
320 set_use_is_gr_complex (cpu, out_GRk);
321 set_use_is_gr_complex (cpu, out_GRk + 1);
322
323 /* ICCi_1 has a latency of 1 cycle. */
324 update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
325
326 return cycles;
327}
328
329int
330frvbf_model_fr500_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
331 int unit_num, int referenced,
332 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
333{
334 int cycles;
335 FRV_VLIW *vliw;
336 int slot;
337
338 /* icc0-icc4 are the upper 4 fields of the CCR. */
339 if (out_ICCi_1 >= 0)
340 out_ICCi_1 += 4;
341
342 vliw = CPU_VLIW (cpu);
343 slot = vliw->next_slot - 1;
344 slot = (*vliw->current_vliw)[slot] - UNIT_I0;
345
346 if (model_insn == FRV_INSN_MODEL_PASS_1)
347 {
348 /* The entire VLIW insn must wait if there is a dependency on a register
349 which is not ready yet.
350 The latency of the registers may be less than previously recorded,
351 depending on how they were used previously.
352 See Table 13-8 in the LSI. */
353 if (in_GRi != out_GRk && in_GRi >= 0)
354 {
355 if (use_is_gr_complex (cpu, in_GRi))
356 decrease_GR_busy (cpu, in_GRi, 1);
357 }
358 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
359 {
360 if (use_is_gr_complex (cpu, in_GRj))
361 decrease_GR_busy (cpu, in_GRj, 1);
362 }
363 vliw_wait_for_GR (cpu, in_GRi);
364 vliw_wait_for_GR (cpu, in_GRj);
365 vliw_wait_for_GR (cpu, out_GRk);
366 vliw_wait_for_CCR (cpu, out_ICCi_1);
367 vliw_wait_for_idiv_resource (cpu, slot);
368 handle_resource_wait (cpu);
369 load_wait_for_GR (cpu, in_GRi);
370 load_wait_for_GR (cpu, in_GRj);
371 load_wait_for_GR (cpu, out_GRk);
372 trace_vliw_wait_cycles (cpu);
373 return 0;
374 }
375
376 /* GRk has a latency of 19 cycles! */
377 cycles = idesc->timing->units[unit_num].done;
378 update_GR_latency (cpu, out_GRk, cycles + 19);
379 set_use_is_gr_complex (cpu, out_GRk);
380
381 /* ICCi_1 has a latency of 19 cycles. */
382 update_CCR_latency (cpu, out_ICCi_1, cycles + 19);
383 set_use_is_cc_complex (cpu, out_ICCi_1);
384
153431d6
DB		 385 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
386 {
387 /* GNER has a latency of 18 cycles. */
388 update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 18);
389 }
390
b34f6357
DB		 391 /* the idiv resource has a latency of 18 cycles! */
392 update_idiv_resource_latency (cpu, slot, cycles + 18);
393
394 return cycles;
395}
396
397int
398frvbf_model_fr500_u_branch (SIM_CPU *cpu, const IDESC *idesc,
399 int unit_num, int referenced,
400 INT in_GRi, INT in_GRj,
401 INT in_ICCi_2, INT in_FCCi_2)
402{
403 int cycles;
404 FRV_PROFILE_STATE *ps;
405
406 if (model_insn == FRV_INSN_MODEL_PASS_1)
407 {
408 /* icc0-icc4 are the upper 4 fields of the CCR. */
409 if (in_ICCi_2 >= 0)
410 in_ICCi_2 += 4;
411
412 /* The entire VLIW insn must wait if there is a dependency on a register
413 which is not ready yet.
414 The latency of the registers may be less than previously recorded,
415 depending on how they were used previously.
416 See Table 13-8 in the LSI. */
417 if (in_GRi >= 0)
418 {
419 if (use_is_gr_complex (cpu, in_GRi))
420 decrease_GR_busy (cpu, in_GRi, 1);
421 }
422 if (in_GRj != in_GRi && in_GRj >= 0)
423 {
424 if (use_is_gr_complex (cpu, in_GRj))
425 decrease_GR_busy (cpu, in_GRj, 1);
426 }
427 vliw_wait_for_GR (cpu, in_GRi);
428 vliw_wait_for_GR (cpu, in_GRj);
429 vliw_wait_for_CCR (cpu, in_ICCi_2);
430 vliw_wait_for_CCR (cpu, in_FCCi_2);
431 handle_resource_wait (cpu);
432 load_wait_for_GR (cpu, in_GRi);
433 load_wait_for_GR (cpu, in_GRj);
434 trace_vliw_wait_cycles (cpu);
435 return 0;
436 }
437
438 /* When counting branches taken or not taken, don't consider branches after
439 the first taken branch in a vliw insn. */
440 ps = CPU_PROFILE_STATE (cpu);
441 if (! ps->vliw_branch_taken)
442 {
443 /* (1 << 4): The pc is the 5th element in inputs, outputs.
444 ??? can be cleaned up */
445 PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
446 int taken = (referenced & (1 << 4)) != 0;
447 if (taken)
448 {
449 ++PROFILE_MODEL_TAKEN_COUNT (p);
450 ps->vliw_branch_taken = 1;
451 }
452 else
453 ++PROFILE_MODEL_UNTAKEN_COUNT (p);
454 }
455
456 cycles = idesc->timing->units[unit_num].done;
457 return cycles;
458}
459
460int
461frvbf_model_fr500_u_trap (SIM_CPU *cpu, const IDESC *idesc,
462 int unit_num, int referenced,
463 INT in_GRi, INT in_GRj,
464 INT in_ICCi_2, INT in_FCCi_2)
465{
466 int cycles;
b34f6357
DB		 467
468 if (model_insn == FRV_INSN_MODEL_PASS_1)
469 {
470 /* icc0-icc4 are the upper 4 fields of the CCR. */
471 if (in_ICCi_2 >= 0)
472 in_ICCi_2 += 4;
473
474 /* The entire VLIW insn must wait if there is a dependency on a register
475 which is not ready yet.
476 The latency of the registers may be less than previously recorded,
477 depending on how they were used previously.
478 See Table 13-8 in the LSI. */
479 if (in_GRi >= 0)
480 {
481 if (use_is_gr_complex (cpu, in_GRi))
482 decrease_GR_busy (cpu, in_GRi, 1);
483 }
484 if (in_GRj != in_GRi && in_GRj >= 0)
485 {
486 if (use_is_gr_complex (cpu, in_GRj))
487 decrease_GR_busy (cpu, in_GRj, 1);
488 }
489 vliw_wait_for_GR (cpu, in_GRi);
490 vliw_wait_for_GR (cpu, in_GRj);
491 vliw_wait_for_CCR (cpu, in_ICCi_2);
492 vliw_wait_for_CCR (cpu, in_FCCi_2);
493 handle_resource_wait (cpu);
494 load_wait_for_GR (cpu, in_GRi);
495 load_wait_for_GR (cpu, in_GRj);
496 trace_vliw_wait_cycles (cpu);
497 return 0;
498 }
499
500 cycles = idesc->timing->units[unit_num].done;
501 return cycles;
502}
503
504int
505frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc,
506 int unit_num, int referenced,
507 INT in_ICCi_3, INT in_FCCi_3)
508{
509 int cycles;
b34f6357
DB		 510
511 if (model_insn == FRV_INSN_MODEL_PASS_1)
512 {
513 /* icc0-icc4 are the upper 4 fields of the CCR. */
514 if (in_ICCi_3 >= 0)
515 in_ICCi_3 += 4;
516
517 /* The entire VLIW insn must wait if there is a dependency on a register
518 which is not ready yet. */
519 vliw_wait_for_CCR (cpu, in_ICCi_3);
520 vliw_wait_for_CCR (cpu, in_FCCi_3);
521 handle_resource_wait (cpu);
522 trace_vliw_wait_cycles (cpu);
523 return 0;
524 }
525
526 cycles = idesc->timing->units[unit_num].done;
527 return cycles;
528}
529
153431d6
DB		 530int
531frvbf_model_fr500_u_clrgr (SIM_CPU *cpu, const IDESC *idesc,
532 int unit_num, int referenced,
533 INT in_GRk)
534{
535 int cycles;
536
537 if (model_insn == FRV_INSN_MODEL_PASS_1)
538 {
539 /* Wait for both GNER registers or just the one specified. */
540 if (in_GRk == -1)
541 {
542 vliw_wait_for_SPR (cpu, H_SPR_GNER0);
543 vliw_wait_for_SPR (cpu, H_SPR_GNER1);
544 }
545 else
546 vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk));
547 handle_resource_wait (cpu);
548 trace_vliw_wait_cycles (cpu);
549 return 0;
550 }
551
552 cycles = idesc->timing->units[unit_num].done;
553 return cycles;
554}
555
556int
557frvbf_model_fr500_u_clrfr (SIM_CPU *cpu, const IDESC *idesc,
558 int unit_num, int referenced,
559 INT in_FRk)
560{
561 int cycles;
562
563 if (model_insn == FRV_INSN_MODEL_PASS_1)
564 {
565 /* Wait for both GNER registers or just the one specified. */
566 if (in_FRk == -1)
567 {
568 vliw_wait_for_SPR (cpu, H_SPR_FNER0);
569 vliw_wait_for_SPR (cpu, H_SPR_FNER1);
570 }
571 else
572 vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk));
573 handle_resource_wait (cpu);
574 trace_vliw_wait_cycles (cpu);
575 return 0;
576 }
577
578 cycles = idesc->timing->units[unit_num].done;
579 return cycles;
580}
581
1c453cd6
DB		 582int
583frvbf_model_fr500_u_commit (SIM_CPU *cpu, const IDESC *idesc,
584 int unit_num, int referenced,
585 INT in_GRk, INT in_FRk)
586{
587 int cycles;
588
589 if (model_insn == FRV_INSN_MODEL_PASS_1)
590 {
591 /* If GR is specified, then FR is not and vice-versa. If neither is
592 then it's a commitga or commitfa. Check the insn attribute to
593 figure out which. */
594 if (in_GRk != -1)
595 vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk));
596 else if (in_FRk != -1)
597 vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk));
598 else if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_FR_ACCESS))
599 {
600 vliw_wait_for_SPR (cpu, H_SPR_FNER0);
601 vliw_wait_for_SPR (cpu, H_SPR_FNER1);
602 }
603 else
604 {
605 vliw_wait_for_SPR (cpu, H_SPR_GNER0);
606 vliw_wait_for_SPR (cpu, H_SPR_GNER1);
607 }
608 handle_resource_wait (cpu);
609 trace_vliw_wait_cycles (cpu);
610 return 0;
611 }
612
613 cycles = idesc->timing->units[unit_num].done;
614 return cycles;
615}
616
b34f6357
DB		 617int
618frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
619 int unit_num, int referenced,
620 INT out_GRkhi, INT out_GRklo)
621{
622 int cycles;
623
624 if (model_insn == FRV_INSN_MODEL_PASS_1)
625 {
626 /* The entire VLIW insn must wait if there is a dependency on a GR
627 which is not ready yet. */
628 vliw_wait_for_GR (cpu, out_GRkhi);
629 vliw_wait_for_GR (cpu, out_GRklo);
630 handle_resource_wait (cpu);
631 load_wait_for_GR (cpu, out_GRkhi);
632 load_wait_for_GR (cpu, out_GRklo);
633 trace_vliw_wait_cycles (cpu);
634 return 0;
635 }
636
637 /* GRk is available immediately to the next VLIW insn. */
638 cycles = idesc->timing->units[unit_num].done;
639
640 set_use_not_gr_complex (cpu, out_GRkhi);
641 set_use_not_gr_complex (cpu, out_GRklo);
642
643 return cycles;
644}
645
646int
647frvbf_model_fr500_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
648 int unit_num, int referenced,
649 INT in_GRi, INT in_GRj,
650 INT out_GRk, INT out_GRdoublek)
651{
652 int cycles;
653
654 if (model_insn == FRV_INSN_MODEL_PASS_1)
655 {
656 /* The entire VLIW insn must wait if there is a dependency on a register
657 which is not ready yet.
658 The latency of the registers may be less than previously recorded,
659 depending on how they were used previously.
660 See Table 13-8 in the LSI. */
661 if (in_GRi != out_GRk && in_GRi != out_GRdoublek
662 && in_GRi != out_GRdoublek + 1 && in_GRi >= 0)
663 {
664 if (use_is_gr_complex (cpu, in_GRi))
665 decrease_GR_busy (cpu, in_GRi, 1);
666 }
667 if (in_GRj != in_GRi && in_GRj != out_GRk && in_GRj != out_GRdoublek
668 && in_GRj != out_GRdoublek + 1 && in_GRj >= 0)
669
670 {
671 if (use_is_gr_complex (cpu, in_GRj))
672 decrease_GR_busy (cpu, in_GRj, 1);
673 }
674 vliw_wait_for_GR (cpu, in_GRi);
675 vliw_wait_for_GR (cpu, in_GRj);
676 vliw_wait_for_GR (cpu, out_GRk);
677 vliw_wait_for_GRdouble (cpu, out_GRdoublek);
678 handle_resource_wait (cpu);
679 load_wait_for_GR (cpu, in_GRi);
680 load_wait_for_GR (cpu, in_GRj);
681 load_wait_for_GR (cpu, out_GRk);
682 load_wait_for_GRdouble (cpu, out_GRdoublek);
683 trace_vliw_wait_cycles (cpu);
684 return 0;
685 }
686
687 cycles = idesc->timing->units[unit_num].done;
688
689 /* The latency of GRk for a load will depend on how long it takes to retrieve
690 the the data from the cache or memory. */
691 update_GR_latency_for_load (cpu, out_GRk, cycles);
692 update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
693
1c453cd6
DB		 694 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
695 {
696 /* GNER has a latency of 2 cycles. */
697 update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2);
698 update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2);
699 }
700
701 if (out_GRk >= 0)
702 set_use_is_gr_complex (cpu, out_GRk);
703 if (out_GRdoublek != -1)
704 {
705 set_use_is_gr_complex (cpu, out_GRdoublek);
706 set_use_is_gr_complex (cpu, out_GRdoublek + 1);
707 }
b34f6357
DB		 708
709 return cycles;
710}
711
712int
713frvbf_model_fr500_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
714 int unit_num, int referenced,
715 INT in_GRi, INT in_GRj,
716 INT in_GRk, INT in_GRdoublek)
717{
718 int cycles;
719
720 if (model_insn == FRV_INSN_MODEL_PASS_1)
721 {
722 /* The entire VLIW insn must wait if there is a dependency on a register
723 which is not ready yet.
724 The latency of the registers may be less than previously recorded,
725 depending on how they were used previously.
726 See Table 13-8 in the LSI. */
727 if (in_GRi >= 0)
728 {
729 if (use_is_gr_complex (cpu, in_GRi))
730 decrease_GR_busy (cpu, in_GRi, 1);
731 }
732 if (in_GRj != in_GRi && in_GRj >= 0)
733 {
734 if (use_is_gr_complex (cpu, in_GRj))
735 decrease_GR_busy (cpu, in_GRj, 1);
736 }
737 if (in_GRk != in_GRi && in_GRk != in_GRj && in_GRk >= 0)
738 {
739 if (use_is_gr_complex (cpu, in_GRk))
740 decrease_GR_busy (cpu, in_GRk, 1);
741 }
742 if (in_GRdoublek != in_GRi && in_GRdoublek != in_GRj
743 && in_GRdoublek + 1 != in_GRi && in_GRdoublek + 1 != in_GRj
744 && in_GRdoublek >= 0)
745 {
746 if (use_is_gr_complex (cpu, in_GRdoublek))
747 decrease_GR_busy (cpu, in_GRdoublek, 1);
748 if (use_is_gr_complex (cpu, in_GRdoublek + 1))
749 decrease_GR_busy (cpu, in_GRdoublek + 1, 1);
750 }
751 vliw_wait_for_GR (cpu, in_GRi);
752 vliw_wait_for_GR (cpu, in_GRj);
753 vliw_wait_for_GR (cpu, in_GRk);
754 vliw_wait_for_GRdouble (cpu, in_GRdoublek);
755 handle_resource_wait (cpu);
756 load_wait_for_GR (cpu, in_GRi);
757 load_wait_for_GR (cpu, in_GRj);
758 load_wait_for_GR (cpu, in_GRk);
759 load_wait_for_GRdouble (cpu, in_GRdoublek);
760 trace_vliw_wait_cycles (cpu);
761 return 0;
762 }
763
764 cycles = idesc->timing->units[unit_num].done;
765
766 return cycles;
767}
768
769int
770frvbf_model_fr500_u_gr_r_store (SIM_CPU *cpu, const IDESC *idesc,
771 int unit_num, int referenced,
772 INT in_GRi, INT in_GRj,
773 INT in_GRk, INT in_GRdoublek)
774{
775 int cycles = frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
776 in_GRi, in_GRj, in_GRk,
777 in_GRdoublek);
778
779 if (model_insn == FRV_INSN_MODEL_PASS_2)
780 {
781 if (CPU_RSTR_INVALIDATE(cpu))
782 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
783 }
784
785 return cycles;
786}
787
788int
789frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
790 int unit_num, int referenced,
791 INT in_GRi, INT in_GRj,
792 INT out_FRk, INT out_FRdoublek)
793{
794 int cycles;
795
796 if (model_insn == FRV_INSN_MODEL_PASS_1)
797 {
798 /* The entire VLIW insn must wait if there is a dependency on a register
799 which is not ready yet.
800 The latency of the registers may be less than previously recorded,
801 depending on how they were used previously.
802 See Table 13-8 in the LSI. */
803 if (in_GRi >= 0)
804 {
805 if (use_is_gr_complex (cpu, in_GRi))
806 decrease_GR_busy (cpu, in_GRi, 1);
807 }
808 if (in_GRj != in_GRi && in_GRj >= 0)
809 {
810 if (use_is_gr_complex (cpu, in_GRj))
811 decrease_GR_busy (cpu, in_GRj, 1);
812 }
813 if (out_FRk >= 0)
814 {
815 if (use_is_media (cpu, out_FRk))
816 decrease_FR_busy (cpu, out_FRk, 1);
817 else
818 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
819 }
820 if (out_FRdoublek >= 0)
821 {
822 if (use_is_media (cpu, out_FRdoublek))
823 decrease_FR_busy (cpu, out_FRdoublek, 1);
824 else
825 adjust_float_register_busy (cpu, -1, -1, out_FRdoublek, 1);
826 if (use_is_media (cpu, out_FRdoublek + 1))
827 decrease_FR_busy (cpu, out_FRdoublek + 1, 1);
828 else
829 adjust_float_register_busy (cpu, -1, -1, out_FRdoublek + 1, 1);
830 }
831 vliw_wait_for_GR (cpu, in_GRi);
832 vliw_wait_for_GR (cpu, in_GRj);
833 vliw_wait_for_FR (cpu, out_FRk);
834 vliw_wait_for_FRdouble (cpu, out_FRdoublek);
1c453cd6
DB		 835 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
836 {
837 vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
838 vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
839 }
b34f6357
DB		 840 handle_resource_wait (cpu);
841 load_wait_for_GR (cpu, in_GRi);
842 load_wait_for_GR (cpu, in_GRj);
843 load_wait_for_FR (cpu, out_FRk);
844 load_wait_for_FRdouble (cpu, out_FRdoublek);
845 trace_vliw_wait_cycles (cpu);
846 return 0;
847 }
848
849 cycles = idesc->timing->units[unit_num].done;
850
851 /* The latency of FRk for a load will depend on how long it takes to retrieve
852 the the data from the cache or memory. */
853 update_FR_latency_for_load (cpu, out_FRk, cycles);
854 update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles);
855
1c453cd6
DB		 856 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
857 {
858 /* FNER has a latency of 3 cycles. */
859 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), cycles + 3);
860 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), cycles + 3);
861 }
862
b34f6357
DB		 863 fr500_reset_fr_flags (cpu, out_FRk);
864
865 return cycles;
866}
867
868int
869frvbf_model_fr500_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
870 int unit_num, int referenced,
871 INT in_GRi, INT in_GRj,
872 INT in_FRk, INT in_FRdoublek)
873{
874 int cycles;
875
876 if (model_insn == FRV_INSN_MODEL_PASS_1)
877 {
878 /* The entire VLIW insn must wait if there is a dependency on a register
879 which is not ready yet.
880 The latency of the registers may be less than previously recorded,
881 depending on how they were used previously.
882 See Table 13-8 in the LSI. */
883 if (in_GRi >= 0)
884 {
885 if (use_is_gr_complex (cpu, in_GRi))
886 decrease_GR_busy (cpu, in_GRi, 1);
887 }
888 if (in_GRj != in_GRi && in_GRj >= 0)
889 {
890 if (use_is_gr_complex (cpu, in_GRj))
891 decrease_GR_busy (cpu, in_GRj, 1);
892 }
893 if (in_FRk >= 0)
894 {
895 if (use_is_media (cpu, in_FRk))
896 decrease_FR_busy (cpu, in_FRk, 1);
897 else
898 adjust_float_register_busy (cpu, -1, -1, in_FRk, 1);
899 }
900 if (in_FRdoublek >= 0)
901 {
902 if (use_is_media (cpu, in_FRdoublek))
903 decrease_FR_busy (cpu, in_FRdoublek, 1);
904 else
905 adjust_float_register_busy (cpu, -1, -1, in_FRdoublek, 1);
906 if (use_is_media (cpu, in_FRdoublek + 1))
907 decrease_FR_busy (cpu, in_FRdoublek + 1, 1);
908 else
909 adjust_float_register_busy (cpu, -1, -1, in_FRdoublek + 1, 1);
910 }
911 vliw_wait_for_GR (cpu, in_GRi);
912 vliw_wait_for_GR (cpu, in_GRj);
913 vliw_wait_for_FR (cpu, in_FRk);
914 vliw_wait_for_FRdouble (cpu, in_FRdoublek);
915 handle_resource_wait (cpu);
916 load_wait_for_GR (cpu, in_GRi);
917 load_wait_for_GR (cpu, in_GRj);
918 load_wait_for_FR (cpu, in_FRk);
919 load_wait_for_FRdouble (cpu, in_FRdoublek);
920 trace_vliw_wait_cycles (cpu);
921 return 0;
922 }
923
924 cycles = idesc->timing->units[unit_num].done;
925
926 return cycles;
927}
928
929int
930frvbf_model_fr500_u_fr_r_store (SIM_CPU *cpu, const IDESC *idesc,
931 int unit_num, int referenced,
932 INT in_GRi, INT in_GRj,
933 INT in_FRk, INT in_FRdoublek)
934{
935 int cycles = frvbf_model_fr500_u_fr_store (cpu, idesc, unit_num, referenced,
936 in_GRi, in_GRj, in_FRk,
937 in_FRdoublek);
938
939 if (model_insn == FRV_INSN_MODEL_PASS_2)
940 {
941 if (CPU_RSTR_INVALIDATE(cpu))
942 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
943 }
944
945 return cycles;
946}
947
948int
949frvbf_model_fr500_u_swap (SIM_CPU *cpu, const IDESC *idesc,
950 int unit_num, int referenced,
951 INT in_GRi, INT in_GRj, INT out_GRk)
952{
953 int cycles;
954
955 if (model_insn == FRV_INSN_MODEL_PASS_1)
956 {
957 /* The entire VLIW insn must wait if there is a dependency on a register
958 which is not ready yet.
959 The latency of the registers may be less than previously recorded,
960 depending on how they were used previously.
961 See Table 13-8 in the LSI. */
962 if (in_GRi != out_GRk && in_GRi >= 0)
963 {
964 if (use_is_gr_complex (cpu, in_GRi))
965 decrease_GR_busy (cpu, in_GRi, 1);
966 }
967 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
968 {
969 if (use_is_gr_complex (cpu, in_GRj))
970 decrease_GR_busy (cpu, in_GRj, 1);
971 }
972 vliw_wait_for_GR (cpu, in_GRi);
973 vliw_wait_for_GR (cpu, in_GRj);
974 vliw_wait_for_GR (cpu, out_GRk);
975 handle_resource_wait (cpu);
976 load_wait_for_GR (cpu, in_GRi);
977 load_wait_for_GR (cpu, in_GRj);
978 load_wait_for_GR (cpu, out_GRk);
979 trace_vliw_wait_cycles (cpu);
980 return 0;
981 }
982
983 cycles = idesc->timing->units[unit_num].done;
984
985 /* The latency of GRk will depend on how long it takes to swap
986 the the data from the cache or memory. */
987 update_GR_latency_for_swap (cpu, out_GRk, cycles);
988 set_use_is_gr_complex (cpu, out_GRk);
989
990 return cycles;
991}
992
993int
994frvbf_model_fr500_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc,
995 int unit_num, int referenced,
996 INT in_FRj, INT out_FRk)
997{
998 int cycles;
999
1000 if (model_insn == FRV_INSN_MODEL_PASS_1)
1001 {
1002 /* The entire VLIW insn must wait if there is a dependency on a register
1003 which is not ready yet. */
1004 if (in_FRj >= 0)
1005 {
1006 if (use_is_media (cpu, in_FRj))
1007 decrease_FR_busy (cpu, in_FRj, 1);
1008 else
1009 adjust_float_register_busy (cpu, -1, in_FRj, -1, 1);
1010 }
1011 if (out_FRk >= 0 && out_FRk != in_FRj)
1012 {
1013 if (use_is_media (cpu, out_FRk))
1014 decrease_FR_busy (cpu, out_FRk, 1);
1015 else
1016 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
1017 }
1018 vliw_wait_for_FR (cpu, in_FRj);
1019 vliw_wait_for_FR (cpu, out_FRk);
1020 handle_resource_wait (cpu);
1021 load_wait_for_FR (cpu, in_FRj);
1022 load_wait_for_FR (cpu, out_FRk);
1023 trace_vliw_wait_cycles (cpu);
1024 return 0;
1025 }
1026
1027 /* The latency of FRj is 3 cycles. */
1028 cycles = idesc->timing->units[unit_num].done;
1029 update_FR_latency (cpu, out_FRk, cycles + 3);
1030
1031 return cycles;
1032}
1033
1034int
1035frvbf_model_fr500_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
1036 int unit_num, int referenced,
1037 INT in_FRk, INT out_GRj)
1038{
1039 int cycles;
1040
1041 if (model_insn == FRV_INSN_MODEL_PASS_1)
1042 {
1043 /* The entire VLIW insn must wait if there is a dependency on a register
1044 which is not ready yet. */
1045 if (in_FRk >= 0)
1046 {
1047 if (use_is_media (cpu, in_FRk))
1048 decrease_FR_busy (cpu, in_FRk, 1);
1049 else
1050 adjust_float_register_busy (cpu, -1, in_FRk, -1, 1);
1051 }
1052 vliw_wait_for_FR (cpu, in_FRk);
1053 vliw_wait_for_GR (cpu, out_GRj);
1054 handle_resource_wait (cpu);
1055 load_wait_for_FR (cpu, in_FRk);
1056 load_wait_for_GR (cpu, out_GRj);
1057 trace_vliw_wait_cycles (cpu);
1058 return 0;
1059 }
1060
1061 /* The latency of GRj is 2 cycles. */
1062 cycles = idesc->timing->units[unit_num].done;
1063 update_GR_latency (cpu, out_GRj, cycles + 2);
1064 set_use_is_gr_complex (cpu, out_GRj);
1065
1066 return cycles;
1067}
1068
1069int
1070frvbf_model_fr500_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
1071 int unit_num, int referenced,
1072 INT in_spr, INT out_GRj)
1073{
1074 int cycles;
1075
1076 if (model_insn == FRV_INSN_MODEL_PASS_1)
1077 {
1078 /* The entire VLIW insn must wait if there is a dependency on a register
153431d6
DB		 1079 which is not ready yet. */
1080 vliw_wait_for_SPR (cpu, in_spr);
b34f6357
DB		 1081 vliw_wait_for_GR (cpu, out_GRj);
1082 handle_resource_wait (cpu);
1083 load_wait_for_GR (cpu, out_GRj);
1084 trace_vliw_wait_cycles (cpu);
1085 return 0;
1086 }
1087
1088 cycles = idesc->timing->units[unit_num].done;
1089
1090#if 0 /* no latency? */
1091 /* The latency of GRj is 2 cycles. */
1092 update_GR_latency (cpu, out_GRj, cycles + 2);
1093#endif
1094
1095 return cycles;
1096}
1097
1098int
1099frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
1100 int unit_num, int referenced,
1101 INT in_GRj, INT out_FRk)
1102{
1103 int cycles;
1104
1105 if (model_insn == FRV_INSN_MODEL_PASS_1)
1106 {
1107 /* The entire VLIW insn must wait if there is a dependency on a register
1108 which is not ready yet.
1109 The latency of the registers may be less than previously recorded,
1110 depending on how they were used previously.
1111 See Table 13-8 in the LSI. */
1112 if (in_GRj >= 0)
1113 {
1114 if (use_is_gr_complex (cpu, in_GRj))
1115 decrease_GR_busy (cpu, in_GRj, 1);
1116 }
1117 if (out_FRk >= 0)
1118 {
1119 if (use_is_media (cpu, out_FRk))
1120 decrease_FR_busy (cpu, out_FRk, 1);
1121 else
1c453cd6 1122 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
b34f6357
DB		 1123 }
1124 vliw_wait_for_GR (cpu, in_GRj);
1125 vliw_wait_for_FR (cpu, out_FRk);
1126 handle_resource_wait (cpu);
1127 load_wait_for_GR (cpu, in_GRj);
1128 load_wait_for_FR (cpu, out_FRk);
1129 trace_vliw_wait_cycles (cpu);
1130 return 0;
1131 }
1132
1133 /* The latency of FRk is 2 cycles. */
1134 cycles = idesc->timing->units[unit_num].done;
1135 update_FR_latency (cpu, out_FRk, cycles + 2);
1136
1137 /* Mark this use of the register as NOT a floating point op. */
1138 fr500_reset_fr_flags (cpu, out_FRk);
1139
1140 return cycles;
1141}
1142
1143int
1144frvbf_model_fr500_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
1145 int unit_num, int referenced,
1146 INT in_GRj, INT out_spr)
1147{
1148 int cycles;
1149
1150 if (model_insn == FRV_INSN_MODEL_PASS_1)
1151 {
1152 /* The entire VLIW insn must wait if there is a dependency on a register
1153 which is not ready yet.
1154 The latency of the registers may be less than previously recorded,
1155 depending on how they were used previously.
1156 See Table 13-8 in the LSI. */
1157 if (in_GRj >= 0)
1158 {
1159 if (use_is_gr_complex (cpu, in_GRj))
1160 decrease_GR_busy (cpu, in_GRj, 1);
1161 }
1162 vliw_wait_for_GR (cpu, in_GRj);
153431d6 1163 vliw_wait_for_SPR (cpu, out_spr);
b34f6357
DB		 1164 handle_resource_wait (cpu);
1165 load_wait_for_GR (cpu, in_GRj);
1166 trace_vliw_wait_cycles (cpu);
1167 return 0;
1168 }
1169
1170 cycles = idesc->timing->units[unit_num].done;
1171
1172#if 0
1173 /* The latency of spr is ? cycles. */
1174 update_SPR_latency (cpu, out_spr, cycles + ?);
1175#endif
1176
1177 return cycles;
1178}
1179
1180int
1181frvbf_model_fr500_u_ici (SIM_CPU *cpu, const IDESC *idesc,
1182 int unit_num, int referenced,
1183 INT in_GRi, INT in_GRj)
1184{
1185 int cycles;
1186
1187 if (model_insn == FRV_INSN_MODEL_PASS_1)
1188 {
1189 /* The entire VLIW insn must wait if there is a dependency on a register
1190 which is not ready yet.
1191 The latency of the registers may be less than previously recorded,
1192 depending on how they were used previously.
1193 See Table 13-8 in the LSI. */
1194 if (in_GRi >= 0)
1195 {
1196 if (use_is_gr_complex (cpu, in_GRi))
1197 decrease_GR_busy (cpu, in_GRi, 1);
1198 }
1199 if (in_GRj != in_GRi && in_GRj >= 0)
1200 {
1201 if (use_is_gr_complex (cpu, in_GRj))
1202 decrease_GR_busy (cpu, in_GRj, 1);
1203 }
1204 vliw_wait_for_GR (cpu, in_GRi);
1205 vliw_wait_for_GR (cpu, in_GRj);
1206 handle_resource_wait (cpu);
1207 load_wait_for_GR (cpu, in_GRi);
1208 load_wait_for_GR (cpu, in_GRj);
1209 trace_vliw_wait_cycles (cpu);
1210 return 0;
1211 }
1212
1213 cycles = idesc->timing->units[unit_num].done;
1214 request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles);
1215 return cycles;
1216}
1217
1218int
1219frvbf_model_fr500_u_dci (SIM_CPU *cpu, const IDESC *idesc,
1220 int unit_num, int referenced,
1221 INT in_GRi, INT in_GRj)
1222{
1223 int cycles;
1224
1225 if (model_insn == FRV_INSN_MODEL_PASS_1)
1226 {
1227 /* The entire VLIW insn must wait if there is a dependency on a register
1228 which is not ready yet.
1229 The latency of the registers may be less than previously recorded,
1230 depending on how they were used previously.
1231 See Table 13-8 in the LSI. */
1232 if (in_GRi >= 0)
1233 {
1234 if (use_is_gr_complex (cpu, in_GRi))
1235 decrease_GR_busy (cpu, in_GRi, 1);
1236 }
1237 if (in_GRj != in_GRi && in_GRj >= 0)
1238 {
1239 if (use_is_gr_complex (cpu, in_GRj))
1240 decrease_GR_busy (cpu, in_GRj, 1);
1241 }
1242 vliw_wait_for_GR (cpu, in_GRi);
1243 vliw_wait_for_GR (cpu, in_GRj);
1244 handle_resource_wait (cpu);
1245 load_wait_for_GR (cpu, in_GRi);
1246 load_wait_for_GR (cpu, in_GRj);
1247 trace_vliw_wait_cycles (cpu);
1248 return 0;
1249 }
1250
1251 cycles = idesc->timing->units[unit_num].done;
1252 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
1253 return cycles;
1254}
1255
1256int
1257frvbf_model_fr500_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
1258 int unit_num, int referenced,
1259 INT in_GRi, INT in_GRj)
1260{
1261 int cycles;
1262
1263 if (model_insn == FRV_INSN_MODEL_PASS_1)
1264 {
1265 /* The entire VLIW insn must wait if there is a dependency on a register
1266 which is not ready yet.
1267 The latency of the registers may be less than previously recorded,
1268 depending on how they were used previously.
1269 See Table 13-8 in the LSI. */
1270 if (in_GRi >= 0)
1271 {
1272 if (use_is_gr_complex (cpu, in_GRi))
1273 decrease_GR_busy (cpu, in_GRi, 1);
1274 }
1275 if (in_GRj != in_GRi && in_GRj >= 0)
1276 {
1277 if (use_is_gr_complex (cpu, in_GRj))
1278 decrease_GR_busy (cpu, in_GRj, 1);
1279 }
1280 vliw_wait_for_GR (cpu, in_GRi);
1281 vliw_wait_for_GR (cpu, in_GRj);
1282 handle_resource_wait (cpu);
1283 load_wait_for_GR (cpu, in_GRi);
1284 load_wait_for_GR (cpu, in_GRj);
1285 trace_vliw_wait_cycles (cpu);
1286 return 0;
1287 }
1288
1289 cycles = idesc->timing->units[unit_num].done;
1290 request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles);
1291 return cycles;
1292}
1293
1294int
1295frvbf_model_fr500_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
1296 int unit_num, int referenced,
1297 INT in_GRi, INT in_GRj)
1298{
1299 int cycles;
1300
1301 if (model_insn == FRV_INSN_MODEL_PASS_1)
1302 {
1303 /* The entire VLIW insn must wait if there is a dependency on a register
1304 which is not ready yet.
1305 The latency of the registers may be less than previously recorded,
1306 depending on how they were used previously.
1307 See Table 13-8 in the LSI. */
1308 if (in_GRi >= 0)
1309 {
1310 if (use_is_gr_complex (cpu, in_GRi))
1311 decrease_GR_busy (cpu, in_GRi, 1);
1312 }
1313 if (in_GRj != in_GRi && in_GRj >= 0)
1314 {
1315 if (use_is_gr_complex (cpu, in_GRj))
1316 decrease_GR_busy (cpu, in_GRj, 1);
1317 }
1318 vliw_wait_for_GR (cpu, in_GRi);
1319 vliw_wait_for_GR (cpu, in_GRj);
1320 handle_resource_wait (cpu);
1321 load_wait_for_GR (cpu, in_GRi);
1322 load_wait_for_GR (cpu, in_GRj);
1323 trace_vliw_wait_cycles (cpu);
1324 return 0;
1325 }
1326
1327 cycles = idesc->timing->units[unit_num].done;
1328 request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles);
1329 return cycles;
1330}
1331
1332int
1333frvbf_model_fr500_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
1334 int unit_num, int referenced,
1335 INT in_GRi, INT in_GRj)
1336{
1337 int cycles;
1338
1339 if (model_insn == FRV_INSN_MODEL_PASS_1)
1340 {
1341 /* The entire VLIW insn must wait if there is a dependency on a register
1342 which is not ready yet.
1343 The latency of the registers may be less than previously recorded,
1344 depending on how they were used previously.
1345 See Table 13-8 in the LSI. */
1346 if (in_GRi >= 0)
1347 {
1348 if (use_is_gr_complex (cpu, in_GRi))
1349 decrease_GR_busy (cpu, in_GRi, 1);
1350 }
1351 if (in_GRj != in_GRi && in_GRj >= 0)
1352 {
1353 if (use_is_gr_complex (cpu, in_GRj))
1354 decrease_GR_busy (cpu, in_GRj, 1);
1355 }
1356 vliw_wait_for_GR (cpu, in_GRi);
1357 vliw_wait_for_GR (cpu, in_GRj);
1358 handle_resource_wait (cpu);
1359 load_wait_for_GR (cpu, in_GRi);
1360 load_wait_for_GR (cpu, in_GRj);
1361 trace_vliw_wait_cycles (cpu);
1362 return 0;
1363 }
1364
1365 cycles = idesc->timing->units[unit_num].done;
1366 request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles);
1367 return cycles;
1368}
1369
1370int
1371frvbf_model_fr500_u_icul (SIM_CPU *cpu, const IDESC *idesc,
1372 int unit_num, int referenced,
1373 INT in_GRi, INT in_GRj)
1374{
1375 int cycles;
1376
1377 if (model_insn == FRV_INSN_MODEL_PASS_1)
1378 {
1379 /* The entire VLIW insn must wait if there is a dependency on a register
1380 which is not ready yet.
1381 The latency of the registers may be less than previously recorded,
1382 depending on how they were used previously.
1383 See Table 13-8 in the LSI. */
1384 if (in_GRi >= 0)
1385 {
1386 if (use_is_gr_complex (cpu, in_GRi))
1387 decrease_GR_busy (cpu, in_GRi, 1);
1388 }
1389 if (in_GRj != in_GRi && in_GRj >= 0)
1390 {
1391 if (use_is_gr_complex (cpu, in_GRj))
1392 decrease_GR_busy (cpu, in_GRj, 1);
1393 }
1394 vliw_wait_for_GR (cpu, in_GRi);
1395 vliw_wait_for_GR (cpu, in_GRj);
1396 handle_resource_wait (cpu);
1397 load_wait_for_GR (cpu, in_GRi);
1398 load_wait_for_GR (cpu, in_GRj);
1399 trace_vliw_wait_cycles (cpu);
1400 return 0;
1401 }
1402
1403 cycles = idesc->timing->units[unit_num].done;
1404 request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles);
1405 return cycles;
1406}
1407
1408int
1409frvbf_model_fr500_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
1410 int unit_num, int referenced,
1411 INT in_GRi, INT in_GRj)
1412{
1413 int cycles;
1414
1415 if (model_insn == FRV_INSN_MODEL_PASS_1)
1416 {
1417 /* The entire VLIW insn must wait if there is a dependency on a register
1418 which is not ready yet.
1419 The latency of the registers may be less than previously recorded,
1420 depending on how they were used previously.
1421 See Table 13-8 in the LSI. */
1422 if (in_GRi >= 0)
1423 {
1424 if (use_is_gr_complex (cpu, in_GRi))
1425 decrease_GR_busy (cpu, in_GRi, 1);
1426 }
1427 if (in_GRj != in_GRi && in_GRj >= 0)
1428 {
1429 if (use_is_gr_complex (cpu, in_GRj))
1430 decrease_GR_busy (cpu, in_GRj, 1);
1431 }
1432 vliw_wait_for_GR (cpu, in_GRi);
1433 vliw_wait_for_GR (cpu, in_GRj);
1434 handle_resource_wait (cpu);
1435 load_wait_for_GR (cpu, in_GRi);
1436 load_wait_for_GR (cpu, in_GRj);
1437 trace_vliw_wait_cycles (cpu);
1438 return 0;
1439 }
1440
1441 cycles = idesc->timing->units[unit_num].done;
1442 request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles);
1443 return cycles;
1444}
1445
b34f6357
DB		 1446int
1447frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc,
1448 int unit_num, int referenced,
1449 INT in_FRi, INT in_FRj,
1450 INT in_FRdoublei, INT in_FRdoublej,
1451 INT out_FRk, INT out_FRdoublek)
1452{
1453 int cycles;
1454 FRV_PROFILE_STATE *ps;
1455
1456 if (model_insn == FRV_INSN_MODEL_PASS_1)
1457 return 0;
1458
1459 /* The preprocessing can execute right away. */
1460 cycles = idesc->timing->units[unit_num].done;
1461
1462 /* The post processing must wait if there is a dependency on a FR
1463 which is not ready yet. */
1464 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1465 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1466 1);
1467 ps = CPU_PROFILE_STATE (cpu);
1468 ps->post_wait = cycles;
1469 post_wait_for_FR (cpu, in_FRi);
1470 post_wait_for_FR (cpu, in_FRj);
1471 post_wait_for_FR (cpu, out_FRk);
1472 post_wait_for_FRdouble (cpu, in_FRdoublei);
1473 post_wait_for_FRdouble (cpu, in_FRdoublej);
1474 post_wait_for_FRdouble (cpu, out_FRdoublek);
1c453cd6
DB		 1475 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1476 {
1477 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
1478 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
1479 }
b34f6357
DB		 1480 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1481 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1482 1);
1483
1484 /* The latency of FRk will be at least the latency of the other inputs. */
1485 update_FR_latency (cpu, out_FRk, ps->post_wait);
1486 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1487
1c453cd6
DB		 1488 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1489 {
1490 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
1491 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
1492 }
1493
b34f6357
DB		 1494 /* Once initiated, post-processing will take 3 cycles. */
1495 update_FR_ptime (cpu, out_FRk, 3);
1496 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1497
1c453cd6
DB		 1498 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1499 {
1500 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
1501 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
1502 }
1503
b34f6357
DB		 1504 /* Mark this use of the register as a floating point op. */
1505 if (out_FRk >= 0)
1506 set_use_is_fpop (cpu, out_FRk);
1507 if (out_FRdoublek >= 0)
1508 {
1509 set_use_is_fpop (cpu, out_FRdoublek);
1510 if (out_FRdoublek < 63)
1511 set_use_is_fpop (cpu, out_FRdoublek + 1);
1512 }
1513
1514 return cycles;
1515}
1516
1517int
1518frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc,
1519 int unit_num, int referenced,
1520 INT in_FRi, INT in_FRj,
1521 INT in_FRdoublei, INT in_FRdoublej,
1522 INT out_FRk, INT out_FRdoublek)
1523{
1524 int cycles;
1525 INT dual_FRi;
1526 INT dual_FRj;
1527 INT dual_FRk;
1528 INT dual_FRdoublei;
1529 INT dual_FRdoublej;
1530 INT dual_FRdoublek;
1531 FRV_PROFILE_STATE *ps;
1532
1533 if (model_insn == FRV_INSN_MODEL_PASS_1)
1534 return 0;
1535
1536 /* The preprocessing can execute right away. */
1537 cycles = idesc->timing->units[unit_num].done;
1538
1539 /* The post processing must wait if there is a dependency on a FR
1540 which is not ready yet. */
1541 dual_FRi = DUAL_REG (in_FRi);
1542 dual_FRj = DUAL_REG (in_FRj);
1543 dual_FRk = DUAL_REG (out_FRk);
1544 dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei);
1545 dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej);
1546 dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek);
1547
1548 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1549 adjust_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
1550 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1551 1);
1552 adjust_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej,
1553 dual_FRdoublek, 1);
1554 ps = CPU_PROFILE_STATE (cpu);
1555 ps->post_wait = cycles;
1556 post_wait_for_FR (cpu, in_FRi);
1557 post_wait_for_FR (cpu, in_FRj);
1558 post_wait_for_FR (cpu, out_FRk);
1559 post_wait_for_FR (cpu, dual_FRi);
1560 post_wait_for_FR (cpu, dual_FRj);
1561 post_wait_for_FR (cpu, dual_FRk);
1562 post_wait_for_FRdouble (cpu, in_FRdoublei);
1563 post_wait_for_FRdouble (cpu, in_FRdoublej);
1564 post_wait_for_FRdouble (cpu, out_FRdoublek);
1565 post_wait_for_FRdouble (cpu, dual_FRdoublei);
1566 post_wait_for_FRdouble (cpu, dual_FRdoublej);
1567 post_wait_for_FRdouble (cpu, dual_FRdoublek);
1c453cd6
DB		 1568 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1569 {
1570 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
1571 post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRk));
1572 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
1573 post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRdoublek));
1574 }
b34f6357
DB		 1575 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1576 restore_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
1577 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1578 1);
1579 restore_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej,
1580 dual_FRdoublek, 1);
1581
1582 /* The latency of FRk will be at least the latency of the other inputs. */
1583 update_FR_latency (cpu, out_FRk, ps->post_wait);
1584 update_FR_latency (cpu, dual_FRk, ps->post_wait);
1585 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1586 update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait);
1587
1c453cd6
DB		 1588 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1589 {
1590 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
1591 update_SPR_latency (cpu, FNER_FOR_FR (dual_FRk), ps->post_wait);
1592 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
1593 update_SPR_latency (cpu, FNER_FOR_FR (dual_FRdoublek), ps->post_wait);
1594 }
1595
b34f6357
DB		 1596 /* Once initiated, post-processing will take 3 cycles. */
1597 update_FR_ptime (cpu, out_FRk, 3);
1598 update_FR_ptime (cpu, dual_FRk, 3);
1599 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1600 update_FRdouble_ptime (cpu, dual_FRdoublek, 3);
1601
1c453cd6
DB		 1602 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1603 {
1604 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
1605 update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRk), 3);
1606 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
1607 update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRdoublek), 3);
1608 }
1609
b34f6357
DB		 1610 /* Mark this use of the register as a floating point op. */
1611 if (out_FRk >= 0)
1612 set_use_is_fpop (cpu, out_FRk);
1613 if (dual_FRk >= 0)
1614 set_use_is_fpop (cpu, dual_FRk);
1615 if (out_FRdoublek >= 0)
1616 {
1617 set_use_is_fpop (cpu, out_FRdoublek);
1618 if (out_FRdoublek < 63)
1619 set_use_is_fpop (cpu, out_FRdoublek + 1);
1620 }
1621 if (dual_FRdoublek >= 0)
1622 {
1623 set_use_is_fpop (cpu, dual_FRdoublek);
1624 if (dual_FRdoublek < 63)
1625 set_use_is_fpop (cpu, dual_FRdoublek + 1);
1626 }
1627
1628 return cycles;
1629}
1630
1631int
1632frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc,
1633 int unit_num, int referenced,
1634 INT in_FRi, INT in_FRj, INT out_FRk)
1635{
1636 int cycles;
1637 FRV_VLIW *vliw;
1638 int slot;
1639 FRV_PROFILE_STATE *ps;
1640
1641 if (model_insn == FRV_INSN_MODEL_PASS_1)
1642 return 0;
1643
1644 cycles = idesc->timing->units[unit_num].done;
1645
1646 /* The post processing must wait if there is a dependency on a FR
1647 which is not ready yet. */
1648 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1649 ps = CPU_PROFILE_STATE (cpu);
1650 ps->post_wait = cycles;
1651 post_wait_for_FR (cpu, in_FRi);
1652 post_wait_for_FR (cpu, in_FRj);
1653 post_wait_for_FR (cpu, out_FRk);
1c453cd6
DB		 1654 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1655 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
b34f6357
DB		 1656 vliw = CPU_VLIW (cpu);
1657 slot = vliw->next_slot - 1;
1658 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1659 post_wait_for_fdiv (cpu, slot);
1660 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1661
1662 /* The latency of FRk will be at least the latency of the other inputs. */
1663 /* Once initiated, post-processing will take 10 cycles. */
1664 update_FR_latency (cpu, out_FRk, ps->post_wait);
1665 update_FR_ptime (cpu, out_FRk, 10);
1666
1c453cd6
DB		 1667 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1668 {
1669 /* FNER has a latency of 10 cycles. */
1670 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
1671 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 10);
1672 }
1673
b34f6357
DB		 1674 /* The latency of the fdiv unit will be at least the latency of the other
1675 inputs. Once initiated, post-processing will take 9 cycles. */
1676 update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9);
1677
1678 /* Mark this use of the register as a floating point op. */
1679 set_use_is_fpop (cpu, out_FRk);
1680
1681 return cycles;
1682}
1683
1684int
1685frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc,
1686 int unit_num, int referenced,
1687 INT in_FRj, INT in_FRdoublej,
1688 INT out_FRk, INT out_FRdoublek)
1689{
1690 int cycles;
1691 FRV_VLIW *vliw;
1692 int slot;
1693 FRV_PROFILE_STATE *ps;
1694
1695 if (model_insn == FRV_INSN_MODEL_PASS_1)
1696 return 0;
1697
1698 cycles = idesc->timing->units[unit_num].done;
1699
1700 /* The post processing must wait if there is a dependency on a FR
1701 which is not ready yet. */
1702 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1703 adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1704 ps = CPU_PROFILE_STATE (cpu);
1705 ps->post_wait = cycles;
1706 post_wait_for_FR (cpu, in_FRj);
1707 post_wait_for_FR (cpu, out_FRk);
1708 post_wait_for_FRdouble (cpu, in_FRdoublej);
1709 post_wait_for_FRdouble (cpu, out_FRdoublek);
1c453cd6
DB		 1710 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1711 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
b34f6357
DB		 1712 vliw = CPU_VLIW (cpu);
1713 slot = vliw->next_slot - 1;
1714 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1715 post_wait_for_fsqrt (cpu, slot);
1716 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1717 restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1718
1719 /* The latency of FRk will be at least the latency of the other inputs. */
1720 update_FR_latency (cpu, out_FRk, ps->post_wait);
1721 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1c453cd6
DB		 1722 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1723 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
b34f6357
DB		 1724
1725 /* Once initiated, post-processing will take 15 cycles. */
1726 update_FR_ptime (cpu, out_FRk, 15);
1727 update_FRdouble_ptime (cpu, out_FRdoublek, 15);
1728
1c453cd6
DB		 1729 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1730 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 15);
1731
b34f6357
DB		 1732 /* The latency of the sqrt unit will be the latency of the other
1733 inputs plus 14 cycles. */
1734 update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
1735
1736 /* Mark this use of the register as a floating point op. */
1737 if (out_FRk >= 0)
1738 set_use_is_fpop (cpu, out_FRk);
1739 if (out_FRdoublek >= 0)
1740 {
1741 set_use_is_fpop (cpu, out_FRdoublek);
1742 if (out_FRdoublek < 63)
1743 set_use_is_fpop (cpu, out_FRdoublek + 1);
1744 }
1745
1746 return cycles;
1747}
1748
1749int
1750frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *cpu, const IDESC *idesc,
1751 int unit_num, int referenced,
1752 INT in_FRj, INT out_FRk)
1753{
1754 int cycles;
1755 FRV_VLIW *vliw;
1756 int slot;
1757 INT dual_FRj;
1758 INT dual_FRk;
1759 FRV_PROFILE_STATE *ps;
1760
1761 if (model_insn == FRV_INSN_MODEL_PASS_1)
1762 return 0;
1763
1764 cycles = idesc->timing->units[unit_num].done;
1765
1766 /* The post processing must wait if there is a dependency on a FR
1767 which is not ready yet. */
1768 dual_FRj = DUAL_REG (in_FRj);
1769 dual_FRk = DUAL_REG (out_FRk);
1770 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1771 adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1772 ps = CPU_PROFILE_STATE (cpu);
1773 ps->post_wait = cycles;
1774 post_wait_for_FR (cpu, in_FRj);
1775 post_wait_for_FR (cpu, out_FRk);
1776 post_wait_for_FR (cpu, dual_FRj);
1777 post_wait_for_FR (cpu, dual_FRk);
1778
1779 vliw = CPU_VLIW (cpu);
1780 slot = vliw->next_slot - 1;
1781 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1782 post_wait_for_fsqrt (cpu, slot);
1783 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1784 restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1785
1786 /* The latency of FRk will be at least the latency of the other inputs. */
1787 update_FR_latency (cpu, out_FRk, ps->post_wait);
1788 update_FR_latency (cpu, dual_FRk, ps->post_wait);
1789
1790 /* Once initiated, post-processing will take 15 cycles. */
1791 update_FR_ptime (cpu, out_FRk, 15);
1792 update_FR_ptime (cpu, dual_FRk, 15);
1793
1794 /* The latency of the sqrt unit will be at least the latency of the other
1795 inputs. */
1796 update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
1797
1798 /* Mark this use of the register as a floating point op. */
1799 if (out_FRk >= 0)
1800 set_use_is_fpop (cpu, out_FRk);
1801 if (dual_FRk >= 0)
1802 set_use_is_fpop (cpu, dual_FRk);
1803
1804 return cycles;
1805}
1806
1807int
1808frvbf_model_fr500_u_float_compare (SIM_CPU *cpu, const IDESC *idesc,
1809 int unit_num, int referenced,
1810 INT in_FRi, INT in_FRj,
1811 INT in_FRdoublei, INT in_FRdoublej,
1812 INT out_FCCi_2)
1813{
1814 int cycles;
1815 FRV_PROFILE_STATE *ps;
1816
1817 if (model_insn == FRV_INSN_MODEL_PASS_1)
1818 return 0;
1819
1820 /* The preprocessing can execute right away. */
1821 cycles = idesc->timing->units[unit_num].done;
1822
1823 /* The post processing must wait if there is a dependency on a FR
1824 which is not ready yet. */
1825 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
1826 ps = CPU_PROFILE_STATE (cpu);
1827 ps->post_wait = cycles;
1828 post_wait_for_FR (cpu, in_FRi);
1829 post_wait_for_FR (cpu, in_FRj);
1830 post_wait_for_FRdouble (cpu, in_FRdoublei);
1831 post_wait_for_FRdouble (cpu, in_FRdoublej);
1832 post_wait_for_CCR (cpu, out_FCCi_2);
1833 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
1834
1835 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1836 cycles. */
1837 update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
1838
1839 return cycles;
1840}
1841
1842int
1843frvbf_model_fr500_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc,
1844 int unit_num, int referenced,
1845 INT in_FRi, INT in_FRj,
1846 INT out_FCCi_2)
1847{
1848 int cycles;
1849 INT dual_FRi;
1850 INT dual_FRj;
1851 INT dual_FCCi_2;
1852 FRV_PROFILE_STATE *ps;
1853
1854 if (model_insn == FRV_INSN_MODEL_PASS_1)
1855 return 0;
1856
1857 /* The preprocessing can execute right away. */
1858 cycles = idesc->timing->units[unit_num].done;
1859
1860 /* The post processing must wait if there is a dependency on a FR
1861 which is not ready yet. */
1862 ps = CPU_PROFILE_STATE (cpu);
1863 ps->post_wait = cycles;
1864 dual_FRi = DUAL_REG (in_FRi);
1865 dual_FRj = DUAL_REG (in_FRj);
1866 dual_FCCi_2 = out_FCCi_2 + 1;
1867 adjust_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
1868 adjust_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
1869 post_wait_for_FR (cpu, in_FRi);
1870 post_wait_for_FR (cpu, in_FRj);
1871 post_wait_for_FR (cpu, dual_FRi);
1872 post_wait_for_FR (cpu, dual_FRj);
1873 post_wait_for_CCR (cpu, out_FCCi_2);
1874 post_wait_for_CCR (cpu, dual_FCCi_2);
1875 restore_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
1876 restore_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
1877
1878 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1879 cycles. */
1880 update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
1881 update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3);
1882
1883 return cycles;
1884}
1885
1886int
1887frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc,
1888 int unit_num, int referenced,
1889 INT in_FRj, INT in_FRintj, INT in_FRdoublej,
1890 INT out_FRk, INT out_FRintk,
1891 INT out_FRdoublek)
1892{
1893 int cycles;
1894 FRV_PROFILE_STATE *ps;
1895
1896 if (model_insn == FRV_INSN_MODEL_PASS_1)
1897 return 0;
1898
1899 /* The preprocessing can execute right away. */
1900 cycles = idesc->timing->units[unit_num].done;
1901
1902 /* The post processing must wait if there is a dependency on a FR
1903 which is not ready yet. */
1904 ps = CPU_PROFILE_STATE (cpu);
1905 ps->post_wait = cycles;
1906 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1907 adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1908 adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1909 post_wait_for_FR (cpu, in_FRj);
1910 post_wait_for_FR (cpu, in_FRintj);
1911 post_wait_for_FRdouble (cpu, in_FRdoublej);
1912 post_wait_for_FR (cpu, out_FRk);
1913 post_wait_for_FR (cpu, out_FRintk);
1914 post_wait_for_FRdouble (cpu, out_FRdoublek);
1c453cd6
DB		 1915 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1916 {
1917 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
1918 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk));
1919 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
1920 }
b34f6357
DB		 1921 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1922 restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1923 restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1924
1925 /* The latency of FRk will be at least the latency of the other inputs. */
1926 update_FR_latency (cpu, out_FRk, ps->post_wait);
1927 update_FR_latency (cpu, out_FRintk, ps->post_wait);
1928 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1929
1c453cd6
DB		 1930 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1931 {
1932 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
1933 update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait);
1934 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
1935 }
1936
b34f6357
DB		 1937 /* Once initiated, post-processing will take 3 cycles. */
1938 update_FR_ptime (cpu, out_FRk, 3);
1939 update_FR_ptime (cpu, out_FRintk, 3);
1940 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1941
1c453cd6
DB		 1942 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1943 {
1944 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
1945 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 3);
1946 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
1947 }
1948
b34f6357
DB		 1949 /* Mark this use of the register as a floating point op. */
1950 if (out_FRk >= 0)
1951 set_use_is_fpop (cpu, out_FRk);
1952 if (out_FRintk >= 0)
1953 set_use_is_fpop (cpu, out_FRintk);
1954 if (out_FRdoublek >= 0)
1955 {
1956 set_use_is_fpop (cpu, out_FRdoublek);
1957 set_use_is_fpop (cpu, out_FRdoublek + 1);
1958 }
1959
1960 return cycles;
1961}
1962
1963int
1964frvbf_model_fr500_u_float_dual_convert (SIM_CPU *cpu, const IDESC *idesc,
1965 int unit_num, int referenced,
1966 INT in_FRj, INT in_FRintj,
1967 INT out_FRk, INT out_FRintk)
1968{
1969 int cycles;
1970 INT dual_FRj;
1971 INT dual_FRintj;
1972 INT dual_FRk;
1973 INT dual_FRintk;
1974 FRV_PROFILE_STATE *ps;
1975
1976 if (model_insn == FRV_INSN_MODEL_PASS_1)
1977 return 0;
1978
1979 /* The preprocessing can execute right away. */
1980 cycles = idesc->timing->units[unit_num].done;
1981
1982 /* The post processing must wait if there is a dependency on a FR
1983 which is not ready yet. */
1984 ps = CPU_PROFILE_STATE (cpu);
1985 ps->post_wait = cycles;
1986 dual_FRj = DUAL_REG (in_FRj);
1987 dual_FRintj = DUAL_REG (in_FRintj);
1988 dual_FRk = DUAL_REG (out_FRk);
1989 dual_FRintk = DUAL_REG (out_FRintk);
1990 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1991 adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1992 adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1993 adjust_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
1994 post_wait_for_FR (cpu, in_FRj);
1995 post_wait_for_FR (cpu, in_FRintj);
1996 post_wait_for_FR (cpu, out_FRk);
1997 post_wait_for_FR (cpu, out_FRintk);
1998 post_wait_for_FR (cpu, dual_FRj);
1999 post_wait_for_FR (cpu, dual_FRintj);
2000 post_wait_for_FR (cpu, dual_FRk);
2001 post_wait_for_FR (cpu, dual_FRintk);
2002 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
2003 restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
2004 restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
2005 restore_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
2006
2007 /* The latency of FRk will be at least the latency of the other inputs. */
2008 update_FR_latency (cpu, out_FRk, ps->post_wait);
2009 update_FR_latency (cpu, out_FRintk, ps->post_wait);
2010 update_FR_latency (cpu, dual_FRk, ps->post_wait);
2011 update_FR_latency (cpu, dual_FRintk, ps->post_wait);
2012
2013 /* Once initiated, post-processing will take 3 cycles. */
2014 update_FR_ptime (cpu, out_FRk, 3);
2015 update_FR_ptime (cpu, out_FRintk, 3);
2016 update_FR_ptime (cpu, dual_FRk, 3);
2017 update_FR_ptime (cpu, dual_FRintk, 3);
2018
2019 /* Mark this use of the register as a floating point op. */
2020 if (out_FRk >= 0)
2021 set_use_is_fpop (cpu, out_FRk);
2022 if (out_FRintk >= 0)
2023 set_use_is_fpop (cpu, out_FRintk);
2024
2025 return cycles;
2026}
2027
2028int
2029frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc,
2030 int unit_num, int referenced,
2031 INT in_FRi, INT in_FRj, INT in_ACC40Si, INT in_ACCGi,
2032 INT out_FRk,
2033 INT out_ACC40Sk, INT out_ACC40Uk, INT out_ACCGk)
2034{
2035 int cycles;
2036 FRV_PROFILE_STATE *ps;
2037 const CGEN_INSN *insn;
2038 int is_media_s1;
2039 int is_media_s2;
2040 int busy_adjustment[] = {0, 0, 0};
2041 int *fr;
2042 int *acc;
2043
2044 if (model_insn == FRV_INSN_MODEL_PASS_1)
2045 return 0;
2046
2047 /* The preprocessing can execute right away. */
2048 cycles = idesc->timing->units[unit_num].done;
2049
2050 ps = CPU_PROFILE_STATE (cpu);
2051 insn = idesc->idata;
2052
2053 /* If the previous use of the registers was a media op,
2054 then their latency will be less than previously recorded.
2055 See Table 13-13 in the LSI. */
2056 if (in_FRi >= 0)
2057 {
2058 if (use_is_media (cpu, in_FRi))
2059 {
2060 busy_adjustment[0] = 2;
2061 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2062 }
2063 else
2064 enforce_full_fr_latency (cpu, in_FRi);
2065 }
2066 if (in_FRj >= 0 && in_FRj != in_FRi)
2067 {
2068 if (use_is_media (cpu, in_FRj))
2069 {
2070 busy_adjustment[1] = 2;
2071 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
2072 }
2073 else
2074 enforce_full_fr_latency (cpu, in_FRj);
2075 }
2076 if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
2077 {
2078 if (use_is_media (cpu, out_FRk))
2079 {
2080 busy_adjustment[2] = 2;
2081 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
2082 }
2083 else
2084 enforce_full_fr_latency (cpu, out_FRk);
2085 }
2086
2087 /* The post processing must wait if there is a dependency on a FR
2088 which is not ready yet. */
2089 ps->post_wait = cycles;
2090 post_wait_for_FR (cpu, in_FRi);
2091 post_wait_for_FR (cpu, in_FRj);
2092 post_wait_for_FR (cpu, out_FRk);
2093 post_wait_for_ACC (cpu, in_ACC40Si);
2094 post_wait_for_ACC (cpu, in_ACCGi);
2095 post_wait_for_ACC (cpu, out_ACC40Sk);
2096 post_wait_for_ACC (cpu, out_ACC40Uk);
2097 post_wait_for_ACC (cpu, out_ACCGk);
2098
2099 /* Restore the busy cycles of the registers we used. */
2100 fr = ps->fr_busy;
2101 if (in_FRi >= 0)
2102 fr[in_FRi] += busy_adjustment[0];
2103 if (in_FRj >= 0)
2104 fr[in_FRj] += busy_adjustment[1];
2105 if (out_FRk >= 0)
2106 fr[out_FRk] += busy_adjustment[2];
2107
2108 /* The latency of tht output register will be at least the latency of the
2109 other inputs. Once initiated, post-processing will take 3 cycles. */
2110 if (out_FRk >= 0)
2111 {
2112 update_FR_latency (cpu, out_FRk, ps->post_wait);
2113 update_FR_ptime (cpu, out_FRk, 3);
2114 /* Mark this use of the register as a media op. */
2115 set_use_is_media (cpu, out_FRk);
2116 }
2117 /* The latency of tht output accumulator will be at least the latency of the
2118 other inputs. Once initiated, post-processing will take 1 cycle. */
2119 if (out_ACC40Sk >= 0)
2120 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2121 if (out_ACC40Uk >= 0)
2122 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
2123 if (out_ACCGk >= 0)
2124 update_ACC_latency (cpu, out_ACCGk, ps->post_wait + 1);
2125
2126 return cycles;
2127}
2128
2129int
2130frvbf_model_fr500_u_media_quad_arith (SIM_CPU *cpu, const IDESC *idesc,
2131 int unit_num, int referenced,
2132 INT in_FRi, INT in_FRj,
2133 INT out_FRk)
2134{
2135 int cycles;
2136 INT dual_FRi;
2137 INT dual_FRj;
2138 INT dual_FRk;
2139 FRV_PROFILE_STATE *ps;
2140 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2141 int *fr;
2142
2143 if (model_insn == FRV_INSN_MODEL_PASS_1)
2144 return 0;
2145
2146 /* The preprocessing can execute right away. */
2147 cycles = idesc->timing->units[unit_num].done;
2148
2149 ps = CPU_PROFILE_STATE (cpu);
2150 dual_FRi = DUAL_REG (in_FRi);
2151 dual_FRj = DUAL_REG (in_FRj);
2152 dual_FRk = DUAL_REG (out_FRk);
2153
2154 /* If the previous use of the registers was a media op,
2155 then their latency will be less than previously recorded.
2156 See Table 13-13 in the LSI. */
2157 if (use_is_media (cpu, in_FRi))
2158 {
2159 busy_adjustment[0] = 2;
2160 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2161 }
2162 else
2163 enforce_full_fr_latency (cpu, in_FRi);
2164 if (dual_FRi >= 0 && use_is_media (cpu, dual_FRi))
2165 {
2166 busy_adjustment[1] = 2;
2167 decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]);
2168 }
2169 else
2170 enforce_full_fr_latency (cpu, dual_FRi);
2171 if (in_FRj != in_FRi)
2172 {
2173 if (use_is_media (cpu, in_FRj))
2174 {
2175 busy_adjustment[2] = 2;
2176 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2177 }
2178 else
2179 enforce_full_fr_latency (cpu, in_FRj);
2180 if (dual_FRj >= 0 && use_is_media (cpu, dual_FRj))
2181 {
2182 busy_adjustment[3] = 2;
2183 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]);
2184 }
2185 else
2186 enforce_full_fr_latency (cpu, dual_FRj + 1);
2187 }
2188 if (out_FRk != in_FRi && out_FRk != in_FRj)
2189 {
2190 if (use_is_media (cpu, out_FRk))
2191 {
2192 busy_adjustment[4] = 2;
2193 decrease_FR_busy (cpu, out_FRk, busy_adjustment[4]);
2194 }
2195 else
2196 enforce_full_fr_latency (cpu, out_FRk);
2197 if (dual_FRk >= 0 && use_is_media (cpu, dual_FRk))
2198 {
2199 busy_adjustment[5] = 2;
2200 decrease_FR_busy (cpu, dual_FRk, busy_adjustment[5]);
2201 }
2202 else
2203 enforce_full_fr_latency (cpu, dual_FRk);
2204 }
2205
2206 /* The post processing must wait if there is a dependency on a FR
2207 which is not ready yet. */
2208 ps->post_wait = cycles;
2209 post_wait_for_FR (cpu, in_FRi);
2210 post_wait_for_FR (cpu, dual_FRi);
2211 post_wait_for_FR (cpu, in_FRj);
2212 post_wait_for_FR (cpu, dual_FRj);
2213 post_wait_for_FR (cpu, out_FRk);
2214 post_wait_for_FR (cpu, dual_FRk);
2215
2216 /* Restore the busy cycles of the registers we used. */
2217 fr = ps->fr_busy;
2218 fr[in_FRi] += busy_adjustment[0];
2219 if (dual_FRi >= 0)
2220 fr[dual_FRi] += busy_adjustment[1];
2221 fr[in_FRj] += busy_adjustment[2];
2222 if (dual_FRj >= 0)
2223 fr[dual_FRj] += busy_adjustment[3];
2224 fr[out_FRk] += busy_adjustment[4];
2225 if (dual_FRk >= 0)
2226 fr[dual_FRk] += busy_adjustment[5];
2227
2228 /* The latency of tht output register will be at least the latency of the
2229 other inputs. */
2230 update_FR_latency (cpu, out_FRk, ps->post_wait);
2231
2232 /* Once initiated, post-processing will take 3 cycles. */
2233 update_FR_ptime (cpu, out_FRk, 3);
2234
2235 /* Mark this use of the register as a media op. */
2236 set_use_is_media (cpu, out_FRk);
2237 if (dual_FRk >= 0)
2238 {
2239 update_FR_latency (cpu, dual_FRk, ps->post_wait);
2240 update_FR_ptime (cpu, dual_FRk, 3);
2241 /* Mark this use of the register as a media op. */
2242 set_use_is_media (cpu, dual_FRk);
2243 }
2244
2245 return cycles;
2246}
2247
2248int
2249frvbf_model_fr500_u_media_dual_mul (SIM_CPU *cpu, const IDESC *idesc,
2250 int unit_num, int referenced,
2251 INT in_FRi, INT in_FRj,
2252 INT out_ACC40Sk, INT out_ACC40Uk)
2253{
2254 int cycles;
2255 INT dual_ACC40Sk;
2256 INT dual_ACC40Uk;
2257 FRV_PROFILE_STATE *ps;
2258 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2259 int *fr;
2260 int *acc;
2261
2262 if (model_insn == FRV_INSN_MODEL_PASS_1)
2263 return 0;
2264
2265 /* The preprocessing can execute right away. */
2266 cycles = idesc->timing->units[unit_num].done;
2267
2268 ps = CPU_PROFILE_STATE (cpu);
2269 dual_ACC40Sk = DUAL_REG (out_ACC40Sk);
2270 dual_ACC40Uk = DUAL_REG (out_ACC40Uk);
2271
2272 /* If the previous use of the registers was a media op,
2273 then their latency will be less than previously recorded.
2274 See Table 13-13 in the LSI. */
2275 if (use_is_media (cpu, in_FRi))
2276 {
2277 busy_adjustment[0] = 2;
2278 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2279 }
2280 else
2281 enforce_full_fr_latency (cpu, in_FRi);
2282 if (in_FRj != in_FRi)
2283 {
2284 if (use_is_media (cpu, in_FRj))
2285 {
2286 busy_adjustment[1] = 2;
2287 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
2288 }
2289 else
2290 enforce_full_fr_latency (cpu, in_FRj);
2291 }
2292 if (out_ACC40Sk >= 0)
2293 {
2294 busy_adjustment[2] = 1;
2295 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]);
2296 }
2297 if (dual_ACC40Sk >= 0)
2298 {
2299 busy_adjustment[3] = 1;
2300 decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]);
2301 }
2302 if (out_ACC40Uk >= 0)
2303 {
2304 busy_adjustment[4] = 1;
2305 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
2306 }
2307 if (dual_ACC40Uk >= 0)
2308 {
2309 busy_adjustment[5] = 1;
2310 decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]);
2311 }
2312
2313 /* The post processing must wait if there is a dependency on a FR
2314 which is not ready yet. */
2315 ps->post_wait = cycles;
2316 post_wait_for_FR (cpu, in_FRi);
2317 post_wait_for_FR (cpu, in_FRj);
2318 post_wait_for_ACC (cpu, out_ACC40Sk);
2319 post_wait_for_ACC (cpu, dual_ACC40Sk);
2320 post_wait_for_ACC (cpu, out_ACC40Uk);
2321 post_wait_for_ACC (cpu, dual_ACC40Uk);
2322
2323 /* Restore the busy cycles of the registers we used. */
2324 fr = ps->fr_busy;
2325 acc = ps->acc_busy;
2326 fr[in_FRi] += busy_adjustment[0];
2327 fr[in_FRj] += busy_adjustment[1];
2328 if (out_ACC40Sk >= 0)
2329 acc[out_ACC40Sk] += busy_adjustment[2];
2330 if (dual_ACC40Sk >= 0)
2331 acc[dual_ACC40Sk] += busy_adjustment[3];
2332 if (out_ACC40Uk >= 0)
2333 acc[out_ACC40Uk] += busy_adjustment[4];
2334 if (dual_ACC40Uk >= 0)
2335 acc[dual_ACC40Uk] += busy_adjustment[5];
2336
2337 /* The latency of tht output register will be at least the latency of the
2338 other inputs. Once initiated, post-processing will take 1 cycle. */
2339 if (out_ACC40Sk >= 0)
2340 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2341 if (dual_ACC40Sk >= 0)
2342 update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1);
2343 if (out_ACC40Uk >= 0)
2344 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
2345 if (dual_ACC40Uk >= 0)
2346 update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1);
2347
2348 return cycles;
2349}
2350
2351int
2352frvbf_model_fr500_u_media_quad_mul (SIM_CPU *cpu, const IDESC *idesc,
2353 int unit_num, int referenced,
2354 INT in_FRi, INT in_FRj,
2355 INT out_ACC40Sk, INT out_ACC40Uk)
2356{
2357 int cycles;
2358 INT FRi_1;
2359 INT FRj_1;
2360 INT ACC40Sk_1;
2361 INT ACC40Sk_2;
2362 INT ACC40Sk_3;
2363 INT ACC40Uk_1;
2364 INT ACC40Uk_2;
2365 INT ACC40Uk_3;
2366 FRV_PROFILE_STATE *ps;
2367 int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0};
2368 int *fr;
2369 int *acc;
2370
2371 if (model_insn == FRV_INSN_MODEL_PASS_1)
2372 return 0;
2373
2374 /* The preprocessing can execute right away. */
2375 cycles = idesc->timing->units[unit_num].done;
2376
2377 FRi_1 = DUAL_REG (in_FRi);
2378 FRj_1 = DUAL_REG (in_FRj);
2379 ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
2380 ACC40Sk_2 = DUAL_REG (ACC40Sk_1);
2381 ACC40Sk_3 = DUAL_REG (ACC40Sk_2);
2382 ACC40Uk_1 = DUAL_REG (out_ACC40Uk);
2383 ACC40Uk_2 = DUAL_REG (ACC40Uk_1);
2384 ACC40Uk_3 = DUAL_REG (ACC40Uk_2);
2385
2386 /* If the previous use of the registers was a media op,
2387 then their latency will be less than previously recorded.
2388 See Table 13-13 in the LSI. */
2389 ps = CPU_PROFILE_STATE (cpu);
2390 if (use_is_media (cpu, in_FRi))
2391 {
2392 busy_adjustment[0] = 2;
2393 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2394 }
2395 else
2396 enforce_full_fr_latency (cpu, in_FRi);
2397 if (FRi_1 >= 0)
2398 {
2399 if (use_is_media (cpu, FRi_1))
2400 {
2401 busy_adjustment[1] = 2;
2402 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2403 }
2404 else
2405 enforce_full_fr_latency (cpu, FRi_1);
2406 }
2407 if (in_FRj != in_FRi)
2408 {
2409 if (use_is_media (cpu, in_FRj))
2410 {
2411 busy_adjustment[2] = 2;
2412 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2413 }
2414 else
2415 enforce_full_fr_latency (cpu, in_FRj);
2416 if (FRj_1 >= 0)
2417 {
2418 if (use_is_media (cpu, FRj_1))
2419 {
2420 busy_adjustment[3] = 2;
2421 decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]);
2422 }
2423 else
2424 enforce_full_fr_latency (cpu, FRj_1);
2425 }
2426 }
2427 if (out_ACC40Sk >= 0)
2428 {
2429 busy_adjustment[4] = 1;
2430 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
2431
2432 if (ACC40Sk_1 >= 0)
2433 {
2434 busy_adjustment[5] = 1;
2435 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
2436 }
2437 if (ACC40Sk_2 >= 0)
2438 {
2439 busy_adjustment[6] = 1;
2440 decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]);
2441 }
2442 if (ACC40Sk_3 >= 0)
2443 {
2444 busy_adjustment[7] = 1;
2445 decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]);
2446 }
2447 }
2448 else if (out_ACC40Uk >= 0)
2449 {
2450 busy_adjustment[4] = 1;
2451 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
2452
2453 if (ACC40Uk_1 >= 0)
2454 {
2455 busy_adjustment[5] = 1;
2456 decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]);
2457 }
2458 if (ACC40Uk_2 >= 0)
2459 {
2460 busy_adjustment[6] = 1;
2461 decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]);
2462 }
2463 if (ACC40Uk_3 >= 0)
2464 {
2465 busy_adjustment[7] = 1;
2466 decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]);
2467 }
2468 }
2469
2470 /* The post processing must wait if there is a dependency on a FR
2471 which is not ready yet. */
2472 ps->post_wait = cycles;
2473 post_wait_for_FR (cpu, in_FRi);
2474 post_wait_for_FR (cpu, FRi_1);
2475 post_wait_for_FR (cpu, in_FRj);
2476 post_wait_for_FR (cpu, FRj_1);
2477 post_wait_for_ACC (cpu, out_ACC40Sk);
2478 post_wait_for_ACC (cpu, ACC40Sk_1);
2479 post_wait_for_ACC (cpu, ACC40Sk_2);
2480 post_wait_for_ACC (cpu, ACC40Sk_3);
2481 post_wait_for_ACC (cpu, out_ACC40Uk);
2482 post_wait_for_ACC (cpu, ACC40Uk_1);
2483 post_wait_for_ACC (cpu, ACC40Uk_2);
2484 post_wait_for_ACC (cpu, ACC40Uk_3);
2485
2486 /* Restore the busy cycles of the registers we used. */
2487 fr = ps->fr_busy;
2488 acc = ps->acc_busy;
2489 fr[in_FRi] += busy_adjustment[0];
2490 if (FRi_1 >= 0)
2491 fr[FRi_1] += busy_adjustment[1];
2492 fr[in_FRj] += busy_adjustment[2];
2493 if (FRj_1 > 0)
2494 fr[FRj_1] += busy_adjustment[3];
2495 if (out_ACC40Sk >= 0)
2496 {
2497 acc[out_ACC40Sk] += busy_adjustment[4];
2498 if (ACC40Sk_1 >= 0)
2499 acc[ACC40Sk_1] += busy_adjustment[5];
2500 if (ACC40Sk_2 >= 0)
2501 acc[ACC40Sk_2] += busy_adjustment[6];
2502 if (ACC40Sk_3 >= 0)
2503 acc[ACC40Sk_3] += busy_adjustment[7];
2504 }
2505 else if (out_ACC40Uk >= 0)
2506 {
2507 acc[out_ACC40Uk] += busy_adjustment[4];
2508 if (ACC40Uk_1 >= 0)
2509 acc[ACC40Uk_1] += busy_adjustment[5];
2510 if (ACC40Uk_2 >= 0)
2511 acc[ACC40Uk_2] += busy_adjustment[6];
2512 if (ACC40Uk_3 >= 0)
2513 acc[ACC40Uk_3] += busy_adjustment[7];
2514 }
2515
2516 /* The latency of tht output register will be at least the latency of the
2517 other inputs. Once initiated, post-processing will take 1 cycle. */
2518 if (out_ACC40Sk >= 0)
2519 {
2520 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2521 if (ACC40Sk_1 >= 0)
2522 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
2523 if (ACC40Sk_2 >= 0)
2524 update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);
2525 if (ACC40Sk_3 >= 0)
2526 update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);
2527 }
2528 else if (out_ACC40Uk >= 0)
2529 {
2530 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
2531 if (ACC40Uk_1 >= 0)
2532 update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1);
2533 if (ACC40Uk_2 >= 0)
2534 update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1);
2535 if (ACC40Uk_3 >= 0)
2536 update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1);
2537 }
2538
2539 return cycles;
2540}
2541
2542int
2543frvbf_model_fr500_u_media_quad_complex (SIM_CPU *cpu, const IDESC *idesc,
2544 int unit_num, int referenced,
2545 INT in_FRi, INT in_FRj,
2546 INT out_ACC40Sk)
2547{
2548 int cycles;
2549 INT FRi_1;
2550 INT FRj_1;
2551 INT ACC40Sk_1;
2552 FRV_PROFILE_STATE *ps;
2553 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2554 int *fr;
2555 int *acc;
2556
2557 if (model_insn == FRV_INSN_MODEL_PASS_1)
2558 return 0;
2559
2560 /* The preprocessing can execute right away. */
2561 cycles = idesc->timing->units[unit_num].done;
2562
2563 FRi_1 = DUAL_REG (in_FRi);
2564 FRj_1 = DUAL_REG (in_FRj);
2565 ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
2566
2567 /* If the previous use of the registers was a media op,
2568 then their latency will be less than previously recorded.
2569 See Table 13-13 in the LSI. */
2570 ps = CPU_PROFILE_STATE (cpu);
2571 if (use_is_media (cpu, in_FRi))
2572 {
2573 busy_adjustment[0] = 2;
2574 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2575 }
2576 else
2577 enforce_full_fr_latency (cpu, in_FRi);
2578 if (FRi_1 >= 0)
2579 {
2580 if (use_is_media (cpu, FRi_1))
2581 {
2582 busy_adjustment[1] = 2;
2583 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2584 }
2585 else
2586 enforce_full_fr_latency (cpu, FRi_1);
2587 }
2588 if (in_FRj != in_FRi)
2589 {
2590 if (use_is_media (cpu, in_FRj))
2591 {
2592 busy_adjustment[2] = 2;
2593 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2594 }
2595 else
2596 enforce_full_fr_latency (cpu, in_FRj);
2597 if (FRj_1 >= 0)
2598 {
2599 if (use_is_media (cpu, FRj_1))
2600 {
2601 busy_adjustment[3] = 2;
2602 decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]);
2603 }
2604 else
2605 enforce_full_fr_latency (cpu, FRj_1);
2606 }
2607 }
2608 if (out_ACC40Sk >= 0)
2609 {
2610 busy_adjustment[4] = 1;
2611 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
2612
2613 if (ACC40Sk_1 >= 0)
2614 {
2615 busy_adjustment[5] = 1;
2616 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
2617 }
2618 }
2619
2620 /* The post processing must wait if there is a dependency on a FR
2621 which is not ready yet. */
2622 ps->post_wait = cycles;
2623 post_wait_for_FR (cpu, in_FRi);
2624 post_wait_for_FR (cpu, FRi_1);
2625 post_wait_for_FR (cpu, in_FRj);
2626 post_wait_for_FR (cpu, FRj_1);
2627 post_wait_for_ACC (cpu, out_ACC40Sk);
2628 post_wait_for_ACC (cpu, ACC40Sk_1);
2629
2630 /* Restore the busy cycles of the registers we used. */
2631 fr = ps->fr_busy;
2632 acc = ps->acc_busy;
2633 fr[in_FRi] += busy_adjustment[0];
2634 if (FRi_1 >= 0)
2635 fr[FRi_1] += busy_adjustment[1];
2636 fr[in_FRj] += busy_adjustment[2];
2637 if (FRj_1 > 0)
2638 fr[FRj_1] += busy_adjustment[3];
2639 if (out_ACC40Sk >= 0)
2640 {
2641 acc[out_ACC40Sk] += busy_adjustment[4];
2642 if (ACC40Sk_1 >= 0)
2643 acc[ACC40Sk_1] += busy_adjustment[5];
2644 }
2645
2646 /* The latency of tht output register will be at least the latency of the
2647 other inputs. Once initiated, post-processing will take 1 cycle. */
2648 if (out_ACC40Sk >= 0)
2649 {
2650 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2651 if (ACC40Sk_1 >= 0)
2652 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
2653 }
2654
2655 return cycles;
2656}
2657
2658int
2659frvbf_model_fr500_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
2660 int unit_num, int referenced,
2661 INT in_FRi,
2662 INT out_FRk)
2663{
2664 int cycles;
2665 INT dual_FRk;
2666 FRV_PROFILE_STATE *ps;
2667 int busy_adjustment[] = {0, 0, 0};
2668 int *fr;
2669
2670 if (model_insn == FRV_INSN_MODEL_PASS_1)
2671 return 0;
2672
2673 /* The preprocessing can execute right away. */
2674 cycles = idesc->timing->units[unit_num].done;
2675
2676 /* If the previous use of the registers was a media op,
2677 then their latency will be less than previously recorded.
2678 See Table 13-13 in the LSI. */
2679 dual_FRk = DUAL_REG (out_FRk);
2680 ps = CPU_PROFILE_STATE (cpu);
2681 if (use_is_media (cpu, in_FRi))
2682 {
2683 busy_adjustment[0] = 2;
2684 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2685 }
2686 else
2687 enforce_full_fr_latency (cpu, in_FRi);
2688 if (out_FRk != in_FRi)
2689 {
2690 if (use_is_media (cpu, out_FRk))
2691 {
2692 busy_adjustment[1] = 2;
2693 decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]);
2694 }
2695 else
2696 enforce_full_fr_latency (cpu, out_FRk);
2697 }
2698 if (dual_FRk >= 0 && dual_FRk != in_FRi)
2699 {
2700 if (use_is_media (cpu, dual_FRk))
2701 {
2702 busy_adjustment[2] = 2;
2703 decrease_FR_busy (cpu, dual_FRk, busy_adjustment[2]);
2704 }
2705 else
2706 enforce_full_fr_latency (cpu, dual_FRk);
2707 }
2708
2709 /* The post processing must wait if there is a dependency on a FR
2710 which is not ready yet. */
2711 ps->post_wait = cycles;
2712 post_wait_for_FR (cpu, in_FRi);
2713 post_wait_for_FR (cpu, out_FRk);
2714 post_wait_for_FR (cpu, dual_FRk);
2715
2716 /* Restore the busy cycles of the registers we used. */
2717 fr = ps->fr_busy;
2718 fr[in_FRi] += busy_adjustment[0];
2719 fr[out_FRk] += busy_adjustment[1];
2720 if (dual_FRk >= 0)
2721 fr[dual_FRk] += busy_adjustment[2];
2722
1c453cd6 2723 /* The latency of the output register will be at least the latency of the
b34f6357
DB		 2724 other inputs. Once initiated, post-processing will take 3 cycles. */
2725 update_FR_latency (cpu, out_FRk, ps->post_wait);
2726 update_FR_ptime (cpu, out_FRk, 3);
2727
2728 /* Mark this use of the register as a media op. */
2729 set_use_is_media (cpu, out_FRk);
2730 if (dual_FRk >= 0)
2731 {
2732 update_FR_latency (cpu, dual_FRk, ps->post_wait);
2733 update_FR_ptime (cpu, dual_FRk, 3);
2734
2735 /* Mark this use of the register as a media op. */
2736 set_use_is_media (cpu, dual_FRk);
2737 }
2738
2739 return cycles;
2740}
2741
2742int
2743frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *cpu, const IDESC *idesc,
2744 int unit_num, int referenced,
2745 INT in_FRi,
2746 INT out_FRk)
2747{
2748 int cycles;
2749 INT FRi_1;
2750 INT FRk_1;
2751 INT FRk_2;
2752 INT FRk_3;
2753 FRV_PROFILE_STATE *ps;
2754 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2755 int *fr;
2756
2757 if (model_insn == FRV_INSN_MODEL_PASS_1)
2758 return 0;
2759
2760 /* The preprocessing can execute right away. */
2761 cycles = idesc->timing->units[unit_num].done;
2762
2763 FRi_1 = DUAL_REG (in_FRi);
2764 FRk_1 = DUAL_REG (out_FRk);
2765 FRk_2 = DUAL_REG (FRk_1);
2766 FRk_3 = DUAL_REG (FRk_2);
2767
2768 /* If the previous use of the registers was a media op,
2769 then their latency will be less than previously recorded.
2770 See Table 13-13 in the LSI. */
2771 ps = CPU_PROFILE_STATE (cpu);
2772 if (use_is_media (cpu, in_FRi))
2773 {
2774 busy_adjustment[0] = 2;
2775 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2776 }
2777 else
2778 enforce_full_fr_latency (cpu, in_FRi);
2779 if (FRi_1 >= 0 && use_is_media (cpu, FRi_1))
2780 {
2781 busy_adjustment[1] = 2;
2782 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2783 }
2784 else
2785 enforce_full_fr_latency (cpu, FRi_1);
2786 if (out_FRk != in_FRi)
2787 {
2788 if (use_is_media (cpu, out_FRk))
2789 {
2790 busy_adjustment[2] = 2;
2791 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
2792 }
2793 else
2794 enforce_full_fr_latency (cpu, out_FRk);
2795 if (FRk_1 >= 0 && FRk_1 != in_FRi)
2796 {
2797 if (use_is_media (cpu, FRk_1))
2798 {
2799 busy_adjustment[3] = 2;
2800 decrease_FR_busy (cpu, FRk_1, busy_adjustment[3]);
2801 }
2802 else
2803 enforce_full_fr_latency (cpu, FRk_1);
2804 }
2805 if (FRk_2 >= 0 && FRk_2 != in_FRi)
2806 {
2807 if (use_is_media (cpu, FRk_2))
2808 {
2809 busy_adjustment[4] = 2;
2810 decrease_FR_busy (cpu, FRk_2, busy_adjustment[4]);
2811 }
2812 else
2813 enforce_full_fr_latency (cpu, FRk_2);
2814 }
2815 if (FRk_3 >= 0 && FRk_3 != in_FRi)
2816 {
2817 if (use_is_media (cpu, FRk_3))
2818 {
2819 busy_adjustment[5] = 2;
2820 decrease_FR_busy (cpu, FRk_3, busy_adjustment[5]);
2821 }
2822 else
2823 enforce_full_fr_latency (cpu, FRk_3);
2824 }
2825 }
2826
2827 /* The post processing must wait if there is a dependency on a FR
2828 which is not ready yet. */
2829 ps->post_wait = cycles;
2830 post_wait_for_FR (cpu, in_FRi);
2831 post_wait_for_FR (cpu, FRi_1);
2832 post_wait_for_FR (cpu, out_FRk);
2833 post_wait_for_FR (cpu, FRk_1);
2834 post_wait_for_FR (cpu, FRk_2);
2835 post_wait_for_FR (cpu, FRk_3);
2836
2837 /* Restore the busy cycles of the registers we used. */
2838 fr = ps->fr_busy;
2839 fr[in_FRi] += busy_adjustment[0];
2840 if (FRi_1 >= 0)
2841 fr[FRi_1] += busy_adjustment[1];
2842 fr[out_FRk] += busy_adjustment[2];
2843 if (FRk_1 >= 0)
2844 fr[FRk_1] += busy_adjustment[3];
2845 if (FRk_2 >= 0)
2846 fr[FRk_2] += busy_adjustment[4];
2847 if (FRk_3 >= 0)
2848 fr[FRk_3] += busy_adjustment[5];
2849
2850 /* The latency of tht output register will be at least the latency of the
2851 other inputs. Once initiated, post-processing will take 3 cycles. */
2852 update_FR_latency (cpu, out_FRk, ps->post_wait);
2853 update_FR_ptime (cpu, out_FRk, 3);
2854
2855 /* Mark this use of the register as a media op. */
2856 set_use_is_media (cpu, out_FRk);
2857 if (FRk_1 >= 0)
2858 {
2859 update_FR_latency (cpu, FRk_1, ps->post_wait);
2860 update_FR_ptime (cpu, FRk_1, 3);
2861
2862 /* Mark this use of the register as a media op. */
2863 set_use_is_media (cpu, FRk_1);
2864 }
2865 if (FRk_2 >= 0)
2866 {
2867 update_FR_latency (cpu, FRk_2, ps->post_wait);
2868 update_FR_ptime (cpu, FRk_2, 3);
2869
2870 /* Mark this use of the register as a media op. */
2871 set_use_is_media (cpu, FRk_2);
2872 }
2873 if (FRk_3 >= 0)
2874 {
2875 update_FR_latency (cpu, FRk_3, ps->post_wait);
2876 update_FR_ptime (cpu, FRk_3, 3);
2877
2878 /* Mark this use of the register as a media op. */
2879 set_use_is_media (cpu, FRk_3);
2880 }
2881
2882 return cycles;
2883}
2884
2885int
2886frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *cpu, const IDESC *idesc,
2887 int unit_num, int referenced,
2888 INT in_FRj,
2889 INT out_FRk)
2890{
2891 return frvbf_model_fr500_u_media_dual_expand (cpu, idesc, unit_num,
2892 referenced, in_FRj, out_FRk);
2893}
2894
2895int
2896frvbf_model_fr500_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
2897 int unit_num, int referenced,
2898 INT in_FRj,
2899 INT out_FRk)
2900{
2901 int cycles;
2902 INT dual_FRj;
2903 FRV_PROFILE_STATE *ps;
2904 int busy_adjustment[] = {0, 0, 0};
2905 int *fr;
2906
2907 if (model_insn == FRV_INSN_MODEL_PASS_1)
2908 return 0;
2909
2910 /* The preprocessing can execute right away. */
2911 cycles = idesc->timing->units[unit_num].done;
2912
2913 /* If the previous use of the registers was a media op,
2914 then their latency will be less than previously recorded.
2915 See Table 13-13 in the LSI. */
2916 dual_FRj = DUAL_REG (in_FRj);
2917 ps = CPU_PROFILE_STATE (cpu);
2918 if (use_is_media (cpu, in_FRj))
2919 {
2920 busy_adjustment[0] = 2;
2921 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
2922 }
2923 else
2924 enforce_full_fr_latency (cpu, in_FRj);
2925 if (dual_FRj >= 0)
2926 {
2927 if (use_is_media (cpu, dual_FRj))
2928 {
2929 busy_adjustment[1] = 2;
2930 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]);
2931 }
2932 else
2933 enforce_full_fr_latency (cpu, dual_FRj);
2934 }
2935 if (out_FRk != in_FRj)
2936 {
2937 if (use_is_media (cpu, out_FRk))
2938 {
2939 busy_adjustment[2] = 2;
2940 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
2941 }
2942 else
2943 enforce_full_fr_latency (cpu, out_FRk);
2944 }
2945
2946 /* The post processing must wait if there is a dependency on a FR
2947 which is not ready yet. */
2948 ps->post_wait = cycles;
2949 post_wait_for_FR (cpu, in_FRj);
2950 post_wait_for_FR (cpu, dual_FRj);
2951 post_wait_for_FR (cpu, out_FRk);
2952
2953 /* Restore the busy cycles of the registers we used. */
2954 fr = ps->fr_busy;
2955 fr[in_FRj] += busy_adjustment[0];
2956 if (dual_FRj >= 0)
2957 fr[dual_FRj] += busy_adjustment[1];
2958 fr[out_FRk] += busy_adjustment[2];
2959
2960 /* The latency of tht output register will be at least the latency of the
2961 other inputs. */
2962 update_FR_latency (cpu, out_FRk, ps->post_wait);
2963
2964 /* Once initiated, post-processing will take 3 cycles. */
2965 update_FR_ptime (cpu, out_FRk, 3);
2966
2967 /* Mark this use of the register as a media op. */
2968 set_use_is_media (cpu, out_FRk);
2969
2970 return cycles;
2971}
2972
2973int
2974frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *cpu, const IDESC *idesc,
2975 int unit_num, int referenced,
2976 INT in_FRj,
2977 INT out_FRk)
2978{
2979 int cycles;
2980 INT FRk_1;
2981 INT FRk_2;
2982 INT FRk_3;
2983 FRV_PROFILE_STATE *ps;
2984 int busy_adjustment[] = {0, 0, 0, 0, 0};
2985 int *fr;
2986
2987 if (model_insn == FRV_INSN_MODEL_PASS_1)
2988 return 0;
2989
2990 /* The preprocessing can execute right away. */
2991 cycles = idesc->timing->units[unit_num].done;
2992
2993 FRk_1 = DUAL_REG (out_FRk);
2994 FRk_2 = DUAL_REG (FRk_1);
2995 FRk_3 = DUAL_REG (FRk_2);
2996
2997 /* If the previous use of the registers was a media op,
2998 then their latency will be less than previously recorded.
2999 See Table 13-13 in the LSI. */
3000 ps = CPU_PROFILE_STATE (cpu);
3001 if (use_is_media (cpu, in_FRj))
3002 {
3003 busy_adjustment[0] = 2;
3004 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
3005 }
3006 else
3007 enforce_full_fr_latency (cpu, in_FRj);
3008 if (out_FRk != in_FRj)
3009 {
3010 if (use_is_media (cpu, out_FRk))
3011 {
3012 busy_adjustment[1] = 2;
3013 decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]);
3014 }
3015 else
3016 enforce_full_fr_latency (cpu, out_FRk);
3017 if (FRk_1 >= 0 && FRk_1 != in_FRj)
3018 {
3019 if (use_is_media (cpu, FRk_1))
3020 {
3021 busy_adjustment[2] = 2;
3022 decrease_FR_busy (cpu, FRk_1, busy_adjustment[2]);
3023 }
3024 else
3025 enforce_full_fr_latency (cpu, FRk_1);
3026 }
3027 if (FRk_2 >= 0 && FRk_2 != in_FRj)
3028 {
3029 if (use_is_media (cpu, FRk_2))
3030 {
3031 busy_adjustment[3] = 2;
3032 decrease_FR_busy (cpu, FRk_2, busy_adjustment[3]);
3033 }
3034 else
3035 enforce_full_fr_latency (cpu, FRk_2);
3036 }
3037 if (FRk_3 >= 0 && FRk_3 != in_FRj)
3038 {
3039 if (use_is_media (cpu, FRk_3))
3040 {
3041 busy_adjustment[4] = 2;
3042 decrease_FR_busy (cpu, FRk_3, busy_adjustment[4]);
3043 }
3044 else
3045 enforce_full_fr_latency (cpu, FRk_3);
3046 }
3047 }
3048
3049 /* The post processing must wait if there is a dependency on a FR
3050 which is not ready yet. */
3051 ps->post_wait = cycles;
3052 post_wait_for_FR (cpu, in_FRj);
3053 post_wait_for_FR (cpu, out_FRk);
3054 post_wait_for_FR (cpu, FRk_1);
3055 post_wait_for_FR (cpu, FRk_2);
3056 post_wait_for_FR (cpu, FRk_3);
3057
3058 /* Restore the busy cycles of the registers we used. */
3059 fr = ps->fr_busy;
3060 fr[in_FRj] += busy_adjustment[0];
3061 fr[out_FRk] += busy_adjustment[1];
3062 if (FRk_1 >= 0)
3063 fr[FRk_1] += busy_adjustment[2];
3064 if (FRk_2 >= 0)
3065 fr[FRk_2] += busy_adjustment[3];
3066 if (FRk_3 >= 0)
3067 fr[FRk_3] += busy_adjustment[4];
3068
3069 /* The latency of tht output register will be at least the latency of the
3070 other inputs. Once initiated, post-processing will take 3 cycles. */
3071 update_FR_latency (cpu, out_FRk, ps->post_wait);
3072 update_FR_ptime (cpu, out_FRk, 3);
3073
3074 /* Mark this use of the register as a media op. */
3075 set_use_is_media (cpu, out_FRk);
3076 if (FRk_1 >= 0)
3077 {
3078 update_FR_latency (cpu, FRk_1, ps->post_wait);
3079 update_FR_ptime (cpu, FRk_1, 3);
3080
3081 /* Mark this use of the register as a media op. */
3082 set_use_is_media (cpu, FRk_1);
3083 }
3084 if (FRk_2 >= 0)
3085 {
3086 update_FR_latency (cpu, FRk_2, ps->post_wait);
3087 update_FR_ptime (cpu, FRk_2, 3);
3088
3089 /* Mark this use of the register as a media op. */
3090 set_use_is_media (cpu, FRk_2);
3091 }
3092 if (FRk_3 >= 0)
3093 {
3094 update_FR_latency (cpu, FRk_3, ps->post_wait);
3095 update_FR_ptime (cpu, FRk_3, 3);
3096
3097 /* Mark this use of the register as a media op. */
3098 set_use_is_media (cpu, FRk_3);
3099 }
3100
3101 return cycles;
3102}
3103
3104int
3105frvbf_model_fr500_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
3106 int unit_num, int referenced)
3107{
3108 int cycles;
3109 if (model_insn == FRV_INSN_MODEL_PASS_1)
3110 {
3111 int i;
3112 /* Wait for ALL resources. */
3113 for (i = 0; i < 64; ++i)
3114 {
3115 enforce_full_fr_latency (cpu, i);
3116 vliw_wait_for_GR (cpu, i);
3117 vliw_wait_for_FR (cpu, i);
3118 vliw_wait_for_ACC (cpu, i);
3119 }
3120 for (i = 0; i < 8; ++i)
3121 vliw_wait_for_CCR (cpu, i);
3122 for (i = 0; i < 2; ++i)
3123 {
3124 vliw_wait_for_idiv_resource (cpu, i);
3125 vliw_wait_for_fdiv_resource (cpu, i);
3126 vliw_wait_for_fsqrt_resource (cpu, i);
3127 }
3128 handle_resource_wait (cpu);
3129 for (i = 0; i < 64; ++i)
3130 {
3131 load_wait_for_GR (cpu, i);
3132 load_wait_for_FR (cpu, i);
3133 }
3134 trace_vliw_wait_cycles (cpu);
3135 return 0;
3136 }
3137
3138 cycles = idesc->timing->units[unit_num].done;
3139 return cycles;
3140}
3141
3142int
3143frvbf_model_fr500_u_membar (SIM_CPU *cpu, const IDESC *idesc,
3144 int unit_num, int referenced)
3145{
3146 int cycles;
3147 if (model_insn == FRV_INSN_MODEL_PASS_1)
3148 {
3149 int i;
3150 /* Wait for ALL resources, except GR and ICC. */
3151 for (i = 0; i < 64; ++i)
3152 {
3153 enforce_full_fr_latency (cpu, i);
3154 vliw_wait_for_FR (cpu, i);
3155 vliw_wait_for_ACC (cpu, i);
3156 }
3157 for (i = 0; i < 4; ++i)
3158 vliw_wait_for_CCR (cpu, i);
3159 for (i = 0; i < 2; ++i)
3160 {
3161 vliw_wait_for_idiv_resource (cpu, i);
3162 vliw_wait_for_fdiv_resource (cpu, i);
3163 vliw_wait_for_fsqrt_resource (cpu, i);
3164 }
3165 handle_resource_wait (cpu);
3166 for (i = 0; i < 64; ++i)
3167 {
3168 load_wait_for_FR (cpu, i);
3169 }
3170 trace_vliw_wait_cycles (cpu);
3171 return 0;
3172 }
3173
3174 cycles = idesc->timing->units[unit_num].done;
3175 return cycles;
3176}
3177
3178/* The frv machine is a fictional implementation of the fr500 which implements
3179 all frv architectural features. */
3180int
3181frvbf_model_frv_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3182 int unit_num, int referenced)
3183{
3184 return idesc->timing->units[unit_num].done;
3185}
3186
3187/* The simple machine is a fictional implementation of the fr500 which
3188 implements limited frv architectural features. */
3189int
3190frvbf_model_simple_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3191 int unit_num, int referenced)
3192{
3193 return idesc->timing->units[unit_num].done;
3194}
3195
3196/* The tomcat machine is models a prototype fr500 machine which had a few
3197 bugs and restrictions to work around. */
3198int
3199frvbf_model_tomcat_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3200 int unit_num, int referenced)
3201{
3202 return idesc->timing->units[unit_num].done;
3203}
3204
3205#endif /* WITH_PROFILE_MODEL_P */
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