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[thirdparty/binutils-gdb.git] / sim / frv / profile-fr500.c
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b34f6357
DB		 1/* frv simulator fr500 dependent profiling code.
2
e2882c85 3 Copyright (C) 1998-2018 Free Software Foundation, Inc.
b34f6357
DB		 4 Contributed by Red Hat
5
6This file is part of the GNU simulators.
7
8This program is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
4744ac1b
JB		 10the Free Software Foundation; either version 3 of the License, or
11(at your option) any later version.
b34f6357
DB		 12
13This program is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
4744ac1b
JB		 18You should have received a copy of the GNU General Public License
19along with this program. If not, see <http://www.gnu.org/licenses/>.
b34f6357
DB		 20
21*/
22#define WANT_CPU
23#define WANT_CPU_FRVBF
24
25#include "sim-main.h"
26#include "bfd.h"
27
28#if WITH_PROFILE_MODEL_P
29
30#include "profile.h"
31#include "profile-fr500.h"
32
33/* Initialize cycle counting for an insn.
34 FIRST_P is non-zero if this is the first insn in a set of parallel
35 insns. */
36void
37fr500_model_insn_before (SIM_CPU *cpu, int first_p)
38{
39 if (first_p)
40 {
41 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
42 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
43 ps->cur_gr_complex = ps->prev_gr_complex;
44 d->cur_fpop = d->prev_fpop;
45 d->cur_media = d->prev_media;
46 d->cur_cc_complex = d->prev_cc_complex;
47 }
48}
49
50/* Record the cycles computed for an insn.
51 LAST_P is non-zero if this is the last insn in a set of parallel insns,
52 and we update the total cycle count.
53 CYCLES is the cycle count of the insn. */
54void
55fr500_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
56{
57 if (last_p)
58 {
59 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
60 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
61 ps->prev_gr_complex = ps->cur_gr_complex;
62 d->prev_fpop = d->cur_fpop;
63 d->prev_media = d->cur_media;
64 d->prev_cc_complex = d->cur_cc_complex;
65 }
66}
67
68static void
69set_use_is_fpop (SIM_CPU *cpu, INT fr)
70{
71 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
72 fr500_reset_fr_flags (cpu, (fr));
73 d->cur_fpop |= (((DI)1) << (fr));
74}
75
76static void
77set_use_not_fpop (SIM_CPU *cpu, INT fr)
78{
79 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
80 d->cur_fpop &= ~(((DI)1) << (fr));
81}
82
83static int
84use_is_fpop (SIM_CPU *cpu, INT fr)
85{
86 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
87 return d->prev_fpop & (((DI)1) << (fr));
88}
89
90static void
91set_use_is_media ( SIM_CPU *cpu, INT fr)
92{
93 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
94 fr500_reset_fr_flags (cpu, (fr));
95 d->cur_media |= (((DI)1) << (fr));
96}
97
98static void
99set_use_not_media (SIM_CPU *cpu, INT fr)
100{
101 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
102 d->cur_media &= ~(((DI)1) << (fr));
103}
104
105static int
106use_is_media (SIM_CPU *cpu, INT fr)
107{
108 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
109 return d->prev_media & (((DI)1) << (fr));
110}
111
112static void
113set_use_is_cc_complex (SIM_CPU *cpu, INT cc)
114{
115 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
116 fr500_reset_cc_flags (cpu, cc);
117 d->cur_cc_complex |= (((DI)1) << (cc));
118}
119
120static void
121set_use_not_cc_complex (SIM_CPU *cpu, INT cc)
122{
123 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
124 d->cur_cc_complex &= ~(((DI)1) << (cc));
125}
126
127static int
128use_is_cc_complex (SIM_CPU *cpu, INT cc)
129{
130 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
131 return d->prev_cc_complex & (((DI)1) << (cc));
132}
133
134void
135fr500_reset_fr_flags (SIM_CPU *cpu, INT fr)
136{
137 set_use_not_fpop (cpu, fr);
138 set_use_not_media (cpu, fr);
139}
140
141void
142fr500_reset_cc_flags (SIM_CPU *cpu, INT cc)
143{
144 set_use_not_cc_complex (cpu, cc);
145}
146
147/* Latency of floating point registers may be less than recorded when followed
148 by another floating point insn. */
149static void
150adjust_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
151 int cycles)
152{
153 /* If the registers were previously used in a floating point op,
154 then their latency will be less than previously recorded.
155 See Table 13-13 in the LSI. */
156 if (in_FRi >= 0)
157 if (use_is_fpop (cpu, in_FRi))
158 decrease_FR_busy (cpu, in_FRi, cycles);
159 else
160 enforce_full_fr_latency (cpu, in_FRi);
161
162 if (in_FRj >= 0 && in_FRj != in_FRi)
163 if (use_is_fpop (cpu, in_FRj))
164 decrease_FR_busy (cpu, in_FRj, cycles);
165 else
166 enforce_full_fr_latency (cpu, in_FRj);
167
168 if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
169 if (use_is_fpop (cpu, out_FRk))
170 decrease_FR_busy (cpu, out_FRk, cycles);
171 else
172 enforce_full_fr_latency (cpu, out_FRk);
173}
174
175/* Latency of floating point registers may be less than recorded when followed
176 by another floating point insn. */
177static void
178adjust_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
179 int cycles)
180{
181 /* If the registers were previously used in a floating point op,
182 then their latency will be less than previously recorded.
183 See Table 13-13 in the LSI. */
184 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
185 if (in_FRi >= 0) ++in_FRi;
186 if (in_FRj >= 0) ++in_FRj;
187 if (out_FRk >= 0) ++out_FRk;
188 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
189}
190
191/* Latency of floating point registers is less than recorded when followed
192 by another floating point insn. */
193static void
194restore_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
195 int cycles)
196{
197 /* If the registers were previously used in a floating point op,
198 then their latency will be less than previously recorded.
199 See Table 13-13 in the LSI. */
200 if (in_FRi >= 0 && use_is_fpop (cpu, in_FRi))
201 increase_FR_busy (cpu, in_FRi, cycles);
202 if (in_FRj != in_FRi && use_is_fpop (cpu, in_FRj))
203 increase_FR_busy (cpu, in_FRj, cycles);
204 if (out_FRk != in_FRi && out_FRk != in_FRj && use_is_fpop (cpu, out_FRk))
205 increase_FR_busy (cpu, out_FRk, cycles);
206}
207
208/* Latency of floating point registers is less than recorded when followed
209 by another floating point insn. */
210static void
211restore_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
212 int cycles)
213{
214 /* If the registers were previously used in a floating point op,
215 then their latency will be less than previously recorded.
216 See Table 13-13 in the LSI. */
217 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
218 if (in_FRi >= 0) ++in_FRi;
219 if (in_FRj >= 0) ++in_FRj;
220 if (out_FRk >= 0) ++out_FRk;
221 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
222}
223
224int
225frvbf_model_fr500_u_exec (SIM_CPU *cpu, const IDESC *idesc,
226 int unit_num, int referenced)
227{
228 return idesc->timing->units[unit_num].done;
229}
230
231int
232frvbf_model_fr500_u_integer (SIM_CPU *cpu, const IDESC *idesc,
233 int unit_num, int referenced,
234 INT in_GRi, INT in_GRj, INT out_GRk,
235 INT out_ICCi_1)
236{
237 int cycles;
238
239 if (model_insn == FRV_INSN_MODEL_PASS_1)
240 {
241 /* icc0-icc4 are the upper 4 fields of the CCR. */
242 if (out_ICCi_1 >= 0)
243 out_ICCi_1 += 4;
244
245 /* The entire VLIW insn must wait if there is a dependency on a register
246 which is not ready yet.
247 The latency of the registers may be less than previously recorded,
248 depending on how they were used previously.
249 See Table 13-8 in the LSI. */
250 if (in_GRi != out_GRk && in_GRi >= 0)
251 {
252 if (use_is_gr_complex (cpu, in_GRi))
253 decrease_GR_busy (cpu, in_GRi, 1);
254 }
255 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
256 {
257 if (use_is_gr_complex (cpu, in_GRj))
258 decrease_GR_busy (cpu, in_GRj, 1);
259 }
260 vliw_wait_for_GR (cpu, in_GRi);
261 vliw_wait_for_GR (cpu, in_GRj);
262 vliw_wait_for_GR (cpu, out_GRk);
263 vliw_wait_for_CCR (cpu, out_ICCi_1);
264 handle_resource_wait (cpu);
265 load_wait_for_GR (cpu, in_GRi);
266 load_wait_for_GR (cpu, in_GRj);
267 load_wait_for_GR (cpu, out_GRk);
268 trace_vliw_wait_cycles (cpu);
269 return 0;
270 }
271
272 /* GRk is available immediately to the next VLIW insn as is ICCi_1. */
273 cycles = idesc->timing->units[unit_num].done;
274 return cycles;
275}
276
277int
278frvbf_model_fr500_u_imul (SIM_CPU *cpu, const IDESC *idesc,
279 int unit_num, int referenced,
280 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
281{
282 int cycles;
283 /* icc0-icc4 are the upper 4 fields of the CCR. */
284 if (out_ICCi_1 >= 0)
285 out_ICCi_1 += 4;
286
287 if (model_insn == FRV_INSN_MODEL_PASS_1)
288 {
289 /* The entire VLIW insn must wait if there is a dependency on a register
290 which is not ready yet.
291 The latency of the registers may be less than previously recorded,
292 depending on how they were used previously.
293 See Table 13-8 in the LSI. */
294 if (in_GRi != out_GRk && in_GRi >= 0)
295 {
296 if (use_is_gr_complex (cpu, in_GRi))
297 decrease_GR_busy (cpu, in_GRi, 1);
298 }
299 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
300 {
301 if (use_is_gr_complex (cpu, in_GRj))
302 decrease_GR_busy (cpu, in_GRj, 1);
303 }
304 vliw_wait_for_GR (cpu, in_GRi);
305 vliw_wait_for_GR (cpu, in_GRj);
306 vliw_wait_for_GRdouble (cpu, out_GRk);
307 vliw_wait_for_CCR (cpu, out_ICCi_1);
308 handle_resource_wait (cpu);
309 load_wait_for_GR (cpu, in_GRi);
310 load_wait_for_GR (cpu, in_GRj);
311 load_wait_for_GRdouble (cpu, out_GRk);
312 trace_vliw_wait_cycles (cpu);
313 return 0;
314 }
315
316 /* GRk has a latency of 2 cycles. */
317 cycles = idesc->timing->units[unit_num].done;
318 update_GRdouble_latency (cpu, out_GRk, cycles + 2);
319 set_use_is_gr_complex (cpu, out_GRk);
320 set_use_is_gr_complex (cpu, out_GRk + 1);
321
322 /* ICCi_1 has a latency of 1 cycle. */
323 update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
324
325 return cycles;
326}
327
328int
329frvbf_model_fr500_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
330 int unit_num, int referenced,
331 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
332{
333 int cycles;
334 FRV_VLIW *vliw;
335 int slot;
336
337 /* icc0-icc4 are the upper 4 fields of the CCR. */
338 if (out_ICCi_1 >= 0)
339 out_ICCi_1 += 4;
340
341 vliw = CPU_VLIW (cpu);
342 slot = vliw->next_slot - 1;
343 slot = (*vliw->current_vliw)[slot] - UNIT_I0;
344
345 if (model_insn == FRV_INSN_MODEL_PASS_1)
346 {
347 /* The entire VLIW insn must wait if there is a dependency on a register
348 which is not ready yet.
349 The latency of the registers may be less than previously recorded,
350 depending on how they were used previously.
351 See Table 13-8 in the LSI. */
352 if (in_GRi != out_GRk && in_GRi >= 0)
353 {
354 if (use_is_gr_complex (cpu, in_GRi))
355 decrease_GR_busy (cpu, in_GRi, 1);
356 }
357 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
358 {
359 if (use_is_gr_complex (cpu, in_GRj))
360 decrease_GR_busy (cpu, in_GRj, 1);
361 }
362 vliw_wait_for_GR (cpu, in_GRi);
363 vliw_wait_for_GR (cpu, in_GRj);
364 vliw_wait_for_GR (cpu, out_GRk);
365 vliw_wait_for_CCR (cpu, out_ICCi_1);
366 vliw_wait_for_idiv_resource (cpu, slot);
367 handle_resource_wait (cpu);
368 load_wait_for_GR (cpu, in_GRi);
369 load_wait_for_GR (cpu, in_GRj);
370 load_wait_for_GR (cpu, out_GRk);
371 trace_vliw_wait_cycles (cpu);
372 return 0;
373 }
374
375 /* GRk has a latency of 19 cycles! */
376 cycles = idesc->timing->units[unit_num].done;
377 update_GR_latency (cpu, out_GRk, cycles + 19);
378 set_use_is_gr_complex (cpu, out_GRk);
379
380 /* ICCi_1 has a latency of 19 cycles. */
381 update_CCR_latency (cpu, out_ICCi_1, cycles + 19);
382 set_use_is_cc_complex (cpu, out_ICCi_1);
383
153431d6
DB		 384 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
385 {
386 /* GNER has a latency of 18 cycles. */
387 update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 18);
388 }
389
b34f6357
DB		 390 /* the idiv resource has a latency of 18 cycles! */
391 update_idiv_resource_latency (cpu, slot, cycles + 18);
392
393 return cycles;
394}
395
396int
397frvbf_model_fr500_u_branch (SIM_CPU *cpu, const IDESC *idesc,
398 int unit_num, int referenced,
399 INT in_GRi, INT in_GRj,
400 INT in_ICCi_2, INT in_FCCi_2)
401{
402 int cycles;
403 FRV_PROFILE_STATE *ps;
404
405 if (model_insn == FRV_INSN_MODEL_PASS_1)
406 {
407 /* icc0-icc4 are the upper 4 fields of the CCR. */
408 if (in_ICCi_2 >= 0)
409 in_ICCi_2 += 4;
410
411 /* The entire VLIW insn must wait if there is a dependency on a register
412 which is not ready yet.
413 The latency of the registers may be less than previously recorded,
414 depending on how they were used previously.
415 See Table 13-8 in the LSI. */
416 if (in_GRi >= 0)
417 {
418 if (use_is_gr_complex (cpu, in_GRi))
419 decrease_GR_busy (cpu, in_GRi, 1);
420 }
421 if (in_GRj != in_GRi && in_GRj >= 0)
422 {
423 if (use_is_gr_complex (cpu, in_GRj))
424 decrease_GR_busy (cpu, in_GRj, 1);
425 }
426 vliw_wait_for_GR (cpu, in_GRi);
427 vliw_wait_for_GR (cpu, in_GRj);
428 vliw_wait_for_CCR (cpu, in_ICCi_2);
429 vliw_wait_for_CCR (cpu, in_FCCi_2);
430 handle_resource_wait (cpu);
431 load_wait_for_GR (cpu, in_GRi);
432 load_wait_for_GR (cpu, in_GRj);
433 trace_vliw_wait_cycles (cpu);
434 return 0;
435 }
436
437 /* When counting branches taken or not taken, don't consider branches after
438 the first taken branch in a vliw insn. */
439 ps = CPU_PROFILE_STATE (cpu);
440 if (! ps->vliw_branch_taken)
441 {
442 /* (1 << 4): The pc is the 5th element in inputs, outputs.
443 ??? can be cleaned up */
444 PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
445 int taken = (referenced & (1 << 4)) != 0;
446 if (taken)
447 {
448 ++PROFILE_MODEL_TAKEN_COUNT (p);
449 ps->vliw_branch_taken = 1;
450 }
451 else
452 ++PROFILE_MODEL_UNTAKEN_COUNT (p);
453 }
454
455 cycles = idesc->timing->units[unit_num].done;
456 return cycles;
457}
458
459int
460frvbf_model_fr500_u_trap (SIM_CPU *cpu, const IDESC *idesc,
461 int unit_num, int referenced,
462 INT in_GRi, INT in_GRj,
463 INT in_ICCi_2, INT in_FCCi_2)
464{
465 int cycles;
b34f6357
DB		 466
467 if (model_insn == FRV_INSN_MODEL_PASS_1)
468 {
469 /* icc0-icc4 are the upper 4 fields of the CCR. */
470 if (in_ICCi_2 >= 0)
471 in_ICCi_2 += 4;
472
473 /* The entire VLIW insn must wait if there is a dependency on a register
474 which is not ready yet.
475 The latency of the registers may be less than previously recorded,
476 depending on how they were used previously.
477 See Table 13-8 in the LSI. */
478 if (in_GRi >= 0)
479 {
480 if (use_is_gr_complex (cpu, in_GRi))
481 decrease_GR_busy (cpu, in_GRi, 1);
482 }
483 if (in_GRj != in_GRi && in_GRj >= 0)
484 {
485 if (use_is_gr_complex (cpu, in_GRj))
486 decrease_GR_busy (cpu, in_GRj, 1);
487 }
488 vliw_wait_for_GR (cpu, in_GRi);
489 vliw_wait_for_GR (cpu, in_GRj);
490 vliw_wait_for_CCR (cpu, in_ICCi_2);
491 vliw_wait_for_CCR (cpu, in_FCCi_2);
492 handle_resource_wait (cpu);
493 load_wait_for_GR (cpu, in_GRi);
494 load_wait_for_GR (cpu, in_GRj);
495 trace_vliw_wait_cycles (cpu);
496 return 0;
497 }
498
499 cycles = idesc->timing->units[unit_num].done;
500 return cycles;
501}
502
503int
504frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc,
505 int unit_num, int referenced,
506 INT in_ICCi_3, INT in_FCCi_3)
507{
508 int cycles;
b34f6357
DB		 509
510 if (model_insn == FRV_INSN_MODEL_PASS_1)
511 {
512 /* icc0-icc4 are the upper 4 fields of the CCR. */
513 if (in_ICCi_3 >= 0)
514 in_ICCi_3 += 4;
515
516 /* The entire VLIW insn must wait if there is a dependency on a register
517 which is not ready yet. */
518 vliw_wait_for_CCR (cpu, in_ICCi_3);
519 vliw_wait_for_CCR (cpu, in_FCCi_3);
520 handle_resource_wait (cpu);
521 trace_vliw_wait_cycles (cpu);
522 return 0;
523 }
524
525 cycles = idesc->timing->units[unit_num].done;
526 return cycles;
527}
528
153431d6
DB		 529int
530frvbf_model_fr500_u_clrgr (SIM_CPU *cpu, const IDESC *idesc,
531 int unit_num, int referenced,
532 INT in_GRk)
533{
534 int cycles;
535
536 if (model_insn == FRV_INSN_MODEL_PASS_1)
537 {
538 /* Wait for both GNER registers or just the one specified. */
539 if (in_GRk == -1)
540 {
541 vliw_wait_for_SPR (cpu, H_SPR_GNER0);
542 vliw_wait_for_SPR (cpu, H_SPR_GNER1);
543 }
544 else
545 vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk));
546 handle_resource_wait (cpu);
547 trace_vliw_wait_cycles (cpu);
548 return 0;
549 }
550
551 cycles = idesc->timing->units[unit_num].done;
552 return cycles;
553}
554
555int
556frvbf_model_fr500_u_clrfr (SIM_CPU *cpu, const IDESC *idesc,
557 int unit_num, int referenced,
558 INT in_FRk)
559{
560 int cycles;
561
562 if (model_insn == FRV_INSN_MODEL_PASS_1)
563 {
564 /* Wait for both GNER registers or just the one specified. */
565 if (in_FRk == -1)
566 {
567 vliw_wait_for_SPR (cpu, H_SPR_FNER0);
568 vliw_wait_for_SPR (cpu, H_SPR_FNER1);
569 }
570 else
571 vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk));
572 handle_resource_wait (cpu);
573 trace_vliw_wait_cycles (cpu);
574 return 0;
575 }
576
577 cycles = idesc->timing->units[unit_num].done;
578 return cycles;
579}
580
1c453cd6
DB		 581int
582frvbf_model_fr500_u_commit (SIM_CPU *cpu, const IDESC *idesc,
583 int unit_num, int referenced,
584 INT in_GRk, INT in_FRk)
585{
586 int cycles;
587
588 if (model_insn == FRV_INSN_MODEL_PASS_1)
589 {
590 /* If GR is specified, then FR is not and vice-versa. If neither is
591 then it's a commitga or commitfa. Check the insn attribute to
592 figure out which. */
593 if (in_GRk != -1)
594 vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk));
595 else if (in_FRk != -1)
596 vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk));
597 else if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_FR_ACCESS))
598 {
599 vliw_wait_for_SPR (cpu, H_SPR_FNER0);
600 vliw_wait_for_SPR (cpu, H_SPR_FNER1);
601 }
602 else
603 {
604 vliw_wait_for_SPR (cpu, H_SPR_GNER0);
605 vliw_wait_for_SPR (cpu, H_SPR_GNER1);
606 }
607 handle_resource_wait (cpu);
608 trace_vliw_wait_cycles (cpu);
609 return 0;
610 }
611
612 cycles = idesc->timing->units[unit_num].done;
613 return cycles;
614}
615
b34f6357
DB		 616int
617frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
618 int unit_num, int referenced,
619 INT out_GRkhi, INT out_GRklo)
620{
621 int cycles;
622
623 if (model_insn == FRV_INSN_MODEL_PASS_1)
624 {
625 /* The entire VLIW insn must wait if there is a dependency on a GR
626 which is not ready yet. */
627 vliw_wait_for_GR (cpu, out_GRkhi);
628 vliw_wait_for_GR (cpu, out_GRklo);
629 handle_resource_wait (cpu);
630 load_wait_for_GR (cpu, out_GRkhi);
631 load_wait_for_GR (cpu, out_GRklo);
632 trace_vliw_wait_cycles (cpu);
633 return 0;
634 }
635
636 /* GRk is available immediately to the next VLIW insn. */
637 cycles = idesc->timing->units[unit_num].done;
638
639 set_use_not_gr_complex (cpu, out_GRkhi);
640 set_use_not_gr_complex (cpu, out_GRklo);
641
642 return cycles;
643}
644
645int
646frvbf_model_fr500_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
647 int unit_num, int referenced,
648 INT in_GRi, INT in_GRj,
649 INT out_GRk, INT out_GRdoublek)
650{
651 int cycles;
652
653 if (model_insn == FRV_INSN_MODEL_PASS_1)
654 {
655 /* The entire VLIW insn must wait if there is a dependency on a register
656 which is not ready yet.
657 The latency of the registers may be less than previously recorded,
658 depending on how they were used previously.
659 See Table 13-8 in the LSI. */
660 if (in_GRi != out_GRk && in_GRi != out_GRdoublek
661 && in_GRi != out_GRdoublek + 1 && in_GRi >= 0)
662 {
663 if (use_is_gr_complex (cpu, in_GRi))
664 decrease_GR_busy (cpu, in_GRi, 1);
665 }
666 if (in_GRj != in_GRi && in_GRj != out_GRk && in_GRj != out_GRdoublek
667 && in_GRj != out_GRdoublek + 1 && in_GRj >= 0)
668
669 {
670 if (use_is_gr_complex (cpu, in_GRj))
671 decrease_GR_busy (cpu, in_GRj, 1);
672 }
673 vliw_wait_for_GR (cpu, in_GRi);
674 vliw_wait_for_GR (cpu, in_GRj);
675 vliw_wait_for_GR (cpu, out_GRk);
676 vliw_wait_for_GRdouble (cpu, out_GRdoublek);
677 handle_resource_wait (cpu);
678 load_wait_for_GR (cpu, in_GRi);
679 load_wait_for_GR (cpu, in_GRj);
680 load_wait_for_GR (cpu, out_GRk);
681 load_wait_for_GRdouble (cpu, out_GRdoublek);
682 trace_vliw_wait_cycles (cpu);
683 return 0;
684 }
685
686 cycles = idesc->timing->units[unit_num].done;
687
688 /* The latency of GRk for a load will depend on how long it takes to retrieve
689 the the data from the cache or memory. */
690 update_GR_latency_for_load (cpu, out_GRk, cycles);
691 update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
692
1c453cd6
DB		 693 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
694 {
695 /* GNER has a latency of 2 cycles. */
696 update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2);
697 update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2);
698 }
699
700 if (out_GRk >= 0)
701 set_use_is_gr_complex (cpu, out_GRk);
702 if (out_GRdoublek != -1)
703 {
704 set_use_is_gr_complex (cpu, out_GRdoublek);
705 set_use_is_gr_complex (cpu, out_GRdoublek + 1);
706 }
b34f6357
DB		 707
708 return cycles;
709}
710
711int
712frvbf_model_fr500_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
713 int unit_num, int referenced,
714 INT in_GRi, INT in_GRj,
715 INT in_GRk, INT in_GRdoublek)
716{
717 int cycles;
718
719 if (model_insn == FRV_INSN_MODEL_PASS_1)
720 {
721 /* The entire VLIW insn must wait if there is a dependency on a register
722 which is not ready yet.
723 The latency of the registers may be less than previously recorded,
724 depending on how they were used previously.
725 See Table 13-8 in the LSI. */
726 if (in_GRi >= 0)
727 {
728 if (use_is_gr_complex (cpu, in_GRi))
729 decrease_GR_busy (cpu, in_GRi, 1);
730 }
731 if (in_GRj != in_GRi && in_GRj >= 0)
732 {
733 if (use_is_gr_complex (cpu, in_GRj))
734 decrease_GR_busy (cpu, in_GRj, 1);
735 }
736 if (in_GRk != in_GRi && in_GRk != in_GRj && in_GRk >= 0)
737 {
738 if (use_is_gr_complex (cpu, in_GRk))
739 decrease_GR_busy (cpu, in_GRk, 1);
740 }
741 if (in_GRdoublek != in_GRi && in_GRdoublek != in_GRj
742 && in_GRdoublek + 1 != in_GRi && in_GRdoublek + 1 != in_GRj
743 && in_GRdoublek >= 0)
744 {
745 if (use_is_gr_complex (cpu, in_GRdoublek))
746 decrease_GR_busy (cpu, in_GRdoublek, 1);
747 if (use_is_gr_complex (cpu, in_GRdoublek + 1))
748 decrease_GR_busy (cpu, in_GRdoublek + 1, 1);
749 }
750 vliw_wait_for_GR (cpu, in_GRi);
751 vliw_wait_for_GR (cpu, in_GRj);
752 vliw_wait_for_GR (cpu, in_GRk);
753 vliw_wait_for_GRdouble (cpu, in_GRdoublek);
754 handle_resource_wait (cpu);
755 load_wait_for_GR (cpu, in_GRi);
756 load_wait_for_GR (cpu, in_GRj);
757 load_wait_for_GR (cpu, in_GRk);
758 load_wait_for_GRdouble (cpu, in_GRdoublek);
759 trace_vliw_wait_cycles (cpu);
760 return 0;
761 }
762
763 cycles = idesc->timing->units[unit_num].done;
764
765 return cycles;
766}
767
768int
769frvbf_model_fr500_u_gr_r_store (SIM_CPU *cpu, const IDESC *idesc,
770 int unit_num, int referenced,
771 INT in_GRi, INT in_GRj,
772 INT in_GRk, INT in_GRdoublek)
773{
774 int cycles = frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
775 in_GRi, in_GRj, in_GRk,
776 in_GRdoublek);
777
778 if (model_insn == FRV_INSN_MODEL_PASS_2)
779 {
780 if (CPU_RSTR_INVALIDATE(cpu))
781 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
782 }
783
784 return cycles;
785}
786
787int
788frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
789 int unit_num, int referenced,
790 INT in_GRi, INT in_GRj,
791 INT out_FRk, INT out_FRdoublek)
792{
793 int cycles;
794
795 if (model_insn == FRV_INSN_MODEL_PASS_1)
796 {
797 /* The entire VLIW insn must wait if there is a dependency on a register
798 which is not ready yet.
799 The latency of the registers may be less than previously recorded,
800 depending on how they were used previously.
801 See Table 13-8 in the LSI. */
802 if (in_GRi >= 0)
803 {
804 if (use_is_gr_complex (cpu, in_GRi))
805 decrease_GR_busy (cpu, in_GRi, 1);
806 }
807 if (in_GRj != in_GRi && in_GRj >= 0)
808 {
809 if (use_is_gr_complex (cpu, in_GRj))
810 decrease_GR_busy (cpu, in_GRj, 1);
811 }
812 if (out_FRk >= 0)
813 {
814 if (use_is_media (cpu, out_FRk))
815 decrease_FR_busy (cpu, out_FRk, 1);
816 else
817 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
818 }
819 if (out_FRdoublek >= 0)
820 {
821 if (use_is_media (cpu, out_FRdoublek))
822 decrease_FR_busy (cpu, out_FRdoublek, 1);
823 else
824 adjust_float_register_busy (cpu, -1, -1, out_FRdoublek, 1);
825 if (use_is_media (cpu, out_FRdoublek + 1))
826 decrease_FR_busy (cpu, out_FRdoublek + 1, 1);
827 else
828 adjust_float_register_busy (cpu, -1, -1, out_FRdoublek + 1, 1);
829 }
830 vliw_wait_for_GR (cpu, in_GRi);
831 vliw_wait_for_GR (cpu, in_GRj);
832 vliw_wait_for_FR (cpu, out_FRk);
833 vliw_wait_for_FRdouble (cpu, out_FRdoublek);
1c453cd6
DB		 834 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
835 {
836 vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
837 vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
838 }
b34f6357
DB		 839 handle_resource_wait (cpu);
840 load_wait_for_GR (cpu, in_GRi);
841 load_wait_for_GR (cpu, in_GRj);
842 load_wait_for_FR (cpu, out_FRk);
843 load_wait_for_FRdouble (cpu, out_FRdoublek);
844 trace_vliw_wait_cycles (cpu);
845 return 0;
846 }
847
848 cycles = idesc->timing->units[unit_num].done;
849
850 /* The latency of FRk for a load will depend on how long it takes to retrieve
851 the the data from the cache or memory. */
852 update_FR_latency_for_load (cpu, out_FRk, cycles);
853 update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles);
854
1c453cd6
DB		 855 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
856 {
857 /* FNER has a latency of 3 cycles. */
858 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), cycles + 3);
859 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), cycles + 3);
860 }
861
b34f6357
DB		 862 fr500_reset_fr_flags (cpu, out_FRk);
863
864 return cycles;
865}
866
867int
868frvbf_model_fr500_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
869 int unit_num, int referenced,
870 INT in_GRi, INT in_GRj,
871 INT in_FRk, INT in_FRdoublek)
872{
873 int cycles;
874
875 if (model_insn == FRV_INSN_MODEL_PASS_1)
876 {
877 /* The entire VLIW insn must wait if there is a dependency on a register
878 which is not ready yet.
879 The latency of the registers may be less than previously recorded,
880 depending on how they were used previously.
881 See Table 13-8 in the LSI. */
882 if (in_GRi >= 0)
883 {
884 if (use_is_gr_complex (cpu, in_GRi))
885 decrease_GR_busy (cpu, in_GRi, 1);
886 }
887 if (in_GRj != in_GRi && in_GRj >= 0)
888 {
889 if (use_is_gr_complex (cpu, in_GRj))
890 decrease_GR_busy (cpu, in_GRj, 1);
891 }
892 if (in_FRk >= 0)
893 {
894 if (use_is_media (cpu, in_FRk))
895 decrease_FR_busy (cpu, in_FRk, 1);
896 else
897 adjust_float_register_busy (cpu, -1, -1, in_FRk, 1);
898 }
899 if (in_FRdoublek >= 0)
900 {
901 if (use_is_media (cpu, in_FRdoublek))
902 decrease_FR_busy (cpu, in_FRdoublek, 1);
903 else
904 adjust_float_register_busy (cpu, -1, -1, in_FRdoublek, 1);
905 if (use_is_media (cpu, in_FRdoublek + 1))
906 decrease_FR_busy (cpu, in_FRdoublek + 1, 1);
907 else
908 adjust_float_register_busy (cpu, -1, -1, in_FRdoublek + 1, 1);
909 }
910 vliw_wait_for_GR (cpu, in_GRi);
911 vliw_wait_for_GR (cpu, in_GRj);
912 vliw_wait_for_FR (cpu, in_FRk);
913 vliw_wait_for_FRdouble (cpu, in_FRdoublek);
914 handle_resource_wait (cpu);
915 load_wait_for_GR (cpu, in_GRi);
916 load_wait_for_GR (cpu, in_GRj);
917 load_wait_for_FR (cpu, in_FRk);
918 load_wait_for_FRdouble (cpu, in_FRdoublek);
919 trace_vliw_wait_cycles (cpu);
920 return 0;
921 }
922
923 cycles = idesc->timing->units[unit_num].done;
924
925 return cycles;
926}
927
928int
929frvbf_model_fr500_u_fr_r_store (SIM_CPU *cpu, const IDESC *idesc,
930 int unit_num, int referenced,
931 INT in_GRi, INT in_GRj,
932 INT in_FRk, INT in_FRdoublek)
933{
934 int cycles = frvbf_model_fr500_u_fr_store (cpu, idesc, unit_num, referenced,
935 in_GRi, in_GRj, in_FRk,
936 in_FRdoublek);
937
938 if (model_insn == FRV_INSN_MODEL_PASS_2)
939 {
940 if (CPU_RSTR_INVALIDATE(cpu))
941 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
942 }
943
944 return cycles;
945}
946
947int
948frvbf_model_fr500_u_swap (SIM_CPU *cpu, const IDESC *idesc,
949 int unit_num, int referenced,
950 INT in_GRi, INT in_GRj, INT out_GRk)
951{
952 int cycles;
953
954 if (model_insn == FRV_INSN_MODEL_PASS_1)
955 {
956 /* The entire VLIW insn must wait if there is a dependency on a register
957 which is not ready yet.
958 The latency of the registers may be less than previously recorded,
959 depending on how they were used previously.
960 See Table 13-8 in the LSI. */
961 if (in_GRi != out_GRk && in_GRi >= 0)
962 {
963 if (use_is_gr_complex (cpu, in_GRi))
964 decrease_GR_busy (cpu, in_GRi, 1);
965 }
966 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
967 {
968 if (use_is_gr_complex (cpu, in_GRj))
969 decrease_GR_busy (cpu, in_GRj, 1);
970 }
971 vliw_wait_for_GR (cpu, in_GRi);
972 vliw_wait_for_GR (cpu, in_GRj);
973 vliw_wait_for_GR (cpu, out_GRk);
974 handle_resource_wait (cpu);
975 load_wait_for_GR (cpu, in_GRi);
976 load_wait_for_GR (cpu, in_GRj);
977 load_wait_for_GR (cpu, out_GRk);
978 trace_vliw_wait_cycles (cpu);
979 return 0;
980 }
981
982 cycles = idesc->timing->units[unit_num].done;
983
984 /* The latency of GRk will depend on how long it takes to swap
985 the the data from the cache or memory. */
986 update_GR_latency_for_swap (cpu, out_GRk, cycles);
987 set_use_is_gr_complex (cpu, out_GRk);
988
989 return cycles;
990}
991
992int
993frvbf_model_fr500_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc,
994 int unit_num, int referenced,
995 INT in_FRj, INT out_FRk)
996{
997 int cycles;
998
999 if (model_insn == FRV_INSN_MODEL_PASS_1)
1000 {
1001 /* The entire VLIW insn must wait if there is a dependency on a register
1002 which is not ready yet. */
1003 if (in_FRj >= 0)
1004 {
1005 if (use_is_media (cpu, in_FRj))
1006 decrease_FR_busy (cpu, in_FRj, 1);
1007 else
1008 adjust_float_register_busy (cpu, -1, in_FRj, -1, 1);
1009 }
1010 if (out_FRk >= 0 && out_FRk != in_FRj)
1011 {
1012 if (use_is_media (cpu, out_FRk))
1013 decrease_FR_busy (cpu, out_FRk, 1);
1014 else
1015 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
1016 }
1017 vliw_wait_for_FR (cpu, in_FRj);
1018 vliw_wait_for_FR (cpu, out_FRk);
1019 handle_resource_wait (cpu);
1020 load_wait_for_FR (cpu, in_FRj);
1021 load_wait_for_FR (cpu, out_FRk);
1022 trace_vliw_wait_cycles (cpu);
1023 return 0;
1024 }
1025
1026 /* The latency of FRj is 3 cycles. */
1027 cycles = idesc->timing->units[unit_num].done;
1028 update_FR_latency (cpu, out_FRk, cycles + 3);
1029
1030 return cycles;
1031}
1032
1033int
1034frvbf_model_fr500_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
1035 int unit_num, int referenced,
1036 INT in_FRk, INT out_GRj)
1037{
1038 int cycles;
1039
1040 if (model_insn == FRV_INSN_MODEL_PASS_1)
1041 {
1042 /* The entire VLIW insn must wait if there is a dependency on a register
1043 which is not ready yet. */
1044 if (in_FRk >= 0)
1045 {
1046 if (use_is_media (cpu, in_FRk))
1047 decrease_FR_busy (cpu, in_FRk, 1);
1048 else
1049 adjust_float_register_busy (cpu, -1, in_FRk, -1, 1);
1050 }
1051 vliw_wait_for_FR (cpu, in_FRk);
1052 vliw_wait_for_GR (cpu, out_GRj);
1053 handle_resource_wait (cpu);
1054 load_wait_for_FR (cpu, in_FRk);
1055 load_wait_for_GR (cpu, out_GRj);
1056 trace_vliw_wait_cycles (cpu);
1057 return 0;
1058 }
1059
1060 /* The latency of GRj is 2 cycles. */
1061 cycles = idesc->timing->units[unit_num].done;
1062 update_GR_latency (cpu, out_GRj, cycles + 2);
1063 set_use_is_gr_complex (cpu, out_GRj);
1064
1065 return cycles;
1066}
1067
1068int
1069frvbf_model_fr500_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
1070 int unit_num, int referenced,
1071 INT in_spr, INT out_GRj)
1072{
1073 int cycles;
1074
1075 if (model_insn == FRV_INSN_MODEL_PASS_1)
1076 {
1077 /* The entire VLIW insn must wait if there is a dependency on a register
153431d6
DB		 1078 which is not ready yet. */
1079 vliw_wait_for_SPR (cpu, in_spr);
b34f6357
DB		 1080 vliw_wait_for_GR (cpu, out_GRj);
1081 handle_resource_wait (cpu);
1082 load_wait_for_GR (cpu, out_GRj);
1083 trace_vliw_wait_cycles (cpu);
1084 return 0;
1085 }
1086
1087 cycles = idesc->timing->units[unit_num].done;
1088
1089#if 0 /* no latency? */
1090 /* The latency of GRj is 2 cycles. */
1091 update_GR_latency (cpu, out_GRj, cycles + 2);
1092#endif
1093
1094 return cycles;
1095}
1096
1097int
1098frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
1099 int unit_num, int referenced,
1100 INT in_GRj, INT out_FRk)
1101{
1102 int cycles;
1103
1104 if (model_insn == FRV_INSN_MODEL_PASS_1)
1105 {
1106 /* The entire VLIW insn must wait if there is a dependency on a register
1107 which is not ready yet.
1108 The latency of the registers may be less than previously recorded,
1109 depending on how they were used previously.
1110 See Table 13-8 in the LSI. */
1111 if (in_GRj >= 0)
1112 {
1113 if (use_is_gr_complex (cpu, in_GRj))
1114 decrease_GR_busy (cpu, in_GRj, 1);
1115 }
1116 if (out_FRk >= 0)
1117 {
1118 if (use_is_media (cpu, out_FRk))
1119 decrease_FR_busy (cpu, out_FRk, 1);
1120 else
1c453cd6 1121 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
b34f6357
DB		 1122 }
1123 vliw_wait_for_GR (cpu, in_GRj);
1124 vliw_wait_for_FR (cpu, out_FRk);
1125 handle_resource_wait (cpu);
1126 load_wait_for_GR (cpu, in_GRj);
1127 load_wait_for_FR (cpu, out_FRk);
1128 trace_vliw_wait_cycles (cpu);
1129 return 0;
1130 }
1131
1132 /* The latency of FRk is 2 cycles. */
1133 cycles = idesc->timing->units[unit_num].done;
1134 update_FR_latency (cpu, out_FRk, cycles + 2);
1135
1136 /* Mark this use of the register as NOT a floating point op. */
1137 fr500_reset_fr_flags (cpu, out_FRk);
1138
1139 return cycles;
1140}
1141
1142int
1143frvbf_model_fr500_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
1144 int unit_num, int referenced,
1145 INT in_GRj, INT out_spr)
1146{
1147 int cycles;
1148
1149 if (model_insn == FRV_INSN_MODEL_PASS_1)
1150 {
1151 /* The entire VLIW insn must wait if there is a dependency on a register
1152 which is not ready yet.
1153 The latency of the registers may be less than previously recorded,
1154 depending on how they were used previously.
1155 See Table 13-8 in the LSI. */
1156 if (in_GRj >= 0)
1157 {
1158 if (use_is_gr_complex (cpu, in_GRj))
1159 decrease_GR_busy (cpu, in_GRj, 1);
1160 }
1161 vliw_wait_for_GR (cpu, in_GRj);
153431d6 1162 vliw_wait_for_SPR (cpu, out_spr);
b34f6357
DB		 1163 handle_resource_wait (cpu);
1164 load_wait_for_GR (cpu, in_GRj);
1165 trace_vliw_wait_cycles (cpu);
1166 return 0;
1167 }
1168
1169 cycles = idesc->timing->units[unit_num].done;
1170
1171#if 0
1172 /* The latency of spr is ? cycles. */
1173 update_SPR_latency (cpu, out_spr, cycles + ?);
1174#endif
1175
1176 return cycles;
1177}
1178
1179int
1180frvbf_model_fr500_u_ici (SIM_CPU *cpu, const IDESC *idesc,
1181 int unit_num, int referenced,
1182 INT in_GRi, INT in_GRj)
1183{
1184 int cycles;
1185
1186 if (model_insn == FRV_INSN_MODEL_PASS_1)
1187 {
1188 /* The entire VLIW insn must wait if there is a dependency on a register
1189 which is not ready yet.
1190 The latency of the registers may be less than previously recorded,
1191 depending on how they were used previously.
1192 See Table 13-8 in the LSI. */
1193 if (in_GRi >= 0)
1194 {
1195 if (use_is_gr_complex (cpu, in_GRi))
1196 decrease_GR_busy (cpu, in_GRi, 1);
1197 }
1198 if (in_GRj != in_GRi && in_GRj >= 0)
1199 {
1200 if (use_is_gr_complex (cpu, in_GRj))
1201 decrease_GR_busy (cpu, in_GRj, 1);
1202 }
1203 vliw_wait_for_GR (cpu, in_GRi);
1204 vliw_wait_for_GR (cpu, in_GRj);
1205 handle_resource_wait (cpu);
1206 load_wait_for_GR (cpu, in_GRi);
1207 load_wait_for_GR (cpu, in_GRj);
1208 trace_vliw_wait_cycles (cpu);
1209 return 0;
1210 }
1211
1212 cycles = idesc->timing->units[unit_num].done;
1213 request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles);
1214 return cycles;
1215}
1216
1217int
1218frvbf_model_fr500_u_dci (SIM_CPU *cpu, const IDESC *idesc,
1219 int unit_num, int referenced,
1220 INT in_GRi, INT in_GRj)
1221{
1222 int cycles;
1223
1224 if (model_insn == FRV_INSN_MODEL_PASS_1)
1225 {
1226 /* The entire VLIW insn must wait if there is a dependency on a register
1227 which is not ready yet.
1228 The latency of the registers may be less than previously recorded,
1229 depending on how they were used previously.
1230 See Table 13-8 in the LSI. */
1231 if (in_GRi >= 0)
1232 {
1233 if (use_is_gr_complex (cpu, in_GRi))
1234 decrease_GR_busy (cpu, in_GRi, 1);
1235 }
1236 if (in_GRj != in_GRi && in_GRj >= 0)
1237 {
1238 if (use_is_gr_complex (cpu, in_GRj))
1239 decrease_GR_busy (cpu, in_GRj, 1);
1240 }
1241 vliw_wait_for_GR (cpu, in_GRi);
1242 vliw_wait_for_GR (cpu, in_GRj);
1243 handle_resource_wait (cpu);
1244 load_wait_for_GR (cpu, in_GRi);
1245 load_wait_for_GR (cpu, in_GRj);
1246 trace_vliw_wait_cycles (cpu);
1247 return 0;
1248 }
1249
1250 cycles = idesc->timing->units[unit_num].done;
1251 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
1252 return cycles;
1253}
1254
1255int
1256frvbf_model_fr500_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
1257 int unit_num, int referenced,
1258 INT in_GRi, INT in_GRj)
1259{
1260 int cycles;
1261
1262 if (model_insn == FRV_INSN_MODEL_PASS_1)
1263 {
1264 /* The entire VLIW insn must wait if there is a dependency on a register
1265 which is not ready yet.
1266 The latency of the registers may be less than previously recorded,
1267 depending on how they were used previously.
1268 See Table 13-8 in the LSI. */
1269 if (in_GRi >= 0)
1270 {
1271 if (use_is_gr_complex (cpu, in_GRi))
1272 decrease_GR_busy (cpu, in_GRi, 1);
1273 }
1274 if (in_GRj != in_GRi && in_GRj >= 0)
1275 {
1276 if (use_is_gr_complex (cpu, in_GRj))
1277 decrease_GR_busy (cpu, in_GRj, 1);
1278 }
1279 vliw_wait_for_GR (cpu, in_GRi);
1280 vliw_wait_for_GR (cpu, in_GRj);
1281 handle_resource_wait (cpu);
1282 load_wait_for_GR (cpu, in_GRi);
1283 load_wait_for_GR (cpu, in_GRj);
1284 trace_vliw_wait_cycles (cpu);
1285 return 0;
1286 }
1287
1288 cycles = idesc->timing->units[unit_num].done;
1289 request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles);
1290 return cycles;
1291}
1292
1293int
1294frvbf_model_fr500_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
1295 int unit_num, int referenced,
1296 INT in_GRi, INT in_GRj)
1297{
1298 int cycles;
1299
1300 if (model_insn == FRV_INSN_MODEL_PASS_1)
1301 {
1302 /* The entire VLIW insn must wait if there is a dependency on a register
1303 which is not ready yet.
1304 The latency of the registers may be less than previously recorded,
1305 depending on how they were used previously.
1306 See Table 13-8 in the LSI. */
1307 if (in_GRi >= 0)
1308 {
1309 if (use_is_gr_complex (cpu, in_GRi))
1310 decrease_GR_busy (cpu, in_GRi, 1);
1311 }
1312 if (in_GRj != in_GRi && in_GRj >= 0)
1313 {
1314 if (use_is_gr_complex (cpu, in_GRj))
1315 decrease_GR_busy (cpu, in_GRj, 1);
1316 }
1317 vliw_wait_for_GR (cpu, in_GRi);
1318 vliw_wait_for_GR (cpu, in_GRj);
1319 handle_resource_wait (cpu);
1320 load_wait_for_GR (cpu, in_GRi);
1321 load_wait_for_GR (cpu, in_GRj);
1322 trace_vliw_wait_cycles (cpu);
1323 return 0;
1324 }
1325
1326 cycles = idesc->timing->units[unit_num].done;
1327 request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles);
1328 return cycles;
1329}
1330
1331int
1332frvbf_model_fr500_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
1333 int unit_num, int referenced,
1334 INT in_GRi, INT in_GRj)
1335{
1336 int cycles;
1337
1338 if (model_insn == FRV_INSN_MODEL_PASS_1)
1339 {
1340 /* The entire VLIW insn must wait if there is a dependency on a register
1341 which is not ready yet.
1342 The latency of the registers may be less than previously recorded,
1343 depending on how they were used previously.
1344 See Table 13-8 in the LSI. */
1345 if (in_GRi >= 0)
1346 {
1347 if (use_is_gr_complex (cpu, in_GRi))
1348 decrease_GR_busy (cpu, in_GRi, 1);
1349 }
1350 if (in_GRj != in_GRi && in_GRj >= 0)
1351 {
1352 if (use_is_gr_complex (cpu, in_GRj))
1353 decrease_GR_busy (cpu, in_GRj, 1);
1354 }
1355 vliw_wait_for_GR (cpu, in_GRi);
1356 vliw_wait_for_GR (cpu, in_GRj);
1357 handle_resource_wait (cpu);
1358 load_wait_for_GR (cpu, in_GRi);
1359 load_wait_for_GR (cpu, in_GRj);
1360 trace_vliw_wait_cycles (cpu);
1361 return 0;
1362 }
1363
1364 cycles = idesc->timing->units[unit_num].done;
1365 request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles);
1366 return cycles;
1367}
1368
1369int
1370frvbf_model_fr500_u_icul (SIM_CPU *cpu, const IDESC *idesc,
1371 int unit_num, int referenced,
1372 INT in_GRi, INT in_GRj)
1373{
1374 int cycles;
1375
1376 if (model_insn == FRV_INSN_MODEL_PASS_1)
1377 {
1378 /* The entire VLIW insn must wait if there is a dependency on a register
1379 which is not ready yet.
1380 The latency of the registers may be less than previously recorded,
1381 depending on how they were used previously.
1382 See Table 13-8 in the LSI. */
1383 if (in_GRi >= 0)
1384 {
1385 if (use_is_gr_complex (cpu, in_GRi))
1386 decrease_GR_busy (cpu, in_GRi, 1);
1387 }
1388 if (in_GRj != in_GRi && in_GRj >= 0)
1389 {
1390 if (use_is_gr_complex (cpu, in_GRj))
1391 decrease_GR_busy (cpu, in_GRj, 1);
1392 }
1393 vliw_wait_for_GR (cpu, in_GRi);
1394 vliw_wait_for_GR (cpu, in_GRj);
1395 handle_resource_wait (cpu);
1396 load_wait_for_GR (cpu, in_GRi);
1397 load_wait_for_GR (cpu, in_GRj);
1398 trace_vliw_wait_cycles (cpu);
1399 return 0;
1400 }
1401
1402 cycles = idesc->timing->units[unit_num].done;
1403 request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles);
1404 return cycles;
1405}
1406
1407int
1408frvbf_model_fr500_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
1409 int unit_num, int referenced,
1410 INT in_GRi, INT in_GRj)
1411{
1412 int cycles;
1413
1414 if (model_insn == FRV_INSN_MODEL_PASS_1)
1415 {
1416 /* The entire VLIW insn must wait if there is a dependency on a register
1417 which is not ready yet.
1418 The latency of the registers may be less than previously recorded,
1419 depending on how they were used previously.
1420 See Table 13-8 in the LSI. */
1421 if (in_GRi >= 0)
1422 {
1423 if (use_is_gr_complex (cpu, in_GRi))
1424 decrease_GR_busy (cpu, in_GRi, 1);
1425 }
1426 if (in_GRj != in_GRi && in_GRj >= 0)
1427 {
1428 if (use_is_gr_complex (cpu, in_GRj))
1429 decrease_GR_busy (cpu, in_GRj, 1);
1430 }
1431 vliw_wait_for_GR (cpu, in_GRi);
1432 vliw_wait_for_GR (cpu, in_GRj);
1433 handle_resource_wait (cpu);
1434 load_wait_for_GR (cpu, in_GRi);
1435 load_wait_for_GR (cpu, in_GRj);
1436 trace_vliw_wait_cycles (cpu);
1437 return 0;
1438 }
1439
1440 cycles = idesc->timing->units[unit_num].done;
1441 request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles);
1442 return cycles;
1443}
1444
b34f6357
DB		 1445int
1446frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc,
1447 int unit_num, int referenced,
1448 INT in_FRi, INT in_FRj,
1449 INT in_FRdoublei, INT in_FRdoublej,
1450 INT out_FRk, INT out_FRdoublek)
1451{
1452 int cycles;
1453 FRV_PROFILE_STATE *ps;
1454
1455 if (model_insn == FRV_INSN_MODEL_PASS_1)
1456 return 0;
1457
1458 /* The preprocessing can execute right away. */
1459 cycles = idesc->timing->units[unit_num].done;
1460
1461 /* The post processing must wait if there is a dependency on a FR
1462 which is not ready yet. */
1463 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1464 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1465 1);
1466 ps = CPU_PROFILE_STATE (cpu);
1467 ps->post_wait = cycles;
1468 post_wait_for_FR (cpu, in_FRi);
1469 post_wait_for_FR (cpu, in_FRj);
1470 post_wait_for_FR (cpu, out_FRk);
1471 post_wait_for_FRdouble (cpu, in_FRdoublei);
1472 post_wait_for_FRdouble (cpu, in_FRdoublej);
1473 post_wait_for_FRdouble (cpu, out_FRdoublek);
1c453cd6
DB		 1474 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1475 {
1476 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
1477 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
1478 }
b34f6357
DB		 1479 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1480 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1481 1);
1482
1483 /* The latency of FRk will be at least the latency of the other inputs. */
1484 update_FR_latency (cpu, out_FRk, ps->post_wait);
1485 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1486
1c453cd6
DB		 1487 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1488 {
1489 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
1490 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
1491 }
1492
b34f6357
DB		 1493 /* Once initiated, post-processing will take 3 cycles. */
1494 update_FR_ptime (cpu, out_FRk, 3);
1495 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1496
1c453cd6
DB		 1497 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1498 {
1499 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
1500 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
1501 }
1502
b34f6357
DB		 1503 /* Mark this use of the register as a floating point op. */
1504 if (out_FRk >= 0)
1505 set_use_is_fpop (cpu, out_FRk);
1506 if (out_FRdoublek >= 0)
1507 {
1508 set_use_is_fpop (cpu, out_FRdoublek);
1509 if (out_FRdoublek < 63)
1510 set_use_is_fpop (cpu, out_FRdoublek + 1);
1511 }
1512
1513 return cycles;
1514}
1515
1516int
1517frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc,
1518 int unit_num, int referenced,
1519 INT in_FRi, INT in_FRj,
1520 INT in_FRdoublei, INT in_FRdoublej,
1521 INT out_FRk, INT out_FRdoublek)
1522{
1523 int cycles;
1524 INT dual_FRi;
1525 INT dual_FRj;
1526 INT dual_FRk;
1527 INT dual_FRdoublei;
1528 INT dual_FRdoublej;
1529 INT dual_FRdoublek;
1530 FRV_PROFILE_STATE *ps;
1531
1532 if (model_insn == FRV_INSN_MODEL_PASS_1)
1533 return 0;
1534
1535 /* The preprocessing can execute right away. */
1536 cycles = idesc->timing->units[unit_num].done;
1537
1538 /* The post processing must wait if there is a dependency on a FR
1539 which is not ready yet. */
1540 dual_FRi = DUAL_REG (in_FRi);
1541 dual_FRj = DUAL_REG (in_FRj);
1542 dual_FRk = DUAL_REG (out_FRk);
1543 dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei);
1544 dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej);
1545 dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek);
1546
1547 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1548 adjust_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
1549 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1550 1);
1551 adjust_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej,
1552 dual_FRdoublek, 1);
1553 ps = CPU_PROFILE_STATE (cpu);
1554 ps->post_wait = cycles;
1555 post_wait_for_FR (cpu, in_FRi);
1556 post_wait_for_FR (cpu, in_FRj);
1557 post_wait_for_FR (cpu, out_FRk);
1558 post_wait_for_FR (cpu, dual_FRi);
1559 post_wait_for_FR (cpu, dual_FRj);
1560 post_wait_for_FR (cpu, dual_FRk);
1561 post_wait_for_FRdouble (cpu, in_FRdoublei);
1562 post_wait_for_FRdouble (cpu, in_FRdoublej);
1563 post_wait_for_FRdouble (cpu, out_FRdoublek);
1564 post_wait_for_FRdouble (cpu, dual_FRdoublei);
1565 post_wait_for_FRdouble (cpu, dual_FRdoublej);
1566 post_wait_for_FRdouble (cpu, dual_FRdoublek);
1c453cd6
DB		 1567 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1568 {
1569 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
1570 post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRk));
1571 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
1572 post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRdoublek));
1573 }
b34f6357
DB		 1574 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1575 restore_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
1576 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1577 1);
1578 restore_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej,
1579 dual_FRdoublek, 1);
1580
1581 /* The latency of FRk will be at least the latency of the other inputs. */
1582 update_FR_latency (cpu, out_FRk, ps->post_wait);
1583 update_FR_latency (cpu, dual_FRk, ps->post_wait);
1584 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1585 update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait);
1586
1c453cd6
DB		 1587 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1588 {
1589 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
1590 update_SPR_latency (cpu, FNER_FOR_FR (dual_FRk), ps->post_wait);
1591 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
1592 update_SPR_latency (cpu, FNER_FOR_FR (dual_FRdoublek), ps->post_wait);
1593 }
1594
b34f6357
DB		 1595 /* Once initiated, post-processing will take 3 cycles. */
1596 update_FR_ptime (cpu, out_FRk, 3);
1597 update_FR_ptime (cpu, dual_FRk, 3);
1598 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1599 update_FRdouble_ptime (cpu, dual_FRdoublek, 3);
1600
1c453cd6
DB		 1601 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1602 {
1603 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
1604 update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRk), 3);
1605 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
1606 update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRdoublek), 3);
1607 }
1608
b34f6357
DB		 1609 /* Mark this use of the register as a floating point op. */
1610 if (out_FRk >= 0)
1611 set_use_is_fpop (cpu, out_FRk);
1612 if (dual_FRk >= 0)
1613 set_use_is_fpop (cpu, dual_FRk);
1614 if (out_FRdoublek >= 0)
1615 {
1616 set_use_is_fpop (cpu, out_FRdoublek);
1617 if (out_FRdoublek < 63)
1618 set_use_is_fpop (cpu, out_FRdoublek + 1);
1619 }
1620 if (dual_FRdoublek >= 0)
1621 {
1622 set_use_is_fpop (cpu, dual_FRdoublek);
1623 if (dual_FRdoublek < 63)
1624 set_use_is_fpop (cpu, dual_FRdoublek + 1);
1625 }
1626
1627 return cycles;
1628}
1629
1630int
1631frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc,
1632 int unit_num, int referenced,
1633 INT in_FRi, INT in_FRj, INT out_FRk)
1634{
1635 int cycles;
1636 FRV_VLIW *vliw;
1637 int slot;
1638 FRV_PROFILE_STATE *ps;
1639
1640 if (model_insn == FRV_INSN_MODEL_PASS_1)
1641 return 0;
1642
1643 cycles = idesc->timing->units[unit_num].done;
1644
1645 /* The post processing must wait if there is a dependency on a FR
1646 which is not ready yet. */
1647 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1648 ps = CPU_PROFILE_STATE (cpu);
1649 ps->post_wait = cycles;
1650 post_wait_for_FR (cpu, in_FRi);
1651 post_wait_for_FR (cpu, in_FRj);
1652 post_wait_for_FR (cpu, out_FRk);
1c453cd6
DB		 1653 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1654 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
b34f6357
DB		 1655 vliw = CPU_VLIW (cpu);
1656 slot = vliw->next_slot - 1;
1657 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1658 post_wait_for_fdiv (cpu, slot);
1659 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1660
1661 /* The latency of FRk will be at least the latency of the other inputs. */
1662 /* Once initiated, post-processing will take 10 cycles. */
1663 update_FR_latency (cpu, out_FRk, ps->post_wait);
1664 update_FR_ptime (cpu, out_FRk, 10);
1665
1c453cd6
DB		 1666 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1667 {
1668 /* FNER has a latency of 10 cycles. */
1669 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
1670 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 10);
1671 }
1672
b34f6357
DB		 1673 /* The latency of the fdiv unit will be at least the latency of the other
1674 inputs. Once initiated, post-processing will take 9 cycles. */
1675 update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9);
1676
1677 /* Mark this use of the register as a floating point op. */
1678 set_use_is_fpop (cpu, out_FRk);
1679
1680 return cycles;
1681}
1682
1683int
1684frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc,
1685 int unit_num, int referenced,
1686 INT in_FRj, INT in_FRdoublej,
1687 INT out_FRk, INT out_FRdoublek)
1688{
1689 int cycles;
1690 FRV_VLIW *vliw;
1691 int slot;
1692 FRV_PROFILE_STATE *ps;
1693
1694 if (model_insn == FRV_INSN_MODEL_PASS_1)
1695 return 0;
1696
1697 cycles = idesc->timing->units[unit_num].done;
1698
1699 /* The post processing must wait if there is a dependency on a FR
1700 which is not ready yet. */
1701 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1702 adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1703 ps = CPU_PROFILE_STATE (cpu);
1704 ps->post_wait = cycles;
1705 post_wait_for_FR (cpu, in_FRj);
1706 post_wait_for_FR (cpu, out_FRk);
1707 post_wait_for_FRdouble (cpu, in_FRdoublej);
1708 post_wait_for_FRdouble (cpu, out_FRdoublek);
1c453cd6
DB		 1709 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1710 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
b34f6357
DB		 1711 vliw = CPU_VLIW (cpu);
1712 slot = vliw->next_slot - 1;
1713 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1714 post_wait_for_fsqrt (cpu, slot);
1715 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1716 restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1717
1718 /* The latency of FRk will be at least the latency of the other inputs. */
1719 update_FR_latency (cpu, out_FRk, ps->post_wait);
1720 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1c453cd6
DB		 1721 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1722 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
b34f6357
DB		 1723
1724 /* Once initiated, post-processing will take 15 cycles. */
1725 update_FR_ptime (cpu, out_FRk, 15);
1726 update_FRdouble_ptime (cpu, out_FRdoublek, 15);
1727
1c453cd6
DB		 1728 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1729 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 15);
1730
b34f6357
DB		 1731 /* The latency of the sqrt unit will be the latency of the other
1732 inputs plus 14 cycles. */
1733 update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
1734
1735 /* Mark this use of the register as a floating point op. */
1736 if (out_FRk >= 0)
1737 set_use_is_fpop (cpu, out_FRk);
1738 if (out_FRdoublek >= 0)
1739 {
1740 set_use_is_fpop (cpu, out_FRdoublek);
1741 if (out_FRdoublek < 63)
1742 set_use_is_fpop (cpu, out_FRdoublek + 1);
1743 }
1744
1745 return cycles;
1746}
1747
1748int
1749frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *cpu, const IDESC *idesc,
1750 int unit_num, int referenced,
1751 INT in_FRj, INT out_FRk)
1752{
1753 int cycles;
1754 FRV_VLIW *vliw;
1755 int slot;
1756 INT dual_FRj;
1757 INT dual_FRk;
1758 FRV_PROFILE_STATE *ps;
1759
1760 if (model_insn == FRV_INSN_MODEL_PASS_1)
1761 return 0;
1762
1763 cycles = idesc->timing->units[unit_num].done;
1764
1765 /* The post processing must wait if there is a dependency on a FR
1766 which is not ready yet. */
1767 dual_FRj = DUAL_REG (in_FRj);
1768 dual_FRk = DUAL_REG (out_FRk);
1769 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1770 adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1771 ps = CPU_PROFILE_STATE (cpu);
1772 ps->post_wait = cycles;
1773 post_wait_for_FR (cpu, in_FRj);
1774 post_wait_for_FR (cpu, out_FRk);
1775 post_wait_for_FR (cpu, dual_FRj);
1776 post_wait_for_FR (cpu, dual_FRk);
1777
1778 vliw = CPU_VLIW (cpu);
1779 slot = vliw->next_slot - 1;
1780 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1781 post_wait_for_fsqrt (cpu, slot);
1782 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1783 restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1784
1785 /* The latency of FRk will be at least the latency of the other inputs. */
1786 update_FR_latency (cpu, out_FRk, ps->post_wait);
1787 update_FR_latency (cpu, dual_FRk, ps->post_wait);
1788
1789 /* Once initiated, post-processing will take 15 cycles. */
1790 update_FR_ptime (cpu, out_FRk, 15);
1791 update_FR_ptime (cpu, dual_FRk, 15);
1792
1793 /* The latency of the sqrt unit will be at least the latency of the other
1794 inputs. */
1795 update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
1796
1797 /* Mark this use of the register as a floating point op. */
1798 if (out_FRk >= 0)
1799 set_use_is_fpop (cpu, out_FRk);
1800 if (dual_FRk >= 0)
1801 set_use_is_fpop (cpu, dual_FRk);
1802
1803 return cycles;
1804}
1805
1806int
1807frvbf_model_fr500_u_float_compare (SIM_CPU *cpu, const IDESC *idesc,
1808 int unit_num, int referenced,
1809 INT in_FRi, INT in_FRj,
1810 INT in_FRdoublei, INT in_FRdoublej,
1811 INT out_FCCi_2)
1812{
1813 int cycles;
1814 FRV_PROFILE_STATE *ps;
1815
1816 if (model_insn == FRV_INSN_MODEL_PASS_1)
1817 return 0;
1818
1819 /* The preprocessing can execute right away. */
1820 cycles = idesc->timing->units[unit_num].done;
1821
1822 /* The post processing must wait if there is a dependency on a FR
1823 which is not ready yet. */
1824 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
1825 ps = CPU_PROFILE_STATE (cpu);
1826 ps->post_wait = cycles;
1827 post_wait_for_FR (cpu, in_FRi);
1828 post_wait_for_FR (cpu, in_FRj);
1829 post_wait_for_FRdouble (cpu, in_FRdoublei);
1830 post_wait_for_FRdouble (cpu, in_FRdoublej);
1831 post_wait_for_CCR (cpu, out_FCCi_2);
1832 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
1833
1834 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1835 cycles. */
1836 update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
1837
1838 return cycles;
1839}
1840
1841int
1842frvbf_model_fr500_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc,
1843 int unit_num, int referenced,
1844 INT in_FRi, INT in_FRj,
1845 INT out_FCCi_2)
1846{
1847 int cycles;
1848 INT dual_FRi;
1849 INT dual_FRj;
1850 INT dual_FCCi_2;
1851 FRV_PROFILE_STATE *ps;
1852
1853 if (model_insn == FRV_INSN_MODEL_PASS_1)
1854 return 0;
1855
1856 /* The preprocessing can execute right away. */
1857 cycles = idesc->timing->units[unit_num].done;
1858
1859 /* The post processing must wait if there is a dependency on a FR
1860 which is not ready yet. */
1861 ps = CPU_PROFILE_STATE (cpu);
1862 ps->post_wait = cycles;
1863 dual_FRi = DUAL_REG (in_FRi);
1864 dual_FRj = DUAL_REG (in_FRj);
1865 dual_FCCi_2 = out_FCCi_2 + 1;
1866 adjust_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
1867 adjust_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
1868 post_wait_for_FR (cpu, in_FRi);
1869 post_wait_for_FR (cpu, in_FRj);
1870 post_wait_for_FR (cpu, dual_FRi);
1871 post_wait_for_FR (cpu, dual_FRj);
1872 post_wait_for_CCR (cpu, out_FCCi_2);
1873 post_wait_for_CCR (cpu, dual_FCCi_2);
1874 restore_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
1875 restore_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
1876
1877 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1878 cycles. */
1879 update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
1880 update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3);
1881
1882 return cycles;
1883}
1884
1885int
1886frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc,
1887 int unit_num, int referenced,
1888 INT in_FRj, INT in_FRintj, INT in_FRdoublej,
1889 INT out_FRk, INT out_FRintk,
1890 INT out_FRdoublek)
1891{
1892 int cycles;
1893 FRV_PROFILE_STATE *ps;
1894
1895 if (model_insn == FRV_INSN_MODEL_PASS_1)
1896 return 0;
1897
1898 /* The preprocessing can execute right away. */
1899 cycles = idesc->timing->units[unit_num].done;
1900
1901 /* The post processing must wait if there is a dependency on a FR
1902 which is not ready yet. */
1903 ps = CPU_PROFILE_STATE (cpu);
1904 ps->post_wait = cycles;
1905 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1906 adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1907 adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1908 post_wait_for_FR (cpu, in_FRj);
1909 post_wait_for_FR (cpu, in_FRintj);
1910 post_wait_for_FRdouble (cpu, in_FRdoublej);
1911 post_wait_for_FR (cpu, out_FRk);
1912 post_wait_for_FR (cpu, out_FRintk);
1913 post_wait_for_FRdouble (cpu, out_FRdoublek);
1c453cd6
DB		 1914 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1915 {
1916 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
1917 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk));
1918 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
1919 }
b34f6357
DB		 1920 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1921 restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1922 restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1923
1924 /* The latency of FRk will be at least the latency of the other inputs. */
1925 update_FR_latency (cpu, out_FRk, ps->post_wait);
1926 update_FR_latency (cpu, out_FRintk, ps->post_wait);
1927 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1928
1c453cd6
DB		 1929 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1930 {
1931 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
1932 update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait);
1933 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
1934 }
1935
b34f6357
DB		 1936 /* Once initiated, post-processing will take 3 cycles. */
1937 update_FR_ptime (cpu, out_FRk, 3);
1938 update_FR_ptime (cpu, out_FRintk, 3);
1939 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1940
1c453cd6
DB		 1941 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
1942 {
1943 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
1944 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 3);
1945 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
1946 }
1947
b34f6357
DB		 1948 /* Mark this use of the register as a floating point op. */
1949 if (out_FRk >= 0)
1950 set_use_is_fpop (cpu, out_FRk);
1951 if (out_FRintk >= 0)
1952 set_use_is_fpop (cpu, out_FRintk);
1953 if (out_FRdoublek >= 0)
1954 {
1955 set_use_is_fpop (cpu, out_FRdoublek);
1956 set_use_is_fpop (cpu, out_FRdoublek + 1);
1957 }
1958
1959 return cycles;
1960}
1961
1962int
1963frvbf_model_fr500_u_float_dual_convert (SIM_CPU *cpu, const IDESC *idesc,
1964 int unit_num, int referenced,
1965 INT in_FRj, INT in_FRintj,
1966 INT out_FRk, INT out_FRintk)
1967{
1968 int cycles;
1969 INT dual_FRj;
1970 INT dual_FRintj;
1971 INT dual_FRk;
1972 INT dual_FRintk;
1973 FRV_PROFILE_STATE *ps;
1974
1975 if (model_insn == FRV_INSN_MODEL_PASS_1)
1976 return 0;
1977
1978 /* The preprocessing can execute right away. */
1979 cycles = idesc->timing->units[unit_num].done;
1980
1981 /* The post processing must wait if there is a dependency on a FR
1982 which is not ready yet. */
1983 ps = CPU_PROFILE_STATE (cpu);
1984 ps->post_wait = cycles;
1985 dual_FRj = DUAL_REG (in_FRj);
1986 dual_FRintj = DUAL_REG (in_FRintj);
1987 dual_FRk = DUAL_REG (out_FRk);
1988 dual_FRintk = DUAL_REG (out_FRintk);
1989 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1990 adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1991 adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1992 adjust_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
1993 post_wait_for_FR (cpu, in_FRj);
1994 post_wait_for_FR (cpu, in_FRintj);
1995 post_wait_for_FR (cpu, out_FRk);
1996 post_wait_for_FR (cpu, out_FRintk);
1997 post_wait_for_FR (cpu, dual_FRj);
1998 post_wait_for_FR (cpu, dual_FRintj);
1999 post_wait_for_FR (cpu, dual_FRk);
2000 post_wait_for_FR (cpu, dual_FRintk);
2001 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
2002 restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
2003 restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
2004 restore_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
2005
2006 /* The latency of FRk will be at least the latency of the other inputs. */
2007 update_FR_latency (cpu, out_FRk, ps->post_wait);
2008 update_FR_latency (cpu, out_FRintk, ps->post_wait);
2009 update_FR_latency (cpu, dual_FRk, ps->post_wait);
2010 update_FR_latency (cpu, dual_FRintk, ps->post_wait);
2011
2012 /* Once initiated, post-processing will take 3 cycles. */
2013 update_FR_ptime (cpu, out_FRk, 3);
2014 update_FR_ptime (cpu, out_FRintk, 3);
2015 update_FR_ptime (cpu, dual_FRk, 3);
2016 update_FR_ptime (cpu, dual_FRintk, 3);
2017
2018 /* Mark this use of the register as a floating point op. */
2019 if (out_FRk >= 0)
2020 set_use_is_fpop (cpu, out_FRk);
2021 if (out_FRintk >= 0)
2022 set_use_is_fpop (cpu, out_FRintk);
2023
2024 return cycles;
2025}
2026
2027int
2028frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc,
2029 int unit_num, int referenced,
2030 INT in_FRi, INT in_FRj, INT in_ACC40Si, INT in_ACCGi,
2031 INT out_FRk,
2032 INT out_ACC40Sk, INT out_ACC40Uk, INT out_ACCGk)
2033{
2034 int cycles;
2035 FRV_PROFILE_STATE *ps;
2036 const CGEN_INSN *insn;
2037 int is_media_s1;
2038 int is_media_s2;
2039 int busy_adjustment[] = {0, 0, 0};
2040 int *fr;
2041 int *acc;
2042
2043 if (model_insn == FRV_INSN_MODEL_PASS_1)
2044 return 0;
2045
2046 /* The preprocessing can execute right away. */
2047 cycles = idesc->timing->units[unit_num].done;
2048
2049 ps = CPU_PROFILE_STATE (cpu);
2050 insn = idesc->idata;
2051
2052 /* If the previous use of the registers was a media op,
2053 then their latency will be less than previously recorded.
2054 See Table 13-13 in the LSI. */
2055 if (in_FRi >= 0)
2056 {
2057 if (use_is_media (cpu, in_FRi))
2058 {
2059 busy_adjustment[0] = 2;
2060 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2061 }
2062 else
2063 enforce_full_fr_latency (cpu, in_FRi);
2064 }
2065 if (in_FRj >= 0 && in_FRj != in_FRi)
2066 {
2067 if (use_is_media (cpu, in_FRj))
2068 {
2069 busy_adjustment[1] = 2;
2070 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
2071 }
2072 else
2073 enforce_full_fr_latency (cpu, in_FRj);
2074 }
2075 if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
2076 {
2077 if (use_is_media (cpu, out_FRk))
2078 {
2079 busy_adjustment[2] = 2;
2080 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
2081 }
2082 else
2083 enforce_full_fr_latency (cpu, out_FRk);
2084 }
2085
2086 /* The post processing must wait if there is a dependency on a FR
2087 which is not ready yet. */
2088 ps->post_wait = cycles;
2089 post_wait_for_FR (cpu, in_FRi);
2090 post_wait_for_FR (cpu, in_FRj);
2091 post_wait_for_FR (cpu, out_FRk);
2092 post_wait_for_ACC (cpu, in_ACC40Si);
2093 post_wait_for_ACC (cpu, in_ACCGi);
2094 post_wait_for_ACC (cpu, out_ACC40Sk);
2095 post_wait_for_ACC (cpu, out_ACC40Uk);
2096 post_wait_for_ACC (cpu, out_ACCGk);
2097
2098 /* Restore the busy cycles of the registers we used. */
2099 fr = ps->fr_busy;
2100 if (in_FRi >= 0)
2101 fr[in_FRi] += busy_adjustment[0];
2102 if (in_FRj >= 0)
2103 fr[in_FRj] += busy_adjustment[1];
2104 if (out_FRk >= 0)
2105 fr[out_FRk] += busy_adjustment[2];
2106
2107 /* The latency of tht output register will be at least the latency of the
2108 other inputs. Once initiated, post-processing will take 3 cycles. */
2109 if (out_FRk >= 0)
2110 {
2111 update_FR_latency (cpu, out_FRk, ps->post_wait);
2112 update_FR_ptime (cpu, out_FRk, 3);
2113 /* Mark this use of the register as a media op. */
2114 set_use_is_media (cpu, out_FRk);
2115 }
2116 /* The latency of tht output accumulator will be at least the latency of the
2117 other inputs. Once initiated, post-processing will take 1 cycle. */
2118 if (out_ACC40Sk >= 0)
2119 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2120 if (out_ACC40Uk >= 0)
2121 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
2122 if (out_ACCGk >= 0)
2123 update_ACC_latency (cpu, out_ACCGk, ps->post_wait + 1);
2124
2125 return cycles;
2126}
2127
2128int
2129frvbf_model_fr500_u_media_quad_arith (SIM_CPU *cpu, const IDESC *idesc,
2130 int unit_num, int referenced,
2131 INT in_FRi, INT in_FRj,
2132 INT out_FRk)
2133{
2134 int cycles;
2135 INT dual_FRi;
2136 INT dual_FRj;
2137 INT dual_FRk;
2138 FRV_PROFILE_STATE *ps;
2139 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2140 int *fr;
2141
2142 if (model_insn == FRV_INSN_MODEL_PASS_1)
2143 return 0;
2144
2145 /* The preprocessing can execute right away. */
2146 cycles = idesc->timing->units[unit_num].done;
2147
2148 ps = CPU_PROFILE_STATE (cpu);
2149 dual_FRi = DUAL_REG (in_FRi);
2150 dual_FRj = DUAL_REG (in_FRj);
2151 dual_FRk = DUAL_REG (out_FRk);
2152
2153 /* If the previous use of the registers was a media op,
2154 then their latency will be less than previously recorded.
2155 See Table 13-13 in the LSI. */
2156 if (use_is_media (cpu, in_FRi))
2157 {
2158 busy_adjustment[0] = 2;
2159 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2160 }
2161 else
2162 enforce_full_fr_latency (cpu, in_FRi);
2163 if (dual_FRi >= 0 && use_is_media (cpu, dual_FRi))
2164 {
2165 busy_adjustment[1] = 2;
2166 decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]);
2167 }
2168 else
2169 enforce_full_fr_latency (cpu, dual_FRi);
2170 if (in_FRj != in_FRi)
2171 {
2172 if (use_is_media (cpu, in_FRj))
2173 {
2174 busy_adjustment[2] = 2;
2175 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2176 }
2177 else
2178 enforce_full_fr_latency (cpu, in_FRj);
2179 if (dual_FRj >= 0 && use_is_media (cpu, dual_FRj))
2180 {
2181 busy_adjustment[3] = 2;
2182 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]);
2183 }
2184 else
2185 enforce_full_fr_latency (cpu, dual_FRj + 1);
2186 }
2187 if (out_FRk != in_FRi && out_FRk != in_FRj)
2188 {
2189 if (use_is_media (cpu, out_FRk))
2190 {
2191 busy_adjustment[4] = 2;
2192 decrease_FR_busy (cpu, out_FRk, busy_adjustment[4]);
2193 }
2194 else
2195 enforce_full_fr_latency (cpu, out_FRk);
2196 if (dual_FRk >= 0 && use_is_media (cpu, dual_FRk))
2197 {
2198 busy_adjustment[5] = 2;
2199 decrease_FR_busy (cpu, dual_FRk, busy_adjustment[5]);
2200 }
2201 else
2202 enforce_full_fr_latency (cpu, dual_FRk);
2203 }
2204
2205 /* The post processing must wait if there is a dependency on a FR
2206 which is not ready yet. */
2207 ps->post_wait = cycles;
2208 post_wait_for_FR (cpu, in_FRi);
2209 post_wait_for_FR (cpu, dual_FRi);
2210 post_wait_for_FR (cpu, in_FRj);
2211 post_wait_for_FR (cpu, dual_FRj);
2212 post_wait_for_FR (cpu, out_FRk);
2213 post_wait_for_FR (cpu, dual_FRk);
2214
2215 /* Restore the busy cycles of the registers we used. */
2216 fr = ps->fr_busy;
2217 fr[in_FRi] += busy_adjustment[0];
2218 if (dual_FRi >= 0)
2219 fr[dual_FRi] += busy_adjustment[1];
2220 fr[in_FRj] += busy_adjustment[2];
2221 if (dual_FRj >= 0)
2222 fr[dual_FRj] += busy_adjustment[3];
2223 fr[out_FRk] += busy_adjustment[4];
2224 if (dual_FRk >= 0)
2225 fr[dual_FRk] += busy_adjustment[5];
2226
2227 /* The latency of tht output register will be at least the latency of the
2228 other inputs. */
2229 update_FR_latency (cpu, out_FRk, ps->post_wait);
2230
2231 /* Once initiated, post-processing will take 3 cycles. */
2232 update_FR_ptime (cpu, out_FRk, 3);
2233
2234 /* Mark this use of the register as a media op. */
2235 set_use_is_media (cpu, out_FRk);
2236 if (dual_FRk >= 0)
2237 {
2238 update_FR_latency (cpu, dual_FRk, ps->post_wait);
2239 update_FR_ptime (cpu, dual_FRk, 3);
2240 /* Mark this use of the register as a media op. */
2241 set_use_is_media (cpu, dual_FRk);
2242 }
2243
2244 return cycles;
2245}
2246
2247int
2248frvbf_model_fr500_u_media_dual_mul (SIM_CPU *cpu, const IDESC *idesc,
2249 int unit_num, int referenced,
2250 INT in_FRi, INT in_FRj,
2251 INT out_ACC40Sk, INT out_ACC40Uk)
2252{
2253 int cycles;
2254 INT dual_ACC40Sk;
2255 INT dual_ACC40Uk;
2256 FRV_PROFILE_STATE *ps;
2257 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2258 int *fr;
2259 int *acc;
2260
2261 if (model_insn == FRV_INSN_MODEL_PASS_1)
2262 return 0;
2263
2264 /* The preprocessing can execute right away. */
2265 cycles = idesc->timing->units[unit_num].done;
2266
2267 ps = CPU_PROFILE_STATE (cpu);
2268 dual_ACC40Sk = DUAL_REG (out_ACC40Sk);
2269 dual_ACC40Uk = DUAL_REG (out_ACC40Uk);
2270
2271 /* If the previous use of the registers was a media op,
2272 then their latency will be less than previously recorded.
2273 See Table 13-13 in the LSI. */
2274 if (use_is_media (cpu, in_FRi))
2275 {
2276 busy_adjustment[0] = 2;
2277 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2278 }
2279 else
2280 enforce_full_fr_latency (cpu, in_FRi);
2281 if (in_FRj != in_FRi)
2282 {
2283 if (use_is_media (cpu, in_FRj))
2284 {
2285 busy_adjustment[1] = 2;
2286 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
2287 }
2288 else
2289 enforce_full_fr_latency (cpu, in_FRj);
2290 }
2291 if (out_ACC40Sk >= 0)
2292 {
2293 busy_adjustment[2] = 1;
2294 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]);
2295 }
2296 if (dual_ACC40Sk >= 0)
2297 {
2298 busy_adjustment[3] = 1;
2299 decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]);
2300 }
2301 if (out_ACC40Uk >= 0)
2302 {
2303 busy_adjustment[4] = 1;
2304 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
2305 }
2306 if (dual_ACC40Uk >= 0)
2307 {
2308 busy_adjustment[5] = 1;
2309 decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]);
2310 }
2311
2312 /* The post processing must wait if there is a dependency on a FR
2313 which is not ready yet. */
2314 ps->post_wait = cycles;
2315 post_wait_for_FR (cpu, in_FRi);
2316 post_wait_for_FR (cpu, in_FRj);
2317 post_wait_for_ACC (cpu, out_ACC40Sk);
2318 post_wait_for_ACC (cpu, dual_ACC40Sk);
2319 post_wait_for_ACC (cpu, out_ACC40Uk);
2320 post_wait_for_ACC (cpu, dual_ACC40Uk);
2321
2322 /* Restore the busy cycles of the registers we used. */
2323 fr = ps->fr_busy;
2324 acc = ps->acc_busy;
2325 fr[in_FRi] += busy_adjustment[0];
2326 fr[in_FRj] += busy_adjustment[1];
2327 if (out_ACC40Sk >= 0)
2328 acc[out_ACC40Sk] += busy_adjustment[2];
2329 if (dual_ACC40Sk >= 0)
2330 acc[dual_ACC40Sk] += busy_adjustment[3];
2331 if (out_ACC40Uk >= 0)
2332 acc[out_ACC40Uk] += busy_adjustment[4];
2333 if (dual_ACC40Uk >= 0)
2334 acc[dual_ACC40Uk] += busy_adjustment[5];
2335
2336 /* The latency of tht output register will be at least the latency of the
2337 other inputs. Once initiated, post-processing will take 1 cycle. */
2338 if (out_ACC40Sk >= 0)
2339 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2340 if (dual_ACC40Sk >= 0)
2341 update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1);
2342 if (out_ACC40Uk >= 0)
2343 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
2344 if (dual_ACC40Uk >= 0)
2345 update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1);
2346
2347 return cycles;
2348}
2349
2350int
2351frvbf_model_fr500_u_media_quad_mul (SIM_CPU *cpu, const IDESC *idesc,
2352 int unit_num, int referenced,
2353 INT in_FRi, INT in_FRj,
2354 INT out_ACC40Sk, INT out_ACC40Uk)
2355{
2356 int cycles;
2357 INT FRi_1;
2358 INT FRj_1;
2359 INT ACC40Sk_1;
2360 INT ACC40Sk_2;
2361 INT ACC40Sk_3;
2362 INT ACC40Uk_1;
2363 INT ACC40Uk_2;
2364 INT ACC40Uk_3;
2365 FRV_PROFILE_STATE *ps;
2366 int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0};
2367 int *fr;
2368 int *acc;
2369
2370 if (model_insn == FRV_INSN_MODEL_PASS_1)
2371 return 0;
2372
2373 /* The preprocessing can execute right away. */
2374 cycles = idesc->timing->units[unit_num].done;
2375
2376 FRi_1 = DUAL_REG (in_FRi);
2377 FRj_1 = DUAL_REG (in_FRj);
2378 ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
2379 ACC40Sk_2 = DUAL_REG (ACC40Sk_1);
2380 ACC40Sk_3 = DUAL_REG (ACC40Sk_2);
2381 ACC40Uk_1 = DUAL_REG (out_ACC40Uk);
2382 ACC40Uk_2 = DUAL_REG (ACC40Uk_1);
2383 ACC40Uk_3 = DUAL_REG (ACC40Uk_2);
2384
2385 /* If the previous use of the registers was a media op,
2386 then their latency will be less than previously recorded.
2387 See Table 13-13 in the LSI. */
2388 ps = CPU_PROFILE_STATE (cpu);
2389 if (use_is_media (cpu, in_FRi))
2390 {
2391 busy_adjustment[0] = 2;
2392 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2393 }
2394 else
2395 enforce_full_fr_latency (cpu, in_FRi);
2396 if (FRi_1 >= 0)
2397 {
2398 if (use_is_media (cpu, FRi_1))
2399 {
2400 busy_adjustment[1] = 2;
2401 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2402 }
2403 else
2404 enforce_full_fr_latency (cpu, FRi_1);
2405 }
2406 if (in_FRj != in_FRi)
2407 {
2408 if (use_is_media (cpu, in_FRj))
2409 {
2410 busy_adjustment[2] = 2;
2411 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2412 }
2413 else
2414 enforce_full_fr_latency (cpu, in_FRj);
2415 if (FRj_1 >= 0)
2416 {
2417 if (use_is_media (cpu, FRj_1))
2418 {
2419 busy_adjustment[3] = 2;
2420 decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]);
2421 }
2422 else
2423 enforce_full_fr_latency (cpu, FRj_1);
2424 }
2425 }
2426 if (out_ACC40Sk >= 0)
2427 {
2428 busy_adjustment[4] = 1;
2429 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
2430
2431 if (ACC40Sk_1 >= 0)
2432 {
2433 busy_adjustment[5] = 1;
2434 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
2435 }
2436 if (ACC40Sk_2 >= 0)
2437 {
2438 busy_adjustment[6] = 1;
2439 decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]);
2440 }
2441 if (ACC40Sk_3 >= 0)
2442 {
2443 busy_adjustment[7] = 1;
2444 decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]);
2445 }
2446 }
2447 else if (out_ACC40Uk >= 0)
2448 {
2449 busy_adjustment[4] = 1;
2450 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
2451
2452 if (ACC40Uk_1 >= 0)
2453 {
2454 busy_adjustment[5] = 1;
2455 decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]);
2456 }
2457 if (ACC40Uk_2 >= 0)
2458 {
2459 busy_adjustment[6] = 1;
2460 decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]);
2461 }
2462 if (ACC40Uk_3 >= 0)
2463 {
2464 busy_adjustment[7] = 1;
2465 decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]);
2466 }
2467 }
2468
2469 /* The post processing must wait if there is a dependency on a FR
2470 which is not ready yet. */
2471 ps->post_wait = cycles;
2472 post_wait_for_FR (cpu, in_FRi);
2473 post_wait_for_FR (cpu, FRi_1);
2474 post_wait_for_FR (cpu, in_FRj);
2475 post_wait_for_FR (cpu, FRj_1);
2476 post_wait_for_ACC (cpu, out_ACC40Sk);
2477 post_wait_for_ACC (cpu, ACC40Sk_1);
2478 post_wait_for_ACC (cpu, ACC40Sk_2);
2479 post_wait_for_ACC (cpu, ACC40Sk_3);
2480 post_wait_for_ACC (cpu, out_ACC40Uk);
2481 post_wait_for_ACC (cpu, ACC40Uk_1);
2482 post_wait_for_ACC (cpu, ACC40Uk_2);
2483 post_wait_for_ACC (cpu, ACC40Uk_3);
2484
2485 /* Restore the busy cycles of the registers we used. */
2486 fr = ps->fr_busy;
2487 acc = ps->acc_busy;
2488 fr[in_FRi] += busy_adjustment[0];
2489 if (FRi_1 >= 0)
2490 fr[FRi_1] += busy_adjustment[1];
2491 fr[in_FRj] += busy_adjustment[2];
2492 if (FRj_1 > 0)
2493 fr[FRj_1] += busy_adjustment[3];
2494 if (out_ACC40Sk >= 0)
2495 {
2496 acc[out_ACC40Sk] += busy_adjustment[4];
2497 if (ACC40Sk_1 >= 0)
2498 acc[ACC40Sk_1] += busy_adjustment[5];
2499 if (ACC40Sk_2 >= 0)
2500 acc[ACC40Sk_2] += busy_adjustment[6];
2501 if (ACC40Sk_3 >= 0)
2502 acc[ACC40Sk_3] += busy_adjustment[7];
2503 }
2504 else if (out_ACC40Uk >= 0)
2505 {
2506 acc[out_ACC40Uk] += busy_adjustment[4];
2507 if (ACC40Uk_1 >= 0)
2508 acc[ACC40Uk_1] += busy_adjustment[5];
2509 if (ACC40Uk_2 >= 0)
2510 acc[ACC40Uk_2] += busy_adjustment[6];
2511 if (ACC40Uk_3 >= 0)
2512 acc[ACC40Uk_3] += busy_adjustment[7];
2513 }
2514
2515 /* The latency of tht output register will be at least the latency of the
2516 other inputs. Once initiated, post-processing will take 1 cycle. */
2517 if (out_ACC40Sk >= 0)
2518 {
2519 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2520 if (ACC40Sk_1 >= 0)
2521 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
2522 if (ACC40Sk_2 >= 0)
2523 update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);
2524 if (ACC40Sk_3 >= 0)
2525 update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);
2526 }
2527 else if (out_ACC40Uk >= 0)
2528 {
2529 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
2530 if (ACC40Uk_1 >= 0)
2531 update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1);
2532 if (ACC40Uk_2 >= 0)
2533 update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1);
2534 if (ACC40Uk_3 >= 0)
2535 update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1);
2536 }
2537
2538 return cycles;
2539}
2540
2541int
2542frvbf_model_fr500_u_media_quad_complex (SIM_CPU *cpu, const IDESC *idesc,
2543 int unit_num, int referenced,
2544 INT in_FRi, INT in_FRj,
2545 INT out_ACC40Sk)
2546{
2547 int cycles;
2548 INT FRi_1;
2549 INT FRj_1;
2550 INT ACC40Sk_1;
2551 FRV_PROFILE_STATE *ps;
2552 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2553 int *fr;
2554 int *acc;
2555
2556 if (model_insn == FRV_INSN_MODEL_PASS_1)
2557 return 0;
2558
2559 /* The preprocessing can execute right away. */
2560 cycles = idesc->timing->units[unit_num].done;
2561
2562 FRi_1 = DUAL_REG (in_FRi);
2563 FRj_1 = DUAL_REG (in_FRj);
2564 ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
2565
2566 /* If the previous use of the registers was a media op,
2567 then their latency will be less than previously recorded.
2568 See Table 13-13 in the LSI. */
2569 ps = CPU_PROFILE_STATE (cpu);
2570 if (use_is_media (cpu, in_FRi))
2571 {
2572 busy_adjustment[0] = 2;
2573 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2574 }
2575 else
2576 enforce_full_fr_latency (cpu, in_FRi);
2577 if (FRi_1 >= 0)
2578 {
2579 if (use_is_media (cpu, FRi_1))
2580 {
2581 busy_adjustment[1] = 2;
2582 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2583 }
2584 else
2585 enforce_full_fr_latency (cpu, FRi_1);
2586 }
2587 if (in_FRj != in_FRi)
2588 {
2589 if (use_is_media (cpu, in_FRj))
2590 {
2591 busy_adjustment[2] = 2;
2592 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2593 }
2594 else
2595 enforce_full_fr_latency (cpu, in_FRj);
2596 if (FRj_1 >= 0)
2597 {
2598 if (use_is_media (cpu, FRj_1))
2599 {
2600 busy_adjustment[3] = 2;
2601 decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]);
2602 }
2603 else
2604 enforce_full_fr_latency (cpu, FRj_1);
2605 }
2606 }
2607 if (out_ACC40Sk >= 0)
2608 {
2609 busy_adjustment[4] = 1;
2610 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
2611
2612 if (ACC40Sk_1 >= 0)
2613 {
2614 busy_adjustment[5] = 1;
2615 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
2616 }
2617 }
2618
2619 /* The post processing must wait if there is a dependency on a FR
2620 which is not ready yet. */
2621 ps->post_wait = cycles;
2622 post_wait_for_FR (cpu, in_FRi);
2623 post_wait_for_FR (cpu, FRi_1);
2624 post_wait_for_FR (cpu, in_FRj);
2625 post_wait_for_FR (cpu, FRj_1);
2626 post_wait_for_ACC (cpu, out_ACC40Sk);
2627 post_wait_for_ACC (cpu, ACC40Sk_1);
2628
2629 /* Restore the busy cycles of the registers we used. */
2630 fr = ps->fr_busy;
2631 acc = ps->acc_busy;
2632 fr[in_FRi] += busy_adjustment[0];
2633 if (FRi_1 >= 0)
2634 fr[FRi_1] += busy_adjustment[1];
2635 fr[in_FRj] += busy_adjustment[2];
2636 if (FRj_1 > 0)
2637 fr[FRj_1] += busy_adjustment[3];
2638 if (out_ACC40Sk >= 0)
2639 {
2640 acc[out_ACC40Sk] += busy_adjustment[4];
2641 if (ACC40Sk_1 >= 0)
2642 acc[ACC40Sk_1] += busy_adjustment[5];
2643 }
2644
2645 /* The latency of tht output register will be at least the latency of the
2646 other inputs. Once initiated, post-processing will take 1 cycle. */
2647 if (out_ACC40Sk >= 0)
2648 {
2649 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2650 if (ACC40Sk_1 >= 0)
2651 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
2652 }
2653
2654 return cycles;
2655}
2656
2657int
2658frvbf_model_fr500_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
2659 int unit_num, int referenced,
2660 INT in_FRi,
2661 INT out_FRk)
2662{
2663 int cycles;
2664 INT dual_FRk;
2665 FRV_PROFILE_STATE *ps;
2666 int busy_adjustment[] = {0, 0, 0};
2667 int *fr;
2668
2669 if (model_insn == FRV_INSN_MODEL_PASS_1)
2670 return 0;
2671
2672 /* The preprocessing can execute right away. */
2673 cycles = idesc->timing->units[unit_num].done;
2674
2675 /* If the previous use of the registers was a media op,
2676 then their latency will be less than previously recorded.
2677 See Table 13-13 in the LSI. */
2678 dual_FRk = DUAL_REG (out_FRk);
2679 ps = CPU_PROFILE_STATE (cpu);
2680 if (use_is_media (cpu, in_FRi))
2681 {
2682 busy_adjustment[0] = 2;
2683 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2684 }
2685 else
2686 enforce_full_fr_latency (cpu, in_FRi);
2687 if (out_FRk != in_FRi)
2688 {
2689 if (use_is_media (cpu, out_FRk))
2690 {
2691 busy_adjustment[1] = 2;
2692 decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]);
2693 }
2694 else
2695 enforce_full_fr_latency (cpu, out_FRk);
2696 }
2697 if (dual_FRk >= 0 && dual_FRk != in_FRi)
2698 {
2699 if (use_is_media (cpu, dual_FRk))
2700 {
2701 busy_adjustment[2] = 2;
2702 decrease_FR_busy (cpu, dual_FRk, busy_adjustment[2]);
2703 }
2704 else
2705 enforce_full_fr_latency (cpu, dual_FRk);
2706 }
2707
2708 /* The post processing must wait if there is a dependency on a FR
2709 which is not ready yet. */
2710 ps->post_wait = cycles;
2711 post_wait_for_FR (cpu, in_FRi);
2712 post_wait_for_FR (cpu, out_FRk);
2713 post_wait_for_FR (cpu, dual_FRk);
2714
2715 /* Restore the busy cycles of the registers we used. */
2716 fr = ps->fr_busy;
2717 fr[in_FRi] += busy_adjustment[0];
2718 fr[out_FRk] += busy_adjustment[1];
2719 if (dual_FRk >= 0)
2720 fr[dual_FRk] += busy_adjustment[2];
2721
1c453cd6 2722 /* The latency of the output register will be at least the latency of the
b34f6357
DB		 2723 other inputs. Once initiated, post-processing will take 3 cycles. */
2724 update_FR_latency (cpu, out_FRk, ps->post_wait);
2725 update_FR_ptime (cpu, out_FRk, 3);
2726
2727 /* Mark this use of the register as a media op. */
2728 set_use_is_media (cpu, out_FRk);
2729 if (dual_FRk >= 0)
2730 {
2731 update_FR_latency (cpu, dual_FRk, ps->post_wait);
2732 update_FR_ptime (cpu, dual_FRk, 3);
2733
2734 /* Mark this use of the register as a media op. */
2735 set_use_is_media (cpu, dual_FRk);
2736 }
2737
2738 return cycles;
2739}
2740
2741int
2742frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *cpu, const IDESC *idesc,
2743 int unit_num, int referenced,
2744 INT in_FRi,
2745 INT out_FRk)
2746{
2747 int cycles;
2748 INT FRi_1;
2749 INT FRk_1;
2750 INT FRk_2;
2751 INT FRk_3;
2752 FRV_PROFILE_STATE *ps;
2753 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2754 int *fr;
2755
2756 if (model_insn == FRV_INSN_MODEL_PASS_1)
2757 return 0;
2758
2759 /* The preprocessing can execute right away. */
2760 cycles = idesc->timing->units[unit_num].done;
2761
2762 FRi_1 = DUAL_REG (in_FRi);
2763 FRk_1 = DUAL_REG (out_FRk);
2764 FRk_2 = DUAL_REG (FRk_1);
2765 FRk_3 = DUAL_REG (FRk_2);
2766
2767 /* If the previous use of the registers was a media op,
2768 then their latency will be less than previously recorded.
2769 See Table 13-13 in the LSI. */
2770 ps = CPU_PROFILE_STATE (cpu);
2771 if (use_is_media (cpu, in_FRi))
2772 {
2773 busy_adjustment[0] = 2;
2774 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2775 }
2776 else
2777 enforce_full_fr_latency (cpu, in_FRi);
2778 if (FRi_1 >= 0 && use_is_media (cpu, FRi_1))
2779 {
2780 busy_adjustment[1] = 2;
2781 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2782 }
2783 else
2784 enforce_full_fr_latency (cpu, FRi_1);
2785 if (out_FRk != in_FRi)
2786 {
2787 if (use_is_media (cpu, out_FRk))
2788 {
2789 busy_adjustment[2] = 2;
2790 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
2791 }
2792 else
2793 enforce_full_fr_latency (cpu, out_FRk);
2794 if (FRk_1 >= 0 && FRk_1 != in_FRi)
2795 {
2796 if (use_is_media (cpu, FRk_1))
2797 {
2798 busy_adjustment[3] = 2;
2799 decrease_FR_busy (cpu, FRk_1, busy_adjustment[3]);
2800 }
2801 else
2802 enforce_full_fr_latency (cpu, FRk_1);
2803 }
2804 if (FRk_2 >= 0 && FRk_2 != in_FRi)
2805 {
2806 if (use_is_media (cpu, FRk_2))
2807 {
2808 busy_adjustment[4] = 2;
2809 decrease_FR_busy (cpu, FRk_2, busy_adjustment[4]);
2810 }
2811 else
2812 enforce_full_fr_latency (cpu, FRk_2);
2813 }
2814 if (FRk_3 >= 0 && FRk_3 != in_FRi)
2815 {
2816 if (use_is_media (cpu, FRk_3))
2817 {
2818 busy_adjustment[5] = 2;
2819 decrease_FR_busy (cpu, FRk_3, busy_adjustment[5]);
2820 }
2821 else
2822 enforce_full_fr_latency (cpu, FRk_3);
2823 }
2824 }
2825
2826 /* The post processing must wait if there is a dependency on a FR
2827 which is not ready yet. */
2828 ps->post_wait = cycles;
2829 post_wait_for_FR (cpu, in_FRi);
2830 post_wait_for_FR (cpu, FRi_1);
2831 post_wait_for_FR (cpu, out_FRk);
2832 post_wait_for_FR (cpu, FRk_1);
2833 post_wait_for_FR (cpu, FRk_2);
2834 post_wait_for_FR (cpu, FRk_3);
2835
2836 /* Restore the busy cycles of the registers we used. */
2837 fr = ps->fr_busy;
2838 fr[in_FRi] += busy_adjustment[0];
2839 if (FRi_1 >= 0)
2840 fr[FRi_1] += busy_adjustment[1];
2841 fr[out_FRk] += busy_adjustment[2];
2842 if (FRk_1 >= 0)
2843 fr[FRk_1] += busy_adjustment[3];
2844 if (FRk_2 >= 0)
2845 fr[FRk_2] += busy_adjustment[4];
2846 if (FRk_3 >= 0)
2847 fr[FRk_3] += busy_adjustment[5];
2848
2849 /* The latency of tht output register will be at least the latency of the
2850 other inputs. Once initiated, post-processing will take 3 cycles. */
2851 update_FR_latency (cpu, out_FRk, ps->post_wait);
2852 update_FR_ptime (cpu, out_FRk, 3);
2853
2854 /* Mark this use of the register as a media op. */
2855 set_use_is_media (cpu, out_FRk);
2856 if (FRk_1 >= 0)
2857 {
2858 update_FR_latency (cpu, FRk_1, ps->post_wait);
2859 update_FR_ptime (cpu, FRk_1, 3);
2860
2861 /* Mark this use of the register as a media op. */
2862 set_use_is_media (cpu, FRk_1);
2863 }
2864 if (FRk_2 >= 0)
2865 {
2866 update_FR_latency (cpu, FRk_2, ps->post_wait);
2867 update_FR_ptime (cpu, FRk_2, 3);
2868
2869 /* Mark this use of the register as a media op. */
2870 set_use_is_media (cpu, FRk_2);
2871 }
2872 if (FRk_3 >= 0)
2873 {
2874 update_FR_latency (cpu, FRk_3, ps->post_wait);
2875 update_FR_ptime (cpu, FRk_3, 3);
2876
2877 /* Mark this use of the register as a media op. */
2878 set_use_is_media (cpu, FRk_3);
2879 }
2880
2881 return cycles;
2882}
2883
2884int
2885frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *cpu, const IDESC *idesc,
2886 int unit_num, int referenced,
2887 INT in_FRj,
2888 INT out_FRk)
2889{
2890 return frvbf_model_fr500_u_media_dual_expand (cpu, idesc, unit_num,
2891 referenced, in_FRj, out_FRk);
2892}
2893
2894int
2895frvbf_model_fr500_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
2896 int unit_num, int referenced,
2897 INT in_FRj,
2898 INT out_FRk)
2899{
2900 int cycles;
2901 INT dual_FRj;
2902 FRV_PROFILE_STATE *ps;
2903 int busy_adjustment[] = {0, 0, 0};
2904 int *fr;
2905
2906 if (model_insn == FRV_INSN_MODEL_PASS_1)
2907 return 0;
2908
2909 /* The preprocessing can execute right away. */
2910 cycles = idesc->timing->units[unit_num].done;
2911
2912 /* If the previous use of the registers was a media op,
2913 then their latency will be less than previously recorded.
2914 See Table 13-13 in the LSI. */
2915 dual_FRj = DUAL_REG (in_FRj);
2916 ps = CPU_PROFILE_STATE (cpu);
2917 if (use_is_media (cpu, in_FRj))
2918 {
2919 busy_adjustment[0] = 2;
2920 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
2921 }
2922 else
2923 enforce_full_fr_latency (cpu, in_FRj);
2924 if (dual_FRj >= 0)
2925 {
2926 if (use_is_media (cpu, dual_FRj))
2927 {
2928 busy_adjustment[1] = 2;
2929 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]);
2930 }
2931 else
2932 enforce_full_fr_latency (cpu, dual_FRj);
2933 }
2934 if (out_FRk != in_FRj)
2935 {
2936 if (use_is_media (cpu, out_FRk))
2937 {
2938 busy_adjustment[2] = 2;
2939 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
2940 }
2941 else
2942 enforce_full_fr_latency (cpu, out_FRk);
2943 }
2944
2945 /* The post processing must wait if there is a dependency on a FR
2946 which is not ready yet. */
2947 ps->post_wait = cycles;
2948 post_wait_for_FR (cpu, in_FRj);
2949 post_wait_for_FR (cpu, dual_FRj);
2950 post_wait_for_FR (cpu, out_FRk);
2951
2952 /* Restore the busy cycles of the registers we used. */
2953 fr = ps->fr_busy;
2954 fr[in_FRj] += busy_adjustment[0];
2955 if (dual_FRj >= 0)
2956 fr[dual_FRj] += busy_adjustment[1];
2957 fr[out_FRk] += busy_adjustment[2];
2958
2959 /* The latency of tht output register will be at least the latency of the
2960 other inputs. */
2961 update_FR_latency (cpu, out_FRk, ps->post_wait);
2962
2963 /* Once initiated, post-processing will take 3 cycles. */
2964 update_FR_ptime (cpu, out_FRk, 3);
2965
2966 /* Mark this use of the register as a media op. */
2967 set_use_is_media (cpu, out_FRk);
2968
2969 return cycles;
2970}
2971
2972int
2973frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *cpu, const IDESC *idesc,
2974 int unit_num, int referenced,
2975 INT in_FRj,
2976 INT out_FRk)
2977{
2978 int cycles;
2979 INT FRk_1;
2980 INT FRk_2;
2981 INT FRk_3;
2982 FRV_PROFILE_STATE *ps;
2983 int busy_adjustment[] = {0, 0, 0, 0, 0};
2984 int *fr;
2985
2986 if (model_insn == FRV_INSN_MODEL_PASS_1)
2987 return 0;
2988
2989 /* The preprocessing can execute right away. */
2990 cycles = idesc->timing->units[unit_num].done;
2991
2992 FRk_1 = DUAL_REG (out_FRk);
2993 FRk_2 = DUAL_REG (FRk_1);
2994 FRk_3 = DUAL_REG (FRk_2);
2995
2996 /* If the previous use of the registers was a media op,
2997 then their latency will be less than previously recorded.
2998 See Table 13-13 in the LSI. */
2999 ps = CPU_PROFILE_STATE (cpu);
3000 if (use_is_media (cpu, in_FRj))
3001 {
3002 busy_adjustment[0] = 2;
3003 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
3004 }
3005 else
3006 enforce_full_fr_latency (cpu, in_FRj);
3007 if (out_FRk != in_FRj)
3008 {
3009 if (use_is_media (cpu, out_FRk))
3010 {
3011 busy_adjustment[1] = 2;
3012 decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]);
3013 }
3014 else
3015 enforce_full_fr_latency (cpu, out_FRk);
3016 if (FRk_1 >= 0 && FRk_1 != in_FRj)
3017 {
3018 if (use_is_media (cpu, FRk_1))
3019 {
3020 busy_adjustment[2] = 2;
3021 decrease_FR_busy (cpu, FRk_1, busy_adjustment[2]);
3022 }
3023 else
3024 enforce_full_fr_latency (cpu, FRk_1);
3025 }
3026 if (FRk_2 >= 0 && FRk_2 != in_FRj)
3027 {
3028 if (use_is_media (cpu, FRk_2))
3029 {
3030 busy_adjustment[3] = 2;
3031 decrease_FR_busy (cpu, FRk_2, busy_adjustment[3]);
3032 }
3033 else
3034 enforce_full_fr_latency (cpu, FRk_2);
3035 }
3036 if (FRk_3 >= 0 && FRk_3 != in_FRj)
3037 {
3038 if (use_is_media (cpu, FRk_3))
3039 {
3040 busy_adjustment[4] = 2;
3041 decrease_FR_busy (cpu, FRk_3, busy_adjustment[4]);
3042 }
3043 else
3044 enforce_full_fr_latency (cpu, FRk_3);
3045 }
3046 }
3047
3048 /* The post processing must wait if there is a dependency on a FR
3049 which is not ready yet. */
3050 ps->post_wait = cycles;
3051 post_wait_for_FR (cpu, in_FRj);
3052 post_wait_for_FR (cpu, out_FRk);
3053 post_wait_for_FR (cpu, FRk_1);
3054 post_wait_for_FR (cpu, FRk_2);
3055 post_wait_for_FR (cpu, FRk_3);
3056
3057 /* Restore the busy cycles of the registers we used. */
3058 fr = ps->fr_busy;
3059 fr[in_FRj] += busy_adjustment[0];
3060 fr[out_FRk] += busy_adjustment[1];
3061 if (FRk_1 >= 0)
3062 fr[FRk_1] += busy_adjustment[2];
3063 if (FRk_2 >= 0)
3064 fr[FRk_2] += busy_adjustment[3];
3065 if (FRk_3 >= 0)
3066 fr[FRk_3] += busy_adjustment[4];
3067
3068 /* The latency of tht output register will be at least the latency of the
3069 other inputs. Once initiated, post-processing will take 3 cycles. */
3070 update_FR_latency (cpu, out_FRk, ps->post_wait);
3071 update_FR_ptime (cpu, out_FRk, 3);
3072
3073 /* Mark this use of the register as a media op. */
3074 set_use_is_media (cpu, out_FRk);
3075 if (FRk_1 >= 0)
3076 {
3077 update_FR_latency (cpu, FRk_1, ps->post_wait);
3078 update_FR_ptime (cpu, FRk_1, 3);
3079
3080 /* Mark this use of the register as a media op. */
3081 set_use_is_media (cpu, FRk_1);
3082 }
3083 if (FRk_2 >= 0)
3084 {
3085 update_FR_latency (cpu, FRk_2, ps->post_wait);
3086 update_FR_ptime (cpu, FRk_2, 3);
3087
3088 /* Mark this use of the register as a media op. */
3089 set_use_is_media (cpu, FRk_2);
3090 }
3091 if (FRk_3 >= 0)
3092 {
3093 update_FR_latency (cpu, FRk_3, ps->post_wait);
3094 update_FR_ptime (cpu, FRk_3, 3);
3095
3096 /* Mark this use of the register as a media op. */
3097 set_use_is_media (cpu, FRk_3);
3098 }
3099
3100 return cycles;
3101}
3102
3103int
3104frvbf_model_fr500_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
3105 int unit_num, int referenced)
3106{
3107 int cycles;
3108 if (model_insn == FRV_INSN_MODEL_PASS_1)
3109 {
3110 int i;
3111 /* Wait for ALL resources. */
3112 for (i = 0; i < 64; ++i)
3113 {
3114 enforce_full_fr_latency (cpu, i);
3115 vliw_wait_for_GR (cpu, i);
3116 vliw_wait_for_FR (cpu, i);
3117 vliw_wait_for_ACC (cpu, i);
3118 }
3119 for (i = 0; i < 8; ++i)
3120 vliw_wait_for_CCR (cpu, i);
3121 for (i = 0; i < 2; ++i)
3122 {
3123 vliw_wait_for_idiv_resource (cpu, i);
3124 vliw_wait_for_fdiv_resource (cpu, i);
3125 vliw_wait_for_fsqrt_resource (cpu, i);
3126 }
3127 handle_resource_wait (cpu);
3128 for (i = 0; i < 64; ++i)
3129 {
3130 load_wait_for_GR (cpu, i);
3131 load_wait_for_FR (cpu, i);
3132 }
3133 trace_vliw_wait_cycles (cpu);
3134 return 0;
3135 }
3136
3137 cycles = idesc->timing->units[unit_num].done;
3138 return cycles;
3139}
3140
3141int
3142frvbf_model_fr500_u_membar (SIM_CPU *cpu, const IDESC *idesc,
3143 int unit_num, int referenced)
3144{
3145 int cycles;
3146 if (model_insn == FRV_INSN_MODEL_PASS_1)
3147 {
3148 int i;
3149 /* Wait for ALL resources, except GR and ICC. */
3150 for (i = 0; i < 64; ++i)
3151 {
3152 enforce_full_fr_latency (cpu, i);
3153 vliw_wait_for_FR (cpu, i);
3154 vliw_wait_for_ACC (cpu, i);
3155 }
3156 for (i = 0; i < 4; ++i)
3157 vliw_wait_for_CCR (cpu, i);
3158 for (i = 0; i < 2; ++i)
3159 {
3160 vliw_wait_for_idiv_resource (cpu, i);
3161 vliw_wait_for_fdiv_resource (cpu, i);
3162 vliw_wait_for_fsqrt_resource (cpu, i);
3163 }
3164 handle_resource_wait (cpu);
3165 for (i = 0; i < 64; ++i)
3166 {
3167 load_wait_for_FR (cpu, i);
3168 }
3169 trace_vliw_wait_cycles (cpu);
3170 return 0;
3171 }
3172
3173 cycles = idesc->timing->units[unit_num].done;
3174 return cycles;
3175}
3176
3177/* The frv machine is a fictional implementation of the fr500 which implements
3178 all frv architectural features. */
3179int
3180frvbf_model_frv_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3181 int unit_num, int referenced)
3182{
3183 return idesc->timing->units[unit_num].done;
3184}
3185
3186/* The simple machine is a fictional implementation of the fr500 which
3187 implements limited frv architectural features. */
3188int
3189frvbf_model_simple_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3190 int unit_num, int referenced)
3191{
3192 return idesc->timing->units[unit_num].done;
3193}
3194
3195/* The tomcat machine is models a prototype fr500 machine which had a few
3196 bugs and restrictions to work around. */
3197int
3198frvbf_model_tomcat_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3199 int unit_num, int referenced)
3200{
3201 return idesc->timing->units[unit_num].done;
3202}
3203
3204#endif /* WITH_PROFILE_MODEL_P */
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