[thirdparty/binutils-gdb.git] / sim / h8300 / sim-main.h

/* Main header for the Hitachi h8/300 architecture.  */

#include "bfd.h"

#ifndef SIM_MAIN_H
#define SIM_MAIN_H

#define DEBUG

/* These define the size of main memory for the simulator.

   Note the size of main memory for the H8/300H is only 256k.  Keeping it
   small makes the simulator run much faster and consume less memory.

   The linker knows about the limited size of the simulator's main memory
   on the H8/300H (via the h8300h.sc linker script).  So if you change
   H8300H_MSIZE, be sure to fix the linker script too.

   Also note that there's a separate "eightbit" area aside from main
   memory.  For simplicity, the simulator assumes any data memory reference
   outside of main memory refers to the eightbit area (in theory, this
   can only happen when simulating H8/300H programs).  We make no attempt
   to catch overlapping addresses, wrapped addresses, etc etc.  */

#define H8300_MSIZE (1 << 16)

/* avolkov: 
   Next 2 macros are ugly for any workstation, but while they're work.
   Memory size MUST be configurable.  */
#define H8300H_MSIZE (1 << 24) 
#define H8300S_MSIZE (1 << 24) 

#define CSIZE 1024

enum h8_regnum {
  R0_REGNUM = 0,
  R1_REGNUM = 1,
  R2_REGNUM = 2,
  R3_REGNUM = 3,
  R4_REGNUM = 4,
  R5_REGNUM = 5,
  R6_REGNUM = 6,
  R7_REGNUM = 7,

  SP_REGNUM = R7_REGNUM,	/* Contains address of top of stack */
  FP_REGNUM = R6_REGNUM,	/* Contains address of executing
				   stack frame */
  CCR_REGNUM = 8,		/* Contains processor status */
  PC_REGNUM  = 9,		/* Contains program counter */
  CYCLE_REGNUM = 10,
  EXR_REGNUM  = 11,
  INST_REGNUM = 12,
  TICK_REGNUM = 13,
  MACH_REGNUM = 14,
  MACL_REGNUM = 15,
  SBR_REGNUM =  16,
  VBR_REGNUM =  17,

  ZERO_REGNUM = 18
};

enum h8_typecodes {
  OP_NULL,
  OP_REG,		/* Register direct.  */
  OP_LOWREG,		/* Special reg syntax for "bra".  */
  OP_DISP,		/* Register indirect w/displacement.  */
  /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr.  */
  OP_PREDEC,		/* Register indirect w/pre-decrement.  */
  OP_POSTDEC,		/* Register indirect w/post-decrement.  */
  OP_PREINC,		/* Register indirect w/pre-increment.  */
  OP_POSTINC,		/* Register indirect w/post-increment.  */
  OP_PCREL,		/* PC Relative.  */
  OP_MEM,		/* Absolute memory address.  */
  OP_CCR,		/* Condition Code Register.  */
  OP_IMM,		/* Immediate value.  */
  /*OP_ABS*/		/* Un-used (duplicates op_mem?).  */
  OP_EXR,		/* EXtended control Register.  */
  OP_SBR, 		/* Vector Base Register.  */
  OP_VBR,		/* Short-address Base Register.  */
  OP_MACH,		/* Multiply Accumulator - high.  */
  OP_MACL,		/* Multiply Accumulator - low.   */
  /* FIXME: memory indirect?  */
  OP_INDEXB,		/* Byte index mode */
  OP_INDEXW,		/* Word index mode */
  OP_INDEXL		/* Long index mode */
};

#include "sim-basics.h"
#include "sim-base.h"

/* Structure used to describe addressing */

typedef struct
{
  int type;
  int reg;
  int literal;
} ea_type;

/* Struct for instruction decoder.  */
typedef struct
{
  ea_type src;
  ea_type dst;
  ea_type op3;
  int opcode;
  int next_pc;
  int oldpc;
  int cycles;
#ifdef DEBUG
  struct h8_opcode *op;
#endif
} decoded_inst;

struct _sim_cpu {
  unsigned int regs[20];	/* 8 GR's plus ZERO, SBR, and VBR.  */
  unsigned int pc;

  int macS;			/* MAC Saturating mode */
  int macV;			/* MAC Overflow */
  int macN;			/* MAC Negative */
  int macZ;			/* MAC Zero     */

  int delayed_branch;
  char **command_line;		/* Pointer to command line arguments.  */

  unsigned char *memory;
  int mask;
  
  sim_cpu_base base;
};

struct h8300_sim_state {
  unsigned long memory_size;
#ifdef ADEBUG
  int stats[O_LAST];
#endif
};
#define H8300_SIM_STATE(sd) ((struct h8300_sim_state *) STATE_ARCH_DATA (sd))

/* The current state of the processor; registers, memory, etc.  */

#define cpu_set_pc(CPU, VAL)	(((CPU)->pc)  = (VAL))
#define cpu_get_pc(CPU)		(((CPU)->pc))

/* Magic numbers used to distinguish an exit from a breakpoint.  */
#define LIBC_EXIT_MAGIC1 0xdead	
#define LIBC_EXIT_MAGIC2 0xbeef	
/* Local version of macros for decoding exit status.  
   (included here rather than try to find target version of wait.h)
*/
#define SIM_WIFEXITED(V)	(((V) & 0xff) == 0)
#define SIM_WIFSTOPPED(V)	(!SIM_WIFEXITED (V))
#define SIM_WEXITSTATUS(V)	(((V) >> 8) & 0xff)
#define SIM_WSTOPSIG(V)		((V) & 0x7f)

#endif /* SIM_MAIN_H */
Commit	Line	Data
dc5c3759 MS	1	/* Main header for the Hitachi h8/300 architecture. */
	2
	3	#include "bfd.h"
	4
	5	#ifndef SIM_MAIN_H
	6	#define SIM_MAIN_H
	7
	8	#define DEBUG
	9
	10	/* These define the size of main memory for the simulator.
	11
	12	Note the size of main memory for the H8/300H is only 256k. Keeping it
	13	small makes the simulator run much faster and consume less memory.
	14
	15	The linker knows about the limited size of the simulator's main memory
	16	on the H8/300H (via the h8300h.sc linker script). So if you change
	17	H8300H_MSIZE, be sure to fix the linker script too.
	18
	19	Also note that there's a separate "eightbit" area aside from main
	20	memory. For simplicity, the simulator assumes any data memory reference
	21	outside of main memory refers to the eightbit area (in theory, this
	22	can only happen when simulating H8/300H programs). We make no attempt
	23	to catch overlapping addresses, wrapped addresses, etc etc. */
	24
	25	#define H8300_MSIZE (1 << 16)
	26
	27	/* avolkov:
	28	Next 2 macros are ugly for any workstation, but while they're work.
	29	Memory size MUST be configurable. */
f5d3df96	30	#define H8300H_MSIZE (1 << 24)
dc5c3759 MS	31	#define H8300S_MSIZE (1 << 24)
	32
	33	#define CSIZE 1024
	34
	35	enum h8_regnum {
	36	R0_REGNUM = 0,
	37	R1_REGNUM = 1,
	38	R2_REGNUM = 2,
	39	R3_REGNUM = 3,
	40	R4_REGNUM = 4,
	41	R5_REGNUM = 5,
	42	R6_REGNUM = 6,
	43	R7_REGNUM = 7,
	44
	45	SP_REGNUM = R7_REGNUM, /* Contains address of top of stack */
	46	FP_REGNUM = R6_REGNUM, /* Contains address of executing
	47	stack frame */
	48	CCR_REGNUM = 8, /* Contains processor status */
	49	PC_REGNUM = 9, /* Contains program counter */
	50	CYCLE_REGNUM = 10,
	51	EXR_REGNUM = 11,
	52	INST_REGNUM = 12,
	53	TICK_REGNUM = 13,
18ad32b5 MS	54	MACH_REGNUM = 14,
	55	MACL_REGNUM = 15,
	56	SBR_REGNUM = 16,
	57	VBR_REGNUM = 17,
dc5c3759 MS	58
	59	ZERO_REGNUM = 18
	60	};
	61
	62	enum h8_typecodes {
	63	OP_NULL,
	64	OP_REG, /* Register direct. */
	65	OP_LOWREG, /* Special reg syntax for "bra". */
	66	OP_DISP, /* Register indirect w/displacement. */
	67	/* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr. */
	68	OP_PREDEC, /* Register indirect w/pre-decrement. */
	69	OP_POSTDEC, /* Register indirect w/post-decrement. */
	70	OP_PREINC, /* Register indirect w/pre-increment. */
	71	OP_POSTINC, /* Register indirect w/post-increment. */
	72	OP_PCREL, /* PC Relative. */
	73	OP_MEM, /* Absolute memory address. */
	74	OP_CCR, /* Condition Code Register. */
	75	OP_IMM, /* Immediate value. */
	76	/OP_ABS/ /* Un-used (duplicates op_mem?). */
	77	OP_EXR, /* EXtended control Register. */
	78	OP_SBR, /* Vector Base Register. */
	79	OP_VBR, /* Short-address Base Register. */
	80	OP_MACH, /* Multiply Accumulator - high. */
	81	OP_MACL, /* Multiply Accumulator - low. */
	82	/* FIXME: memory indirect? */
	83	OP_INDEXB, /* Byte index mode */
	84	OP_INDEXW, /* Word index mode */
	85	OP_INDEXL /* Long index mode */
	86	};
	87
	88	#include "sim-basics.h"
dc5c3759 MS	89	#include "sim-base.h"
	90
	91	/* Structure used to describe addressing */
	92
	93	typedef struct
	94	{
	95	int type;
	96	int reg;
	97	int literal;
	98	} ea_type;
	99
	100	/* Struct for instruction decoder. */
	101	typedef struct
	102	{
	103	ea_type src;
	104	ea_type dst;
	105	ea_type op3;
	106	int opcode;
	107	int next_pc;
	108	int oldpc;
	109	int cycles;
	110	#ifdef DEBUG
	111	struct h8_opcode *op;
	112	#endif
	113	} decoded_inst;
	114
	115	struct _sim_cpu {
	116	unsigned int regs[20]; /* 8 GR's plus ZERO, SBR, and VBR. */
	117	unsigned int pc;
	118
	119	int macS; /* MAC Saturating mode */
	120	int macV; /* MAC Overflow */
	121	int macN; /* MAC Negative */
	122	int macZ; /* MAC Zero */
	123
	124	int delayed_branch;
	125	char *command_line; / Pointer to command line arguments. */
	126
	127	unsigned char *memory;
dc5c3759 MS	128	int mask;
	129
	130	sim_cpu_base base;
	131	};
	132
2ad10cb2	133	struct h8300_sim_state {
dc5c3759	134	unsigned long memory_size;
dc5c3759 MS	135	#ifdef ADEBUG
	136	int stats[O_LAST];
	137	#endif
dc5c3759	138	};
2ad10cb2	139	#define H8300_SIM_STATE(sd) ((struct h8300_sim_state *) STATE_ARCH_DATA (sd))
dc5c3759 MS	140
	141	/* The current state of the processor; registers, memory, etc. */
	142
dc5c3759 MS	143	#define cpu_set_pc(CPU, VAL) (((CPU)->pc) = (VAL))
	144	#define cpu_get_pc(CPU) (((CPU)->pc))
	145
	146	/* Magic numbers used to distinguish an exit from a breakpoint. */
	147	#define LIBC_EXIT_MAGIC1 0xdead
	148	#define LIBC_EXIT_MAGIC2 0xbeef
	149	/* Local version of macros for decoding exit status.
	150	(included here rather than try to find target version of wait.h)
	151	*/
f0861129 MS	152	#define SIM_WIFEXITED(V) (((V) & 0xff) == 0)
	153	#define SIM_WIFSTOPPED(V) (!SIM_WIFEXITED (V))
	154	#define SIM_WEXITSTATUS(V) (((V) >> 8) & 0xff)
	155	#define SIM_WSTOPSIG(V) ((V) & 0x7f)
dc5c3759 MS	156
dc5c3759 MS	157	#endif /* SIM_MAIN_H */