[thirdparty/binutils-gdb.git] / sim / lm32 / traps.c

/* Lattice Mico32 exception and system call support.
   Contributed by Jon Beniston <jon@beniston.com>

   Copyright (C) 2009-2021 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* This must come before any other includes.  */
#include "defs.h"

#define WANT_CPU lm32bf
#define WANT_CPU_LM32BF

#include "sim-main.h"
#include "sim-syscall.h"
#include "lm32-sim.h"
#include "targ-vals.h"

/* Handle invalid instructions.  */

SEM_PC
sim_engine_invalid_insn (SIM_CPU * current_cpu, IADDR cia, SEM_PC pc)
{
  SIM_DESC sd = CPU_STATE (current_cpu);

  sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);

  return pc;
}

/* Handle divide instructions. */

USI
lm32bf_divu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2)
{
  SIM_DESC sd = CPU_STATE (current_cpu);
  host_callback *cb = STATE_CALLBACK (sd);

  /* Check for divide by zero */
  if (GET_H_GR (r1) == 0)
    {
      if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
	sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE);
      else
	{
	  /* Save PC in exception address register.  */
	  SET_H_GR (30, pc);
	  /* Save and clear interrupt enable.  */
	  SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
	  /* Branch to divide by zero exception handler.  */
	  return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DIVIDE_BY_ZERO * 32;
	}
    }
  else
    {
      SET_H_GR (r2, (USI) GET_H_GR (r0) / (USI) GET_H_GR (r1));
      return pc + 4;
    }
}

USI
lm32bf_modu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2)
{
  SIM_DESC sd = CPU_STATE (current_cpu);
  host_callback *cb = STATE_CALLBACK (sd);

  /* Check for divide by zero.  */
  if (GET_H_GR (r1) == 0)
    {
      if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
	sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE);
      else
	{
	  /* Save PC in exception address register.  */
	  SET_H_GR (30, pc);
	  /* Save and clear interrupt enable.  */
	  SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
	  /* Branch to divide by zero exception handler.  */
	  return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DIVIDE_BY_ZERO * 32;
	}
    }
  else
    {
      SET_H_GR (r2, (USI) GET_H_GR (r0) % (USI) GET_H_GR (r1));
      return pc + 4;
    }
}

/* Handle break instructions.  */

USI
lm32bf_break_insn (SIM_CPU * current_cpu, IADDR pc)
{
  SIM_DESC sd = CPU_STATE (current_cpu);
  host_callback *cb = STATE_CALLBACK (sd);
  /* Breakpoint.  */
  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
    {
      sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
      return pc;
    }
  else
    {
      /* Save PC in breakpoint address register.  */
      SET_H_GR (31, pc);
      /* Save and clear interrupt enable.  */
      SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 2);
      /* Branch to breakpoint exception handler.  */
      return GET_H_CSR (LM32_CSR_DEBA) + LM32_EID_BREAKPOINT * 32;
    }
}

/* Handle scall instructions.  */

USI
lm32bf_scall_insn (SIM_CPU * current_cpu, IADDR pc)
{
  SIM_DESC sd = CPU_STATE (current_cpu);
  host_callback *cb = STATE_CALLBACK (sd);

  if ((STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
      || (GET_H_GR (8) == TARGET_SYS_exit))
    {
      /* Delegate system call to host O/S.  */
      long result, result2;
      int errcode;

      /* Perform the system call.  */
      sim_syscall_multi (current_cpu, GET_H_GR (8), GET_H_GR (1), GET_H_GR (2),
			 GET_H_GR (3), GET_H_GR (4), &result, &result2,
			 &errcode);
      /* Store the return value in the CPU's registers.  */
      SET_H_GR (1, result);
      SET_H_GR (2, result2);
      SET_H_GR (3, errcode);

      /* Skip over scall instruction.  */
      return pc + 4;
    }
  else
    {
      /* Save PC in exception address register.  */
      SET_H_GR (30, pc);
      /* Save and clear interrupt enable */
      SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
      /* Branch to system call exception handler.  */
      return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_SYSTEM_CALL * 32;
    }
}

/* Handle b instructions.  */

USI
lm32bf_b_insn (SIM_CPU * current_cpu, USI r0, USI f_r0)
{
  SIM_DESC sd = CPU_STATE (current_cpu);
  host_callback *cb = STATE_CALLBACK (sd);

  /* Restore interrupt enable.  */
  if (f_r0 == 30)
    SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 2) >> 1);
  else if (f_r0 == 31)
    SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 4) >> 2);
  return r0;
}

/* Handle wcsr instructions.  */

void
lm32bf_wcsr_insn (SIM_CPU * current_cpu, USI f_csr, USI r1)
{
  SIM_DESC sd = CPU_STATE (current_cpu);
  host_callback *cb = STATE_CALLBACK (sd);

  /* Writing a 1 to IP CSR clears a bit, writing 0 has no effect.  */
  if (f_csr == LM32_CSR_IP)
    SET_H_CSR (f_csr, GET_H_CSR (f_csr) & ~r1);
  else
    SET_H_CSR (f_csr, r1);
}

/* Handle signals.  */

void
lm32_core_signal (SIM_DESC sd,
		  sim_cpu * cpu,
		  sim_cia cia,
		  unsigned map,
		  int nr_bytes,
		  address_word addr,
		  transfer_type transfer, sim_core_signals sig)
{
  const char *copy = (transfer == read_transfer ? "read" : "write");
  address_word ip = CIA_ADDR (cia);
  SIM_CPU *current_cpu = cpu;

  switch (sig)
    {
    case sim_core_unmapped_signal:
      sim_io_eprintf (sd,
		      "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
		      nr_bytes, copy, (unsigned long) addr,
		      (unsigned long) ip);
      SET_H_GR (30, ip);
      /* Save and clear interrupt enable.  */
      SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
      CPU_PC_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
      sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32,
		       sim_stopped, SIM_SIGSEGV);
      break;
    case sim_core_unaligned_signal:
      sim_io_eprintf (sd,
		      "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
		      nr_bytes, copy, (unsigned long) addr,
		      (unsigned long) ip);
      SET_H_GR (30, ip);
      /* Save and clear interrupt enable.  */
      SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
      CPU_PC_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
      sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32,
		       sim_stopped, SIM_SIGBUS);
      break;
    default:
      sim_engine_abort (sd, cpu, cia,
			"sim_core_signal - internal error - bad switch");
    }
}
Commit	Line	Data
c28c63d8 JB	1	/* Lattice Mico32 exception and system call support.
	2	Contributed by Jon Beniston <jon@beniston.com>
	3
3666a048	4	Copyright (C) 2009-2021 Free Software Foundation, Inc.
c28c63d8 JB	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	20
6df01ab8 MF	21	/* This must come before any other includes. */
	22	#include "defs.h"
	23
c28c63d8 JB	24	#define WANT_CPU lm32bf
	25	#define WANT_CPU_LM32BF
	26
	27	#include "sim-main.h"
61a0c964	28	#include "sim-syscall.h"
c28c63d8 JB	29	#include "lm32-sim.h"
	30	#include "targ-vals.h"
	31
c28c63d8 JB	32	/* Handle invalid instructions. */
	33
	34	SEM_PC
	35	sim_engine_invalid_insn (SIM_CPU * current_cpu, IADDR cia, SEM_PC pc)
	36	{
	37	SIM_DESC sd = CPU_STATE (current_cpu);
	38
	39	sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
	40
	41	return pc;
	42	}
	43
	44	/* Handle divide instructions. */
	45
	46	USI
	47	lm32bf_divu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2)
	48	{
	49	SIM_DESC sd = CPU_STATE (current_cpu);
	50	host_callback *cb = STATE_CALLBACK (sd);
	51
	52	/* Check for divide by zero */
	53	if (GET_H_GR (r1) == 0)
	54	{
	55	if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
	56	sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE);
	57	else
	58	{
	59	/* Save PC in exception address register. */
	60	SET_H_GR (30, pc);
	61	/* Save and clear interrupt enable. */
	62	SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
	63	/* Branch to divide by zero exception handler. */
	64	return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DIVIDE_BY_ZERO * 32;
	65	}
	66	}
	67	else
	68	{
	69	SET_H_GR (r2, (USI) GET_H_GR (r0) / (USI) GET_H_GR (r1));
	70	return pc + 4;
	71	}
	72	}
	73
	74	USI
	75	lm32bf_modu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2)
	76	{
	77	SIM_DESC sd = CPU_STATE (current_cpu);
	78	host_callback *cb = STATE_CALLBACK (sd);
	79
	80	/* Check for divide by zero. */
	81	if (GET_H_GR (r1) == 0)
	82	{
	83	if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
	84	sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE);
	85	else
	86	{
	87	/* Save PC in exception address register. */
	88	SET_H_GR (30, pc);
	89	/* Save and clear interrupt enable. */
	90	SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
	91	/* Branch to divide by zero exception handler. */
	92	return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DIVIDE_BY_ZERO * 32;
	93	}
	94	}
	95	else
96	{
97	SET_H_GR (r2, (USI) GET_H_GR (r0) % (USI) GET_H_GR (r1));
98	return pc + 4;
99	}
100	}
101
102	/* Handle break instructions. */
103
104	USI
105	lm32bf_break_insn (SIM_CPU * current_cpu, IADDR pc)
106	{
107	SIM_DESC sd = CPU_STATE (current_cpu);
108	host_callback *cb = STATE_CALLBACK (sd);
109	/* Breakpoint. */
110	if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
111	{
112	sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
113	return pc;
114	}
115	else
116	{
117	/* Save PC in breakpoint address register. */
118	SET_H_GR (31, pc);
119	/* Save and clear interrupt enable. */
120	SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 2);
121	/* Branch to breakpoint exception handler. */
122	return GET_H_CSR (LM32_CSR_DEBA) + LM32_EID_BREAKPOINT * 32;
123	}
124	}
125
126	/* Handle scall instructions. */
127
128	USI
129	lm32bf_scall_insn (SIM_CPU * current_cpu, IADDR pc)
130	{
131	SIM_DESC sd = CPU_STATE (current_cpu);
132	host_callback *cb = STATE_CALLBACK (sd);
133
134	if ((STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
135	\|\| (GET_H_GR (8) == TARGET_SYS_exit))
136	{
137	/* Delegate system call to host O/S. */
7d5c6c43 MF	138	long result, result2;
	139	int errcode;
	140
c28c63d8	141	/* Perform the system call. */
7d5c6c43 MF	142	sim_syscall_multi (current_cpu, GET_H_GR (8), GET_H_GR (1), GET_H_GR (2),
	143	GET_H_GR (3), GET_H_GR (4), &result, &result2,
	144	&errcode);
c28c63d8	145	/* Store the return value in the CPU's registers. */
7d5c6c43 MF	146	SET_H_GR (1, result);
	147	SET_H_GR (2, result2);
	148	SET_H_GR (3, errcode);
	149
c28c63d8 JB	150	/* Skip over scall instruction. */
	151	return pc + 4;
	152	}
	153	else
	154	{
	155	/* Save PC in exception address register. */
	156	SET_H_GR (30, pc);
	157	/* Save and clear interrupt enable */
	158	SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
	159	/* Branch to system call exception handler. */
	160	return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_SYSTEM_CALL * 32;
	161	}
	162	}
	163
	164	/* Handle b instructions. */
	165
	166	USI
	167	lm32bf_b_insn (SIM_CPU * current_cpu, USI r0, USI f_r0)
	168	{
	169	SIM_DESC sd = CPU_STATE (current_cpu);
	170	host_callback *cb = STATE_CALLBACK (sd);
	171
	172	/* Restore interrupt enable. */
	173	if (f_r0 == 30)
	174	SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 2) >> 1);
	175	else if (f_r0 == 31)
	176	SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 4) >> 2);
	177	return r0;
	178	}
	179
	180	/* Handle wcsr instructions. */
	181
	182	void
	183	lm32bf_wcsr_insn (SIM_CPU * current_cpu, USI f_csr, USI r1)
	184	{
	185	SIM_DESC sd = CPU_STATE (current_cpu);
	186	host_callback *cb = STATE_CALLBACK (sd);
	187
	188	/* Writing a 1 to IP CSR clears a bit, writing 0 has no effect. */
	189	if (f_csr == LM32_CSR_IP)
	190	SET_H_CSR (f_csr, GET_H_CSR (f_csr) & ~r1);
	191	else
	192	SET_H_CSR (f_csr, r1);
	193	}
	194
	195	/* Handle signals. */
	196
	197	void
	198	lm32_core_signal (SIM_DESC sd,
	199	sim_cpu * cpu,
	200	sim_cia cia,
	201	unsigned map,
	202	int nr_bytes,
	203	address_word addr,
	204	transfer_type transfer, sim_core_signals sig)
	205	{
	206	const char *copy = (transfer == read_transfer ? "read" : "write");
	207	address_word ip = CIA_ADDR (cia);
	208	SIM_CPU *current_cpu = cpu;
	209
	210	switch (sig)
	211	{
	212	case sim_core_unmapped_signal:
	213	sim_io_eprintf (sd,
214	"core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
215	nr_bytes, copy, (unsigned long) addr,
216	(unsigned long) ip);
217	SET_H_GR (30, ip);
218	/* Save and clear interrupt enable. */
219	SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
034685f9	220	CPU_PC_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
c28c63d8 JB	221	sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32,
	222	sim_stopped, SIM_SIGSEGV);
	223	break;
	224	case sim_core_unaligned_signal:
	225	sim_io_eprintf (sd,
	226	"core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
	227	nr_bytes, copy, (unsigned long) addr,
	228	(unsigned long) ip);
	229	SET_H_GR (30, ip);
	230	/* Save and clear interrupt enable. */
	231	SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
034685f9	232	CPU_PC_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
c28c63d8 JB	233	sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32,
	234	sim_stopped, SIM_SIGBUS);
	235	break;
	236	default:
	237	sim_engine_abort (sd, cpu, cia,
	238	"sim_core_signal - internal error - bad switch");
	239	}
	240	}