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d45a4bef
JB
1/* gdb.c --- sim interface to GDB.
2
8acc9f48 3Copyright (C) 2005-2013 Free Software Foundation, Inc.
d45a4bef
JB
4Contributed by Red Hat, Inc.
5
6This file is part of the GNU simulators.
7
4744ac1b
JB
8This program is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 3 of the License, or
11(at your option) any later version.
d45a4bef 12
4744ac1b
JB
13This program is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
d45a4bef
JB
17
18You should have received a copy of the GNU General Public License
4744ac1b 19along with this program. If not, see <http://www.gnu.org/licenses/>. */
d45a4bef 20
a6ff997c 21#include "config.h"
d45a4bef
JB
22#include <stdio.h>
23#include <assert.h>
24#include <signal.h>
25#include <string.h>
26#include <ctype.h>
27
28#include "ansidecl.h"
29#include "gdb/callback.h"
30#include "gdb/remote-sim.h"
31#include "gdb/signals.h"
32#include "gdb/sim-m32c.h"
33
34#include "cpu.h"
35#include "mem.h"
36#include "load.h"
37#include "syscalls.h"
7cc70e53
DD
38#ifdef TIMER_A
39#include "timer_a.h"
40#endif
d45a4bef
JB
41
42/* I don't want to wrap up all the minisim's data structures in an
43 object and pass that around. That'd be a big change, and neither
44 GDB nor run needs that ability.
45
46 So we just have one instance, that lives in global variables, and
47 each time we open it, we re-initialize it. */
48struct sim_state
49{
50 const char *message;
51};
52
53static struct sim_state the_minisim = {
54 "This is the sole m32c minisim instance. See libsim.a's global variables."
55};
56
57static int open;
58
59SIM_DESC
60sim_open (SIM_OPEN_KIND kind,
61 struct host_callback_struct *callback,
62 struct bfd *abfd, char **argv)
63{
3877a145 64 setbuf (stdout, 0);
d45a4bef
JB
65 if (open)
66 fprintf (stderr, "m32c minisim: re-opened sim\n");
67
68 /* The 'run' interface doesn't use this function, so we don't care
69 about KIND; it's always SIM_OPEN_DEBUG. */
70 if (kind != SIM_OPEN_DEBUG)
71 fprintf (stderr, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n",
72 kind);
73
74 if (abfd)
75 m32c_set_mach (bfd_get_mach (abfd));
76
77 /* We can use ABFD, if non-NULL to select the appropriate
78 architecture. But we only support the r8c right now. */
79
80 set_callbacks (callback);
81
82 /* We don't expect any command-line arguments. */
83
84 init_mem ();
85 init_regs ();
86
87 open = 1;
88 return &the_minisim;
89}
90
91static void
92check_desc (SIM_DESC sd)
93{
94 if (sd != &the_minisim)
95 fprintf (stderr, "m32c minisim: desc != &the_minisim\n");
96}
97
98void
99sim_close (SIM_DESC sd, int quitting)
100{
101 check_desc (sd);
102
103 /* Not much to do. At least free up our memory. */
104 init_mem ();
105
106 open = 0;
107}
108
109static bfd *
110open_objfile (const char *filename)
111{
112 bfd *prog = bfd_openr (filename, 0);
113
114 if (!prog)
115 {
116 fprintf (stderr, "Can't read %s\n", filename);
117 return 0;
118 }
119
120 if (!bfd_check_format (prog, bfd_object))
121 {
122 fprintf (stderr, "%s not a m32c program\n", filename);
123 return 0;
124 }
125
126 return prog;
127}
128
129
130SIM_RC
3877a145 131sim_load (SIM_DESC sd, char *prog, struct bfd * abfd, int from_tty)
d45a4bef
JB
132{
133 check_desc (sd);
134
135 if (!abfd)
136 abfd = open_objfile (prog);
137 if (!abfd)
138 return SIM_RC_FAIL;
139
140 m32c_load (abfd);
141
142 return SIM_RC_OK;
143}
144
145SIM_RC
3877a145 146sim_create_inferior (SIM_DESC sd, struct bfd * abfd, char **argv, char **env)
d45a4bef
JB
147{
148 check_desc (sd);
149
150 if (abfd)
151 m32c_load (abfd);
152
153 return SIM_RC_OK;
154}
155
156int
157sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
158{
159 check_desc (sd);
160
161 if (mem == 0)
162 return 0;
163
164 mem_get_blk ((int) mem, buf, length);
165
166 return length;
167}
168
169int
5558e7e6 170sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length)
d45a4bef
JB
171{
172 check_desc (sd);
173
174 mem_put_blk ((int) mem, buf, length);
175
176 return length;
177}
178
179
180/* Read the LENGTH bytes at BUF as an little-endian value. */
181static DI
182get_le (unsigned char *buf, int length)
183{
184 DI acc = 0;
185 while (--length >= 0)
186 acc = (acc << 8) + buf[length];
187
188 return acc;
189}
190
191/* Store VAL as a little-endian value in the LENGTH bytes at BUF. */
192static void
193put_le (unsigned char *buf, int length, DI val)
194{
195 int i;
196
197 for (i = 0; i < length; i++)
198 {
199 buf[i] = val & 0xff;
200 val >>= 8;
201 }
202}
203
204static int
205check_regno (enum m32c_sim_reg regno)
206{
207 return 0 <= regno && regno < m32c_sim_reg_num_regs;
208}
209
210static size_t
211mask_size (int addr_mask)
212{
213 switch (addr_mask)
214 {
215 case 0xffff:
216 return 2;
217 case 0xfffff:
218 case 0xffffff:
219 return 3;
220 default:
221 fprintf (stderr,
222 "m32c minisim: addr_mask_size: unexpected mask 0x%x\n",
223 addr_mask);
224 return sizeof (addr_mask);
225 }
226}
227
228static size_t
229reg_size (enum m32c_sim_reg regno)
230{
231 switch (regno)
232 {
233 case m32c_sim_reg_r0_bank0:
234 case m32c_sim_reg_r1_bank0:
235 case m32c_sim_reg_r2_bank0:
236 case m32c_sim_reg_r3_bank0:
237 case m32c_sim_reg_r0_bank1:
238 case m32c_sim_reg_r1_bank1:
239 case m32c_sim_reg_r2_bank1:
240 case m32c_sim_reg_r3_bank1:
241 case m32c_sim_reg_flg:
242 case m32c_sim_reg_svf:
243 return 2;
244
245 case m32c_sim_reg_a0_bank0:
246 case m32c_sim_reg_a1_bank0:
247 case m32c_sim_reg_fb_bank0:
248 case m32c_sim_reg_sb_bank0:
249 case m32c_sim_reg_a0_bank1:
250 case m32c_sim_reg_a1_bank1:
251 case m32c_sim_reg_fb_bank1:
252 case m32c_sim_reg_sb_bank1:
253 case m32c_sim_reg_usp:
254 case m32c_sim_reg_isp:
255 return mask_size (addr_mask);
256
257 case m32c_sim_reg_pc:
258 case m32c_sim_reg_intb:
259 case m32c_sim_reg_svp:
260 case m32c_sim_reg_vct:
261 return mask_size (membus_mask);
262
263 case m32c_sim_reg_dmd0:
264 case m32c_sim_reg_dmd1:
265 return 1;
266
267 case m32c_sim_reg_dct0:
268 case m32c_sim_reg_dct1:
269 case m32c_sim_reg_drc0:
270 case m32c_sim_reg_drc1:
271 return 2;
272
273 case m32c_sim_reg_dma0:
274 case m32c_sim_reg_dma1:
275 case m32c_sim_reg_dsa0:
276 case m32c_sim_reg_dsa1:
277 case m32c_sim_reg_dra0:
278 case m32c_sim_reg_dra1:
279 return 3;
280
281 default:
282 fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
283 regno);
284 return -1;
285 }
286}
287
288int
289sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
290{
291 size_t size;
292
293 check_desc (sd);
294
295 if (!check_regno (regno))
296 return 0;
297
298 size = reg_size (regno);
299 if (length == size)
300 {
301 DI val;
302
303 switch (regno)
304 {
305 case m32c_sim_reg_r0_bank0:
306 val = regs.r[0].r_r0;
307 break;
308 case m32c_sim_reg_r1_bank0:
309 val = regs.r[0].r_r1;
310 break;
311 case m32c_sim_reg_r2_bank0:
312 val = regs.r[0].r_r2;
313 break;
314 case m32c_sim_reg_r3_bank0:
315 val = regs.r[0].r_r3;
316 break;
317 case m32c_sim_reg_a0_bank0:
318 val = regs.r[0].r_a0;
319 break;
320 case m32c_sim_reg_a1_bank0:
321 val = regs.r[0].r_a1;
322 break;
323 case m32c_sim_reg_fb_bank0:
324 val = regs.r[0].r_fb;
325 break;
326 case m32c_sim_reg_sb_bank0:
327 val = regs.r[0].r_sb;
328 break;
329 case m32c_sim_reg_r0_bank1:
330 val = regs.r[1].r_r0;
331 break;
332 case m32c_sim_reg_r1_bank1:
333 val = regs.r[1].r_r1;
334 break;
335 case m32c_sim_reg_r2_bank1:
336 val = regs.r[1].r_r2;
337 break;
338 case m32c_sim_reg_r3_bank1:
339 val = regs.r[1].r_r3;
340 break;
341 case m32c_sim_reg_a0_bank1:
342 val = regs.r[1].r_a0;
343 break;
344 case m32c_sim_reg_a1_bank1:
345 val = regs.r[1].r_a1;
346 break;
347 case m32c_sim_reg_fb_bank1:
348 val = regs.r[1].r_fb;
349 break;
350 case m32c_sim_reg_sb_bank1:
351 val = regs.r[1].r_sb;
352 break;
353
354 case m32c_sim_reg_usp:
355 val = regs.r_usp;
356 break;
357 case m32c_sim_reg_isp:
358 val = regs.r_isp;
359 break;
360 case m32c_sim_reg_pc:
361 val = regs.r_pc;
362 break;
363 case m32c_sim_reg_intb:
364 val = regs.r_intbl * 65536 + regs.r_intbl;
365 break;
366 case m32c_sim_reg_flg:
367 val = regs.r_flags;
368 break;
369
370 /* These registers aren't implemented by the minisim. */
371 case m32c_sim_reg_svf:
372 case m32c_sim_reg_svp:
373 case m32c_sim_reg_vct:
374 case m32c_sim_reg_dmd0:
375 case m32c_sim_reg_dmd1:
376 case m32c_sim_reg_dct0:
377 case m32c_sim_reg_dct1:
378 case m32c_sim_reg_drc0:
379 case m32c_sim_reg_drc1:
380 case m32c_sim_reg_dma0:
381 case m32c_sim_reg_dma1:
382 case m32c_sim_reg_dsa0:
383 case m32c_sim_reg_dsa1:
384 case m32c_sim_reg_dra0:
385 case m32c_sim_reg_dra1:
386 return 0;
387
388 default:
389 fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
390 regno);
391 return -1;
392 }
393
394 put_le (buf, length, val);
395 }
396
397 return size;
398}
399
400int
401sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
402{
403 size_t size;
404
405 check_desc (sd);
406
407 if (!check_regno (regno))
dae477fe 408 return -1;
d45a4bef
JB
409
410 size = reg_size (regno);
411
412 if (length == size)
413 {
414 DI val = get_le (buf, length);
415
416 switch (regno)
417 {
418 case m32c_sim_reg_r0_bank0:
419 regs.r[0].r_r0 = val & 0xffff;
420 break;
421 case m32c_sim_reg_r1_bank0:
422 regs.r[0].r_r1 = val & 0xffff;
423 break;
424 case m32c_sim_reg_r2_bank0:
425 regs.r[0].r_r2 = val & 0xffff;
426 break;
427 case m32c_sim_reg_r3_bank0:
428 regs.r[0].r_r3 = val & 0xffff;
429 break;
430 case m32c_sim_reg_a0_bank0:
431 regs.r[0].r_a0 = val & addr_mask;
432 break;
433 case m32c_sim_reg_a1_bank0:
434 regs.r[0].r_a1 = val & addr_mask;
435 break;
436 case m32c_sim_reg_fb_bank0:
437 regs.r[0].r_fb = val & addr_mask;
438 break;
439 case m32c_sim_reg_sb_bank0:
440 regs.r[0].r_sb = val & addr_mask;
441 break;
442 case m32c_sim_reg_r0_bank1:
443 regs.r[1].r_r0 = val & 0xffff;
444 break;
445 case m32c_sim_reg_r1_bank1:
446 regs.r[1].r_r1 = val & 0xffff;
447 break;
448 case m32c_sim_reg_r2_bank1:
449 regs.r[1].r_r2 = val & 0xffff;
450 break;
451 case m32c_sim_reg_r3_bank1:
452 regs.r[1].r_r3 = val & 0xffff;
453 break;
454 case m32c_sim_reg_a0_bank1:
455 regs.r[1].r_a0 = val & addr_mask;
456 break;
457 case m32c_sim_reg_a1_bank1:
458 regs.r[1].r_a1 = val & addr_mask;
459 break;
460 case m32c_sim_reg_fb_bank1:
461 regs.r[1].r_fb = val & addr_mask;
462 break;
463 case m32c_sim_reg_sb_bank1:
464 regs.r[1].r_sb = val & addr_mask;
465 break;
466
467 case m32c_sim_reg_usp:
468 regs.r_usp = val & addr_mask;
469 break;
470 case m32c_sim_reg_isp:
471 regs.r_isp = val & addr_mask;
472 break;
473 case m32c_sim_reg_pc:
474 regs.r_pc = val & membus_mask;
475 break;
476 case m32c_sim_reg_intb:
477 regs.r_intbl = (val & membus_mask) & 0xffff;
478 regs.r_intbh = (val & membus_mask) >> 16;
479 break;
480 case m32c_sim_reg_flg:
481 regs.r_flags = val & 0xffff;
482 break;
483
484 /* These registers aren't implemented by the minisim. */
485 case m32c_sim_reg_svf:
486 case m32c_sim_reg_svp:
487 case m32c_sim_reg_vct:
488 case m32c_sim_reg_dmd0:
489 case m32c_sim_reg_dmd1:
490 case m32c_sim_reg_dct0:
491 case m32c_sim_reg_dct1:
492 case m32c_sim_reg_drc0:
493 case m32c_sim_reg_drc1:
494 case m32c_sim_reg_dma0:
495 case m32c_sim_reg_dma1:
496 case m32c_sim_reg_dsa0:
497 case m32c_sim_reg_dsa1:
498 case m32c_sim_reg_dra0:
499 case m32c_sim_reg_dra1:
500 return 0;
501
502 default:
503 fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
504 regno);
dae477fe 505 return 0;
d45a4bef
JB
506 }
507 }
508
509 return size;
510}
511
512void
513sim_info (SIM_DESC sd, int verbose)
514{
515 check_desc (sd);
516
517 printf ("The m32c minisim doesn't collect any statistics.\n");
518}
519
520static volatile int stop;
521static enum sim_stop reason;
522int siggnal;
523
524
525/* Given a signal number used by the M32C bsp (that is, newlib),
bba258ad 526 return a target signal number used by GDB. */
d45a4bef 527int
bba258ad 528m32c_signal_to_target (int m32c)
d45a4bef
JB
529{
530 switch (m32c)
531 {
532 case 4:
a493e3e2 533 return GDB_SIGNAL_ILL;
d45a4bef
JB
534
535 case 5:
a493e3e2 536 return GDB_SIGNAL_TRAP;
d45a4bef
JB
537
538 case 10:
a493e3e2 539 return GDB_SIGNAL_BUS;
d45a4bef
JB
540
541 case 11:
a493e3e2 542 return GDB_SIGNAL_SEGV;
d45a4bef
JB
543
544 case 24:
a493e3e2 545 return GDB_SIGNAL_XCPU;
d45a4bef
JB
546
547 case 2:
a493e3e2 548 return GDB_SIGNAL_INT;
d45a4bef
JB
549
550 case 8:
a493e3e2 551 return GDB_SIGNAL_FPE;
d45a4bef
JB
552
553 case 6:
a493e3e2 554 return GDB_SIGNAL_ABRT;
d45a4bef
JB
555 }
556
557 return 0;
558}
559
560
561/* Take a step return code RC and set up the variables consulted by
562 sim_stop_reason appropriately. */
563void
564handle_step (int rc)
565{
566 if (M32C_STEPPED (rc) || M32C_HIT_BREAK (rc))
567 {
568 reason = sim_stopped;
a493e3e2 569 siggnal = GDB_SIGNAL_TRAP;
d45a4bef
JB
570 }
571 else if (M32C_STOPPED (rc))
572 {
573 reason = sim_stopped;
bba258ad 574 siggnal = m32c_signal_to_target (M32C_STOP_SIG (rc));
d45a4bef
JB
575 }
576 else
577 {
578 assert (M32C_EXITED (rc));
579 reason = sim_exited;
580 siggnal = M32C_EXIT_STATUS (rc);
581 }
582}
583
584
585void
586sim_resume (SIM_DESC sd, int step, int sig_to_deliver)
587{
588 check_desc (sd);
589
590 if (sig_to_deliver != 0)
591 {
592 fprintf (stderr,
593 "Warning: the m32c minisim does not implement "
594 "signal delivery yet.\n" "Resuming with no signal.\n");
595 }
596
597 if (step)
3877a145
DD
598 {
599 handle_step (decode_opcode ());
600#ifdef TIMER_A
601 update_timer_a ();
602#endif
603 }
d45a4bef
JB
604 else
605 {
606 /* We don't clear 'stop' here, because then we would miss
607 interrupts that arrived on the way here. Instead, we clear
608 the flag in sim_stop_reason, after GDB has disabled the
609 interrupt signal handler. */
610 for (;;)
611 {
612 if (stop)
613 {
614 stop = 0;
615 reason = sim_stopped;
a493e3e2 616 siggnal = GDB_SIGNAL_INT;
d45a4bef
JB
617 break;
618 }
619
620 int rc = decode_opcode ();
3877a145
DD
621#ifdef TIMER_A
622 update_timer_a ();
623#endif
d45a4bef
JB
624
625 if (!M32C_STEPPED (rc))
626 {
627 handle_step (rc);
628 break;
629 }
630 }
631 }
3877a145 632 m32c_sim_restore_console ();
d45a4bef
JB
633}
634
635int
636sim_stop (SIM_DESC sd)
637{
638 stop = 1;
639
640 return 1;
641}
642
643void
644sim_stop_reason (SIM_DESC sd, enum sim_stop *reason_p, int *sigrc_p)
645{
646 check_desc (sd);
647
648 *reason_p = reason;
649 *sigrc_p = siggnal;
650}
651
652void
653sim_do_command (SIM_DESC sd, char *cmd)
654{
655 check_desc (sd);
656
657 char *p = cmd;
658
659 /* Skip leading whitespace. */
660 while (isspace (*p))
661 p++;
662
663 /* Find the extent of the command word. */
664 for (p = cmd; *p; p++)
665 if (isspace (*p))
666 break;
667
668 /* Null-terminate the command word, and record the start of any
669 further arguments. */
670 char *args;
671 if (*p)
672 {
673 *p = '\0';
674 args = p + 1;
675 while (isspace (*args))
676 args++;
677 }
678 else
679 args = p;
680
681 if (strcmp (cmd, "trace") == 0)
682 {
683 if (strcmp (args, "on") == 0)
684 trace = 1;
685 else if (strcmp (args, "off") == 0)
686 trace = 0;
687 else
688 printf ("The 'sim trace' command expects 'on' or 'off' "
689 "as an argument.\n");
690 }
691 else if (strcmp (cmd, "verbose") == 0)
692 {
693 if (strcmp (args, "on") == 0)
694 verbose = 1;
695 else if (strcmp (args, "off") == 0)
696 verbose = 0;
697 else
698 printf ("The 'sim verbose' command expects 'on' or 'off'"
699 " as an argument.\n");
700 }
701 else
702 printf ("The 'sim' command expects either 'trace' or 'verbose'"
703 " as a subcommand.\n");
704}
af9f7da7
MF
705
706char **
707sim_complete_command (SIM_DESC sd, char *text, char *word)
708{
709 return NULL;
710}