[thirdparty/binutils-gdb.git] / sim / m32r / m32r-sim.h

/* collection of junk waiting time to sort out
   Copyright (C) 1996-2021 Free Software Foundation, Inc.
   Contributed by Cygnus Support.

   This file is part of GDB, the GNU debugger.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef M32R_SIM_H
#define M32R_SIM_H

/* GDB register numbers.  */
#define PSW_REGNUM	16
#define CBR_REGNUM	17
#define SPI_REGNUM	18
#define SPU_REGNUM	19
#define BPC_REGNUM	20
#define PC_REGNUM	21
#define ACCL_REGNUM	22
#define ACCH_REGNUM	23
#define ACC1L_REGNUM	24
#define ACC1H_REGNUM	25
#define BBPSW_REGNUM	26
#define BBPC_REGNUM	27
#define EVB_REGNUM	28

extern int m32r_decode_gdb_ctrl_regnum (int);

/* Cover macros for hardware accesses.
   FIXME: Eventually move to cgen.  */
#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)

#ifndef GET_H_CR
extern USI  m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);

#define GET_H_CR(regno) \
  XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
#define SET_H_CR(regno, val) \
  XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
#endif

#ifndef  GET_H_PSW
extern UQI  m32rbf_h_psw_get_handler (SIM_CPU *);
extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);

#define GET_H_PSW() \
  XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
#define SET_H_PSW(val) \
  XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
#endif

/* FIXME: These prototypes are necessary because the cgen generated
   cpu.h, cpux.h and cpu2.h headers do not provide them, and functions
   which take or return parameters that are larger than an int must be
   prototyed in order for them to work correctly.

   The correct solution is to fix the code in cgen/sim.scm to generate
   prototypes for each of the functions it generates.  */
extern DI   m32rbf_h_accum_get_handler (SIM_CPU *);
extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
extern DI   m32r2f_h_accums_get_handler (SIM_CPU *, UINT);
extern void m32r2f_h_accums_set_handler (SIM_CPU *, UINT, DI);

#ifndef  GET_H_ACCUM
#define GET_H_ACCUM() \
  XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
#define SET_H_ACCUM(val) \
  XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
#endif
\f
/* Misc. profile data.  */

typedef struct {
  /* nop insn slot filler count */
  unsigned int fillnop_count;
  /* number of parallel insns */
  unsigned int parallel_count;

  /* FIXME: generalize this to handle all insn lengths, move to common.  */
  /* number of short insns, not including parallel ones */
  unsigned int short_count;
  /* number of long insns */
  unsigned int long_count;

  /* Working area for computing cycle counts.  */
  unsigned long insn_cycles; /* FIXME: delete */
  unsigned long cti_stall;
  unsigned long load_stall;
  unsigned long biggest_cycles;

  /* Bitmask of registers loaded by previous insn.  */
  unsigned int load_regs;
  /* Bitmask of registers loaded by current insn.  */
  unsigned int load_regs_pending;
} M32R_MISC_PROFILE;

/* Initialize the working area.  */
void m32r_init_insn_cycles (SIM_CPU *, int);
/* Update the totals for the insn.  */
void m32r_record_insn_cycles (SIM_CPU *, int);

/* This is invoked by the nop pattern in the .cpu file.  */
#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
do { \
  if (PROFILE_INSN_P (cpu) \
      && (addr & 3) != 0) \
    ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
} while (0)

/* This is invoked by the execute section of mloop{,x}.in.  */
#define PROFILE_COUNT_PARINSNS(cpu) \
do { \
  if (PROFILE_INSN_P (cpu)) \
    ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
} while (0)

/* This is invoked by the execute section of mloop{,x}.in.  */
#define PROFILE_COUNT_SHORTINSNS(cpu) \
do { \
  if (PROFILE_INSN_P (cpu)) \
    ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
} while (0)

/* This is invoked by the execute section of mloop{,x}.in.  */
#define PROFILE_COUNT_LONGINSNS(cpu) \
do { \
  if (PROFILE_INSN_P (cpu)) \
    ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
} while (0)
\f
#define GETTWI GETTSI
#define SETTWI SETTSI
\f
/* Additional execution support.  */

\f
/* Hardware/device support.
   ??? Will eventually want to move device stuff to config files.  */

/* Exception, Interrupt, and Trap addresses */
#define EIT_SYSBREAK_ADDR	0x10
#define EIT_RSVD_INSN_ADDR	0x20
#define EIT_ADDR_EXCP_ADDR	0x30
#define EIT_TRAP_BASE_ADDR	0x40
#define EIT_EXTERN_ADDR		0x80
#define EIT_RESET_ADDR		0x7ffffff0
#define EIT_WAKEUP_ADDR		0x7ffffff0

/* Special purpose traps.  */
#define TRAP_SYSCALL	0
#define TRAP_BREAKPOINT	1

/* Handle the trap insn.  */
USI m32r_trap (SIM_CPU *, PCADDR, int);

#endif /* M32R_SIM_H */
Commit	Line	Data
c906108c	1	/* collection of junk waiting time to sort out
3666a048	2	Copyright (C) 1996-2021 Free Software Foundation, Inc.
c906108c SS	3	Contributed by Cygnus Support.
c906108c SS	4
16b47b25	5	This file is part of GDB, the GNU debugger.
c906108c	6
16b47b25 NC	7	This program is free software; you can redistribute it and/or modify
16b47b25 NC	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
c906108c	11
16b47b25 NC	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
c906108c	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c SS	19
	20	#ifndef M32R_SIM_H
	21	#define M32R_SIM_H
	22
16b47b25	23	/* GDB register numbers. */
c906108c SS	24	#define PSW_REGNUM 16
	25	#define CBR_REGNUM 17
	26	#define SPI_REGNUM 18
	27	#define SPU_REGNUM 19
	28	#define BPC_REGNUM 20
	29	#define PC_REGNUM 21
	30	#define ACCL_REGNUM 22
	31	#define ACCH_REGNUM 23
	32	#define ACC1L_REGNUM 24
	33	#define ACC1H_REGNUM 25
	34	#define BBPSW_REGNUM 26
	35	#define BBPC_REGNUM 27
16b47b25	36	#define EVB_REGNUM 28
c906108c SS	37
	38	extern int m32r_decode_gdb_ctrl_regnum (int);
	39
	40	/* Cover macros for hardware accesses.
	41	FIXME: Eventually move to cgen. */
	42	#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
	43
16b47b25 NC	44	#ifndef GET_H_CR
16b47b25 NC	45	extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
c906108c	46	extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
16b47b25	47
0b2e03b4 AC	48	#define GET_H_CR(regno) \
	49	XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
	50	#define SET_H_CR(regno, val) \
	51	XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
16b47b25	52	#endif
c906108c	53
16b47b25 NC	54	#ifndef GET_H_PSW
16b47b25 NC	55	extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
c906108c	56	extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
16b47b25	57
0b2e03b4 AC	58	#define GET_H_PSW() \
	59	XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
	60	#define SET_H_PSW(val) \
	61	XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
16b47b25	62	#endif
c906108c	63
94cde56a NC	64	/* FIXME: These prototypes are necessary because the cgen generated
	65	cpu.h, cpux.h and cpu2.h headers do not provide them, and functions
	66	which take or return parameters that are larger than an int must be
	67	prototyed in order for them to work correctly.
	68
	69	The correct solution is to fix the code in cgen/sim.scm to generate
	70	prototypes for each of the functions it generates. */
16b47b25	71	extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
c906108c	72	extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
94cde56a NC	73	extern DI m32r2f_h_accums_get_handler (SIM_CPU *, UINT);
94cde56a NC	74	extern void m32r2f_h_accums_set_handler (SIM_CPU *, UINT, DI);
16b47b25	75
94cde56a	76	#ifndef GET_H_ACCUM
0b2e03b4 AC	77	#define GET_H_ACCUM() \
	78	XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
	79	#define SET_H_ACCUM(val) \
	80	XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
16b47b25	81	#endif
c906108c SS	82	\f
	83	/* Misc. profile data. */
	84
	85	typedef struct {
	86	/* nop insn slot filler count */
	87	unsigned int fillnop_count;
	88	/* number of parallel insns */
	89	unsigned int parallel_count;
	90
	91	/* FIXME: generalize this to handle all insn lengths, move to common. */
	92	/* number of short insns, not including parallel ones */
	93	unsigned int short_count;
	94	/* number of long insns */
	95	unsigned int long_count;
	96
	97	/* Working area for computing cycle counts. */
	98	unsigned long insn_cycles; /* FIXME: delete */
	99	unsigned long cti_stall;
	100	unsigned long load_stall;
	101	unsigned long biggest_cycles;
	102
	103	/* Bitmask of registers loaded by previous insn. */
	104	unsigned int load_regs;
	105	/* Bitmask of registers loaded by current insn. */
	106	unsigned int load_regs_pending;
	107	} M32R_MISC_PROFILE;
	108
	109	/* Initialize the working area. */
	110	void m32r_init_insn_cycles (SIM_CPU *, int);
	111	/* Update the totals for the insn. */
	112	void m32r_record_insn_cycles (SIM_CPU *, int);
	113
	114	/* This is invoked by the nop pattern in the .cpu file. */
	115	#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
	116	do { \
	117	if (PROFILE_INSN_P (cpu) \
	118	&& (addr & 3) != 0) \
	119	++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
	120	} while (0)
	121
	122	/* This is invoked by the execute section of mloop{,x}.in. */
	123	#define PROFILE_COUNT_PARINSNS(cpu) \
	124	do { \
	125	if (PROFILE_INSN_P (cpu)) \
	126	++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
	127	} while (0)
	128
	129	/* This is invoked by the execute section of mloop{,x}.in. */
	130	#define PROFILE_COUNT_SHORTINSNS(cpu) \
	131	do { \
	132	if (PROFILE_INSN_P (cpu)) \
	133	++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
	134	} while (0)
	135
	136	/* This is invoked by the execute section of mloop{,x}.in. */
	137	#define PROFILE_COUNT_LONGINSNS(cpu) \
	138	do { \
	139	if (PROFILE_INSN_P (cpu)) \
	140	++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
	141	} while (0)
	142	\f
	143	#define GETTWI GETTSI
	144	#define SETTWI SETTSI
	145	\f
146	/* Additional execution support. */
147
148	\f
149	/* Hardware/device support.
150	??? Will eventually want to move device stuff to config files. */
151
152	/* Exception, Interrupt, and Trap addresses */
153	#define EIT_SYSBREAK_ADDR 0x10
154	#define EIT_RSVD_INSN_ADDR 0x20
155	#define EIT_ADDR_EXCP_ADDR 0x30
156	#define EIT_TRAP_BASE_ADDR 0x40
157	#define EIT_EXTERN_ADDR 0x80
158	#define EIT_RESET_ADDR 0x7ffffff0
159	#define EIT_WAKEUP_ADDR 0x7ffffff0
160
161	/* Special purpose traps. */
162	#define TRAP_SYSCALL 0
163	#define TRAP_BREAKPOINT 1
164
c906108c SS	165	/* Handle the trap insn. */
	166	USI m32r_trap (SIM_CPU *, PCADDR, int);
	167
	168	#endif /* M32R_SIM_H */