[thirdparty/binutils-gdb.git] / sim / m32r / m32rx.c

/* m32rx simulator support code
   Copyright (C) 1997-2021 Free Software Foundation, Inc.
   Contributed by Cygnus Support.

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* This must come before any other includes.  */
#include "defs.h"

#define WANT_CPU m32rxf
#define WANT_CPU_M32RXF

#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"

/* The contents of BUF are in target byte order.  */

int
m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
  return m32rbf_fetch_register (current_cpu, rn, buf, len);
}

/* The contents of BUF are in target byte order.  */

int
m32rxf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
  return m32rbf_store_register (current_cpu, rn, buf, len);
}
\f
/* Cover fns to get/set the control registers.
   FIXME: Duplicated from m32r.c.  The issue is structure offsets.  */

USI
m32rxf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
{
  switch (cr)
    {
    case H_CR_PSW : /* psw */
      return (((CPU (h_bpsw) & 0xc1) << 8)
	      | ((CPU (h_psw) & 0xc0) << 0)
	      | GET_H_COND ());
    case H_CR_BBPSW : /* backup backup psw */
      return CPU (h_bbpsw) & 0xc1;
    case H_CR_CBR : /* condition bit */
      return GET_H_COND ();
    case H_CR_SPI : /* interrupt stack pointer */
      if (! GET_H_SM ())
	return CPU (h_gr[H_GR_SP]);
      else
	return CPU (h_cr[H_CR_SPI]);
    case H_CR_SPU : /* user stack pointer */
      if (GET_H_SM ())
	return CPU (h_gr[H_GR_SP]);
      else
	return CPU (h_cr[H_CR_SPU]);
    case H_CR_BPC : /* backup pc */
      return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
    case H_CR_BBPC : /* backup backup pc */
      return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
    case 4 : /* ??? unspecified, but apparently available */
    case 5 : /* ??? unspecified, but apparently available */
      return CPU (h_cr[cr]);
    default :
      return 0;
    }
}

void
m32rxf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
{
  switch (cr)
    {
    case H_CR_PSW : /* psw */
      {
	int old_sm = (CPU (h_psw) & 0x80) != 0;
	int new_sm = (newval & 0x80) != 0;
	CPU (h_bpsw) = (newval >> 8) & 0xff;
	CPU (h_psw) = newval & 0xff;
	SET_H_COND (newval & 1);
	/* When switching stack modes, update the registers.  */
	if (old_sm != new_sm)
	  {
	    if (old_sm)
	      {
		/* Switching user -> system.  */
		CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
		CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
	      }
	    else
	      {
		/* Switching system -> user.  */
		CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
		CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
	      }
	  }
	break;
      }
    case H_CR_BBPSW : /* backup backup psw */
      CPU (h_bbpsw) = newval & 0xff;
      break;
    case H_CR_CBR : /* condition bit */
      SET_H_COND (newval & 1);
      break;
    case H_CR_SPI : /* interrupt stack pointer */
      if (! GET_H_SM ())
	CPU (h_gr[H_GR_SP]) = newval;
      else
	CPU (h_cr[H_CR_SPI]) = newval;
      break;
    case H_CR_SPU : /* user stack pointer */
      if (GET_H_SM ())
	CPU (h_gr[H_GR_SP]) = newval;
      else
	CPU (h_cr[H_CR_SPU]) = newval;
      break;
    case H_CR_BPC : /* backup pc */
      CPU (h_cr[H_CR_BPC]) = newval;
      break;
    case H_CR_BBPC : /* backup backup pc */
      CPU (h_cr[H_CR_BBPC]) = newval;
      break;
    case 4 : /* ??? unspecified, but apparently available */
    case 5 : /* ??? unspecified, but apparently available */
      CPU (h_cr[cr]) = newval;
      break;
    default :
      /* ignore */
      break;
    }
}

/* Cover fns to access h-psw.  */

UQI
m32rxf_h_psw_get_handler (SIM_CPU *current_cpu)
{
  return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
}

void
m32rxf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
{
  CPU (h_psw) = newval;
  CPU (h_cond) = newval & 1;
}

/* Cover fns to access h-accum.  */

DI
m32rxf_h_accum_get_handler (SIM_CPU *current_cpu)
{
  /* Sign extend the top 8 bits.  */
  DI r;
  r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
  r = XORDI (r, MAKEDI (0x800000, 0));
  r = SUBDI (r, MAKEDI (0x800000, 0));
  return r;
}

void
m32rxf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
{
  CPU (h_accum) = newval;
}

/* Cover fns to access h-accums.  */

DI
m32rxf_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
{
  /* FIXME: Yes, this is just a quick hack.  */
  DI r;
  if (regno == 0)
    r = CPU (h_accum);
  else
    r = CPU (h_accums[1]);
  /* Sign extend the top 8 bits.  */
  r = ANDDI (r, MAKEDI (0xffffff, 0xffffffff));
  r = XORDI (r, MAKEDI (0x800000, 0));
  r = SUBDI (r, MAKEDI (0x800000, 0));
  return r;
}

void
m32rxf_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)
{
  /* FIXME: Yes, this is just a quick hack.  */
  if (regno == 0)
    CPU (h_accum) = newval;
  else
    CPU (h_accums[1]) = newval;
}
\f
#if WITH_PROFILE_MODEL_P

/* Initialize cycle counting for an insn.
   FIRST_P is non-zero if this is the first insn in a set of parallel
   insns.  */

void
m32rxf_model_insn_before (SIM_CPU *cpu, int first_p)
{
  m32rbf_model_insn_before (cpu, first_p);
}

/* Record the cycles computed for an insn.
   LAST_P is non-zero if this is the last insn in a set of parallel insns,
   and we update the total cycle count.
   CYCLES is the cycle count of the insn.  */

void
m32rxf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
{
  m32rbf_model_insn_after (cpu, last_p, cycles);
}

static INLINE void
check_load_stall (SIM_CPU *cpu, int regno)
{
  UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;

  if (regno != -1
      && (h_gr & (1 << regno)) != 0)
    {
      CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
      if (TRACE_INSN_P (cpu))
	cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
    }
}

int
m32rxf_model_m32rx_u_exec (SIM_CPU *cpu, const IDESC *idesc,
			   int unit_num, int referenced,
			   INT sr, INT sr2, INT dr)
{
  check_load_stall (cpu, sr);
  check_load_stall (cpu, sr2);
  return idesc->timing->units[unit_num].done;
}

int
m32rxf_model_m32rx_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
			   int unit_num, int referenced,
			   INT src1, INT src2)
{
  check_load_stall (cpu, src1);
  check_load_stall (cpu, src2);
  return idesc->timing->units[unit_num].done;
}

int
m32rxf_model_m32rx_u_mac (SIM_CPU *cpu, const IDESC *idesc,
			   int unit_num, int referenced,
			   INT src1, INT src2)
{
  check_load_stall (cpu, src1);
  check_load_stall (cpu, src2);
  return idesc->timing->units[unit_num].done;
}

int
m32rxf_model_m32rx_u_cti (SIM_CPU *cpu, const IDESC *idesc,
			  int unit_num, int referenced,
			  INT sr)
{
  PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
  int taken_p = (referenced & (1 << 1)) != 0;

  check_load_stall (cpu, sr);
  if (taken_p)
    {
      CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
      PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
    }
  else
    PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
  return idesc->timing->units[unit_num].done;
}

int
m32rxf_model_m32rx_u_load (SIM_CPU *cpu, const IDESC *idesc,
			   int unit_num, int referenced,
			   INT sr, INT dr)
{
  CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
  return idesc->timing->units[unit_num].done;
}

int
m32rxf_model_m32rx_u_store (SIM_CPU *cpu, const IDESC *idesc,
			    int unit_num, int referenced,
			    INT src1, INT src2)
{
  return idesc->timing->units[unit_num].done;
}

#endif /* WITH_PROFILE_MODEL_P */
Commit	Line	Data
2df3850c	1	/* m32rx simulator support code
3666a048	2	Copyright (C) 1997-2021 Free Software Foundation, Inc.
2df3850c JM	3	Contributed by Cygnus Support.
	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
2df3850c JM	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
2df3850c	19
6df01ab8 MF	20	/* This must come before any other includes. */
	21	#include "defs.h"
	22
2df3850c JM	23	#define WANT_CPU m32rxf
	24	#define WANT_CPU_M32RXF
	25
	26	#include "sim-main.h"
	27	#include "cgen-mem.h"
	28	#include "cgen-ops.h"
	29
	30	/* The contents of BUF are in target byte order. */
	31
	32	int
	33	m32rxf_fetch_register (SIM_CPU current_cpu, int rn, unsigned char buf, int len)
	34	{
	35	return m32rbf_fetch_register (current_cpu, rn, buf, len);
	36	}
	37
	38	/* The contents of BUF are in target byte order. */
	39
	40	int
	41	m32rxf_store_register (SIM_CPU current_cpu, int rn, unsigned char buf, int len)
	42	{
	43	return m32rbf_store_register (current_cpu, rn, buf, len);
	44	}
	45	\f
	46	/* Cover fns to get/set the control registers.
	47	FIXME: Duplicated from m32r.c. The issue is structure offsets. */
	48
	49	USI
	50	m32rxf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
	51	{
	52	switch (cr)
	53	{
	54	case H_CR_PSW : /* psw */
	55	return (((CPU (h_bpsw) & 0xc1) << 8)
	56	\| ((CPU (h_psw) & 0xc0) << 0)
	57	\| GET_H_COND ());
	58	case H_CR_BBPSW : /* backup backup psw */
	59	return CPU (h_bbpsw) & 0xc1;
	60	case H_CR_CBR : /* condition bit */
	61	return GET_H_COND ();
	62	case H_CR_SPI : /* interrupt stack pointer */
	63	if (! GET_H_SM ())
	64	return CPU (h_gr[H_GR_SP]);
	65	else
	66	return CPU (h_cr[H_CR_SPI]);
	67	case H_CR_SPU : /* user stack pointer */
	68	if (GET_H_SM ())
	69	return CPU (h_gr[H_GR_SP]);
	70	else
	71	return CPU (h_cr[H_CR_SPU]);
	72	case H_CR_BPC : /* backup pc */
	73	return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
	74	case H_CR_BBPC : /* backup backup pc */
	75	return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
	76	case 4 : /* ??? unspecified, but apparently available */
	77	case 5 : /* ??? unspecified, but apparently available */
	78	return CPU (h_cr[cr]);
	79	default :
	80	return 0;
	81	}
	82	}
	83
	84	void
	85	m32rxf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
	86	{
87	switch (cr)
88	{
89	case H_CR_PSW : /* psw */
90	{
91	int old_sm = (CPU (h_psw) & 0x80) != 0;
92	int new_sm = (newval & 0x80) != 0;
93	CPU (h_bpsw) = (newval >> 8) & 0xff;
94	CPU (h_psw) = newval & 0xff;
95	SET_H_COND (newval & 1);
96	/* When switching stack modes, update the registers. */
97	if (old_sm != new_sm)
98	{
99	if (old_sm)
100	{
101	/* Switching user -> system. */
102	CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
103	CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
104	}
105	else
106	{
107	/* Switching system -> user. */
108	CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
109	CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
110	}
111	}
112	break;
113	}
114	case H_CR_BBPSW : /* backup backup psw */
115	CPU (h_bbpsw) = newval & 0xff;
116	break;
117	case H_CR_CBR : /* condition bit */
118	SET_H_COND (newval & 1);
119	break;
120	case H_CR_SPI : /* interrupt stack pointer */
121	if (! GET_H_SM ())
122	CPU (h_gr[H_GR_SP]) = newval;
123	else
124	CPU (h_cr[H_CR_SPI]) = newval;
125	break;
126	case H_CR_SPU : /* user stack pointer */
127	if (GET_H_SM ())
128	CPU (h_gr[H_GR_SP]) = newval;
129	else
130	CPU (h_cr[H_CR_SPU]) = newval;
131	break;
132	case H_CR_BPC : /* backup pc */
133	CPU (h_cr[H_CR_BPC]) = newval;
134	break;
135	case H_CR_BBPC : /* backup backup pc */
136	CPU (h_cr[H_CR_BBPC]) = newval;
137	break;
138	case 4 : /* ??? unspecified, but apparently available */
139	case 5 : /* ??? unspecified, but apparently available */
140	CPU (h_cr[cr]) = newval;
141	break;
142	default :
143	/* ignore */
144	break;
145	}
146	}
147
148	/* Cover fns to access h-psw. */
149
150	UQI
151	m32rxf_h_psw_get_handler (SIM_CPU *current_cpu)
152	{
153	return (CPU (h_psw) & 0xfe) \| (CPU (h_cond) & 1);
154	}
155
156	void
157	m32rxf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
158	{
159	CPU (h_psw) = newval;
160	CPU (h_cond) = newval & 1;
161	}
162
163	/* Cover fns to access h-accum. */
164
165	DI
166	m32rxf_h_accum_get_handler (SIM_CPU *current_cpu)
167	{
168	/* Sign extend the top 8 bits. */
169	DI r;
170	r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
171	r = XORDI (r, MAKEDI (0x800000, 0));
172	r = SUBDI (r, MAKEDI (0x800000, 0));
173	return r;
174	}
175
176	void
177	m32rxf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
178	{
179	CPU (h_accum) = newval;
180	}
181
182	/* Cover fns to access h-accums. */
183
184	DI
185	m32rxf_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
186	{
187	/* FIXME: Yes, this is just a quick hack. */
188	DI r;
189	if (regno == 0)
190	r = CPU (h_accum);
191	else
192	r = CPU (h_accums[1]);
193	/* Sign extend the top 8 bits. */
194	r = ANDDI (r, MAKEDI (0xffffff, 0xffffffff));
195	r = XORDI (r, MAKEDI (0x800000, 0));
196	r = SUBDI (r, MAKEDI (0x800000, 0));
197	return r;
198	}
199
200	void
201	m32rxf_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)
202	{
203	/* FIXME: Yes, this is just a quick hack. */
204	if (regno == 0)
205	CPU (h_accum) = newval;
206	else
207	CPU (h_accums[1]) = newval;
208	}
209	\f
210	#if WITH_PROFILE_MODEL_P
211
212	/* Initialize cycle counting for an insn.
213	FIRST_P is non-zero if this is the first insn in a set of parallel
214	insns. */
215
216	void
217	m32rxf_model_insn_before (SIM_CPU *cpu, int first_p)
218	{
219	m32rbf_model_insn_before (cpu, first_p);
220	}
221
222	/* Record the cycles computed for an insn.
223	LAST_P is non-zero if this is the last insn in a set of parallel insns,
224	and we update the total cycle count.
225	CYCLES is the cycle count of the insn. */
226
227	void
228	m32rxf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
229	{
230	m32rbf_model_insn_after (cpu, last_p, cycles);
231	}
232
233	static INLINE void
234	check_load_stall (SIM_CPU *cpu, int regno)
235	{
236	UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
237
238	if (regno != -1
239	&& (h_gr & (1 << regno)) != 0)
240	{
241	CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
242	if (TRACE_INSN_P (cpu))
243	cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
244	}
245	}
246
247	int
248	m32rxf_model_m32rx_u_exec (SIM_CPU cpu, const IDESC idesc,
249	int unit_num, int referenced,
250	INT sr, INT sr2, INT dr)
251	{
252	check_load_stall (cpu, sr);
253	check_load_stall (cpu, sr2);
254	return idesc->timing->units[unit_num].done;
255	}
256
257	int
258	m32rxf_model_m32rx_u_cmp (SIM_CPU cpu, const IDESC idesc,
259	int unit_num, int referenced,
260	INT src1, INT src2)
261	{
262	check_load_stall (cpu, src1);
263	check_load_stall (cpu, src2);
264	return idesc->timing->units[unit_num].done;
265	}
266
267	int
268	m32rxf_model_m32rx_u_mac (SIM_CPU cpu, const IDESC idesc,
269	int unit_num, int referenced,
270	INT src1, INT src2)
271	{
272	check_load_stall (cpu, src1);
273	check_load_stall (cpu, src2);
274	return idesc->timing->units[unit_num].done;
275	}
276
277	int
278	m32rxf_model_m32rx_u_cti (SIM_CPU cpu, const IDESC idesc,
279	int unit_num, int referenced,
280	INT sr)
281	{
282	PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
283	int taken_p = (referenced & (1 << 1)) != 0;
284
285	check_load_stall (cpu, sr);
286	if (taken_p)
287	{
288	CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
289	PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
290	}
291	else
292	PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
293	return idesc->timing->units[unit_num].done;
294	}
295
296	int
297	m32rxf_model_m32rx_u_load (SIM_CPU cpu, const IDESC idesc,
298	int unit_num, int referenced,
299	INT sr, INT dr)
300	{
301	CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending \|= (1 << dr);
302	return idesc->timing->units[unit_num].done;
303	}
304
305	int
306	m32rxf_model_m32rx_u_store (SIM_CPU cpu, const IDESC idesc,
307	int unit_num, int referenced,
308	INT src1, INT src2)
309	{
310	return idesc->timing->units[unit_num].done;
311	}
312
313	#endif /* WITH_PROFILE_MODEL_P */