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* config/sh/tm-sh.h (BELIEVE_PCC_PROMOTION): Define, so that
[thirdparty/binutils-gdb.git] / sim / m32r / modelx.c
CommitLineData
368fc7db 1/* Simulator model support for m32rxf.
e0bd6e18 2
368fc7db 3THIS FILE IS MACHINE GENERATED WITH CGEN.
e0bd6e18 4
ddfae34d 5Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
e0bd6e18
DE		 6
7This file is part of the GNU Simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
368fc7db
DE		 25#define WANT_CPU m32rxf
26#define WANT_CPU_M32RXF
e0bd6e18
DE		 27
28#include "sim-main.h"
e0bd6e18
DE		 29
30/* The profiling data is recorded here, but is accessed via the profiling
31 mechanism. After all, this is information for profiling. */
32
33#if WITH_PROFILE_MODEL_P
34
368fc7db
DE		 35/* Model handlers for each insn. */
36
368fc7db
DE		 37static int
38model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg)
39{
40#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 41 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
42 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 43 int cycles = 0;
44 {
45 int referenced = 0;
46 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 47 INT in_sr = -1;
48 INT in_dr = -1;
49 INT out_dr = -1;
50 in_sr = FLD (in_sr);
51 in_dr = FLD (in_dr);
52 out_dr = FLD (out_dr);
368fc7db 53 referenced |= 1 << 0;
eb234697 54 referenced |= 1 << 1;
368fc7db 55 referenced |= 1 << 2;
eb234697 56 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 57 }
58 return cycles;
59#undef FLD
60}
61
62static int
63model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg)
64{
65#define FLD(f) abuf->fields.fmt_add3.f
ddfae34d
DE		 66 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
67 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 68 int cycles = 0;
69 {
70 int referenced = 0;
71 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 72 INT in_sr = -1;
73 INT in_dr = -1;
74 INT out_dr = -1;
75 in_sr = FLD (in_sr);
76 out_dr = FLD (out_dr);
368fc7db
DE		 77 referenced |= 1 << 0;
78 referenced |= 1 << 2;
eb234697 79 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 80 }
81 return cycles;
82#undef FLD
83}
84
85static int
86model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg)
87{
88#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 89 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
90 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 91 int cycles = 0;
92 {
93 int referenced = 0;
94 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 95 INT in_sr = -1;
96 INT in_dr = -1;
97 INT out_dr = -1;
98 in_sr = FLD (in_sr);
99 in_dr = FLD (in_dr);
100 out_dr = FLD (out_dr);
368fc7db 101 referenced |= 1 << 0;
eb234697 102 referenced |= 1 << 1;
368fc7db 103 referenced |= 1 << 2;
eb234697 104 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 105 }
106 return cycles;
107#undef FLD
108}
109
110static int
111model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg)
112{
113#define FLD(f) abuf->fields.fmt_and3.f
ddfae34d
DE		 114 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
115 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 116 int cycles = 0;
117 {
118 int referenced = 0;
119 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 120 INT in_sr = -1;
121 INT in_dr = -1;
122 INT out_dr = -1;
123 in_sr = FLD (in_sr);
124 out_dr = FLD (out_dr);
368fc7db
DE		 125 referenced |= 1 << 0;
126 referenced |= 1 << 2;
eb234697 127 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 128 }
129 return cycles;
130#undef FLD
131}
132
133static int
134model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg)
135{
136#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 137 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
138 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 139 int cycles = 0;
140 {
141 int referenced = 0;
142 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 143 INT in_sr = -1;
144 INT in_dr = -1;
145 INT out_dr = -1;
146 in_sr = FLD (in_sr);
147 in_dr = FLD (in_dr);
148 out_dr = FLD (out_dr);
368fc7db 149 referenced |= 1 << 0;
eb234697 150 referenced |= 1 << 1;
368fc7db 151 referenced |= 1 << 2;
eb234697 152 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 153 }
154 return cycles;
155#undef FLD
156}
157
158static int
159model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg)
160{
161#define FLD(f) abuf->fields.fmt_or3.f
ddfae34d
DE		 162 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
163 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 164 int cycles = 0;
165 {
166 int referenced = 0;
167 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 168 INT in_sr = -1;
169 INT in_dr = -1;
170 INT out_dr = -1;
171 in_sr = FLD (in_sr);
172 out_dr = FLD (out_dr);
368fc7db
DE		 173 referenced |= 1 << 0;
174 referenced |= 1 << 2;
eb234697 175 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 176 }
177 return cycles;
178#undef FLD
179}
180
181static int
182model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg)
183{
184#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 185 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
186 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 187 int cycles = 0;
188 {
189 int referenced = 0;
190 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 191 INT in_sr = -1;
192 INT in_dr = -1;
193 INT out_dr = -1;
194 in_sr = FLD (in_sr);
195 in_dr = FLD (in_dr);
196 out_dr = FLD (out_dr);
368fc7db 197 referenced |= 1 << 0;
eb234697 198 referenced |= 1 << 1;
368fc7db 199 referenced |= 1 << 2;
eb234697 200 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 201 }
202 return cycles;
203#undef FLD
204}
205
206static int
207model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg)
208{
209#define FLD(f) abuf->fields.fmt_and3.f
ddfae34d
DE		 210 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
211 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 212 int cycles = 0;
213 {
214 int referenced = 0;
215 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 216 INT in_sr = -1;
217 INT in_dr = -1;
218 INT out_dr = -1;
219 in_sr = FLD (in_sr);
220 out_dr = FLD (out_dr);
368fc7db
DE		 221 referenced |= 1 << 0;
222 referenced |= 1 << 2;
eb234697 223 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 224 }
225 return cycles;
226#undef FLD
227}
228
229static int
230model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg)
231{
232#define FLD(f) abuf->fields.fmt_addi.f
ddfae34d
DE		 233 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
234 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 235 int cycles = 0;
236 {
237 int referenced = 0;
238 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 239 INT in_sr = -1;
240 INT in_dr = -1;
241 INT out_dr = -1;
242 in_dr = FLD (in_dr);
243 out_dr = FLD (out_dr);
244 referenced |= 1 << 1;
368fc7db 245 referenced |= 1 << 2;
eb234697 246 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 247 }
248 return cycles;
249#undef FLD
250}
251
252static int
253model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg)
254{
255#define FLD(f) abuf->fields.fmt_addv.f
ddfae34d
DE		 256 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
257 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 258 int cycles = 0;
259 {
260 int referenced = 0;
261 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 262 INT in_sr = -1;
263 INT in_dr = -1;
264 INT out_dr = -1;
265 in_sr = FLD (in_sr);
266 in_dr = FLD (in_dr);
267 out_dr = FLD (out_dr);
368fc7db 268 referenced |= 1 << 0;
eb234697 269 referenced |= 1 << 1;
368fc7db 270 referenced |= 1 << 2;
eb234697 271 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 272 }
273 return cycles;
274#undef FLD
275}
276
277static int
278model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg)
279{
280#define FLD(f) abuf->fields.fmt_addv3.f
ddfae34d
DE		 281 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
282 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 283 int cycles = 0;
284 {
285 int referenced = 0;
286 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 287 INT in_sr = -1;
288 INT in_dr = -1;
289 INT out_dr = -1;
290 in_sr = FLD (in_sr);
291 out_dr = FLD (out_dr);
368fc7db
DE		 292 referenced |= 1 << 0;
293 referenced |= 1 << 2;
eb234697 294 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 295 }
296 return cycles;
297#undef FLD
298}
299
300static int
301model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg)
302{
303#define FLD(f) abuf->fields.fmt_addx.f
ddfae34d
DE		 304 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
305 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 306 int cycles = 0;
307 {
308 int referenced = 0;
309 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 310 INT in_sr = -1;
311 INT in_dr = -1;
312 INT out_dr = -1;
313 in_sr = FLD (in_sr);
314 in_dr = FLD (in_dr);
315 out_dr = FLD (out_dr);
368fc7db 316 referenced |= 1 << 0;
eb234697 317 referenced |= 1 << 1;
368fc7db 318 referenced |= 1 << 2;
eb234697 319 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 320 }
321 return cycles;
322#undef FLD
323}
324
325static int
326model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg)
327{
328#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
ddfae34d
DE		 329 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
330 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 331 int cycles = 0;
332 {
333 int referenced = 0;
334 int UNUSED insn_referenced = abuf->written;
eb234697 335 INT in_sr = -1;
368fc7db 336 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 337 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 338 }
339 return cycles;
340#undef FLD
341}
342
343static int
344model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg)
345{
346#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
ddfae34d
DE		 347 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
348 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 349 int cycles = 0;
350 {
351 int referenced = 0;
352 int UNUSED insn_referenced = abuf->written;
eb234697 353 INT in_sr = -1;
368fc7db 354 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 355 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 356 }
357 return cycles;
358#undef FLD
359}
360
361static int
362model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg)
363{
364#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
ddfae34d
DE		 365 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
366 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 367 int cycles = 0;
368 {
369 int referenced = 0;
370 int UNUSED insn_referenced = abuf->written;
eb234697 371 INT in_sr = -1;
368fc7db 372 if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
eb234697 373 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 374 }
375 {
376 int referenced = 0;
377 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 378 INT in_src1 = -1;
379 INT in_src2 = -1;
380 in_src1 = FLD (in_src1);
381 in_src2 = FLD (in_src2);
368fc7db
DE		 382 referenced |= 1 << 0;
383 referenced |= 1 << 1;
eb234697 384 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
368fc7db
DE		 385 }
386 return cycles;
387#undef FLD
388}
389
390static int
391model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg)
392{
393#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 394 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
395 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 396 int cycles = 0;
397 {
398 int referenced = 0;
399 int UNUSED insn_referenced = abuf->written;
eb234697 400 INT in_sr = -1;
368fc7db 401 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 402 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 403 }
404 {
405 int referenced = 0;
406 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 407 INT in_src1 = -1;
408 INT in_src2 = -1;
409 in_src2 = FLD (in_src2);
368fc7db 410 referenced |= 1 << 1;
eb234697 411 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
368fc7db
DE		 412 }
413 return cycles;
414#undef FLD
415}
416
417static int
418model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg)
419{
420#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 421 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
422 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 423 int cycles = 0;
424 {
425 int referenced = 0;
426 int UNUSED insn_referenced = abuf->written;
eb234697 427 INT in_sr = -1;
368fc7db 428 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 429 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 430 }
431 {
432 int referenced = 0;
433 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 434 INT in_src1 = -1;
435 INT in_src2 = -1;
436 in_src2 = FLD (in_src2);
368fc7db 437 referenced |= 1 << 1;
eb234697 438 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
368fc7db
DE		 439 }
440 return cycles;
441#undef FLD
442}
443
444static int
445model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg)
446{
447#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 448 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
449 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 450 int cycles = 0;
451 {
452 int referenced = 0;
453 int UNUSED insn_referenced = abuf->written;
eb234697 454 INT in_sr = -1;
368fc7db 455 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 456 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 457 }
458 {
459 int referenced = 0;
460 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 461 INT in_src1 = -1;
462 INT in_src2 = -1;
463 in_src2 = FLD (in_src2);
368fc7db 464 referenced |= 1 << 1;
eb234697 465 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
368fc7db
DE		 466 }
467 return cycles;
468#undef FLD
469}
470
471static int
472model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg)
473{
474#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 475 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
476 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 477 int cycles = 0;
478 {
479 int referenced = 0;
480 int UNUSED insn_referenced = abuf->written;
eb234697 481 INT in_sr = -1;
368fc7db 482 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 483 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 484 }
485 {
486 int referenced = 0;
487 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 488 INT in_src1 = -1;
489 INT in_src2 = -1;
490 in_src2 = FLD (in_src2);
368fc7db 491 referenced |= 1 << 1;
eb234697 492 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
368fc7db
DE		 493 }
494 return cycles;
495#undef FLD
496}
497
498static int
499model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg)
500{
501#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 502 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
503 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 504 int cycles = 0;
505 {
506 int referenced = 0;
507 int UNUSED insn_referenced = abuf->written;
eb234697 508 INT in_sr = -1;
368fc7db 509 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 510 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 511 }
512 {
513 int referenced = 0;
514 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 515 INT in_src1 = -1;
516 INT in_src2 = -1;
517 in_src2 = FLD (in_src2);
368fc7db 518 referenced |= 1 << 1;
eb234697 519 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
368fc7db
DE		 520 }
521 return cycles;
522#undef FLD
523}
524
525static int
526model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg)
527{
528#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
ddfae34d
DE		 529 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
530 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 531 int cycles = 0;
532 {
533 int referenced = 0;
534 int UNUSED insn_referenced = abuf->written;
eb234697 535 INT in_sr = -1;
368fc7db 536 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 537 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 538 }
539 {
540 int referenced = 0;
541 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 542 INT in_src1 = -1;
543 INT in_src2 = -1;
544 in_src2 = FLD (in_src2);
368fc7db 545 referenced |= 1 << 1;
eb234697 546 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
368fc7db
DE		 547 }
548 return cycles;
549#undef FLD
550}
551
552static int
553model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg)
554{
555#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
ddfae34d
DE		 556 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
557 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 558 int cycles = 0;
559 {
560 int referenced = 0;
561 int UNUSED insn_referenced = abuf->written;
eb234697 562 INT in_sr = -1;
368fc7db 563 referenced |= 1 << 1;
eb234697 564 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 565 }
566 return cycles;
567#undef FLD
568}
569
570static int
571model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg)
572{
573#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
ddfae34d
DE		 574 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
575 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 576 int cycles = 0;
577 {
578 int referenced = 0;
579 int UNUSED insn_referenced = abuf->written;
eb234697 580 INT in_sr = -1;
368fc7db 581 referenced |= 1 << 1;
eb234697 582 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 583 }
584 return cycles;
585#undef FLD
586}
587
588static int
589model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
590{
591#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
ddfae34d
DE		 592 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
593 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 594 int cycles = 0;
595 {
596 int referenced = 0;
597 int UNUSED insn_referenced = abuf->written;
eb234697 598 INT in_sr = -1;
368fc7db 599 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
eb234697 600 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 601 }
602 return cycles;
603#undef FLD
604}
605
606static int
607model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
608{
609#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
ddfae34d
DE		 610 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
611 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 612 int cycles = 0;
613 {
614 int referenced = 0;
615 int UNUSED insn_referenced = abuf->written;
eb234697 616 INT in_sr = -1;
368fc7db 617 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
eb234697 618 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 619 }
620 return cycles;
621#undef FLD
622}
623
624static int
625model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
626{
627#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
ddfae34d
DE		 628 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
629 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 630 int cycles = 0;
631 {
632 int referenced = 0;
633 int UNUSED insn_referenced = abuf->written;
eb234697 634 INT in_sr = -1;
368fc7db 635 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 636 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 637 }
638 return cycles;
639#undef FLD
640}
641
642static int
643model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
644{
645#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
ddfae34d
DE		 646 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
647 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 648 int cycles = 0;
649 {
650 int referenced = 0;
651 int UNUSED insn_referenced = abuf->written;
eb234697 652 INT in_sr = -1;
368fc7db 653 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 654 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 655 }
656 return cycles;
657#undef FLD
658}
659
660static int
661model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg)
662{
663#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
ddfae34d
DE		 664 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
665 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 666 int cycles = 0;
667 {
668 int referenced = 0;
669 int UNUSED insn_referenced = abuf->written;
eb234697 670 INT in_sr = -1;
368fc7db 671 if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
eb234697 672 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 673 }
674 {
675 int referenced = 0;
676 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 677 INT in_src1 = -1;
678 INT in_src2 = -1;
679 in_src1 = FLD (in_src1);
680 in_src2 = FLD (in_src2);
368fc7db
DE		 681 referenced |= 1 << 0;
682 referenced |= 1 << 1;
eb234697 683 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
368fc7db
DE		 684 }
685 return cycles;
686#undef FLD
687}
688
689static int
690model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg)
691{
692#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
ddfae34d
DE		 693 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
694 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 695 int cycles = 0;
696 {
697 int referenced = 0;
698 int UNUSED insn_referenced = abuf->written;
eb234697 699 INT in_sr = -1;
368fc7db 700 referenced |= 1 << 1;
eb234697 701 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 702 }
703 return cycles;
704#undef FLD
705}
706
707static int
708model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg)
709{
710#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
ddfae34d
DE		 711 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
712 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 713 int cycles = 0;
714 {
715 int referenced = 0;
716 int UNUSED insn_referenced = abuf->written;
eb234697 717 INT in_sr = -1;
368fc7db 718 referenced |= 1 << 1;
eb234697 719 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 720 }
721 return cycles;
722#undef FLD
723}
724
725static int
726model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
727{
728#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
ddfae34d
DE		 729 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
730 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 731 int cycles = 0;
732 {
733 int referenced = 0;
734 int UNUSED insn_referenced = abuf->written;
eb234697 735 INT in_sr = -1;
368fc7db 736 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
eb234697 737 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 738 }
739 return cycles;
740#undef FLD
741}
742
743static int
744model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
745{
746#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
ddfae34d
DE		 747 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
748 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 749 int cycles = 0;
750 {
751 int referenced = 0;
752 int UNUSED insn_referenced = abuf->written;
eb234697 753 INT in_sr = -1;
368fc7db 754 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
eb234697 755 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 756 }
757 return cycles;
758#undef FLD
759}
760
761static int
762model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg)
763{
764#define FLD(f) abuf->fields.fmt_cmp.f
ddfae34d
DE		 765 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
766 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 767 int cycles = 0;
768 {
769 int referenced = 0;
770 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 771 INT in_src1 = -1;
772 INT in_src2 = -1;
773 in_src1 = FLD (in_src1);
774 in_src2 = FLD (in_src2);
368fc7db
DE		 775 referenced |= 1 << 0;
776 referenced |= 1 << 1;
eb234697 777 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 778 }
779 return cycles;
780#undef FLD
781}
782
783static int
784model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg)
785{
786#define FLD(f) abuf->fields.fmt_cmpi.f
ddfae34d
DE		 787 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
788 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 789 int cycles = 0;
790 {
791 int referenced = 0;
792 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 793 INT in_src1 = -1;
794 INT in_src2 = -1;
795 in_src2 = FLD (in_src2);
368fc7db 796 referenced |= 1 << 1;
eb234697 797 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 798 }
799 return cycles;
800#undef FLD
801}
802
803static int
804model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg)
805{
806#define FLD(f) abuf->fields.fmt_cmp.f
ddfae34d
DE		 807 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
808 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 809 int cycles = 0;
810 {
811 int referenced = 0;
812 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 813 INT in_src1 = -1;
814 INT in_src2 = -1;
815 in_src1 = FLD (in_src1);
816 in_src2 = FLD (in_src2);
368fc7db
DE		 817 referenced |= 1 << 0;
818 referenced |= 1 << 1;
eb234697 819 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 820 }
821 return cycles;
822#undef FLD
823}
824
825static int
826model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg)
827{
828#define FLD(f) abuf->fields.fmt_cmpi.f
ddfae34d
DE		 829 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
830 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 831 int cycles = 0;
832 {
833 int referenced = 0;
834 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 835 INT in_src1 = -1;
836 INT in_src2 = -1;
837 in_src2 = FLD (in_src2);
368fc7db 838 referenced |= 1 << 1;
eb234697 839 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 840 }
841 return cycles;
842#undef FLD
843}
844
845static int
846model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
847{
848#define FLD(f) abuf->fields.fmt_cmp.f
ddfae34d
DE		 849 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
850 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 851 int cycles = 0;
852 {
853 int referenced = 0;
854 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 855 INT in_src1 = -1;
856 INT in_src2 = -1;
857 in_src1 = FLD (in_src1);
858 in_src2 = FLD (in_src2);
368fc7db
DE		 859 referenced |= 1 << 0;
860 referenced |= 1 << 1;
eb234697 861 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 862 }
863 return cycles;
864#undef FLD
865}
866
867static int
868model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg)
869{
870#define FLD(f) abuf->fields.fmt_cmpz.f
ddfae34d
DE		 871 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
872 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 873 int cycles = 0;
874 {
875 int referenced = 0;
876 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 877 INT in_src1 = -1;
878 INT in_src2 = -1;
879 in_src2 = FLD (in_src2);
368fc7db 880 referenced |= 1 << 1;
eb234697 881 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 882 }
883 return cycles;
884#undef FLD
885}
886
887static int
888model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg)
889{
890#define FLD(f) abuf->fields.fmt_div.f
ddfae34d
DE		 891 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
892 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 893 int cycles = 0;
894 {
895 int referenced = 0;
896 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 897 INT in_sr = -1;
898 INT in_dr = -1;
899 INT out_dr = -1;
900 in_sr = FLD (in_sr);
901 in_dr = FLD (in_dr);
902 out_dr = FLD (out_dr);
368fc7db 903 referenced |= 1 << 0;
eb234697 904 if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
368fc7db 905 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
eb234697 906 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 907 }
908 return cycles;
909#undef FLD
910}
911
912static int
913model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg)
914{
915#define FLD(f) abuf->fields.fmt_div.f
ddfae34d
DE		 916 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
917 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 918 int cycles = 0;
919 {
920 int referenced = 0;
921 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 922 INT in_sr = -1;
923 INT in_dr = -1;
924 INT out_dr = -1;
925 in_sr = FLD (in_sr);
926 in_dr = FLD (in_dr);
927 out_dr = FLD (out_dr);
368fc7db 928 referenced |= 1 << 0;
eb234697 929 if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
368fc7db 930 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
eb234697 931 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 932 }
933 return cycles;
934#undef FLD
935}
936
937static int
938model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg)
939{
940#define FLD(f) abuf->fields.fmt_div.f
ddfae34d
DE		 941 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
942 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 943 int cycles = 0;
944 {
945 int referenced = 0;
946 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 947 INT in_sr = -1;
948 INT in_dr = -1;
949 INT out_dr = -1;
950 in_sr = FLD (in_sr);
951 in_dr = FLD (in_dr);
952 out_dr = FLD (out_dr);
368fc7db 953 referenced |= 1 << 0;
eb234697 954 if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
368fc7db 955 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
eb234697 956 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 957 }
958 return cycles;
959#undef FLD
960}
961
962static int
963model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg)
964{
965#define FLD(f) abuf->fields.fmt_div.f
ddfae34d
DE		 966 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
967 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 968 int cycles = 0;
969 {
970 int referenced = 0;
971 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 972 INT in_sr = -1;
973 INT in_dr = -1;
974 INT out_dr = -1;
975 in_sr = FLD (in_sr);
976 in_dr = FLD (in_dr);
977 out_dr = FLD (out_dr);
368fc7db 978 referenced |= 1 << 0;
eb234697 979 if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
368fc7db 980 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
eb234697 981 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 982 }
983 return cycles;
984#undef FLD
985}
986
987static int
988model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg)
989{
990#define FLD(f) abuf->fields.fmt_div.f
ddfae34d
DE		 991 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
992 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 993 int cycles = 0;
994 {
995 int referenced = 0;
996 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 997 INT in_sr = -1;
998 INT in_dr = -1;
999 INT out_dr = -1;
1000 in_sr = FLD (in_sr);
1001 in_dr = FLD (in_dr);
1002 out_dr = FLD (out_dr);
368fc7db 1003 referenced |= 1 << 0;
eb234697 1004 if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
368fc7db 1005 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
eb234697 1006 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1007 }
1008 return cycles;
1009#undef FLD
1010}
1011
1012static int
1013model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg)
1014{
1015#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
ddfae34d
DE		 1016 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1017 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1018 int cycles = 0;
1019 {
1020 int referenced = 0;
1021 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1022 INT in_sr = -1;
1023 in_sr = FLD (in_sr);
368fc7db
DE		 1024 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1025 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 1026 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 1027 }
1028 return cycles;
1029#undef FLD
1030}
1031
1032static int
1033model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg)
1034{
1035#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
ddfae34d
DE		 1036 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1037 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1038 int cycles = 0;
1039 {
1040 int referenced = 0;
1041 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1042 INT in_sr = -1;
1043 in_sr = FLD (in_sr);
368fc7db
DE		 1044 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1045 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
eb234697 1046 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 1047 }
1048 return cycles;
1049#undef FLD
1050}
1051
1052static int
1053model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg)
1054{
1055#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
ddfae34d
DE		 1056 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1057 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1058 int cycles = 0;
1059 {
1060 int referenced = 0;
1061 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1062 INT in_sr = -1;
1063 in_sr = FLD (in_sr);
368fc7db
DE		 1064 referenced |= 1 << 0;
1065 referenced |= 1 << 1;
eb234697 1066 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 1067 }
1068 return cycles;
1069#undef FLD
1070}
1071
1072static int
1073model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg)
1074{
1075#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
ddfae34d
DE		 1076 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1077 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1078 int cycles = 0;
1079 {
1080 int referenced = 0;
1081 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1082 INT in_sr = -1;
1083 in_sr = FLD (in_sr);
368fc7db
DE		 1084 referenced |= 1 << 0;
1085 referenced |= 1 << 1;
eb234697 1086 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
368fc7db
DE		 1087 }
1088 return cycles;
1089#undef FLD
1090}
1091
1092static int
1093model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg)
1094{
1095#define FLD(f) abuf->fields.fmt_ld.f
ddfae34d
DE		 1096 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1097 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1098 int cycles = 0;
1099 {
1100 int referenced = 0;
1101 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1102 INT in_sr = 0;
1103 INT out_dr = 0;
1104 in_sr = FLD (in_sr);
1105 out_dr = FLD (out_dr);
368fc7db
DE		 1106 referenced |= 1 << 0;
1107 referenced |= 1 << 1;
eb234697 1108 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1109 }
1110 return cycles;
1111#undef FLD
1112}
1113
1114static int
1115model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg)
1116{
1117#define FLD(f) abuf->fields.fmt_ld_d.f
ddfae34d
DE		 1118 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1119 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1120 int cycles = 0;
1121 {
1122 int referenced = 0;
1123 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1124 INT in_sr = 0;
1125 INT out_dr = 0;
1126 in_sr = FLD (in_sr);
1127 out_dr = FLD (out_dr);
368fc7db
DE		 1128 referenced |= 1 << 0;
1129 referenced |= 1 << 1;
eb234697 1130 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1131 }
1132 return cycles;
1133#undef FLD
1134}
1135
1136static int
1137model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg)
1138{
1139#define FLD(f) abuf->fields.fmt_ldb.f
ddfae34d
DE		 1140 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1141 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1142 int cycles = 0;
1143 {
1144 int referenced = 0;
1145 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1146 INT in_sr = 0;
1147 INT out_dr = 0;
1148 in_sr = FLD (in_sr);
1149 out_dr = FLD (out_dr);
368fc7db
DE		 1150 referenced |= 1 << 0;
1151 referenced |= 1 << 1;
eb234697 1152 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1153 }
1154 return cycles;
1155#undef FLD
1156}
1157
1158static int
1159model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
1160{
1161#define FLD(f) abuf->fields.fmt_ldb_d.f
ddfae34d
DE		 1162 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1163 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1164 int cycles = 0;
1165 {
1166 int referenced = 0;
1167 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1168 INT in_sr = 0;
1169 INT out_dr = 0;
1170 in_sr = FLD (in_sr);
1171 out_dr = FLD (out_dr);
368fc7db
DE		 1172 referenced |= 1 << 0;
1173 referenced |= 1 << 1;
eb234697 1174 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1175 }
1176 return cycles;
1177#undef FLD
1178}
1179
1180static int
1181model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg)
1182{
1183#define FLD(f) abuf->fields.fmt_ldh.f
ddfae34d
DE		 1184 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1185 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1186 int cycles = 0;
1187 {
1188 int referenced = 0;
1189 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1190 INT in_sr = 0;
1191 INT out_dr = 0;
1192 in_sr = FLD (in_sr);
1193 out_dr = FLD (out_dr);
368fc7db
DE		 1194 referenced |= 1 << 0;
1195 referenced |= 1 << 1;
eb234697 1196 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1197 }
1198 return cycles;
1199#undef FLD
1200}
1201
1202static int
1203model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
1204{
1205#define FLD(f) abuf->fields.fmt_ldh_d.f
ddfae34d
DE		 1206 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1207 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1208 int cycles = 0;
1209 {
1210 int referenced = 0;
1211 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1212 INT in_sr = 0;
1213 INT out_dr = 0;
1214 in_sr = FLD (in_sr);
1215 out_dr = FLD (out_dr);
368fc7db
DE		 1216 referenced |= 1 << 0;
1217 referenced |= 1 << 1;
eb234697 1218 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1219 }
1220 return cycles;
1221#undef FLD
1222}
1223
1224static int
1225model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg)
1226{
1227#define FLD(f) abuf->fields.fmt_ldb.f
ddfae34d
DE		 1228 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1229 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1230 int cycles = 0;
1231 {
1232 int referenced = 0;
1233 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1234 INT in_sr = 0;
1235 INT out_dr = 0;
1236 in_sr = FLD (in_sr);
1237 out_dr = FLD (out_dr);
368fc7db
DE		 1238 referenced |= 1 << 0;
1239 referenced |= 1 << 1;
eb234697 1240 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1241 }
1242 return cycles;
1243#undef FLD
1244}
1245
1246static int
1247model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
1248{
1249#define FLD(f) abuf->fields.fmt_ldb_d.f
ddfae34d
DE		 1250 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1251 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1252 int cycles = 0;
1253 {
1254 int referenced = 0;
1255 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1256 INT in_sr = 0;
1257 INT out_dr = 0;
1258 in_sr = FLD (in_sr);
1259 out_dr = FLD (out_dr);
368fc7db
DE		 1260 referenced |= 1 << 0;
1261 referenced |= 1 << 1;
eb234697 1262 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1263 }
1264 return cycles;
1265#undef FLD
1266}
1267
1268static int
1269model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg)
1270{
1271#define FLD(f) abuf->fields.fmt_ldh.f
ddfae34d
DE		 1272 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1273 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1274 int cycles = 0;
1275 {
1276 int referenced = 0;
1277 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1278 INT in_sr = 0;
1279 INT out_dr = 0;
1280 in_sr = FLD (in_sr);
1281 out_dr = FLD (out_dr);
368fc7db
DE		 1282 referenced |= 1 << 0;
1283 referenced |= 1 << 1;
eb234697 1284 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1285 }
1286 return cycles;
1287#undef FLD
1288}
1289
1290static int
1291model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
1292{
1293#define FLD(f) abuf->fields.fmt_ldh_d.f
ddfae34d
DE		 1294 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1295 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1296 int cycles = 0;
1297 {
1298 int referenced = 0;
1299 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1300 INT in_sr = 0;
1301 INT out_dr = 0;
1302 in_sr = FLD (in_sr);
1303 out_dr = FLD (out_dr);
368fc7db
DE		 1304 referenced |= 1 << 0;
1305 referenced |= 1 << 1;
eb234697 1306 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1307 }
1308 return cycles;
1309#undef FLD
1310}
1311
1312static int
1313model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
1314{
1315#define FLD(f) abuf->fields.fmt_ld_plus.f
ddfae34d
DE		 1316 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1317 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1318 int cycles = 0;
1319 {
1320 int referenced = 0;
1321 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1322 INT in_sr = 0;
1323 INT out_dr = 0;
1324 in_sr = FLD (in_sr);
1325 out_dr = FLD (out_dr);
368fc7db
DE		 1326 referenced |= 1 << 0;
1327 referenced |= 1 << 1;
eb234697 1328 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1329 }
1330 {
1331 int referenced = 0;
1332 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1333 INT in_sr = -1;
1334 INT in_dr = -1;
1335 INT out_dr = -1;
1336 in_dr = FLD (in_sr);
1337 out_dr = FLD (out_sr);
368fc7db
DE		 1338 referenced |= 1 << 0;
1339 referenced |= 1 << 2;
eb234697 1340 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1341 }
1342 return cycles;
1343#undef FLD
1344}
1345
1346static int
1347model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg)
1348{
1349#define FLD(f) abuf->fields.fmt_ld24.f
ddfae34d
DE		 1350 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1351 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1352 int cycles = 0;
1353 {
1354 int referenced = 0;
1355 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1356 INT in_sr = -1;
1357 INT in_dr = -1;
1358 INT out_dr = -1;
1359 out_dr = FLD (out_dr);
368fc7db 1360 referenced |= 1 << 2;
eb234697 1361 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1362 }
1363 return cycles;
1364#undef FLD
1365}
1366
1367static int
1368model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
1369{
1370#define FLD(f) abuf->fields.fmt_ldi8.f
ddfae34d
DE		 1371 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1372 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1373 int cycles = 0;
1374 {
1375 int referenced = 0;
1376 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1377 INT in_sr = -1;
1378 INT in_dr = -1;
1379 INT out_dr = -1;
1380 out_dr = FLD (out_dr);
368fc7db 1381 referenced |= 1 << 2;
eb234697 1382 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1383 }
1384 return cycles;
1385#undef FLD
1386}
1387
1388static int
1389model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
1390{
1391#define FLD(f) abuf->fields.fmt_ldi16.f
ddfae34d
DE		 1392 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1393 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1394 int cycles = 0;
1395 {
1396 int referenced = 0;
1397 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1398 INT in_sr = -1;
1399 INT in_dr = -1;
1400 INT out_dr = -1;
1401 out_dr = FLD (out_dr);
368fc7db 1402 referenced |= 1 << 2;
eb234697 1403 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1404 }
1405 return cycles;
1406#undef FLD
1407}
1408
1409static int
1410model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg)
1411{
1412#define FLD(f) abuf->fields.fmt_lock.f
ddfae34d
DE		 1413 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1414 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1415 int cycles = 0;
1416 {
1417 int referenced = 0;
1418 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1419 INT in_sr = 0;
1420 INT out_dr = 0;
1421 in_sr = FLD (in_sr);
1422 out_dr = FLD (out_dr);
368fc7db
DE		 1423 referenced |= 1 << 0;
1424 referenced |= 1 << 1;
eb234697 1425 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 1426 }
1427 return cycles;
1428#undef FLD
1429}
1430
1431static int
1432model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg)
1433{
1434#define FLD(f) abuf->fields.fmt_machi_a.f
ddfae34d
DE		 1435 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1436 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1437 int cycles = 0;
1438 {
1439 int referenced = 0;
1440 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1441 INT in_src1 = -1;
1442 INT in_src2 = -1;
1443 in_src1 = FLD (in_src1);
1444 in_src2 = FLD (in_src2);
368fc7db
DE		 1445 referenced |= 1 << 0;
1446 referenced |= 1 << 1;
eb234697 1447 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 1448 }
1449 return cycles;
1450#undef FLD
1451}
1452
1453static int
1454model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
1455{
1456#define FLD(f) abuf->fields.fmt_machi_a.f
ddfae34d
DE		 1457 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1458 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1459 int cycles = 0;
1460 {
1461 int referenced = 0;
1462 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1463 INT in_src1 = -1;
1464 INT in_src2 = -1;
1465 in_src1 = FLD (in_src1);
1466 in_src2 = FLD (in_src2);
368fc7db
DE		 1467 referenced |= 1 << 0;
1468 referenced |= 1 << 1;
eb234697 1469 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 1470 }
1471 return cycles;
1472#undef FLD
1473}
1474
1475static int
1476model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1477{
1478#define FLD(f) abuf->fields.fmt_machi_a.f
ddfae34d
DE		 1479 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1480 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1481 int cycles = 0;
1482 {
1483 int referenced = 0;
1484 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1485 INT in_src1 = -1;
1486 INT in_src2 = -1;
1487 in_src1 = FLD (in_src1);
1488 in_src2 = FLD (in_src2);
368fc7db
DE		 1489 referenced |= 1 << 0;
1490 referenced |= 1 << 1;
eb234697 1491 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 1492 }
1493 return cycles;
1494#undef FLD
1495}
1496
1497static int
1498model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1499{
1500#define FLD(f) abuf->fields.fmt_machi_a.f
ddfae34d
DE		 1501 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1502 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1503 int cycles = 0;
1504 {
1505 int referenced = 0;
1506 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1507 INT in_src1 = -1;
1508 INT in_src2 = -1;
1509 in_src1 = FLD (in_src1);
1510 in_src2 = FLD (in_src2);
368fc7db
DE		 1511 referenced |= 1 << 0;
1512 referenced |= 1 << 1;
eb234697 1513 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 1514 }
1515 return cycles;
1516#undef FLD
1517}
1518
1519static int
1520model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg)
1521{
1522#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 1523 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1524 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1525 int cycles = 0;
1526 {
1527 int referenced = 0;
1528 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1529 INT in_sr = -1;
1530 INT in_dr = -1;
1531 INT out_dr = -1;
1532 in_sr = FLD (in_sr);
1533 in_dr = FLD (in_dr);
1534 out_dr = FLD (out_dr);
368fc7db 1535 referenced |= 1 << 0;
eb234697 1536 referenced |= 1 << 1;
368fc7db 1537 referenced |= 1 << 2;
eb234697 1538 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1539 }
1540 return cycles;
1541#undef FLD
1542}
1543
1544static int
1545model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
1546{
1547#define FLD(f) abuf->fields.fmt_mulhi_a.f
ddfae34d
DE		 1548 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1549 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1550 int cycles = 0;
1551 {
1552 int referenced = 0;
1553 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1554 INT in_src1 = -1;
1555 INT in_src2 = -1;
1556 in_src1 = FLD (in_src1);
1557 in_src2 = FLD (in_src2);
368fc7db
DE		 1558 referenced |= 1 << 0;
1559 referenced |= 1 << 1;
eb234697 1560 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 1561 }
1562 return cycles;
1563#undef FLD
1564}
1565
1566static int
1567model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
1568{
1569#define FLD(f) abuf->fields.fmt_mulhi_a.f
ddfae34d
DE		 1570 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1571 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1572 int cycles = 0;
1573 {
1574 int referenced = 0;
1575 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1576 INT in_src1 = -1;
1577 INT in_src2 = -1;
1578 in_src1 = FLD (in_src1);
1579 in_src2 = FLD (in_src2);
368fc7db
DE		 1580 referenced |= 1 << 0;
1581 referenced |= 1 << 1;
eb234697 1582 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 1583 }
1584 return cycles;
1585#undef FLD
1586}
1587
1588static int
1589model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1590{
1591#define FLD(f) abuf->fields.fmt_mulhi_a.f
ddfae34d
DE		 1592 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1593 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1594 int cycles = 0;
1595 {
1596 int referenced = 0;
1597 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1598 INT in_src1 = -1;
1599 INT in_src2 = -1;
1600 in_src1 = FLD (in_src1);
1601 in_src2 = FLD (in_src2);
368fc7db
DE		 1602 referenced |= 1 << 0;
1603 referenced |= 1 << 1;
eb234697 1604 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 1605 }
1606 return cycles;
1607#undef FLD
1608}
1609
1610static int
1611model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1612{
1613#define FLD(f) abuf->fields.fmt_mulhi_a.f
ddfae34d
DE		 1614 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1615 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1616 int cycles = 0;
1617 {
1618 int referenced = 0;
1619 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1620 INT in_src1 = -1;
1621 INT in_src2 = -1;
1622 in_src1 = FLD (in_src1);
1623 in_src2 = FLD (in_src2);
368fc7db
DE		 1624 referenced |= 1 << 0;
1625 referenced |= 1 << 1;
eb234697 1626 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 1627 }
1628 return cycles;
1629#undef FLD
1630}
1631
1632static int
1633model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg)
1634{
1635#define FLD(f) abuf->fields.fmt_mv.f
ddfae34d
DE		 1636 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1637 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1638 int cycles = 0;
1639 {
1640 int referenced = 0;
1641 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1642 INT in_sr = -1;
1643 INT in_dr = -1;
1644 INT out_dr = -1;
1645 in_sr = FLD (in_sr);
1646 out_dr = FLD (out_dr);
368fc7db
DE		 1647 referenced |= 1 << 0;
1648 referenced |= 1 << 2;
eb234697 1649 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1650 }
1651 return cycles;
1652#undef FLD
1653}
1654
1655static int
1656model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
1657{
1658#define FLD(f) abuf->fields.fmt_mvfachi_a.f
ddfae34d
DE		 1659 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1660 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1661 int cycles = 0;
1662 {
1663 int referenced = 0;
1664 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1665 INT in_sr = -1;
1666 INT in_dr = -1;
1667 INT out_dr = -1;
1668 out_dr = FLD (out_dr);
368fc7db 1669 referenced |= 1 << 2;
eb234697 1670 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1671 }
1672 return cycles;
1673#undef FLD
1674}
1675
1676static int
1677model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1678{
1679#define FLD(f) abuf->fields.fmt_mvfachi_a.f
ddfae34d
DE		 1680 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1681 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1682 int cycles = 0;
1683 {
1684 int referenced = 0;
1685 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1686 INT in_sr = -1;
1687 INT in_dr = -1;
1688 INT out_dr = -1;
1689 out_dr = FLD (out_dr);
368fc7db 1690 referenced |= 1 << 2;
eb234697 1691 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1692 }
1693 return cycles;
1694#undef FLD
1695}
1696
1697static int
1698model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
1699{
1700#define FLD(f) abuf->fields.fmt_mvfachi_a.f
ddfae34d
DE		 1701 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1702 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1703 int cycles = 0;
1704 {
1705 int referenced = 0;
1706 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1707 INT in_sr = -1;
1708 INT in_dr = -1;
1709 INT out_dr = -1;
1710 out_dr = FLD (out_dr);
368fc7db 1711 referenced |= 1 << 2;
eb234697 1712 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1713 }
1714 return cycles;
1715#undef FLD
1716}
1717
1718static int
1719model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg)
1720{
1721#define FLD(f) abuf->fields.fmt_mvfc.f
ddfae34d
DE		 1722 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1723 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1724 int cycles = 0;
1725 {
1726 int referenced = 0;
1727 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1728 INT in_sr = -1;
1729 INT in_dr = -1;
1730 INT out_dr = -1;
1731 out_dr = FLD (out_dr);
368fc7db 1732 referenced |= 1 << 2;
eb234697 1733 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1734 }
1735 return cycles;
1736#undef FLD
1737}
1738
1739static int
1740model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
1741{
1742#define FLD(f) abuf->fields.fmt_mvtachi_a.f
ddfae34d
DE		 1743 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1744 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1745 int cycles = 0;
1746 {
1747 int referenced = 0;
1748 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1749 INT in_sr = -1;
1750 INT in_dr = -1;
1751 INT out_dr = -1;
1752 in_sr = FLD (in_src1);
1753 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1754 }
1755 return cycles;
1756#undef FLD
1757}
1758
1759static int
1760model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1761{
1762#define FLD(f) abuf->fields.fmt_mvtachi_a.f
ddfae34d
DE		 1763 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1764 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1765 int cycles = 0;
1766 {
1767 int referenced = 0;
1768 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1769 INT in_sr = -1;
1770 INT in_dr = -1;
1771 INT out_dr = -1;
1772 in_sr = FLD (in_src1);
1773 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1774 }
1775 return cycles;
1776#undef FLD
1777}
1778
1779static int
1780model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg)
1781{
1782#define FLD(f) abuf->fields.fmt_mvtc.f
ddfae34d
DE		 1783 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1784 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1785 int cycles = 0;
1786 {
1787 int referenced = 0;
1788 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1789 INT in_sr = -1;
1790 INT in_dr = -1;
1791 INT out_dr = -1;
1792 in_sr = FLD (in_sr);
368fc7db 1793 referenced |= 1 << 0;
eb234697 1794 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1795 }
1796 return cycles;
1797#undef FLD
1798}
1799
1800static int
1801model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
1802{
1803#define FLD(f) abuf->fields.fmt_mv.f
ddfae34d
DE		 1804 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1805 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1806 int cycles = 0;
1807 {
1808 int referenced = 0;
1809 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1810 INT in_sr = -1;
1811 INT in_dr = -1;
1812 INT out_dr = -1;
1813 in_sr = FLD (in_sr);
1814 out_dr = FLD (out_dr);
368fc7db
DE		 1815 referenced |= 1 << 0;
1816 referenced |= 1 << 2;
eb234697 1817 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1818 }
1819 return cycles;
1820#undef FLD
1821}
1822
1823static int
1824model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
1825{
1826#define FLD(f) abuf->fields.fmt_nop.f
ddfae34d
DE		 1827 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1828 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1829 int cycles = 0;
1830 {
1831 int referenced = 0;
1832 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1833 INT in_sr = -1;
1834 INT in_dr = -1;
1835 INT out_dr = -1;
1836 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1837 }
1838 return cycles;
1839#undef FLD
1840}
1841
1842static int
1843model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg)
1844{
1845#define FLD(f) abuf->fields.fmt_mv.f
ddfae34d
DE		 1846 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1847 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1848 int cycles = 0;
1849 {
1850 int referenced = 0;
1851 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1852 INT in_sr = -1;
1853 INT in_dr = -1;
1854 INT out_dr = -1;
1855 in_sr = FLD (in_sr);
1856 out_dr = FLD (out_dr);
368fc7db
DE		 1857 referenced |= 1 << 0;
1858 referenced |= 1 << 2;
eb234697 1859 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1860 }
1861 return cycles;
1862#undef FLD
1863}
1864
1865static int
1866model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
1867{
1868#define FLD(f) abuf->fields.fmt_rac_dsi.f
ddfae34d
DE		 1869 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1870 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1871 int cycles = 0;
1872 {
1873 int referenced = 0;
1874 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1875 INT in_src1 = -1;
1876 INT in_src2 = -1;
1877 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 1878 }
1879 return cycles;
1880#undef FLD
1881}
1882
1883static int
1884model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
1885{
1886#define FLD(f) abuf->fields.fmt_rac_dsi.f
ddfae34d
DE		 1887 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1888 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1889 int cycles = 0;
1890 {
1891 int referenced = 0;
1892 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1893 INT in_src1 = -1;
1894 INT in_src2 = -1;
1895 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 1896 }
1897 return cycles;
1898#undef FLD
1899}
1900
1901static int
1902model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
1903{
1904#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
ddfae34d
DE		 1905 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1906 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1907 int cycles = 0;
1908 {
1909 int referenced = 0;
1910 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1911 INT in_sr = -1;
1912 INT in_dr = -1;
1913 INT out_dr = -1;
1914 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1915 }
1916 return cycles;
1917#undef FLD
1918}
1919
1920static int
1921model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg)
1922{
1923#define FLD(f) abuf->fields.fmt_seth.f
ddfae34d
DE		 1924 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1925 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1926 int cycles = 0;
1927 {
1928 int referenced = 0;
1929 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1930 INT in_sr = -1;
1931 INT in_dr = -1;
1932 INT out_dr = -1;
1933 out_dr = FLD (out_dr);
368fc7db 1934 referenced |= 1 << 2;
eb234697 1935 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1936 }
1937 return cycles;
1938#undef FLD
1939}
1940
1941static int
1942model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg)
1943{
1944#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 1945 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1946 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1947 int cycles = 0;
1948 {
1949 int referenced = 0;
1950 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1951 INT in_sr = -1;
1952 INT in_dr = -1;
1953 INT out_dr = -1;
1954 in_sr = FLD (in_sr);
1955 in_dr = FLD (in_dr);
1956 out_dr = FLD (out_dr);
368fc7db 1957 referenced |= 1 << 0;
eb234697 1958 referenced |= 1 << 1;
368fc7db 1959 referenced |= 1 << 2;
eb234697 1960 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1961 }
1962 return cycles;
1963#undef FLD
1964}
1965
1966static int
1967model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg)
1968{
1969#define FLD(f) abuf->fields.fmt_sll3.f
ddfae34d
DE		 1970 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1971 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1972 int cycles = 0;
1973 {
1974 int referenced = 0;
1975 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1976 INT in_sr = -1;
1977 INT in_dr = -1;
1978 INT out_dr = -1;
1979 in_sr = FLD (in_sr);
1980 out_dr = FLD (out_dr);
368fc7db
DE		 1981 referenced |= 1 << 0;
1982 referenced |= 1 << 2;
eb234697 1983 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 1984 }
1985 return cycles;
1986#undef FLD
1987}
1988
1989static int
1990model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg)
1991{
1992#define FLD(f) abuf->fields.fmt_slli.f
ddfae34d
DE		 1993 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1994 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 1995 int cycles = 0;
1996 {
1997 int referenced = 0;
1998 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 1999 INT in_sr = -1;
2000 INT in_dr = -1;
2001 INT out_dr = -1;
2002 in_dr = FLD (in_dr);
2003 out_dr = FLD (out_dr);
2004 referenced |= 1 << 1;
368fc7db 2005 referenced |= 1 << 2;
eb234697 2006 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2007 }
2008 return cycles;
2009#undef FLD
2010}
2011
2012static int
2013model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg)
2014{
2015#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 2016 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2017 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2018 int cycles = 0;
2019 {
2020 int referenced = 0;
2021 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2022 INT in_sr = -1;
2023 INT in_dr = -1;
2024 INT out_dr = -1;
2025 in_sr = FLD (in_sr);
2026 in_dr = FLD (in_dr);
2027 out_dr = FLD (out_dr);
368fc7db 2028 referenced |= 1 << 0;
eb234697 2029 referenced |= 1 << 1;
368fc7db 2030 referenced |= 1 << 2;
eb234697 2031 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2032 }
2033 return cycles;
2034#undef FLD
2035}
2036
2037static int
2038model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg)
2039{
2040#define FLD(f) abuf->fields.fmt_sll3.f
ddfae34d
DE		 2041 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2042 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2043 int cycles = 0;
2044 {
2045 int referenced = 0;
2046 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2047 INT in_sr = -1;
2048 INT in_dr = -1;
2049 INT out_dr = -1;
2050 in_sr = FLD (in_sr);
2051 out_dr = FLD (out_dr);
368fc7db
DE		 2052 referenced |= 1 << 0;
2053 referenced |= 1 << 2;
eb234697 2054 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2055 }
2056 return cycles;
2057#undef FLD
2058}
2059
2060static int
2061model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg)
2062{
2063#define FLD(f) abuf->fields.fmt_slli.f
ddfae34d
DE		 2064 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2065 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2066 int cycles = 0;
2067 {
2068 int referenced = 0;
2069 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2070 INT in_sr = -1;
2071 INT in_dr = -1;
2072 INT out_dr = -1;
2073 in_dr = FLD (in_dr);
2074 out_dr = FLD (out_dr);
2075 referenced |= 1 << 1;
368fc7db 2076 referenced |= 1 << 2;
eb234697 2077 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2078 }
2079 return cycles;
2080#undef FLD
2081}
2082
2083static int
2084model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg)
2085{
2086#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 2087 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2088 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2089 int cycles = 0;
2090 {
2091 int referenced = 0;
2092 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2093 INT in_sr = -1;
2094 INT in_dr = -1;
2095 INT out_dr = -1;
2096 in_sr = FLD (in_sr);
2097 in_dr = FLD (in_dr);
2098 out_dr = FLD (out_dr);
368fc7db 2099 referenced |= 1 << 0;
eb234697 2100 referenced |= 1 << 1;
368fc7db 2101 referenced |= 1 << 2;
eb234697 2102 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2103 }
2104 return cycles;
2105#undef FLD
2106}
2107
2108static int
2109model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg)
2110{
2111#define FLD(f) abuf->fields.fmt_sll3.f
ddfae34d
DE		 2112 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2113 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2114 int cycles = 0;
2115 {
2116 int referenced = 0;
2117 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2118 INT in_sr = -1;
2119 INT in_dr = -1;
2120 INT out_dr = -1;
2121 in_sr = FLD (in_sr);
2122 out_dr = FLD (out_dr);
368fc7db
DE		 2123 referenced |= 1 << 0;
2124 referenced |= 1 << 2;
eb234697 2125 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2126 }
2127 return cycles;
2128#undef FLD
2129}
2130
2131static int
2132model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg)
2133{
2134#define FLD(f) abuf->fields.fmt_slli.f
ddfae34d
DE		 2135 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2136 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2137 int cycles = 0;
2138 {
2139 int referenced = 0;
2140 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2141 INT in_sr = -1;
2142 INT in_dr = -1;
2143 INT out_dr = -1;
2144 in_dr = FLD (in_dr);
2145 out_dr = FLD (out_dr);
2146 referenced |= 1 << 1;
368fc7db 2147 referenced |= 1 << 2;
eb234697 2148 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2149 }
2150 return cycles;
2151#undef FLD
2152}
2153
2154static int
2155model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg)
2156{
2157#define FLD(f) abuf->fields.fmt_st.f
ddfae34d
DE		 2158 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2159 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2160 int cycles = 0;
2161 {
2162 int referenced = 0;
2163 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2164 INT in_src1 = 0;
2165 INT in_src2 = 0;
2166 in_src1 = FLD (in_src1);
2167 in_src2 = FLD (in_src2);
368fc7db
DE		 2168 referenced |= 1 << 0;
2169 referenced |= 1 << 1;
eb234697 2170 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2171 }
2172 return cycles;
2173#undef FLD
2174}
2175
2176static int
2177model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg)
2178{
2179#define FLD(f) abuf->fields.fmt_st_d.f
ddfae34d
DE		 2180 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2181 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2182 int cycles = 0;
2183 {
2184 int referenced = 0;
2185 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2186 INT in_src1 = 0;
2187 INT in_src2 = 0;
2188 in_src1 = FLD (in_src1);
2189 in_src2 = FLD (in_src2);
368fc7db
DE		 2190 referenced |= 1 << 0;
2191 referenced |= 1 << 1;
eb234697 2192 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2193 }
2194 return cycles;
2195#undef FLD
2196}
2197
2198static int
2199model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg)
2200{
2201#define FLD(f) abuf->fields.fmt_stb.f
ddfae34d
DE		 2202 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2203 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2204 int cycles = 0;
2205 {
2206 int referenced = 0;
2207 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2208 INT in_src1 = 0;
2209 INT in_src2 = 0;
2210 in_src1 = FLD (in_src1);
2211 in_src2 = FLD (in_src2);
368fc7db
DE		 2212 referenced |= 1 << 0;
2213 referenced |= 1 << 1;
eb234697 2214 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2215 }
2216 return cycles;
2217#undef FLD
2218}
2219
2220static int
2221model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg)
2222{
2223#define FLD(f) abuf->fields.fmt_stb_d.f
ddfae34d
DE		 2224 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2225 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2226 int cycles = 0;
2227 {
2228 int referenced = 0;
2229 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2230 INT in_src1 = 0;
2231 INT in_src2 = 0;
2232 in_src1 = FLD (in_src1);
2233 in_src2 = FLD (in_src2);
368fc7db
DE		 2234 referenced |= 1 << 0;
2235 referenced |= 1 << 1;
eb234697 2236 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2237 }
2238 return cycles;
2239#undef FLD
2240}
2241
2242static int
2243model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg)
2244{
2245#define FLD(f) abuf->fields.fmt_sth.f
ddfae34d
DE		 2246 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2247 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2248 int cycles = 0;
2249 {
2250 int referenced = 0;
2251 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2252 INT in_src1 = 0;
2253 INT in_src2 = 0;
2254 in_src1 = FLD (in_src1);
2255 in_src2 = FLD (in_src2);
368fc7db
DE		 2256 referenced |= 1 << 0;
2257 referenced |= 1 << 1;
eb234697 2258 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2259 }
2260 return cycles;
2261#undef FLD
2262}
2263
2264static int
2265model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg)
2266{
2267#define FLD(f) abuf->fields.fmt_sth_d.f
ddfae34d
DE		 2268 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2269 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2270 int cycles = 0;
2271 {
2272 int referenced = 0;
2273 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2274 INT in_src1 = 0;
2275 INT in_src2 = 0;
2276 in_src1 = FLD (in_src1);
2277 in_src2 = FLD (in_src2);
368fc7db
DE		 2278 referenced |= 1 << 0;
2279 referenced |= 1 << 1;
eb234697 2280 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2281 }
2282 return cycles;
2283#undef FLD
2284}
2285
2286static int
2287model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg)
2288{
2289#define FLD(f) abuf->fields.fmt_st_plus.f
ddfae34d
DE		 2290 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2291 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2292 int cycles = 0;
2293 {
2294 int referenced = 0;
2295 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2296 INT in_src1 = 0;
2297 INT in_src2 = 0;
2298 in_src1 = FLD (in_src1);
2299 in_src2 = FLD (in_src2);
368fc7db
DE		 2300 referenced |= 1 << 0;
2301 referenced |= 1 << 1;
eb234697 2302 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2303 }
2304 {
2305 int referenced = 0;
2306 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2307 INT in_sr = -1;
2308 INT in_dr = -1;
2309 INT out_dr = -1;
2310 in_dr = FLD (in_src2);
2311 out_dr = FLD (out_src2);
2312 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2313 }
2314 return cycles;
2315#undef FLD
2316}
2317
2318static int
2319model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg)
2320{
2321#define FLD(f) abuf->fields.fmt_st_plus.f
ddfae34d
DE		 2322 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2323 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2324 int cycles = 0;
2325 {
2326 int referenced = 0;
2327 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2328 INT in_src1 = 0;
2329 INT in_src2 = 0;
2330 in_src1 = FLD (in_src1);
2331 in_src2 = FLD (in_src2);
368fc7db
DE		 2332 referenced |= 1 << 0;
2333 referenced |= 1 << 1;
eb234697 2334 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2335 }
2336 {
2337 int referenced = 0;
2338 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2339 INT in_sr = -1;
2340 INT in_dr = -1;
2341 INT out_dr = -1;
2342 in_dr = FLD (in_src2);
2343 out_dr = FLD (out_src2);
2344 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2345 }
2346 return cycles;
2347#undef FLD
2348}
2349
2350static int
2351model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg)
2352{
2353#define FLD(f) abuf->fields.fmt_add.f
ddfae34d
DE		 2354 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2355 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2356 int cycles = 0;
2357 {
2358 int referenced = 0;
2359 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2360 INT in_sr = -1;
2361 INT in_dr = -1;
2362 INT out_dr = -1;
2363 in_sr = FLD (in_sr);
2364 in_dr = FLD (in_dr);
2365 out_dr = FLD (out_dr);
368fc7db 2366 referenced |= 1 << 0;
eb234697 2367 referenced |= 1 << 1;
368fc7db 2368 referenced |= 1 << 2;
eb234697 2369 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2370 }
2371 return cycles;
2372#undef FLD
2373}
2374
2375static int
2376model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg)
2377{
2378#define FLD(f) abuf->fields.fmt_addv.f
ddfae34d
DE		 2379 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2380 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2381 int cycles = 0;
2382 {
2383 int referenced = 0;
2384 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2385 INT in_sr = -1;
2386 INT in_dr = -1;
2387 INT out_dr = -1;
2388 in_sr = FLD (in_sr);
2389 in_dr = FLD (in_dr);
2390 out_dr = FLD (out_dr);
368fc7db 2391 referenced |= 1 << 0;
eb234697 2392 referenced |= 1 << 1;
368fc7db 2393 referenced |= 1 << 2;
eb234697 2394 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2395 }
2396 return cycles;
2397#undef FLD
2398}
2399
2400static int
2401model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg)
2402{
2403#define FLD(f) abuf->fields.fmt_addx.f
ddfae34d
DE		 2404 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2405 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2406 int cycles = 0;
2407 {
2408 int referenced = 0;
2409 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2410 INT in_sr = -1;
2411 INT in_dr = -1;
2412 INT out_dr = -1;
2413 in_sr = FLD (in_sr);
2414 in_dr = FLD (in_dr);
2415 out_dr = FLD (out_dr);
368fc7db 2416 referenced |= 1 << 0;
eb234697 2417 referenced |= 1 << 1;
368fc7db 2418 referenced |= 1 << 2;
eb234697 2419 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2420 }
2421 return cycles;
2422#undef FLD
2423}
2424
2425static int
2426model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg)
2427{
2428#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
ddfae34d
DE		 2429 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2430 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2431 int cycles = 0;
2432 {
2433 int referenced = 0;
2434 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2435 INT in_sr = -1;
2436 INT in_dr = -1;
2437 INT out_dr = -1;
2438 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2439 }
2440 return cycles;
2441#undef FLD
2442}
2443
2444static int
2445model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg)
2446{
2447#define FLD(f) abuf->fields.fmt_unlock.f
ddfae34d
DE		 2448 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2449 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2450 int cycles = 0;
2451 {
2452 int referenced = 0;
2453 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2454 INT in_sr = 0;
2455 INT out_dr = 0;
2456 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
368fc7db
DE		 2457 }
2458 return cycles;
2459#undef FLD
2460}
2461
2462static int
2463model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg)
2464{
2465#define FLD(f) abuf->fields.fmt_satb.f
ddfae34d
DE		 2466 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2467 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2468 int cycles = 0;
2469 {
2470 int referenced = 0;
2471 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2472 INT in_sr = -1;
2473 INT in_dr = -1;
2474 INT out_dr = -1;
2475 in_sr = FLD (in_sr);
2476 out_dr = FLD (out_dr);
368fc7db
DE		 2477 referenced |= 1 << 0;
2478 referenced |= 1 << 2;
eb234697 2479 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2480 }
2481 return cycles;
2482#undef FLD
2483}
2484
2485static int
2486model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg)
2487{
2488#define FLD(f) abuf->fields.fmt_satb.f
ddfae34d
DE		 2489 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2490 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2491 int cycles = 0;
2492 {
2493 int referenced = 0;
2494 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2495 INT in_sr = -1;
2496 INT in_dr = -1;
2497 INT out_dr = -1;
2498 in_sr = FLD (in_sr);
2499 out_dr = FLD (out_dr);
368fc7db
DE		 2500 referenced |= 1 << 0;
2501 referenced |= 1 << 2;
eb234697 2502 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2503 }
2504 return cycles;
2505#undef FLD
2506}
2507
2508static int
2509model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg)
2510{
2511#define FLD(f) abuf->fields.fmt_sat.f
ddfae34d
DE		 2512 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2513 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2514 int cycles = 0;
2515 {
2516 int referenced = 0;
2517 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2518 INT in_sr = -1;
2519 INT in_dr = -1;
2520 INT out_dr = -1;
2521 in_sr = FLD (in_sr);
2522 out_dr = FLD (out_dr);
368fc7db
DE		 2523 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
2524 referenced |= 1 << 2;
eb234697 2525 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2526 }
2527 return cycles;
2528#undef FLD
2529}
2530
2531static int
2532model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
2533{
2534#define FLD(f) abuf->fields.fmt_cmpz.f
ddfae34d
DE		 2535 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2536 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2537 int cycles = 0;
2538 {
2539 int referenced = 0;
2540 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2541 INT in_src1 = -1;
2542 INT in_src2 = -1;
2543 in_src2 = FLD (in_src2);
368fc7db 2544 referenced |= 1 << 1;
eb234697 2545 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2546 }
2547 return cycles;
2548#undef FLD
2549}
2550
2551static int
2552model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
2553{
2554#define FLD(f) abuf->fields.fmt_sadd.f
ddfae34d
DE		 2555 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2556 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2557 int cycles = 0;
2558 {
2559 int referenced = 0;
2560 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2561 INT in_src1 = -1;
2562 INT in_src2 = -1;
2563 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2564 }
2565 return cycles;
2566#undef FLD
2567}
2568
2569static int
2570model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
2571{
2572#define FLD(f) abuf->fields.fmt_macwu1.f
ddfae34d
DE		 2573 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2574 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2575 int cycles = 0;
2576 {
2577 int referenced = 0;
2578 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2579 INT in_src1 = -1;
2580 INT in_src2 = -1;
2581 in_src1 = FLD (in_src1);
2582 in_src2 = FLD (in_src2);
368fc7db
DE		 2583 referenced |= 1 << 0;
2584 referenced |= 1 << 1;
eb234697 2585 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2586 }
2587 return cycles;
2588#undef FLD
2589}
2590
2591static int
2592model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg)
2593{
2594#define FLD(f) abuf->fields.fmt_msblo.f
ddfae34d
DE		 2595 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2596 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2597 int cycles = 0;
2598 {
2599 int referenced = 0;
2600 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2601 INT in_src1 = -1;
2602 INT in_src2 = -1;
2603 in_src1 = FLD (in_src1);
2604 in_src2 = FLD (in_src2);
368fc7db
DE		 2605 referenced |= 1 << 0;
2606 referenced |= 1 << 1;
eb234697 2607 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2608 }
2609 return cycles;
2610#undef FLD
2611}
2612
2613static int
2614model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
2615{
2616#define FLD(f) abuf->fields.fmt_mulwu1.f
ddfae34d
DE		 2617 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2618 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2619 int cycles = 0;
2620 {
2621 int referenced = 0;
2622 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2623 INT in_src1 = -1;
2624 INT in_src2 = -1;
2625 in_src1 = FLD (in_src1);
2626 in_src2 = FLD (in_src2);
368fc7db
DE		 2627 referenced |= 1 << 0;
2628 referenced |= 1 << 1;
eb234697 2629 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2630 }
2631 return cycles;
2632#undef FLD
2633}
2634
2635static int
2636model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
2637{
2638#define FLD(f) abuf->fields.fmt_macwu1.f
ddfae34d
DE		 2639 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2640 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2641 int cycles = 0;
2642 {
2643 int referenced = 0;
2644 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2645 INT in_src1 = -1;
2646 INT in_src2 = -1;
2647 in_src1 = FLD (in_src1);
2648 in_src2 = FLD (in_src2);
368fc7db
DE		 2649 referenced |= 1 << 0;
2650 referenced |= 1 << 1;
eb234697 2651 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
368fc7db
DE		 2652 }
2653 return cycles;
2654#undef FLD
2655}
2656
2657static int
2658model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
2659{
2660#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
ddfae34d
DE		 2661 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2662 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2663 int cycles = 0;
2664 {
2665 int referenced = 0;
2666 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2667 INT in_sr = -1;
2668 INT in_dr = -1;
2669 INT out_dr = -1;
2670 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2671 }
2672 return cycles;
2673#undef FLD
2674}
2675
2676static int
2677model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
2678{
2679#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
ddfae34d
DE		 2680 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2681 const IDESC * UNUSED idesc = abuf->idesc;
368fc7db
DE		 2682 int cycles = 0;
2683 {
2684 int referenced = 0;
2685 int UNUSED insn_referenced = abuf->written;
eb234697
DE		 2686 INT in_sr = -1;
2687 INT in_dr = -1;
2688 INT out_dr = -1;
2689 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
368fc7db
DE		 2690 }
2691 return cycles;
2692#undef FLD
e0bd6e18
DE		 2693}
2694
2695/* We assume UNIT_NONE == 0 because the tables don't always terminate
2696 entries with it. */
2697
2698/* Model timing data for `m32rx'. */
2699
2700static const INSN_TIMING m32rx_timing[] = {
ddfae34d
DE		 2701 { M32RXF_INSN_X_INVALID, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2702 { M32RXF_INSN_X_AFTER, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2703 { M32RXF_INSN_X_BEFORE, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2704 { M32RXF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2705 { M32RXF_INSN_X_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2706 { M32RXF_INSN_X_BEGIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
368fc7db
DE		 2707 { M32RXF_INSN_ADD, model_m32rx_add, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2708 { M32RXF_INSN_ADD3, model_m32rx_add3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2709 { M32RXF_INSN_AND, model_m32rx_and, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2710 { M32RXF_INSN_AND3, model_m32rx_and3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2711 { M32RXF_INSN_OR, model_m32rx_or, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2712 { M32RXF_INSN_OR3, model_m32rx_or3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2713 { M32RXF_INSN_XOR, model_m32rx_xor, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2714 { M32RXF_INSN_XOR3, model_m32rx_xor3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2715 { M32RXF_INSN_ADDI, model_m32rx_addi, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2716 { M32RXF_INSN_ADDV, model_m32rx_addv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2717 { M32RXF_INSN_ADDV3, model_m32rx_addv3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2718 { M32RXF_INSN_ADDX, model_m32rx_addx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2719 { M32RXF_INSN_BC8, model_m32rx_bc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2720 { M32RXF_INSN_BC24, model_m32rx_bc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2721 { M32RXF_INSN_BEQ, model_m32rx_beq, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2722 { M32RXF_INSN_BEQZ, model_m32rx_beqz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2723 { M32RXF_INSN_BGEZ, model_m32rx_bgez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2724 { M32RXF_INSN_BGTZ, model_m32rx_bgtz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2725 { M32RXF_INSN_BLEZ, model_m32rx_blez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2726 { M32RXF_INSN_BLTZ, model_m32rx_bltz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2727 { M32RXF_INSN_BNEZ, model_m32rx_bnez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2728 { M32RXF_INSN_BL8, model_m32rx_bl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2729 { M32RXF_INSN_BL24, model_m32rx_bl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2730 { M32RXF_INSN_BCL8, model_m32rx_bcl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2731 { M32RXF_INSN_BCL24, model_m32rx_bcl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2732 { M32RXF_INSN_BNC8, model_m32rx_bnc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2733 { M32RXF_INSN_BNC24, model_m32rx_bnc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2734 { M32RXF_INSN_BNE, model_m32rx_bne, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2735 { M32RXF_INSN_BRA8, model_m32rx_bra8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2736 { M32RXF_INSN_BRA24, model_m32rx_bra24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2737 { M32RXF_INSN_BNCL8, model_m32rx_bncl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2738 { M32RXF_INSN_BNCL24, model_m32rx_bncl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2739 { M32RXF_INSN_CMP, model_m32rx_cmp, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2740 { M32RXF_INSN_CMPI, model_m32rx_cmpi, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2741 { M32RXF_INSN_CMPU, model_m32rx_cmpu, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2742 { M32RXF_INSN_CMPUI, model_m32rx_cmpui, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2743 { M32RXF_INSN_CMPEQ, model_m32rx_cmpeq, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2744 { M32RXF_INSN_CMPZ, model_m32rx_cmpz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2745 { M32RXF_INSN_DIV, model_m32rx_div, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2746 { M32RXF_INSN_DIVU, model_m32rx_divu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2747 { M32RXF_INSN_REM, model_m32rx_rem, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2748 { M32RXF_INSN_REMU, model_m32rx_remu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2749 { M32RXF_INSN_DIVH, model_m32rx_divh, { { (int) UNIT_M32RX_U_EXEC, 1, 21 } } },
2750 { M32RXF_INSN_JC, model_m32rx_jc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2751 { M32RXF_INSN_JNC, model_m32rx_jnc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2752 { M32RXF_INSN_JL, model_m32rx_jl, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2753 { M32RXF_INSN_JMP, model_m32rx_jmp, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2754 { M32RXF_INSN_LD, model_m32rx_ld, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2755 { M32RXF_INSN_LD_D, model_m32rx_ld_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2756 { M32RXF_INSN_LDB, model_m32rx_ldb, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2757 { M32RXF_INSN_LDB_D, model_m32rx_ldb_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2758 { M32RXF_INSN_LDH, model_m32rx_ldh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2759 { M32RXF_INSN_LDH_D, model_m32rx_ldh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2760 { M32RXF_INSN_LDUB, model_m32rx_ldub, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2761 { M32RXF_INSN_LDUB_D, model_m32rx_ldub_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2762 { M32RXF_INSN_LDUH, model_m32rx_lduh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2763 { M32RXF_INSN_LDUH_D, model_m32rx_lduh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2764 { M32RXF_INSN_LD_PLUS, model_m32rx_ld_plus, { { (int) UNIT_M32RX_U_LOAD, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2765 { M32RXF_INSN_LD24, model_m32rx_ld24, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2766 { M32RXF_INSN_LDI8, model_m32rx_ldi8, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2767 { M32RXF_INSN_LDI16, model_m32rx_ldi16, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2768 { M32RXF_INSN_LOCK, model_m32rx_lock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2769 { M32RXF_INSN_MACHI_A, model_m32rx_machi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2770 { M32RXF_INSN_MACLO_A, model_m32rx_maclo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2771 { M32RXF_INSN_MACWHI_A, model_m32rx_macwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2772 { M32RXF_INSN_MACWLO_A, model_m32rx_macwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2773 { M32RXF_INSN_MUL, model_m32rx_mul, { { (int) UNIT_M32RX_U_EXEC, 1, 4 } } },
2774 { M32RXF_INSN_MULHI_A, model_m32rx_mulhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2775 { M32RXF_INSN_MULLO_A, model_m32rx_mullo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2776 { M32RXF_INSN_MULWHI_A, model_m32rx_mulwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2777 { M32RXF_INSN_MULWLO_A, model_m32rx_mulwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2778 { M32RXF_INSN_MV, model_m32rx_mv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2779 { M32RXF_INSN_MVFACHI_A, model_m32rx_mvfachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2780 { M32RXF_INSN_MVFACLO_A, model_m32rx_mvfaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2781 { M32RXF_INSN_MVFACMI_A, model_m32rx_mvfacmi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2782 { M32RXF_INSN_MVFC, model_m32rx_mvfc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2783 { M32RXF_INSN_MVTACHI_A, model_m32rx_mvtachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2784 { M32RXF_INSN_MVTACLO_A, model_m32rx_mvtaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2785 { M32RXF_INSN_MVTC, model_m32rx_mvtc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2786 { M32RXF_INSN_NEG, model_m32rx_neg, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2787 { M32RXF_INSN_NOP, model_m32rx_nop, { { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2788 { M32RXF_INSN_NOT, model_m32rx_not, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2789 { M32RXF_INSN_RAC_DSI, model_m32rx_rac_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2790 { M32RXF_INSN_RACH_DSI, model_m32rx_rach_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2791 { M32RXF_INSN_RTE, model_m32rx_rte, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2792 { M32RXF_INSN_SETH, model_m32rx_seth, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2793 { M32RXF_INSN_SLL, model_m32rx_sll, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2794 { M32RXF_INSN_SLL3, model_m32rx_sll3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2795 { M32RXF_INSN_SLLI, model_m32rx_slli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2796 { M32RXF_INSN_SRA, model_m32rx_sra, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2797 { M32RXF_INSN_SRA3, model_m32rx_sra3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2798 { M32RXF_INSN_SRAI, model_m32rx_srai, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2799 { M32RXF_INSN_SRL, model_m32rx_srl, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2800 { M32RXF_INSN_SRL3, model_m32rx_srl3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2801 { M32RXF_INSN_SRLI, model_m32rx_srli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2802 { M32RXF_INSN_ST, model_m32rx_st, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2803 { M32RXF_INSN_ST_D, model_m32rx_st_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2804 { M32RXF_INSN_STB, model_m32rx_stb, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2805 { M32RXF_INSN_STB_D, model_m32rx_stb_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2806 { M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2807 { M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2808 { M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2809 { M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2810 { M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2811 { M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2812 { M32RXF_INSN_SUBX, model_m32rx_subx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2813 { M32RXF_INSN_TRAP, model_m32rx_trap, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2814 { M32RXF_INSN_UNLOCK, model_m32rx_unlock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2815 { M32RXF_INSN_SATB, model_m32rx_satb, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2816 { M32RXF_INSN_SATH, model_m32rx_sath, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2817 { M32RXF_INSN_SAT, model_m32rx_sat, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2818 { M32RXF_INSN_PCMPBZ, model_m32rx_pcmpbz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2819 { M32RXF_INSN_SADD, model_m32rx_sadd, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2820 { M32RXF_INSN_MACWU1, model_m32rx_macwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2821 { M32RXF_INSN_MSBLO, model_m32rx_msblo, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2822 { M32RXF_INSN_MULWU1, model_m32rx_mulwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2823 { M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2824 { M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2825 { M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
e0bd6e18
DE		 2826};
2827
2828#endif /* WITH_PROFILE_MODEL_P */
2829
368fc7db
DE		 2830static void
2831m32rx_model_init (SIM_CPU *cpu)
2832{
2833 CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32RX_DATA));
2834}
2835
e0bd6e18
DE		 2836#if WITH_PROFILE_MODEL_P
2837#define TIMING_DATA(td) td
2838#else
2839#define TIMING_DATA(td) 0
2840#endif
2841
368fc7db
DE		 2842static const MODEL m32rx_models[] =
2843{
2844 { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
e0bd6e18
DE		 2845 { 0 }
2846};
2847
2848/* The properties of this cpu's implementation. */
2849
368fc7db
DE		 2850static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
2851{
2852 sizeof (SIM_CPU),
e0bd6e18 2853#if WITH_SCACHE
368fc7db
DE		 2854 sizeof (SCACHE)
2855#else
2856 0
2857#endif
2858};
2859
2860static const CGEN_INSN *
2861m32rxf_opcode (SIM_CPU *cpu, int inum)
2862{
2863 return CPU_IDESC (cpu) [inum].opcode;
2864}
2865
2866/* start-sanitize-m32rx */
2867static void
2868m32rx_init_cpu (SIM_CPU *cpu)
2869{
2870 CPU_REG_FETCH (cpu) = m32rxf_fetch_register;
2871 CPU_REG_STORE (cpu) = m32rxf_store_register;
2872 CPU_PC_FETCH (cpu) = m32rxf_h_pc_get;
2873 CPU_PC_STORE (cpu) = m32rxf_h_pc_set;
2874 CPU_OPCODE (cpu) = m32rxf_opcode;
2875 CPU_MAX_INSNS (cpu) = M32RXF_INSN_MAX;
2876 CPU_INSN_NAME (cpu) = cgen_insn_name;
2877 CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full;
2878#if WITH_FAST
2879 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_fast;
2880#else
2881 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_full;
e0bd6e18 2882#endif
368fc7db
DE		 2883 m32rxf_init_idesc_table (cpu);
2884}
2885
2886const MACH m32rx_mach =
2887{
2888 "m32rx", "m32rx",
2889 32, 32, & m32rx_models[0], & m32rxf_imp_properties,
2890 m32rx_init_cpu
e0bd6e18
DE		 2891};
2892
368fc7db 2893/* end-sanitize-m32rx */
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