]>
Commit | Line | Data |
---|---|---|
3afece86 | 1 | /* Main simulator entry points specific to the M32R. |
fbb8b6b9 | 2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. |
646c6f2b DE |
3 | Contributed by Cygnus Support. |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2, or (at your option) | |
8 | any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along | |
16 | with this program; if not, write to the Free Software Foundation, Inc., | |
17 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
18 | ||
19 | #include "sim-main.h" | |
5f4c24c0 | 20 | #include "sim-options.h" |
646c6f2b DE |
21 | #include "libiberty.h" |
22 | #include "bfd.h" | |
646c6f2b | 23 | |
368fc7db DE |
24 | #ifdef HAVE_STRING_H |
25 | #include <string.h> | |
26 | #else | |
27 | #ifdef HAVE_STRINGS_H | |
28 | #include <strings.h> | |
29 | #endif | |
30 | #endif | |
31 | #ifdef HAVE_STDLIB_H | |
32 | #include <stdlib.h> | |
33 | #endif | |
34 | ||
fbb8b6b9 | 35 | static void free_state (SIM_DESC); |
0e701ac3 | 36 | static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose); |
646c6f2b | 37 | |
fbb8b6b9 AC |
38 | /* Records simulator descriptor so utilities like m32r_dump_regs can be |
39 | called from gdb. */ | |
40 | SIM_DESC current_state; | |
41 | \f | |
fbb8b6b9 AC |
42 | /* Cover function of sim_state_free to free the cpu buffers as well. */ |
43 | ||
44 | static void | |
45 | free_state (SIM_DESC sd) | |
46 | { | |
5f4c24c0 DE |
47 | if (STATE_MODULES (sd) != NULL) |
48 | sim_module_uninstall (sd); | |
49 | sim_cpu_free_all (sd); | |
fbb8b6b9 AC |
50 | sim_state_free (sd); |
51 | } | |
646c6f2b DE |
52 | |
53 | /* Create an instance of the simulator. */ | |
54 | ||
55 | SIM_DESC | |
247fccde | 56 | sim_open (kind, callback, abfd, argv) |
646c6f2b | 57 | SIM_OPEN_KIND kind; |
247fccde AC |
58 | host_callback *callback; |
59 | struct _bfd *abfd; | |
646c6f2b DE |
60 | char **argv; |
61 | { | |
fbb8b6b9 | 62 | SIM_DESC sd = sim_state_alloc (kind, callback); |
368fc7db | 63 | char c; |
646c6f2b | 64 | |
fbb8b6b9 | 65 | /* The cpu data is kept in a separately allocated chunk of memory. */ |
5f4c24c0 | 66 | if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK) |
fbb8b6b9 AC |
67 | { |
68 | free_state (sd); | |
69 | return 0; | |
70 | } | |
646c6f2b | 71 | |
5f4c24c0 DE |
72 | #if 0 /* FIXME: pc is in mach-specific struct */ |
73 | /* FIXME: watchpoints code shouldn't need this */ | |
74 | { | |
75 | SIM_CPU *current_cpu = STATE_CPU (sd, 0); | |
76 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
77 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
78 | } | |
79 | #endif | |
80 | ||
646c6f2b | 81 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
fbb8b6b9 AC |
82 | { |
83 | free_state (sd); | |
84 | return 0; | |
85 | } | |
646c6f2b | 86 | |
368fc7db DE |
87 | #ifdef HAVE_DV_SOCKSER /* FIXME: was done differently before */ |
88 | if (dv_sockser_install (sd) != SIM_RC_OK) | |
89 | { | |
90 | free_state (sd); | |
91 | return 0; | |
92 | } | |
93 | #endif | |
94 | ||
646c6f2b DE |
95 | #if 0 /* FIXME: 'twould be nice if we could do this */ |
96 | /* These options override any module options. | |
97 | Obviously ambiguity should be avoided, however the caller may wish to | |
98 | augment the meaning of an option. */ | |
99 | if (extra_options != NULL) | |
100 | sim_add_option_table (sd, extra_options); | |
101 | #endif | |
102 | ||
103 | /* getopt will print the error message so we just have to exit if this fails. | |
104 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
105 | print_filtered. */ | |
106 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
107 | { | |
fbb8b6b9 AC |
108 | free_state (sd); |
109 | return 0; | |
110 | } | |
111 | ||
3afece86 DE |
112 | /* Allocate a handler for the control registers and other devices |
113 | if no memory for that range has been allocated by the user. | |
114 | All are allocated in one chunk to keep things from being | |
115 | unnecessarily complicated. */ | |
116 | if (sim_core_read_buffer (sd, NULL, read_map, &c, M32R_DEVICE_ADDR, 1) == 0) | |
117 | sim_core_attach (sd, NULL, | |
118 | 0 /*level*/, | |
119 | access_read_write, | |
120 | 0 /*space ???*/, | |
121 | M32R_DEVICE_ADDR, M32R_DEVICE_LEN /*nr_bytes*/, | |
122 | 0 /*modulo*/, | |
123 | &m32r_devices, | |
124 | NULL /*buffer*/); | |
125 | ||
126 | /* Allocate core managed memory if none specified by user. | |
127 | Use address 4 here in case the user wanted address 0 unmapped. */ | |
128 | if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) | |
368fc7db | 129 | sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE); |
3afece86 | 130 | |
5f4c24c0 | 131 | /* check for/establish the reference program image */ |
fbb8b6b9 AC |
132 | if (sim_analyze_program (sd, |
133 | (STATE_PROG_ARGV (sd) != NULL | |
134 | ? *STATE_PROG_ARGV (sd) | |
135 | : NULL), | |
136 | abfd) != SIM_RC_OK) | |
137 | { | |
fbb8b6b9 AC |
138 | free_state (sd); |
139 | return 0; | |
140 | } | |
141 | ||
142 | /* Establish any remaining configuration options. */ | |
143 | if (sim_config (sd) != SIM_RC_OK) | |
144 | { | |
fbb8b6b9 | 145 | free_state (sd); |
646c6f2b DE |
146 | return 0; |
147 | } | |
148 | ||
149 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
150 | { | |
fbb8b6b9 | 151 | free_state (sd); |
646c6f2b DE |
152 | return 0; |
153 | } | |
154 | ||
155 | /* Initialize various cgen things not done by common framework. */ | |
156 | cgen_init (sd); | |
157 | ||
13ccace0 DE |
158 | /* Open a copy of the opcode table. */ |
159 | STATE_OPCODE_TABLE (sd) = m32r_cgen_opcode_open (STATE_ARCHITECTURE (sd)->mach, | |
160 | CGEN_ENDIAN_BIG); | |
161 | m32r_cgen_init_dis (STATE_OPCODE_TABLE (sd)); | |
162 | ||
fbb8b6b9 | 163 | { |
5f4c24c0 | 164 | int c; |
247fccde | 165 | |
5f4c24c0 | 166 | for (c = 0; c < MAX_NR_PROCESSORS; ++c) |
0e701ac3 AC |
167 | { |
168 | /* Only needed for profiling, but the structure member is small. */ | |
3afece86 DE |
169 | memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c)), 0, |
170 | sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c)))); | |
0e701ac3 | 171 | /* Hook in callback for reporting these stats */ |
5f4c24c0 | 172 | PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, c))) |
0e701ac3 AC |
173 | = print_m32r_misc_cpu; |
174 | } | |
fbb8b6b9 AC |
175 | } |
176 | ||
177 | /* Store in a global so things like sparc32_dump_regs can be invoked | |
178 | from the gdb command line. */ | |
179 | current_state = sd; | |
646c6f2b | 180 | |
fbb8b6b9 | 181 | return sd; |
646c6f2b DE |
182 | } |
183 | ||
184 | void | |
185 | sim_close (sd, quitting) | |
186 | SIM_DESC sd; | |
187 | int quitting; | |
188 | { | |
13ccace0 | 189 | m32r_cgen_opcode_close (STATE_OPCODE_TABLE (sd)); |
646c6f2b DE |
190 | sim_module_uninstall (sd); |
191 | } | |
fbb8b6b9 | 192 | \f |
646c6f2b | 193 | SIM_RC |
fafce69a | 194 | sim_create_inferior (sd, abfd, argv, envp) |
646c6f2b | 195 | SIM_DESC sd; |
fafce69a | 196 | struct _bfd *abfd; |
646c6f2b DE |
197 | char **argv; |
198 | char **envp; | |
199 | { | |
fbb8b6b9 AC |
200 | SIM_CPU *current_cpu = STATE_CPU (sd, 0); |
201 | SIM_ADDR addr; | |
fbb8b6b9 AC |
202 | |
203 | if (abfd != NULL) | |
204 | addr = bfd_get_start_address (abfd); | |
205 | else | |
206 | addr = 0; | |
5f4c24c0 | 207 | sim_pc_set (current_cpu, addr); |
fbb8b6b9 | 208 | |
646c6f2b DE |
209 | #if 0 |
210 | STATE_ARGV (sd) = sim_copy_argv (argv); | |
211 | STATE_ENVP (sd) = sim_copy_argv (envp); | |
212 | #endif | |
fbb8b6b9 | 213 | |
646c6f2b DE |
214 | return SIM_RC_OK; |
215 | } | |
216 | ||
646c6f2b DE |
217 | /* PROFILE_CPU_CALLBACK */ |
218 | ||
219 | static void | |
220 | print_m32r_misc_cpu (SIM_CPU *cpu, int verbose) | |
221 | { | |
222 | SIM_DESC sd = CPU_STATE (cpu); | |
7a418800 | 223 | char buf[20]; |
646c6f2b DE |
224 | |
225 | if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX]) | |
226 | { | |
227 | sim_io_printf (sd, "Miscellaneous Statistics\n\n"); | |
7a418800 | 228 | sim_io_printf (sd, " %-*s %s\n\n", |
646c6f2b | 229 | PROFILE_LABEL_WIDTH, "Fill nops:", |
7a418800 | 230 | sim_add_commas (buf, sizeof (buf), |
3afece86 | 231 | CPU_M32R_MISC_PROFILE (cpu)->fillnop_count)); |
13ccace0 DE |
232 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx) |
233 | sim_io_printf (sd, " %-*s %s\n\n", | |
234 | PROFILE_LABEL_WIDTH, "Parallel insns:", | |
235 | sim_add_commas (buf, sizeof (buf), | |
3afece86 | 236 | CPU_M32R_MISC_PROFILE (cpu)->parallel_count)); |
646c6f2b DE |
237 | } |
238 | } | |
239 | ||
646c6f2b DE |
240 | void |
241 | sim_do_command (sd, cmd) | |
242 | SIM_DESC sd; | |
243 | char *cmd; | |
244 | { | |
3afece86 | 245 | char **argv; |
0e701ac3 | 246 | |
3afece86 DE |
247 | if (cmd == NULL) |
248 | return; | |
249 | ||
250 | argv = buildargv (cmd); | |
251 | ||
252 | if (argv[0] != NULL | |
253 | && strcasecmp (argv[0], "info") == 0 | |
254 | && argv[1] != NULL | |
255 | && strncasecmp (argv[1], "reg", 3) == 0) | |
0e701ac3 | 256 | { |
3afece86 DE |
257 | SI val; |
258 | ||
259 | /* We only support printing bbpsw,bbpc here as there is no equivalent | |
260 | functionality in gdb. */ | |
261 | if (argv[2] == NULL) | |
262 | sim_io_eprintf (sd, "Missing register in `%s'\n", cmd); | |
263 | else if (argv[3] != NULL) | |
264 | sim_io_eprintf (sd, "Too many arguments in `%s'\n", cmd); | |
265 | else if (strcasecmp (argv[2], "bbpsw") == 0) | |
266 | { | |
267 | val = a_m32r_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPSW); | |
268 | sim_io_printf (sd, "bbpsw 0x%x %d\n", val, val); | |
269 | } | |
270 | else if (strcasecmp (argv[2], "bbpc") == 0) | |
271 | { | |
272 | val = a_m32r_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPC); | |
273 | sim_io_printf (sd, "bbpc 0x%x %d\n", val, val); | |
274 | } | |
275 | else | |
276 | sim_io_eprintf (sd, "Printing of register `%s' not supported with `sim info'\n", | |
277 | argv[2]); | |
0e701ac3 | 278 | } |
3afece86 | 279 | else |
0e701ac3 | 280 | { |
3afece86 DE |
281 | if (sim_args_command (sd, cmd) != SIM_RC_OK) |
282 | sim_io_eprintf (sd, "Unknown sim command `%s'\n", cmd); | |
0e701ac3 | 283 | } |
3afece86 DE |
284 | |
285 | freeargv (argv); | |
0e701ac3 | 286 | } |