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Commit | Line | Data |
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c906108c | 1 | /* m32r exception, interrupt, and trap (EIT) support |
3666a048 | 2 | Copyright (C) 1998-2021 Free Software Foundation, Inc. |
c906108c SS |
3 | Contributed by Cygnus Solutions. |
4 | ||
16b47b25 | 5 | This file is part of GDB, the GNU debugger. |
c906108c | 6 | |
16b47b25 NC |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
c906108c | 11 | |
16b47b25 NC |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
c906108c | 19 | |
6df01ab8 MF |
20 | /* This must come before any other includes. */ |
21 | #include "defs.h" | |
22 | ||
c906108c | 23 | #include "sim-main.h" |
1fef66b0 | 24 | #include "sim-signal.h" |
61a0c964 | 25 | #include "sim-syscall.h" |
c906108c | 26 | #include "targ-vals.h" |
32a046ab | 27 | #include <stdlib.h> |
c906108c | 28 | |
16b47b25 | 29 | #define TRAP_FLUSH_CACHE 12 |
0b2e03b4 | 30 | /* The semantic code invokes this for invalid (unrecognized) instructions. */ |
c906108c | 31 | |
16b47b25 NC |
32 | SEM_PC |
33 | sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC pc) | |
c906108c SS |
34 | { |
35 | SIM_DESC sd = CPU_STATE (current_cpu); | |
36 | ||
37 | #if 0 | |
38 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) | |
39 | { | |
40 | h_bsm_set (current_cpu, h_sm_get (current_cpu)); | |
41 | h_bie_set (current_cpu, h_ie_get (current_cpu)); | |
42 | h_bcond_set (current_cpu, h_cond_get (current_cpu)); | |
43 | /* sm not changed */ | |
44 | h_ie_set (current_cpu, 0); | |
45 | h_cond_set (current_cpu, 0); | |
46 | ||
47 | h_bpc_set (current_cpu, cia); | |
48 | ||
49 | sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, | |
50 | EIT_RSVD_INSN_ADDR); | |
51 | } | |
52 | else | |
53 | #endif | |
54 | sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL); | |
16b47b25 NC |
55 | |
56 | return pc; | |
c906108c SS |
57 | } |
58 | ||
59 | /* Process an address exception. */ | |
60 | ||
61 | void | |
62 | m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, | |
63 | unsigned int map, int nr_bytes, address_word addr, | |
64 | transfer_type transfer, sim_core_signals sig) | |
65 | { | |
66 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) | |
67 | { | |
16b47b25 NC |
68 | m32rbf_h_cr_set (current_cpu, H_CR_BBPC, |
69 | m32rbf_h_cr_get (current_cpu, H_CR_BPC)); | |
70 | switch (MACH_NUM (CPU_MACH (current_cpu))) | |
71 | { | |
72 | case MACH_M32R: | |
73 | m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu)); | |
74 | /* sm not changed. */ | |
75 | m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80); | |
76 | break; | |
77 | case MACH_M32RX: | |
78 | m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu)); | |
79 | /* sm not changed. */ | |
80 | m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80); | |
81 | break; | |
82 | case MACH_M32R2: | |
83 | m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu)); | |
84 | /* sm not changed. */ | |
85 | m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80); | |
86 | break; | |
87 | default: | |
88 | abort (); | |
89 | } | |
90 | ||
91 | m32rbf_h_cr_set (current_cpu, H_CR_BPC, cia); | |
c906108c SS |
92 | |
93 | sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, | |
94 | EIT_ADDR_EXCP_ADDR); | |
95 | } | |
96 | else | |
97 | sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, | |
98 | transfer, sig); | |
99 | } | |
100 | \f | |
c906108c SS |
101 | /* Trap support. |
102 | The result is the pc address to continue at. | |
103 | Preprocessing like saving the various registers has already been done. */ | |
104 | ||
105 | USI | |
106 | m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num) | |
107 | { | |
108 | SIM_DESC sd = CPU_STATE (current_cpu); | |
109 | host_callback *cb = STATE_CALLBACK (sd); | |
110 | ||
c906108c SS |
111 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) |
112 | { | |
113 | /* The new pc is the trap vector entry. | |
16b47b25 NC |
114 | We assume there's a branch there to some handler. |
115 | Use cr5 as EVB (EIT Vector Base) register. */ | |
116 | /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */ | |
117 | USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4; | |
c906108c SS |
118 | return new_pc; |
119 | } | |
120 | ||
121 | switch (num) | |
122 | { | |
123 | case TRAP_SYSCALL : | |
124 | { | |
7d5c6c43 MF |
125 | long result, result2; |
126 | int errcode; | |
127 | ||
128 | sim_syscall_multi (current_cpu, | |
129 | m32rbf_h_gr_get (current_cpu, 0), | |
130 | m32rbf_h_gr_get (current_cpu, 1), | |
131 | m32rbf_h_gr_get (current_cpu, 2), | |
132 | m32rbf_h_gr_get (current_cpu, 3), | |
133 | m32rbf_h_gr_get (current_cpu, 4), | |
134 | &result, &result2, &errcode); | |
135 | ||
136 | m32rbf_h_gr_set (current_cpu, 2, errcode); | |
137 | m32rbf_h_gr_set (current_cpu, 0, result); | |
138 | m32rbf_h_gr_set (current_cpu, 1, result2); | |
c906108c SS |
139 | break; |
140 | } | |
141 | ||
142 | case TRAP_BREAKPOINT: | |
143 | sim_engine_halt (sd, current_cpu, NULL, pc, | |
144 | sim_stopped, SIM_SIGTRAP); | |
145 | break; | |
146 | ||
16b47b25 NC |
147 | case TRAP_FLUSH_CACHE: |
148 | /* Do nothing. */ | |
149 | break; | |
150 | ||
c906108c SS |
151 | default : |
152 | { | |
16b47b25 NC |
153 | /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */ |
154 | /* Use cr5 as EVB (EIT Vector Base) register. */ | |
155 | USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4; | |
c906108c SS |
156 | return new_pc; |
157 | } | |
158 | } | |
159 | ||
160 | /* Fake an "rte" insn. */ | |
161 | /* FIXME: Should duplicate all of rte processing. */ | |
162 | return (pc & -4) + 4; | |
163 | } |