[thirdparty/binutils-gdb.git] / sim / m68hc11 / sim-main.h

/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   Written by Stephane Carrez (stcarrez@worldnet.fr)

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#ifndef _SIM_MAIN_H
#define _SIM_MAIN_H

#define WITH_MODULO_MEMORY 1
#define WITH_WATCHPOINTS 1
#define SIM_HANDLES_LMA 1

#include "sim-basics.h"

typedef address_word sim_cia;

#include "sim-signal.h"
#include "sim-base.h"

#include "bfd.h"

#include "opcode/m68hc11.h"

#include "gdb/callback.h"
#include "gdb/remote-sim.h"
#include "opcode/m68hc11.h"
#include "sim-types.h"

typedef unsigned8 uint8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;
typedef unsigned64 uint64;
typedef signed64 int64;

struct _sim_cpu;

#include "interrupts.h"
#include <setjmp.h>

/* Specifies the level of mapping for the IO, EEprom, nvram and external
   RAM.  IO registers are mapped over everything and the external RAM
   is last (ie, it can be hidden by everything above it in the list).  */
enum m68hc11_map_level
{
  M6811_IO_LEVEL,
  M6811_EEPROM_LEVEL,
  M6811_NVRAM_LEVEL,
  M6811_RAM_LEVEL
};

enum cpu_type
{
  CPU_M6811,
  CPU_M6812
};

#define X_REGNUM 	0
#define D_REGNUM	1
#define Y_REGNUM        2
#define SP_REGNUM 	3
#define PC_REGNUM 	4
#define A_REGNUM        5
#define B_REGNUM        6
#define PSW_REGNUM 	7
#define Z_REGNUM        8

typedef struct m6811_regs {
    unsigned short      d;
    unsigned short      ix;
    unsigned short      iy;
    unsigned short      sp;
    unsigned short      pc;
    unsigned char       ccr;
} m6811_regs;


/* Description of 68HC11 IO registers.  Such description is only provided
   for the info command to display the current setting of IO registers
   from GDB.  */
struct io_reg_desc
{
  int        mask;
  const char *short_name;
  const char *long_name;
};
typedef struct io_reg_desc io_reg_desc;

extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
			       int mode);
extern void print_io_byte (SIM_DESC sd, const char *name,
			   io_reg_desc *desc, uint8 val, uint16 addr);


/* List of special 68HC11&68HC12 instructions that are not handled by the
   'gencode.c' generator.  These complex instructions are implemented
   by 'cpu_special'.  */
enum M6811_Special
{
  /* 68HC11 instructions.  */
  M6811_DAA,
  M6811_EMUL_SYSCALL,
  M6811_ILLEGAL,
  M6811_RTI,
  M6811_STOP,
  M6811_SWI,
  M6811_TEST,
  M6811_WAI,

  /* 68HC12 instructions.  */
  M6812_BGND,
  M6812_CALL,
  M6812_IDIVS,
  M6812_EDIV,
  M6812_EDIVS,
  M6812_EMACS,
  M6812_EMUL,
  M6812_EMULS,
  M6812_ETBL,
  M6812_MEM,
  M6812_REV,
  M6812_REVW,
  M6812_RTC,
  M6812_RTI,
  M6812_WAV
};

#define M6811_MAX_PORTS (0x03f+1)
#define M6812_MAX_PORTS (0x3ff+1)
#define MAX_PORTS       (M6812_MAX_PORTS)

struct _sim_cpu;

typedef void (* cpu_interp) (struct _sim_cpu*);

struct _sim_cpu {
  /* CPU registers.  */
  struct m6811_regs     cpu_regs;

  /* CPU interrupts.  */
  struct interrupts     cpu_interrupts;

  /* Pointer to the interpretor routine.  */
  cpu_interp            cpu_interpretor;

  /* Pointer to the architecture currently configured in the simulator.  */
  const struct bfd_arch_info  *cpu_configured_arch;
  
  /* CPU absolute cycle time.  The cycle time is updated after
     each instruction, by the number of cycles taken by the instruction.
     It is cleared only when reset occurs.  */
  signed64              cpu_absolute_cycle;

  /* Number of cycles to increment after the current instruction.
     This is also the number of ticks for the generic event scheduler.  */
  uint8                 cpu_current_cycle;
  int                   cpu_emul_syscall;
  int                   cpu_is_initialized;
  int                   cpu_running;
  int                   cpu_check_memory;
  int                   cpu_stop_on_interrupt;

  /* When this is set, start execution of program at address specified
     in the ELF header.  This is used for testing some programs that do not
     have an interrupt table linked with them.  Programs created during the
     GCC validation are like this. A normal 68HC11 does not behave like
     this (unless there is some OS or downloadable feature).  */
  int                   cpu_use_elf_start;

  /* The starting address specified in ELF header.  */
  int                   cpu_elf_start;
  
  uint16                cpu_insn_pc;

  /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
     get the cycle time.  This is used for the timer rate and for the baud
     rate generation.  */
  unsigned long         cpu_frequency;

  /* The mode in which the CPU is configured (MODA and MODB pins).  */
  unsigned int          cpu_mode;

  /* The cpu being configured.  */
  enum cpu_type         cpu_type;
  
  /* Initial value of the CONFIG register.  */
  uint8                 cpu_config;
  uint8                 cpu_use_local_config;
  
  uint8                 ios[MAX_PORTS];

  struct hw            *hw_cpu;

  /* ... base type ... */
  sim_cpu_base base;
};

/* Returns the cpu absolute cycle time (A virtual counter incremented
   at each 68HC11 E clock).  */
#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
#define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
#define cpu_is_running(PROC)    ((PROC)->cpu_running)

/* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
#define cpu_get_io_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
#define cpu_get_reg_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)

/* Returns the different CPU registers.  */
#define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
#define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
#define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
#define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
#define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
#define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
#define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
#define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_get_tmp3(PROC)         (0)
#define cpu_get_tmp2(PROC)         (0)

#define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
#define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
#define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_set_tmp3(PROC,VAL)     (0)
#define cpu_set_tmp2(PROC,VAL)     (0)

#if 0
/* This is a function in m68hc11_sim.c to keep track of the frame.  */
#define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
#endif

#define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))

#define cpu_set_a(PROC,VAL)  \
      cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
#define cpu_set_b(PROC,VAL)  \
      cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))

#define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
#define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
#define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
#define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
#define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
#define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
#define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
#define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
#define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)

#define cpu_set_ccr_flag(S,B,V) \
cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))

#define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
#define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
#define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
#define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
#define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
#define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
#define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
#define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)

#undef inline
#define inline static __inline__

extern void cpu_memory_exception (struct _sim_cpu *proc,
                                  SIM_SIGNAL excep,
                                  uint16 addr,
                                  const char *message);

inline uint8
memory_read8 (sim_cpu *cpu, uint16 addr)
{
  uint8 val;
  
  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return val;
}

inline void
memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
{
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}

inline uint16
memory_read16 (sim_cpu *cpu, uint16 addr)
{
  uint8 b[2];
  
  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
}

inline void
memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
{
  uint8 b[2];

  b[0] = val >> 8;
  b[1] = val;
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}
extern void
cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);

     inline void
cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_V (proc, 0);
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
}

     inline void
cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
{
  cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

     inline void
cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

inline void
cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}


inline void
cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}

inline void
cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

inline void
cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

/* Push and pop instructions for 68HC11 (next-available stack mode).  */
inline void
cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline void
cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp - 1;

  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline uint8
cpu_m68hc11_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc11_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Push and pop instructions for 68HC12 (last-used stack mode).  */
inline void
cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr --;
  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline void
cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr -= 2;
  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline uint8
cpu_m68hc12_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc12_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Fetch a 8/16 bit value and update the PC.  */
inline uint8
cpu_fetch8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.pc = addr + 1;
  return val;
}

inline uint16
cpu_fetch16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.pc = addr + 2;
  return val;
}

extern void cpu_call (sim_cpu* proc, uint16 addr);
extern void cpu_exg (sim_cpu* proc, uint8 code);
extern void cpu_dbcc (sim_cpu* proc);
extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
extern void cpu_move8 (sim_cpu *proc, uint8 op);
extern void cpu_move16 (sim_cpu *proc, uint8 op);

extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
extern void cpu_push_all (sim_cpu *proc);
extern void cpu_single_step (sim_cpu *proc);

extern void cpu_info (SIM_DESC sd, sim_cpu *proc);

extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);

extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
extern int cpu_reset (sim_cpu *cpu);
extern int cpu_restart (sim_cpu *cpu);
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
                              uint16 addr, const char *message, ...);
extern void emul_os (int op, sim_cpu *cpu);
extern void cpu_interp_m6811 (sim_cpu *cpu);
extern void cpu_interp_m6812 (sim_cpu *cpu);

extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
				      double ton, double toff,
				      signed64 repeat);
extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
				 unsigned addr, uint8 val);

/* The current state of the processor; registers, memory, etc.  */

#define CIA_GET(CPU)      (cpu_get_pc (CPU))
#define CIA_SET(CPU,VAL)  (cpu_set_pc ((CPU), (VAL)))

#if (WITH_SMP)
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
#else
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
#endif

struct sim_state {
  sim_cpu        cpu[MAX_NR_PROCESSORS];
  device         *devices;
  sim_state_base base;
};

extern void sim_set_profile (int n);
extern void sim_set_profile_size (int n);
extern void sim_board_reset (SIM_DESC sd);

extern const char *cycle_to_string (sim_cpu *cpu, signed64 t);

#endif
Commit	Line	Data
81e09ed8	1	/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
5abb9efa	2	Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
e0709f50 AC	3	Written by Stephane Carrez (stcarrez@worldnet.fr)
	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License along
	18	with this program; if not, write to the Free Software Foundation, Inc.,
	19	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	#ifndef _SIM_MAIN_H
	22	#define _SIM_MAIN_H
	23
	24	#define WITH_MODULO_MEMORY 1
	25	#define WITH_WATCHPOINTS 1
	26	#define SIM_HANDLES_LMA 1
	27
	28	#include "sim-basics.h"
	29
	30	typedef address_word sim_cia;
	31
	32	#include "sim-signal.h"
	33	#include "sim-base.h"
	34
	35	#include "bfd.h"
	36
	37	#include "opcode/m68hc11.h"
	38
3c25f8c7 AC	39	#include "gdb/callback.h"
3c25f8c7 AC	40	#include "gdb/remote-sim.h"
e0709f50 AC	41	#include "opcode/m68hc11.h"
	42	#include "sim-types.h"
	43
	44	typedef unsigned8 uint8;
	45	typedef unsigned16 uint16;
	46	typedef signed16 int16;
	47	typedef unsigned32 uint32;
	48	typedef signed32 int32;
	49	typedef unsigned64 uint64;
	50	typedef signed64 int64;
	51
	52	struct _sim_cpu;
	53
	54	#include "interrupts.h"
	55	#include <setjmp.h>
	56
63348d04 SC	57	/* Specifies the level of mapping for the IO, EEprom, nvram and external
	58	RAM. IO registers are mapped over everything and the external RAM
	59	is last (ie, it can be hidden by everything above it in the list). */
	60	enum m68hc11_map_level
	61	{
	62	M6811_IO_LEVEL,
	63	M6811_EEPROM_LEVEL,
	64	M6811_NVRAM_LEVEL,
	65	M6811_RAM_LEVEL
	66	};
	67
81e09ed8 SC	68	enum cpu_type
	69	{
	70	CPU_M6811,
	71	CPU_M6812
	72	};
63348d04	73
e0709f50 AC	74	#define X_REGNUM 0
	75	#define D_REGNUM 1
	76	#define Y_REGNUM 2
	77	#define SP_REGNUM 3
	78	#define PC_REGNUM 4
	79	#define A_REGNUM 5
	80	#define B_REGNUM 6
	81	#define PSW_REGNUM 7
	82	#define Z_REGNUM 8
e0709f50 AC	83
	84	typedef struct m6811_regs {
	85	unsigned short d;
	86	unsigned short ix;
	87	unsigned short iy;
	88	unsigned short sp;
	89	unsigned short pc;
	90	unsigned char ccr;
	91	} m6811_regs;
	92
	93
	94	/* Description of 68HC11 IO registers. Such description is only provided
	95	for the info command to display the current setting of IO registers
	96	from GDB. */
	97	struct io_reg_desc
	98	{
	99	int mask;
	100	const char *short_name;
	101	const char *long_name;
	102	};
	103	typedef struct io_reg_desc io_reg_desc;
	104
	105	extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
	106	int mode);
	107	extern void print_io_byte (SIM_DESC sd, const char *name,
	108	io_reg_desc *desc, uint8 val, uint16 addr);
	109
	110
81e09ed8	111	/* List of special 68HC11&68HC12 instructions that are not handled by the
e0709f50 AC	112	'gencode.c' generator. These complex instructions are implemented
	113	by 'cpu_special'. */
	114	enum M6811_Special
	115	{
81e09ed8 SC	116	/* 68HC11 instructions. */
	117	M6811_DAA,
	118	M6811_EMUL_SYSCALL,
	119	M6811_ILLEGAL,
e0709f50	120	M6811_RTI,
81e09ed8	121	M6811_STOP,
e0709f50 AC	122	M6811_SWI,
e0709f50 AC	123	M6811_TEST,
81e09ed8 SC	124	M6811_WAI,
	125
	126	/* 68HC12 instructions. */
	127	M6812_BGND,
	128	M6812_CALL,
	129	M6812_IDIVS,
	130	M6812_EDIV,
	131	M6812_EDIVS,
	132	M6812_EMACS,
	133	M6812_EMUL,
	134	M6812_EMULS,
	135	M6812_ETBL,
	136	M6812_MEM,
	137	M6812_REV,
	138	M6812_REVW,
	139	M6812_RTC,
	140	M6812_RTI,
	141	M6812_WAV
e0709f50 AC	142	};
e0709f50 AC	143
81e09ed8 SC	144	#define M6811_MAX_PORTS (0x03f+1)
	145	#define M6812_MAX_PORTS (0x3ff+1)
	146	#define MAX_PORTS (M6812_MAX_PORTS)
e0709f50	147
81e09ed8 SC	148	struct _sim_cpu;
	149
	150	typedef void (* cpu_interp) (struct _sim_cpu*);
	151
e0709f50 AC	152	struct _sim_cpu {
	153	/* CPU registers. */
	154	struct m6811_regs cpu_regs;
	155
	156	/* CPU interrupts. */
	157	struct interrupts cpu_interrupts;
	158
81e09ed8 SC	159	/* Pointer to the interpretor routine. */
	160	cpu_interp cpu_interpretor;
	161
	162	/* Pointer to the architecture currently configured in the simulator. */
	163	const struct bfd_arch_info *cpu_configured_arch;
	164
e0709f50 AC	165	/* CPU absolute cycle time. The cycle time is updated after
	166	each instruction, by the number of cycles taken by the instruction.
	167	It is cleared only when reset occurs. */
	168	signed64 cpu_absolute_cycle;
	169
	170	/* Number of cycles to increment after the current instruction.
	171	This is also the number of ticks for the generic event scheduler. */
	172	uint8 cpu_current_cycle;
	173	int cpu_emul_syscall;
	174	int cpu_is_initialized;
	175	int cpu_running;
	176	int cpu_check_memory;
	177	int cpu_stop_on_interrupt;
	178
	179	/* When this is set, start execution of program at address specified
	180	in the ELF header. This is used for testing some programs that do not
	181	have an interrupt table linked with them. Programs created during the
	182	GCC validation are like this. A normal 68HC11 does not behave like
	183	this (unless there is some OS or downloadable feature). */
	184	int cpu_use_elf_start;
	185
	186	/* The starting address specified in ELF header. */
	187	int cpu_elf_start;
	188
	189	uint16 cpu_insn_pc;
e0709f50 AC	190
	191	/* CPU frequency. This is the quartz frequency. It is divided by 4 to
	192	get the cycle time. This is used for the timer rate and for the baud
	193	rate generation. */
	194	unsigned long cpu_frequency;
	195
	196	/* The mode in which the CPU is configured (MODA and MODB pins). */
	197	unsigned int cpu_mode;
	198
81e09ed8 SC	199	/* The cpu being configured. */
	200	enum cpu_type cpu_type;
	201
e0709f50 AC	202	/* Initial value of the CONFIG register. */
	203	uint8 cpu_config;
	204	uint8 cpu_use_local_config;
	205
81e09ed8	206	uint8 ios[MAX_PORTS];
827ec39a SC	207
	208	struct hw *hw_cpu;
	209
e0709f50 AC	210	/* ... base type ... */
	211	sim_cpu_base base;
	212	};
	213
	214	/* Returns the cpu absolute cycle time (A virtual counter incremented
	215	at each 68HC11 E clock). */
	216	#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
	217	#define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
	218	#define cpu_is_running(PROC) ((PROC)->cpu_running)
	219
	220	/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
	221	#define cpu_get_io_base(PROC) \
	222	(((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
	223	#define cpu_get_reg_base(PROC) \
	224	(((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
	225
	226	/* Returns the different CPU registers. */
	227	#define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
	228	#define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
	229	#define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
	230	#define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
	231	#define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
	232	#define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
	233	#define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
	234	#define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
	235
81e09ed8 SC	236	/* 68HC12 specific and Motorola internal registers. */
	237	#define cpu_get_tmp3(PROC) (0)
	238	#define cpu_get_tmp2(PROC) (0)
	239
e0709f50 AC	240	#define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
	241	#define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
	242	#define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
	243
81e09ed8 SC	244	/* 68HC12 specific and Motorola internal registers. */
	245	#define cpu_set_tmp3(PROC,VAL) (0)
	246	#define cpu_set_tmp2(PROC,VAL) (0)
	247
e0709f50 AC	248	#if 0
	249	/* This is a function in m68hc11_sim.c to keep track of the frame. */
	250	#define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
	251	#endif
	252
	253	#define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
	254
	255	#define cpu_set_a(PROC,VAL) \
	256	cpu_set_d(PROC,((VAL) << 8) \| cpu_get_b(PROC))
	257	#define cpu_set_b(PROC,VAL) \
	258	cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)\|(VAL & 0x0FF))
	259
	260	#define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
	261	#define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
	262	#define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
	263	#define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
	264	#define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
	265	#define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
	266	#define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
	267	#define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
	268	#define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
	269
	270	#define cpu_set_ccr_flag(S,B,V) \
	271	cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) \| ((V) ? B : 0))
	272
	273	#define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
	274	#define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
	275	#define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
	276	#define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
	277	#define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
	278	#define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
	279	#define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
	280	#define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
	281
	282	#undef inline
	283	#define inline static __inline__
	284
	285	extern void cpu_memory_exception (struct _sim_cpu *proc,
	286	SIM_SIGNAL excep,
	287	uint16 addr,
	288	const char *message);
	289
	290	inline uint8
	291	memory_read8 (sim_cpu *cpu, uint16 addr)
	292	{
	293	uint8 val;
	294
	295	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	296	{
	297	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	298	"Read error");
	299	}
	300	return val;
	301	}
	302
	303	inline void
	304	memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
	305	{
	306	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	307	{
	308	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	309	"Write error");
	310	}
	311	}
312
313	inline uint16
314	memory_read16 (sim_cpu *cpu, uint16 addr)
315	{
316	uint8 b[2];
317
318	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
319	{
320	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
321	"Read error");
322	}
323	return (((uint16) (b[0])) << 8) \| ((uint16) b[1]);
324	}
325
326	inline void
327	memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
328	{
329	uint8 b[2];
330
331	b[0] = val >> 8;
332	b[1] = val;
333	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
334	{
335	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
336	"Write error");
337	}
338	}
339	extern void
340	cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
341
342	inline void
343	cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
344	{
345	cpu_set_ccr_V (proc, 0);
346	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
347	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
348	}
349
350	inline void
351	cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
352	{
353	cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
354	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
355	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
356	}
357
358	inline void
359	cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
360	{
361	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
362	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
363	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
364	}
365
366	inline void
367	cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
368	{
369	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x80 ? 1 : 0);
370	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x80 ? 1 : 0);
371	cpu_set_ccr_Z (proc, r == 0);
372	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
373	}
374
375
376	inline void
377	cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
378	{
379	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x80 ? 1 : 0);
380	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x80 ? 1 : 0);
381	cpu_set_ccr_Z (proc, r == 0);
382	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
383	}
384
385	inline void
386	cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
387	{
388	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x8000 ? 1 : 0);
389	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x8000 ? 1 : 0);
390	cpu_set_ccr_Z (proc, r == 0);
391	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
392	}
393
394	inline void
395	cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
396	{
397	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x8000 ? 1 : 0);
398	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x8000 ? 1 : 0);
399	cpu_set_ccr_Z (proc, r == 0);
400	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
401	}
402
81e09ed8	403	/* Push and pop instructions for 68HC11 (next-available stack mode). */
e0709f50	404	inline void
81e09ed8	405	cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
e0709f50 AC	406	{
	407	uint16 addr = proc->cpu_regs.sp;
	408
	409	memory_write8 (proc, addr, val);
	410	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	411	}
	412
	413	inline void
81e09ed8	414	cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
e0709f50 AC	415	{
	416	uint16 addr = proc->cpu_regs.sp - 1;
	417
	418	memory_write16 (proc, addr, val);
	419	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	420	}
	421
	422	inline uint8
81e09ed8	423	cpu_m68hc11_pop_uint8 (sim_cpu *proc)
e0709f50 AC	424	{
	425	uint16 addr = proc->cpu_regs.sp;
	426	uint8 val;
	427
	428	val = memory_read8 (proc, addr + 1);
	429	proc->cpu_regs.sp = addr + 1;
e0709f50 AC	430	return val;
	431	}
	432
	433	inline uint16
81e09ed8	434	cpu_m68hc11_pop_uint16 (sim_cpu *proc)
e0709f50 AC	435	{
	436	uint16 addr = proc->cpu_regs.sp;
	437	uint16 val;
	438
	439	val = memory_read16 (proc, addr + 1);
	440	proc->cpu_regs.sp = addr + 2;
e0709f50 AC	441	return val;
	442	}
	443
81e09ed8 SC	444	/* Push and pop instructions for 68HC12 (last-used stack mode). */
	445	inline void
	446	cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
	447	{
	448	uint16 addr = proc->cpu_regs.sp;
	449
	450	addr --;
	451	memory_write8 (proc, addr, val);
	452	proc->cpu_regs.sp = addr;
81e09ed8 SC	453	}
	454
	455	inline void
	456	cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
	457	{
	458	uint16 addr = proc->cpu_regs.sp;
	459
	460	addr -= 2;
	461	memory_write16 (proc, addr, val);
	462	proc->cpu_regs.sp = addr;
81e09ed8 SC	463	}
	464
	465	inline uint8
	466	cpu_m68hc12_pop_uint8 (sim_cpu *proc)
	467	{
	468	uint16 addr = proc->cpu_regs.sp;
	469	uint8 val;
	470
	471	val = memory_read8 (proc, addr);
	472	proc->cpu_regs.sp = addr + 1;
81e09ed8 SC	473	return val;
	474	}
	475
	476	inline uint16
	477	cpu_m68hc12_pop_uint16 (sim_cpu *proc)
	478	{
	479	uint16 addr = proc->cpu_regs.sp;
	480	uint16 val;
	481
	482	val = memory_read16 (proc, addr);
	483	proc->cpu_regs.sp = addr + 2;
81e09ed8 SC	484	return val;
	485	}
	486
	487	/* Fetch a 8/16 bit value and update the PC. */
e0709f50 AC	488	inline uint8
	489	cpu_fetch8 (sim_cpu *proc)
	490	{
	491	uint16 addr = proc->cpu_regs.pc;
	492	uint8 val;
	493
	494	val = memory_read8 (proc, addr);
	495	proc->cpu_regs.pc = addr + 1;
	496	return val;
	497	}
	498
	499	inline uint16
	500	cpu_fetch16 (sim_cpu *proc)
	501	{
	502	uint16 addr = proc->cpu_regs.pc;
	503	uint16 val;
	504
	505	val = memory_read16 (proc, addr);
	506	proc->cpu_regs.pc = addr + 2;
	507	return val;
	508	}
	509
	510	extern void cpu_call (sim_cpu* proc, uint16 addr);
81e09ed8 SC	511	extern void cpu_exg (sim_cpu* proc, uint8 code);
81e09ed8 SC	512	extern void cpu_dbcc (sim_cpu* proc);
e0709f50	513	extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
81e09ed8 SC	514	extern void cpu_move8 (sim_cpu *proc, uint8 op);
81e09ed8 SC	515	extern void cpu_move16 (sim_cpu *proc, uint8 op);
e0709f50 AC	516
e0709f50 AC	517	extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
81e09ed8	518	extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
e0709f50 AC	519	extern void cpu_push_all (sim_cpu *proc);
	520	extern void cpu_single_step (sim_cpu *proc);
	521
	522	extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
	523
	524	extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
	525
e0709f50	526	extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
e0709f50 AC	527	extern int cpu_reset (sim_cpu *cpu);
	528	extern int cpu_restart (sim_cpu *cpu);
	529	extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
	530	uint16 addr, const char *message, ...);
	531	extern void emul_os (int op, sim_cpu *cpu);
81e09ed8 SC	532	extern void cpu_interp_m6811 (sim_cpu *cpu);
81e09ed8 SC	533	extern void cpu_interp_m6812 (sim_cpu *cpu);
e0709f50	534
827ec39a SC	535	extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
	536	double ton, double toff,
	537	signed64 repeat);
	538	extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
	539	extern void m68hc11cpu_set_port (struct hw me, sim_cpu cpu,
	540	unsigned addr, uint8 val);
	541
e0709f50 AC	542	/* The current state of the processor; registers, memory, etc. */
	543
	544	#define CIA_GET(CPU) (cpu_get_pc (CPU))
	545	#define CIA_SET(CPU,VAL) (cpu_set_pc ((CPU), (VAL)))
	546
	547	#if (WITH_SMP)
	548	#define STATE_CPU(sd,n) (&(sd)->cpu[n])
	549	#else
	550	#define STATE_CPU(sd,n) (&(sd)->cpu[0])
	551	#endif
	552
	553	struct sim_state {
	554	sim_cpu cpu[MAX_NR_PROCESSORS];
	555	device *devices;
	556	sim_state_base base;
	557	};
	558
	559	extern void sim_set_profile (int n);
	560	extern void sim_set_profile_size (int n);
	561	extern void sim_board_reset (SIM_DESC sd);
	562
2990a9f4 SC	563	extern const char cycle_to_string (sim_cpu cpu, signed64 t);
2990a9f4 SC	564
e0709f50 AC	565	#endif
	566
	567