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0fda6bd2 | 1 | /* Simulator for Motorola's MCore processor |
3666a048 | 2 | Copyright (C) 1999-2021 Free Software Foundation, Inc. |
2d514e6f SS |
3 | Contributed by Cygnus Solutions. |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
2d514e6f SS |
11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
2d514e6f | 19 | |
6df01ab8 MF |
20 | /* This must come before any other includes. */ |
21 | #include "defs.h" | |
22 | ||
2d514e6f | 23 | #include <signal.h> |
dc049bf4 MF |
24 | #include <stdlib.h> |
25 | #include <string.h> | |
2d514e6f | 26 | #include <sys/param.h> |
4185814e | 27 | #include <unistd.h> |
2d514e6f | 28 | #include "bfd.h" |
df68e12b | 29 | #include "sim/callback.h" |
2d514e6f | 30 | #include "libiberty.h" |
df68e12b | 31 | #include "sim/sim.h" |
2d514e6f | 32 | |
ea6b7543 MF |
33 | #include "sim-main.h" |
34 | #include "sim-base.h" | |
61a0c964 | 35 | #include "sim-syscall.h" |
ea6b7543 MF |
36 | #include "sim-options.h" |
37 | ||
ea6b7543 | 38 | #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) |
2d514e6f SS |
39 | |
40 | ||
feb703b3 MF |
41 | static unsigned long |
42 | mcore_extract_unsigned_integer (unsigned char *addr, int len) | |
2d514e6f SS |
43 | { |
44 | unsigned long retval; | |
45 | unsigned char * p; | |
46 | unsigned char * startaddr = (unsigned char *)addr; | |
47 | unsigned char * endaddr = startaddr + len; | |
ba14f941 | 48 | |
2d514e6f | 49 | if (len > (int) sizeof (unsigned long)) |
feb703b3 | 50 | printf ("That operation is not available on integers of more than %zu bytes.", |
2d514e6f | 51 | sizeof (unsigned long)); |
ba14f941 | 52 | |
2d514e6f SS |
53 | /* Start at the most significant end of the integer, and work towards |
54 | the least significant. */ | |
55 | retval = 0; | |
cd0fc7c3 | 56 | |
63a027a3 NC |
57 | if (! target_big_endian) |
58 | { | |
59 | for (p = endaddr; p > startaddr;) | |
60 | retval = (retval << 8) | * -- p; | |
61 | } | |
62 | else | |
cd0fc7c3 SS |
63 | { |
64 | for (p = startaddr; p < endaddr;) | |
65 | retval = (retval << 8) | * p ++; | |
66 | } | |
ba14f941 | 67 | |
2d514e6f SS |
68 | return retval; |
69 | } | |
70 | ||
feb703b3 MF |
71 | static void |
72 | mcore_store_unsigned_integer (unsigned char *addr, int len, unsigned long val) | |
2d514e6f SS |
73 | { |
74 | unsigned char * p; | |
75 | unsigned char * startaddr = (unsigned char *)addr; | |
76 | unsigned char * endaddr = startaddr + len; | |
cd0fc7c3 | 77 | |
63a027a3 NC |
78 | if (! target_big_endian) |
79 | { | |
80 | for (p = startaddr; p < endaddr;) | |
81 | { | |
82 | * p ++ = val & 0xff; | |
83 | val >>= 8; | |
84 | } | |
85 | } | |
86 | else | |
2d514e6f | 87 | { |
cd0fc7c3 SS |
88 | for (p = endaddr; p > startaddr;) |
89 | { | |
90 | * -- p = val & 0xff; | |
91 | val >>= 8; | |
92 | } | |
2d514e6f SS |
93 | } |
94 | } | |
95 | ||
ea6b7543 | 96 | static int memcycles = 1; |
2d514e6f | 97 | |
7eed1055 MF |
98 | #define gr cpu->active_gregs |
99 | #define cr cpu->regs.cregs | |
100 | #define sr cr[0] | |
101 | #define vbr cr[1] | |
102 | #define esr cr[2] | |
103 | #define fsr cr[3] | |
104 | #define epc cr[4] | |
105 | #define fpc cr[5] | |
106 | #define ss0 cr[6] | |
107 | #define ss1 cr[7] | |
108 | #define ss2 cr[8] | |
109 | #define ss3 cr[9] | |
110 | #define ss4 cr[10] | |
111 | #define gcr cr[11] | |
112 | #define gsr cr[12] | |
2d514e6f SS |
113 | |
114 | /* maniuplate the carry bit */ | |
7eed1055 MF |
115 | #define C_ON() (sr & 1) |
116 | #define C_VALUE() (sr & 1) | |
117 | #define C_OFF() ((sr & 1) == 0) | |
118 | #define SET_C() {sr |= 1;} | |
119 | #define CLR_C() {sr &= 0xfffffffe;} | |
120 | #define NEW_C(v) {CLR_C(); sr |= ((v) & 1);} | |
121 | ||
122 | #define SR_AF() ((sr >> 1) & 1) | |
123 | static void set_active_regs (SIM_CPU *cpu) | |
124 | { | |
125 | if (SR_AF()) | |
126 | cpu->active_gregs = cpu->regs.alt_gregs; | |
127 | else | |
128 | cpu->active_gregs = cpu->regs.gregs; | |
129 | } | |
2d514e6f SS |
130 | |
131 | #define TRAPCODE 1 /* r1 holds which function we want */ | |
132 | #define PARM1 2 /* first parameter */ | |
133 | #define PARM2 3 | |
134 | #define PARM3 4 | |
135 | #define PARM4 5 | |
136 | #define RET1 2 /* register for return values. */ | |
137 | ||
4cd93614 | 138 | /* Default to a 8 Mbyte (== 2^23) memory space. */ |
f63036b8 | 139 | #define DEFAULT_MEMORY_SIZE 0x800000 |
2d514e6f SS |
140 | |
141 | static void | |
7eed1055 | 142 | set_initial_gprs (SIM_CPU *cpu) |
2d514e6f | 143 | { |
2d514e6f | 144 | /* Set up machine just out of reset. */ |
7eed1055 MF |
145 | CPU_PC_SET (cpu, 0); |
146 | sr = 0; | |
ba14f941 | 147 | |
2d514e6f | 148 | /* Clean out the GPRs and alternate GPRs. */ |
7eed1055 MF |
149 | memset (&cpu->regs.gregs, 0, sizeof(cpu->regs.gregs)); |
150 | memset (&cpu->regs.alt_gregs, 0, sizeof(cpu->regs.alt_gregs)); | |
ba14f941 | 151 | |
2d514e6f | 152 | /* Make our register set point to the right place. */ |
7eed1055 | 153 | set_active_regs (cpu); |
ba14f941 | 154 | |
2d514e6f | 155 | /* ABI specifies initial values for these registers. */ |
7eed1055 | 156 | gr[0] = DEFAULT_MEMORY_SIZE - 4; |
ba14f941 | 157 | |
2d514e6f | 158 | /* dac fix, the stack address must be 8-byte aligned! */ |
7eed1055 MF |
159 | gr[0] = gr[0] - gr[0] % 8; |
160 | gr[PARM1] = 0; | |
161 | gr[PARM2] = 0; | |
162 | gr[PARM3] = 0; | |
163 | gr[PARM4] = gr[0]; | |
2d514e6f SS |
164 | } |
165 | ||
767e68f1 MF |
166 | /* Simulate a monitor trap. */ |
167 | ||
2d514e6f | 168 | static void |
7eed1055 | 169 | handle_trap1 (SIM_DESC sd, SIM_CPU *cpu) |
2d514e6f | 170 | { |
767e68f1 | 171 | /* XXX: We don't pass back the actual errno value. */ |
7eed1055 MF |
172 | gr[RET1] = sim_syscall (cpu, gr[TRAPCODE], gr[PARM1], gr[PARM2], gr[PARM3], |
173 | gr[PARM4]); | |
2d514e6f SS |
174 | } |
175 | ||
176 | static void | |
7eed1055 | 177 | process_stub (SIM_DESC sd, SIM_CPU *cpu, int what) |
2d514e6f SS |
178 | { |
179 | /* These values should match those in libgloss/mcore/syscalls.s. */ | |
180 | switch (what) | |
181 | { | |
182 | case 3: /* _read */ | |
cd0fc7c3 | 183 | case 4: /* _write */ |
2d514e6f SS |
184 | case 5: /* _open */ |
185 | case 6: /* _close */ | |
186 | case 10: /* _unlink */ | |
187 | case 19: /* _lseek */ | |
188 | case 43: /* _times */ | |
7eed1055 MF |
189 | gr[TRAPCODE] = what; |
190 | handle_trap1 (sd, cpu); | |
2d514e6f | 191 | break; |
ba14f941 | 192 | |
2d514e6f | 193 | default: |
f63036b8 | 194 | if (STATE_VERBOSE_P (sd)) |
2d514e6f SS |
195 | fprintf (stderr, "Unhandled stub opcode: %d\n", what); |
196 | break; | |
197 | } | |
198 | } | |
199 | ||
200 | static void | |
7eed1055 | 201 | util (SIM_DESC sd, SIM_CPU *cpu, unsigned what) |
2d514e6f SS |
202 | { |
203 | switch (what) | |
204 | { | |
205 | case 0: /* exit */ | |
7eed1055 | 206 | sim_engine_halt (sd, cpu, NULL, cpu->regs.pc, sim_exited, gr[PARM1]); |
2d514e6f SS |
207 | break; |
208 | ||
209 | case 1: /* printf */ | |
f63036b8 MF |
210 | if (STATE_VERBOSE_P (sd)) |
211 | fprintf (stderr, "WARNING: printf unimplemented\n"); | |
2d514e6f | 212 | break; |
ba14f941 | 213 | |
2d514e6f | 214 | case 2: /* scanf */ |
f63036b8 | 215 | if (STATE_VERBOSE_P (sd)) |
2d514e6f SS |
216 | fprintf (stderr, "WARNING: scanf unimplemented\n"); |
217 | break; | |
ba14f941 | 218 | |
2d514e6f | 219 | case 3: /* utime */ |
7eed1055 | 220 | gr[RET1] = cpu->insts; |
2d514e6f SS |
221 | break; |
222 | ||
223 | case 0xFF: | |
7eed1055 | 224 | process_stub (sd, cpu, gr[1]); |
2d514e6f | 225 | break; |
ba14f941 | 226 | |
2d514e6f | 227 | default: |
f63036b8 | 228 | if (STATE_VERBOSE_P (sd)) |
2d514e6f SS |
229 | fprintf (stderr, "Unhandled util code: %x\n", what); |
230 | break; | |
231 | } | |
ba14f941 | 232 | } |
2d514e6f SS |
233 | |
234 | /* For figuring out whether we carried; addc/subc use this. */ | |
235 | static int | |
feb703b3 | 236 | iu_carry (unsigned long a, unsigned long b, int cin) |
2d514e6f SS |
237 | { |
238 | unsigned long x; | |
ba14f941 | 239 | |
2d514e6f SS |
240 | x = (a & 0xffff) + (b & 0xffff) + cin; |
241 | x = (x >> 16) + (a >> 16) + (b >> 16); | |
242 | x >>= 16; | |
243 | ||
244 | return (x != 0); | |
245 | } | |
246 | ||
e53e5aab MF |
247 | /* TODO: Convert to common watchpoints. */ |
248 | #undef WATCHFUNCTIONS | |
2d514e6f SS |
249 | #ifdef WATCHFUNCTIONS |
250 | ||
251 | #define MAXWL 80 | |
252 | word WL[MAXWL]; | |
253 | char * WLstr[MAXWL]; | |
254 | ||
255 | int ENDWL=0; | |
256 | int WLincyc; | |
257 | int WLcyc[MAXWL]; | |
258 | int WLcnts[MAXWL]; | |
259 | int WLmax[MAXWL]; | |
260 | int WLmin[MAXWL]; | |
261 | word WLendpc; | |
262 | int WLbcyc; | |
263 | int WLW; | |
264 | #endif | |
265 | ||
266 | #define RD (inst & 0xF) | |
267 | #define RS ((inst >> 4) & 0xF) | |
268 | #define RX ((inst >> 8) & 0xF) | |
269 | #define IMM5 ((inst >> 4) & 0x1F) | |
270 | #define IMM4 ((inst) & 0xF) | |
271 | ||
7eed1055 MF |
272 | #define rbat(X) sim_core_read_1 (cpu, 0, read_map, X) |
273 | #define rhat(X) sim_core_read_2 (cpu, 0, read_map, X) | |
274 | #define rlat(X) sim_core_read_4 (cpu, 0, read_map, X) | |
275 | #define wbat(X, D) sim_core_write_1 (cpu, 0, write_map, X, D) | |
276 | #define what(X, D) sim_core_write_2 (cpu, 0, write_map, X, D) | |
277 | #define wlat(X, D) sim_core_write_4 (cpu, 0, write_map, X, D) | |
f63036b8 | 278 | |
2d514e6f SS |
279 | static int tracing = 0; |
280 | ||
02962cd9 | 281 | #define ILLEGAL() \ |
7eed1055 | 282 | sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL) |
02962cd9 MF |
283 | |
284 | static void | |
7eed1055 | 285 | step_once (SIM_DESC sd, SIM_CPU *cpu) |
2d514e6f SS |
286 | { |
287 | int needfetch; | |
288 | word ibuf; | |
289 | word pc; | |
290 | unsigned short inst; | |
2d514e6f SS |
291 | int memops; |
292 | int bonus_cycles; | |
293 | int insts; | |
294 | int w; | |
295 | int cycs; | |
e53e5aab | 296 | #ifdef WATCHFUNCTIONS |
2d514e6f | 297 | word WLhash; |
e53e5aab | 298 | #endif |
2d514e6f | 299 | |
7eed1055 | 300 | pc = CPU_PC_GET (cpu); |
2d514e6f | 301 | |
cd0fc7c3 | 302 | /* Fetch the initial instructions that we'll decode. */ |
2d514e6f SS |
303 | ibuf = rlat (pc & 0xFFFFFFFC); |
304 | needfetch = 0; | |
305 | ||
306 | memops = 0; | |
307 | bonus_cycles = 0; | |
308 | insts = 0; | |
ba14f941 | 309 | |
2d514e6f | 310 | /* make our register set point to the right place */ |
7eed1055 | 311 | set_active_regs (cpu); |
ba14f941 | 312 | |
e53e5aab | 313 | #ifdef WATCHFUNCTIONS |
2d514e6f SS |
314 | /* make a hash to speed exec loop, hope it's nonzero */ |
315 | WLhash = 0xFFFFFFFF; | |
316 | ||
317 | for (w = 1; w <= ENDWL; w++) | |
318 | WLhash = WLhash & WL[w]; | |
e53e5aab | 319 | #endif |
2d514e6f | 320 | |
02962cd9 | 321 | /* TODO: Unindent this block. */ |
2d514e6f | 322 | { |
cd0fc7c3 | 323 | word oldpc; |
ba14f941 | 324 | |
2d514e6f | 325 | insts ++; |
ba14f941 | 326 | |
2d514e6f SS |
327 | if (pc & 02) |
328 | { | |
63a027a3 NC |
329 | if (! target_big_endian) |
330 | inst = ibuf >> 16; | |
331 | else | |
cd0fc7c3 | 332 | inst = ibuf & 0xFFFF; |
2d514e6f SS |
333 | needfetch = 1; |
334 | } | |
335 | else | |
336 | { | |
63a027a3 NC |
337 | if (! target_big_endian) |
338 | inst = ibuf & 0xFFFF; | |
339 | else | |
cd0fc7c3 | 340 | inst = ibuf >> 16; |
2d514e6f SS |
341 | } |
342 | ||
343 | #ifdef WATCHFUNCTIONS | |
344 | /* now scan list of watch addresses, if match, count it and | |
345 | note return address and count cycles until pc=return address */ | |
ba14f941 | 346 | |
2d514e6f SS |
347 | if ((WLincyc == 1) && (pc == WLendpc)) |
348 | { | |
7eed1055 | 349 | cycs = (cpu->cycles + (insts + bonus_cycles + |
2d514e6f | 350 | (memops * memcycles)) - WLbcyc); |
ba14f941 | 351 | |
2d514e6f SS |
352 | if (WLcnts[WLW] == 1) |
353 | { | |
354 | WLmax[WLW] = cycs; | |
355 | WLmin[WLW] = cycs; | |
356 | WLcyc[WLW] = 0; | |
357 | } | |
ba14f941 | 358 | |
2d514e6f SS |
359 | if (cycs > WLmax[WLW]) |
360 | { | |
361 | WLmax[WLW] = cycs; | |
362 | } | |
ba14f941 | 363 | |
2d514e6f SS |
364 | if (cycs < WLmin[WLW]) |
365 | { | |
366 | WLmin[WLW] = cycs; | |
367 | } | |
ba14f941 | 368 | |
2d514e6f SS |
369 | WLcyc[WLW] += cycs; |
370 | WLincyc = 0; | |
371 | WLendpc = 0; | |
ba14f941 | 372 | } |
2d514e6f | 373 | |
cd0fc7c3 | 374 | /* Optimize with a hash to speed loop. */ |
2d514e6f SS |
375 | if (WLincyc == 0) |
376 | { | |
377 | if ((WLhash == 0) || ((WLhash & pc) != 0)) | |
378 | { | |
379 | for (w=1; w <= ENDWL; w++) | |
380 | { | |
381 | if (pc == WL[w]) | |
382 | { | |
383 | WLcnts[w]++; | |
7eed1055 | 384 | WLbcyc = cpu->cycles + insts |
2d514e6f | 385 | + bonus_cycles + (memops * memcycles); |
7eed1055 | 386 | WLendpc = gr[15]; |
2d514e6f SS |
387 | WLincyc = 1; |
388 | WLW = w; | |
389 | break; | |
390 | } | |
391 | } | |
392 | } | |
393 | } | |
394 | #endif | |
395 | ||
396 | if (tracing) | |
43236bb2 | 397 | fprintf (stderr, "%.4lx: inst = %.4x ", pc, inst); |
cd0fc7c3 SS |
398 | |
399 | oldpc = pc; | |
ba14f941 | 400 | |
2d514e6f | 401 | pc += 2; |
ba14f941 | 402 | |
2d514e6f SS |
403 | switch (inst >> 8) |
404 | { | |
405 | case 0x00: | |
406 | switch RS | |
407 | { | |
408 | case 0x0: | |
409 | switch RD | |
410 | { | |
411 | case 0x0: /* bkpt */ | |
9e086581 | 412 | pc -= 2; |
7eed1055 | 413 | sim_engine_halt (sd, cpu, NULL, pc - 2, |
02962cd9 | 414 | sim_stopped, SIM_SIGTRAP); |
2d514e6f | 415 | break; |
ba14f941 | 416 | |
2d514e6f SS |
417 | case 0x1: /* sync */ |
418 | break; | |
ba14f941 | 419 | |
2d514e6f | 420 | case 0x2: /* rte */ |
7eed1055 MF |
421 | pc = epc; |
422 | sr = esr; | |
2d514e6f | 423 | needfetch = 1; |
ba14f941 | 424 | |
7eed1055 | 425 | set_active_regs (cpu); |
2d514e6f SS |
426 | break; |
427 | ||
428 | case 0x3: /* rfi */ | |
7eed1055 MF |
429 | pc = fpc; |
430 | sr = fsr; | |
2d514e6f SS |
431 | needfetch = 1; |
432 | ||
7eed1055 | 433 | set_active_regs (cpu); |
2d514e6f | 434 | break; |
ba14f941 | 435 | |
2d514e6f | 436 | case 0x4: /* stop */ |
f63036b8 | 437 | if (STATE_VERBOSE_P (sd)) |
2d514e6f SS |
438 | fprintf (stderr, "WARNING: stop unimplemented\n"); |
439 | break; | |
ba14f941 | 440 | |
2d514e6f | 441 | case 0x5: /* wait */ |
f63036b8 | 442 | if (STATE_VERBOSE_P (sd)) |
2d514e6f SS |
443 | fprintf (stderr, "WARNING: wait unimplemented\n"); |
444 | break; | |
ba14f941 | 445 | |
2d514e6f | 446 | case 0x6: /* doze */ |
f63036b8 | 447 | if (STATE_VERBOSE_P (sd)) |
cd0fc7c3 | 448 | fprintf (stderr, "WARNING: doze unimplemented\n"); |
2d514e6f | 449 | break; |
ba14f941 | 450 | |
2d514e6f | 451 | case 0x7: |
02962cd9 | 452 | ILLEGAL (); /* illegal */ |
2d514e6f | 453 | break; |
ba14f941 | 454 | |
2d514e6f SS |
455 | case 0x8: /* trap 0 */ |
456 | case 0xA: /* trap 2 */ | |
457 | case 0xB: /* trap 3 */ | |
7eed1055 | 458 | sim_engine_halt (sd, cpu, NULL, pc, |
02962cd9 | 459 | sim_stopped, SIM_SIGTRAP); |
2d514e6f | 460 | break; |
ba14f941 | 461 | |
2d514e6f SS |
462 | case 0xC: /* trap 4 */ |
463 | case 0xD: /* trap 5 */ | |
464 | case 0xE: /* trap 6 */ | |
02962cd9 | 465 | ILLEGAL (); /* illegal */ |
2d514e6f | 466 | break; |
ba14f941 | 467 | |
2d514e6f | 468 | case 0xF: /* trap 7 */ |
7eed1055 | 469 | sim_engine_halt (sd, cpu, NULL, pc, /* integer div-by-0 */ |
02962cd9 | 470 | sim_stopped, SIM_SIGTRAP); |
2d514e6f | 471 | break; |
ba14f941 | 472 | |
2d514e6f | 473 | case 0x9: /* trap 1 */ |
7eed1055 | 474 | handle_trap1 (sd, cpu); |
2d514e6f SS |
475 | break; |
476 | } | |
477 | break; | |
ba14f941 | 478 | |
2d514e6f | 479 | case 0x1: |
02962cd9 | 480 | ILLEGAL (); /* illegal */ |
2d514e6f | 481 | break; |
ba14f941 | 482 | |
2d514e6f | 483 | case 0x2: /* mvc */ |
7eed1055 | 484 | gr[RD] = C_VALUE(); |
2d514e6f SS |
485 | break; |
486 | case 0x3: /* mvcv */ | |
7eed1055 | 487 | gr[RD] = C_OFF(); |
2d514e6f SS |
488 | break; |
489 | case 0x4: /* ldq */ | |
490 | { | |
7eed1055 | 491 | word addr = gr[RD]; |
2d514e6f | 492 | int regno = 4; /* always r4-r7 */ |
ba14f941 | 493 | |
2d514e6f SS |
494 | bonus_cycles++; |
495 | memops += 4; | |
496 | do | |
497 | { | |
7eed1055 | 498 | gr[regno] = rlat (addr); |
2d514e6f SS |
499 | addr += 4; |
500 | regno++; | |
501 | } | |
502 | while ((regno&0x3) != 0); | |
503 | } | |
504 | break; | |
505 | case 0x5: /* stq */ | |
506 | { | |
7eed1055 | 507 | word addr = gr[RD]; |
2d514e6f | 508 | int regno = 4; /* always r4-r7 */ |
ba14f941 | 509 | |
2d514e6f SS |
510 | memops += 4; |
511 | bonus_cycles++; | |
512 | do | |
513 | { | |
7eed1055 | 514 | wlat (addr, gr[regno]); |
2d514e6f SS |
515 | addr += 4; |
516 | regno++; | |
517 | } | |
518 | while ((regno & 0x3) != 0); | |
519 | } | |
520 | break; | |
521 | case 0x6: /* ldm */ | |
522 | { | |
7eed1055 | 523 | word addr = gr[0]; |
2d514e6f | 524 | int regno = RD; |
ba14f941 | 525 | |
2d514e6f SS |
526 | /* bonus cycle is really only needed if |
527 | the next insn shifts the last reg loaded. | |
ba14f941 | 528 | |
2d514e6f SS |
529 | bonus_cycles++; |
530 | */ | |
531 | memops += 16-regno; | |
532 | while (regno <= 0xF) | |
533 | { | |
7eed1055 | 534 | gr[regno] = rlat (addr); |
2d514e6f SS |
535 | addr += 4; |
536 | regno++; | |
537 | } | |
538 | } | |
539 | break; | |
540 | case 0x7: /* stm */ | |
541 | { | |
7eed1055 | 542 | word addr = gr[0]; |
2d514e6f | 543 | int regno = RD; |
ba14f941 | 544 | |
2d514e6f SS |
545 | /* this should be removed! */ |
546 | /* bonus_cycles ++; */ | |
547 | ||
548 | memops += 16 - regno; | |
549 | while (regno <= 0xF) | |
550 | { | |
7eed1055 | 551 | wlat (addr, gr[regno]); |
2d514e6f SS |
552 | addr += 4; |
553 | regno++; | |
554 | } | |
555 | } | |
556 | break; | |
557 | ||
558 | case 0x8: /* dect */ | |
7eed1055 | 559 | gr[RD] -= C_VALUE(); |
2d514e6f SS |
560 | break; |
561 | case 0x9: /* decf */ | |
7eed1055 | 562 | gr[RD] -= C_OFF(); |
2d514e6f SS |
563 | break; |
564 | case 0xA: /* inct */ | |
7eed1055 | 565 | gr[RD] += C_VALUE(); |
2d514e6f SS |
566 | break; |
567 | case 0xB: /* incf */ | |
7eed1055 | 568 | gr[RD] += C_OFF(); |
2d514e6f SS |
569 | break; |
570 | case 0xC: /* jmp */ | |
7eed1055 | 571 | pc = gr[RD]; |
392a587b | 572 | if (tracing && RD == 15) |
43236bb2 | 573 | fprintf (stderr, "Func return, r2 = %lxx, r3 = %lx\n", |
7eed1055 | 574 | gr[2], gr[3]); |
2d514e6f SS |
575 | bonus_cycles++; |
576 | needfetch = 1; | |
577 | break; | |
578 | case 0xD: /* jsr */ | |
7eed1055 MF |
579 | gr[15] = pc; |
580 | pc = gr[RD]; | |
2d514e6f SS |
581 | bonus_cycles++; |
582 | needfetch = 1; | |
583 | break; | |
584 | case 0xE: /* ff1 */ | |
585 | { | |
586 | word tmp, i; | |
7eed1055 | 587 | tmp = gr[RD]; |
2d514e6f SS |
588 | for (i = 0; !(tmp & 0x80000000) && i < 32; i++) |
589 | tmp <<= 1; | |
7eed1055 | 590 | gr[RD] = i; |
2d514e6f SS |
591 | } |
592 | break; | |
593 | case 0xF: /* brev */ | |
594 | { | |
595 | word tmp; | |
7eed1055 | 596 | tmp = gr[RD]; |
2d514e6f SS |
597 | tmp = ((tmp & 0xaaaaaaaa) >> 1) | ((tmp & 0x55555555) << 1); |
598 | tmp = ((tmp & 0xcccccccc) >> 2) | ((tmp & 0x33333333) << 2); | |
599 | tmp = ((tmp & 0xf0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f) << 4); | |
600 | tmp = ((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8); | |
7eed1055 | 601 | gr[RD] = ((tmp & 0xffff0000) >> 16) | ((tmp & 0x0000ffff) << 16); |
2d514e6f SS |
602 | } |
603 | break; | |
604 | } | |
605 | break; | |
606 | case 0x01: | |
607 | switch RS | |
608 | { | |
ba14f941 | 609 | case 0x0: /* xtrb3 */ |
7eed1055 MF |
610 | gr[1] = (gr[RD]) & 0xFF; |
611 | NEW_C (gr[RD] != 0); | |
2d514e6f SS |
612 | break; |
613 | case 0x1: /* xtrb2 */ | |
7eed1055 MF |
614 | gr[1] = (gr[RD]>>8) & 0xFF; |
615 | NEW_C (gr[RD] != 0); | |
2d514e6f SS |
616 | break; |
617 | case 0x2: /* xtrb1 */ | |
7eed1055 MF |
618 | gr[1] = (gr[RD]>>16) & 0xFF; |
619 | NEW_C (gr[RD] != 0); | |
2d514e6f SS |
620 | break; |
621 | case 0x3: /* xtrb0 */ | |
7eed1055 MF |
622 | gr[1] = (gr[RD]>>24) & 0xFF; |
623 | NEW_C (gr[RD] != 0); | |
2d514e6f SS |
624 | break; |
625 | case 0x4: /* zextb */ | |
7eed1055 | 626 | gr[RD] &= 0x000000FF; |
2d514e6f SS |
627 | break; |
628 | case 0x5: /* sextb */ | |
629 | { | |
630 | long tmp; | |
7eed1055 | 631 | tmp = gr[RD]; |
2d514e6f SS |
632 | tmp <<= 24; |
633 | tmp >>= 24; | |
7eed1055 | 634 | gr[RD] = tmp; |
2d514e6f SS |
635 | } |
636 | break; | |
637 | case 0x6: /* zexth */ | |
7eed1055 | 638 | gr[RD] &= 0x0000FFFF; |
2d514e6f SS |
639 | break; |
640 | case 0x7: /* sexth */ | |
641 | { | |
642 | long tmp; | |
7eed1055 | 643 | tmp = gr[RD]; |
2d514e6f SS |
644 | tmp <<= 16; |
645 | tmp >>= 16; | |
7eed1055 | 646 | gr[RD] = tmp; |
2d514e6f SS |
647 | } |
648 | break; | |
ba14f941 | 649 | case 0x8: /* declt */ |
7eed1055 MF |
650 | --gr[RD]; |
651 | NEW_C ((long)gr[RD] < 0); | |
2d514e6f SS |
652 | break; |
653 | case 0x9: /* tstnbz */ | |
654 | { | |
7eed1055 | 655 | word tmp = gr[RD]; |
2d514e6f SS |
656 | NEW_C ((tmp & 0xFF000000) != 0 && |
657 | (tmp & 0x00FF0000) != 0 && (tmp & 0x0000FF00) != 0 && | |
658 | (tmp & 0x000000FF) != 0); | |
659 | } | |
ba14f941 | 660 | break; |
2d514e6f | 661 | case 0xA: /* decgt */ |
7eed1055 MF |
662 | --gr[RD]; |
663 | NEW_C ((long)gr[RD] > 0); | |
2d514e6f SS |
664 | break; |
665 | case 0xB: /* decne */ | |
7eed1055 MF |
666 | --gr[RD]; |
667 | NEW_C ((long)gr[RD] != 0); | |
2d514e6f SS |
668 | break; |
669 | case 0xC: /* clrt */ | |
670 | if (C_ON()) | |
7eed1055 | 671 | gr[RD] = 0; |
2d514e6f SS |
672 | break; |
673 | case 0xD: /* clrf */ | |
674 | if (C_OFF()) | |
7eed1055 | 675 | gr[RD] = 0; |
2d514e6f SS |
676 | break; |
677 | case 0xE: /* abs */ | |
7eed1055 MF |
678 | if (gr[RD] & 0x80000000) |
679 | gr[RD] = ~gr[RD] + 1; | |
2d514e6f SS |
680 | break; |
681 | case 0xF: /* not */ | |
7eed1055 | 682 | gr[RD] = ~gr[RD]; |
2d514e6f SS |
683 | break; |
684 | } | |
685 | break; | |
686 | case 0x02: /* movt */ | |
687 | if (C_ON()) | |
7eed1055 | 688 | gr[RD] = gr[RS]; |
2d514e6f SS |
689 | break; |
690 | case 0x03: /* mult */ | |
691 | /* consume 2 bits per cycle from rs, until rs is 0 */ | |
692 | { | |
7eed1055 | 693 | unsigned int t = gr[RS]; |
2d514e6f | 694 | int ticks; |
ba14f941 | 695 | for (ticks = 0; t != 0 ; t >>= 2) |
2d514e6f SS |
696 | ticks++; |
697 | bonus_cycles += ticks; | |
698 | } | |
699 | bonus_cycles += 2; /* min. is 3, so add 2, plus ticks above */ | |
392a587b | 700 | if (tracing) |
43236bb2 | 701 | fprintf (stderr, " mult %lx by %lx to give %lx", |
7eed1055 MF |
702 | gr[RD], gr[RS], gr[RD] * gr[RS]); |
703 | gr[RD] = gr[RD] * gr[RS]; | |
2d514e6f SS |
704 | break; |
705 | case 0x04: /* loopt */ | |
706 | if (C_ON()) | |
707 | { | |
708 | pc += (IMM4 << 1) - 32; | |
709 | bonus_cycles ++; | |
710 | needfetch = 1; | |
711 | } | |
7eed1055 MF |
712 | --gr[RS]; /* not RD! */ |
713 | NEW_C (((long)gr[RS]) > 0); | |
ba14f941 | 714 | break; |
2d514e6f | 715 | case 0x05: /* subu */ |
7eed1055 | 716 | gr[RD] -= gr[RS]; |
2d514e6f SS |
717 | break; |
718 | case 0x06: /* addc */ | |
719 | { | |
720 | unsigned long tmp, a, b; | |
7eed1055 MF |
721 | a = gr[RD]; |
722 | b = gr[RS]; | |
723 | gr[RD] = a + b + C_VALUE (); | |
2d514e6f SS |
724 | tmp = iu_carry (a, b, C_VALUE ()); |
725 | NEW_C (tmp); | |
726 | } | |
727 | break; | |
728 | case 0x07: /* subc */ | |
729 | { | |
730 | unsigned long tmp, a, b; | |
7eed1055 MF |
731 | a = gr[RD]; |
732 | b = gr[RS]; | |
733 | gr[RD] = a - b + C_VALUE () - 1; | |
2d514e6f SS |
734 | tmp = iu_carry (a,~b, C_VALUE ()); |
735 | NEW_C (tmp); | |
736 | } | |
737 | break; | |
738 | case 0x08: /* illegal */ | |
739 | case 0x09: /* illegal*/ | |
02962cd9 | 740 | ILLEGAL (); |
2d514e6f SS |
741 | break; |
742 | case 0x0A: /* movf */ | |
743 | if (C_OFF()) | |
7eed1055 | 744 | gr[RD] = gr[RS]; |
2d514e6f SS |
745 | break; |
746 | case 0x0B: /* lsr */ | |
ba14f941 | 747 | { |
2d514e6f | 748 | unsigned long dst, src; |
7eed1055 MF |
749 | dst = gr[RD]; |
750 | src = gr[RS]; | |
c5394b80 JM |
751 | /* We must not rely solely upon the native shift operations, since they |
752 | may not match the M*Core's behaviour on boundary conditions. */ | |
753 | dst = src > 31 ? 0 : dst >> src; | |
7eed1055 | 754 | gr[RD] = dst; |
2d514e6f SS |
755 | } |
756 | break; | |
757 | case 0x0C: /* cmphs */ | |
7eed1055 MF |
758 | NEW_C ((unsigned long )gr[RD] >= |
759 | (unsigned long)gr[RS]); | |
2d514e6f SS |
760 | break; |
761 | case 0x0D: /* cmplt */ | |
7eed1055 | 762 | NEW_C ((long)gr[RD] < (long)gr[RS]); |
2d514e6f SS |
763 | break; |
764 | case 0x0E: /* tst */ | |
7eed1055 | 765 | NEW_C ((gr[RD] & gr[RS]) != 0); |
2d514e6f SS |
766 | break; |
767 | case 0x0F: /* cmpne */ | |
7eed1055 | 768 | NEW_C (gr[RD] != gr[RS]); |
2d514e6f SS |
769 | break; |
770 | case 0x10: case 0x11: /* mfcr */ | |
771 | { | |
772 | unsigned r; | |
773 | r = IMM5; | |
774 | if (r <= LAST_VALID_CREG) | |
7eed1055 | 775 | gr[RD] = cr[r]; |
2d514e6f | 776 | else |
02962cd9 | 777 | ILLEGAL (); |
2d514e6f SS |
778 | } |
779 | break; | |
780 | ||
781 | case 0x12: /* mov */ | |
7eed1055 | 782 | gr[RD] = gr[RS]; |
392a587b | 783 | if (tracing) |
7eed1055 | 784 | fprintf (stderr, "MOV %lx into reg %d", gr[RD], RD); |
2d514e6f SS |
785 | break; |
786 | ||
787 | case 0x13: /* bgenr */ | |
7eed1055 MF |
788 | if (gr[RS] & 0x20) |
789 | gr[RD] = 0; | |
2d514e6f | 790 | else |
7eed1055 | 791 | gr[RD] = 1 << (gr[RS] & 0x1F); |
2d514e6f SS |
792 | break; |
793 | ||
794 | case 0x14: /* rsub */ | |
7eed1055 | 795 | gr[RD] = gr[RS] - gr[RD]; |
2d514e6f SS |
796 | break; |
797 | ||
798 | case 0x15: /* ixw */ | |
7eed1055 | 799 | gr[RD] += gr[RS]<<2; |
2d514e6f SS |
800 | break; |
801 | ||
802 | case 0x16: /* and */ | |
7eed1055 | 803 | gr[RD] &= gr[RS]; |
2d514e6f SS |
804 | break; |
805 | ||
806 | case 0x17: /* xor */ | |
7eed1055 | 807 | gr[RD] ^= gr[RS]; |
2d514e6f SS |
808 | break; |
809 | ||
810 | case 0x18: case 0x19: /* mtcr */ | |
811 | { | |
812 | unsigned r; | |
813 | r = IMM5; | |
814 | if (r <= LAST_VALID_CREG) | |
7eed1055 | 815 | cr[r] = gr[RD]; |
2d514e6f | 816 | else |
02962cd9 | 817 | ILLEGAL (); |
ba14f941 | 818 | |
2d514e6f | 819 | /* we might have changed register sets... */ |
7eed1055 | 820 | set_active_regs (cpu); |
2d514e6f SS |
821 | } |
822 | break; | |
823 | ||
824 | case 0x1A: /* asr */ | |
c5394b80 JM |
825 | /* We must not rely solely upon the native shift operations, since they |
826 | may not match the M*Core's behaviour on boundary conditions. */ | |
7eed1055 MF |
827 | if (gr[RS] > 30) |
828 | gr[RD] = ((long) gr[RD]) < 0 ? -1 : 0; | |
c5394b80 | 829 | else |
7eed1055 | 830 | gr[RD] = (long) gr[RD] >> gr[RS]; |
2d514e6f SS |
831 | break; |
832 | ||
833 | case 0x1B: /* lsl */ | |
c5394b80 JM |
834 | /* We must not rely solely upon the native shift operations, since they |
835 | may not match the M*Core's behaviour on boundary conditions. */ | |
7eed1055 | 836 | gr[RD] = gr[RS] > 31 ? 0 : gr[RD] << gr[RS]; |
2d514e6f SS |
837 | break; |
838 | ||
839 | case 0x1C: /* addu */ | |
7eed1055 | 840 | gr[RD] += gr[RS]; |
2d514e6f SS |
841 | break; |
842 | ||
843 | case 0x1D: /* ixh */ | |
7eed1055 | 844 | gr[RD] += gr[RS] << 1; |
2d514e6f SS |
845 | break; |
846 | ||
847 | case 0x1E: /* or */ | |
7eed1055 | 848 | gr[RD] |= gr[RS]; |
2d514e6f SS |
849 | break; |
850 | ||
851 | case 0x1F: /* andn */ | |
7eed1055 | 852 | gr[RD] &= ~gr[RS]; |
2d514e6f SS |
853 | break; |
854 | case 0x20: case 0x21: /* addi */ | |
7eed1055 MF |
855 | gr[RD] = |
856 | gr[RD] + (IMM5 + 1); | |
2d514e6f SS |
857 | break; |
858 | case 0x22: case 0x23: /* cmplti */ | |
859 | { | |
860 | int tmp = (IMM5 + 1); | |
7eed1055 | 861 | if (gr[RD] < tmp) |
2d514e6f SS |
862 | { |
863 | SET_C(); | |
864 | } | |
865 | else | |
866 | { | |
867 | CLR_C(); | |
868 | } | |
869 | } | |
870 | break; | |
871 | case 0x24: case 0x25: /* subi */ | |
7eed1055 MF |
872 | gr[RD] = |
873 | gr[RD] - (IMM5 + 1); | |
2d514e6f SS |
874 | break; |
875 | case 0x26: case 0x27: /* illegal */ | |
02962cd9 | 876 | ILLEGAL (); |
2d514e6f SS |
877 | break; |
878 | case 0x28: case 0x29: /* rsubi */ | |
7eed1055 MF |
879 | gr[RD] = |
880 | IMM5 - gr[RD]; | |
2d514e6f SS |
881 | break; |
882 | case 0x2A: case 0x2B: /* cmpnei */ | |
7eed1055 | 883 | if (gr[RD] != IMM5) |
2d514e6f SS |
884 | { |
885 | SET_C(); | |
886 | } | |
887 | else | |
888 | { | |
889 | CLR_C(); | |
890 | } | |
891 | break; | |
ba14f941 | 892 | |
2d514e6f SS |
893 | case 0x2C: case 0x2D: /* bmaski, divu */ |
894 | { | |
895 | unsigned imm = IMM5; | |
ba14f941 | 896 | |
2d514e6f SS |
897 | if (imm == 1) |
898 | { | |
899 | int exe; | |
900 | int rxnlz, r1nlz; | |
901 | unsigned int rx, r1; | |
902 | ||
7eed1055 MF |
903 | rx = gr[RD]; |
904 | r1 = gr[1]; | |
2d514e6f SS |
905 | exe = 0; |
906 | ||
907 | /* unsigned divide */ | |
7eed1055 | 908 | gr[RD] = (word) ((unsigned int) gr[RD] / (unsigned int)gr[1] ); |
ba14f941 | 909 | |
2d514e6f SS |
910 | /* compute bonus_cycles for divu */ |
911 | for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32); r1nlz ++) | |
912 | r1 = r1 << 1; | |
913 | ||
914 | for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32); rxnlz ++) | |
915 | rx = rx << 1; | |
916 | ||
917 | if (r1nlz < rxnlz) | |
918 | exe += 4; | |
919 | else | |
920 | exe += 5 + r1nlz - rxnlz; | |
921 | ||
922 | if (exe >= (2 * memcycles - 1)) | |
923 | { | |
924 | bonus_cycles += exe - (2 * memcycles) + 1; | |
925 | } | |
926 | } | |
927 | else if (imm == 0 || imm >= 8) | |
928 | { | |
929 | /* bmaski */ | |
930 | if (imm == 0) | |
7eed1055 | 931 | gr[RD] = -1; |
2d514e6f | 932 | else |
7eed1055 | 933 | gr[RD] = (1 << imm) - 1; |
2d514e6f SS |
934 | } |
935 | else | |
936 | { | |
937 | /* illegal */ | |
02962cd9 | 938 | ILLEGAL (); |
2d514e6f SS |
939 | } |
940 | } | |
941 | break; | |
942 | case 0x2E: case 0x2F: /* andi */ | |
7eed1055 | 943 | gr[RD] = gr[RD] & IMM5; |
2d514e6f SS |
944 | break; |
945 | case 0x30: case 0x31: /* bclri */ | |
7eed1055 | 946 | gr[RD] = gr[RD] & ~(1<<IMM5); |
2d514e6f SS |
947 | break; |
948 | case 0x32: case 0x33: /* bgeni, divs */ | |
949 | { | |
950 | unsigned imm = IMM5; | |
951 | if (imm == 1) | |
952 | { | |
953 | int exe,sc; | |
954 | int rxnlz, r1nlz; | |
955 | signed int rx, r1; | |
ba14f941 | 956 | |
2d514e6f | 957 | /* compute bonus_cycles for divu */ |
7eed1055 MF |
958 | rx = gr[RD]; |
959 | r1 = gr[1]; | |
2d514e6f | 960 | exe = 0; |
ba14f941 | 961 | |
2d514e6f SS |
962 | if (((rx < 0) && (r1 > 0)) || ((rx >= 0) && (r1 < 0))) |
963 | sc = 1; | |
964 | else | |
965 | sc = 0; | |
ba14f941 | 966 | |
2d514e6f SS |
967 | rx = abs (rx); |
968 | r1 = abs (r1); | |
ba14f941 | 969 | |
2d514e6f | 970 | /* signed divide, general registers are of type int, so / op is OK */ |
7eed1055 | 971 | gr[RD] = gr[RD] / gr[1]; |
ba14f941 | 972 | |
2d514e6f SS |
973 | for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32) ; r1nlz ++ ) |
974 | r1 = r1 << 1; | |
ba14f941 | 975 | |
2d514e6f SS |
976 | for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32) ; rxnlz ++ ) |
977 | rx = rx << 1; | |
ba14f941 | 978 | |
2d514e6f SS |
979 | if (r1nlz < rxnlz) |
980 | exe += 5; | |
981 | else | |
982 | exe += 6 + r1nlz - rxnlz + sc; | |
ba14f941 | 983 | |
2d514e6f SS |
984 | if (exe >= (2 * memcycles - 1)) |
985 | { | |
986 | bonus_cycles += exe - (2 * memcycles) + 1; | |
987 | } | |
988 | } | |
989 | else if (imm >= 7) | |
990 | { | |
991 | /* bgeni */ | |
7eed1055 | 992 | gr[RD] = (1 << IMM5); |
2d514e6f SS |
993 | } |
994 | else | |
995 | { | |
996 | /* illegal */ | |
02962cd9 | 997 | ILLEGAL (); |
2d514e6f SS |
998 | } |
999 | break; | |
1000 | } | |
1001 | case 0x34: case 0x35: /* bseti */ | |
7eed1055 | 1002 | gr[RD] = gr[RD] | (1 << IMM5); |
2d514e6f SS |
1003 | break; |
1004 | case 0x36: case 0x37: /* btsti */ | |
7eed1055 | 1005 | NEW_C (gr[RD] >> IMM5); |
2d514e6f SS |
1006 | break; |
1007 | case 0x38: case 0x39: /* xsr, rotli */ | |
1008 | { | |
1009 | unsigned imm = IMM5; | |
7eed1055 | 1010 | unsigned long tmp = gr[RD]; |
2d514e6f SS |
1011 | if (imm == 0) |
1012 | { | |
1013 | word cbit; | |
1014 | cbit = C_VALUE(); | |
1015 | NEW_C (tmp); | |
7eed1055 | 1016 | gr[RD] = (cbit << 31) | (tmp >> 1); |
2d514e6f SS |
1017 | } |
1018 | else | |
7eed1055 | 1019 | gr[RD] = (tmp << imm) | (tmp >> (32 - imm)); |
2d514e6f SS |
1020 | } |
1021 | break; | |
1022 | case 0x3A: case 0x3B: /* asrc, asri */ | |
1023 | { | |
1024 | unsigned imm = IMM5; | |
7eed1055 | 1025 | long tmp = gr[RD]; |
2d514e6f SS |
1026 | if (imm == 0) |
1027 | { | |
1028 | NEW_C (tmp); | |
7eed1055 | 1029 | gr[RD] = tmp >> 1; |
2d514e6f SS |
1030 | } |
1031 | else | |
7eed1055 | 1032 | gr[RD] = tmp >> imm; |
2d514e6f SS |
1033 | } |
1034 | break; | |
1035 | case 0x3C: case 0x3D: /* lslc, lsli */ | |
1036 | { | |
1037 | unsigned imm = IMM5; | |
7eed1055 | 1038 | unsigned long tmp = gr[RD]; |
2d514e6f SS |
1039 | if (imm == 0) |
1040 | { | |
1041 | NEW_C (tmp >> 31); | |
7eed1055 | 1042 | gr[RD] = tmp << 1; |
2d514e6f SS |
1043 | } |
1044 | else | |
7eed1055 | 1045 | gr[RD] = tmp << imm; |
2d514e6f SS |
1046 | } |
1047 | break; | |
1048 | case 0x3E: case 0x3F: /* lsrc, lsri */ | |
1049 | { | |
1050 | unsigned imm = IMM5; | |
7eed1055 | 1051 | unsigned long tmp = gr[RD]; |
2d514e6f SS |
1052 | if (imm == 0) |
1053 | { | |
1054 | NEW_C (tmp); | |
7eed1055 | 1055 | gr[RD] = tmp >> 1; |
2d514e6f SS |
1056 | } |
1057 | else | |
7eed1055 | 1058 | gr[RD] = tmp >> imm; |
2d514e6f SS |
1059 | } |
1060 | break; | |
1061 | case 0x40: case 0x41: case 0x42: case 0x43: | |
1062 | case 0x44: case 0x45: case 0x46: case 0x47: | |
1063 | case 0x48: case 0x49: case 0x4A: case 0x4B: | |
1064 | case 0x4C: case 0x4D: case 0x4E: case 0x4F: | |
02962cd9 | 1065 | ILLEGAL (); |
2d514e6f SS |
1066 | break; |
1067 | case 0x50: | |
7eed1055 | 1068 | util (sd, cpu, inst & 0xFF); |
2d514e6f SS |
1069 | break; |
1070 | case 0x51: case 0x52: case 0x53: | |
1071 | case 0x54: case 0x55: case 0x56: case 0x57: | |
1072 | case 0x58: case 0x59: case 0x5A: case 0x5B: | |
1073 | case 0x5C: case 0x5D: case 0x5E: case 0x5F: | |
02962cd9 | 1074 | ILLEGAL (); |
2d514e6f SS |
1075 | break; |
1076 | case 0x60: case 0x61: case 0x62: case 0x63: /* movi */ | |
1077 | case 0x64: case 0x65: case 0x66: case 0x67: | |
7eed1055 | 1078 | gr[RD] = (inst >> 4) & 0x7F; |
2d514e6f SS |
1079 | break; |
1080 | case 0x68: case 0x69: case 0x6A: case 0x6B: | |
1081 | case 0x6C: case 0x6D: case 0x6E: case 0x6F: /* illegal */ | |
02962cd9 | 1082 | ILLEGAL (); |
2d514e6f SS |
1083 | break; |
1084 | case 0x71: case 0x72: case 0x73: | |
1085 | case 0x74: case 0x75: case 0x76: case 0x77: | |
1086 | case 0x78: case 0x79: case 0x7A: case 0x7B: | |
1087 | case 0x7C: case 0x7D: case 0x7E: /* lrw */ | |
7eed1055 | 1088 | gr[RX] = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); |
2d514e6f | 1089 | if (tracing) |
43236bb2 | 1090 | fprintf (stderr, "LRW of 0x%x from 0x%lx to reg %d", |
2d514e6f SS |
1091 | rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC), |
1092 | (pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC, RX); | |
1093 | memops++; | |
1094 | break; | |
1095 | case 0x7F: /* jsri */ | |
7eed1055 | 1096 | gr[15] = pc; |
392a587b | 1097 | if (tracing) |
43236bb2 MF |
1098 | fprintf (stderr, |
1099 | "func call: r2 = %lx r3 = %lx r4 = %lx r5 = %lx r6 = %lx r7 = %lx\n", | |
7eed1055 | 1100 | gr[2], gr[3], gr[4], gr[5], gr[6], gr[7]); |
2d514e6f SS |
1101 | case 0x70: /* jmpi */ |
1102 | pc = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); | |
1103 | memops++; | |
1104 | bonus_cycles++; | |
1105 | needfetch = 1; | |
1106 | break; | |
1107 | ||
1108 | case 0x80: case 0x81: case 0x82: case 0x83: | |
1109 | case 0x84: case 0x85: case 0x86: case 0x87: | |
1110 | case 0x88: case 0x89: case 0x8A: case 0x8B: | |
1111 | case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */ | |
7eed1055 | 1112 | gr[RX] = rlat (gr[RD] + ((inst >> 2) & 0x003C)); |
2d514e6f | 1113 | if (tracing) |
43236bb2 | 1114 | fprintf (stderr, "load reg %d from 0x%lx with 0x%lx", |
2d514e6f | 1115 | RX, |
7eed1055 | 1116 | gr[RD] + ((inst >> 2) & 0x003C), gr[RX]); |
2d514e6f SS |
1117 | memops++; |
1118 | break; | |
1119 | case 0x90: case 0x91: case 0x92: case 0x93: | |
1120 | case 0x94: case 0x95: case 0x96: case 0x97: | |
1121 | case 0x98: case 0x99: case 0x9A: case 0x9B: | |
1122 | case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */ | |
7eed1055 | 1123 | wlat (gr[RD] + ((inst >> 2) & 0x003C), gr[RX]); |
2d514e6f | 1124 | if (tracing) |
43236bb2 | 1125 | fprintf (stderr, "store reg %d (containing 0x%lx) to 0x%lx", |
7eed1055 MF |
1126 | RX, gr[RX], |
1127 | gr[RD] + ((inst >> 2) & 0x003C)); | |
2d514e6f SS |
1128 | memops++; |
1129 | break; | |
1130 | case 0xA0: case 0xA1: case 0xA2: case 0xA3: | |
1131 | case 0xA4: case 0xA5: case 0xA6: case 0xA7: | |
1132 | case 0xA8: case 0xA9: case 0xAA: case 0xAB: | |
1133 | case 0xAC: case 0xAD: case 0xAE: case 0xAF: /* ld.b */ | |
7eed1055 | 1134 | gr[RX] = rbat (gr[RD] + RS); |
2d514e6f SS |
1135 | memops++; |
1136 | break; | |
1137 | case 0xB0: case 0xB1: case 0xB2: case 0xB3: | |
1138 | case 0xB4: case 0xB5: case 0xB6: case 0xB7: | |
1139 | case 0xB8: case 0xB9: case 0xBA: case 0xBB: | |
1140 | case 0xBC: case 0xBD: case 0xBE: case 0xBF: /* st.b */ | |
7eed1055 | 1141 | wbat (gr[RD] + RS, gr[RX]); |
2d514e6f SS |
1142 | memops++; |
1143 | break; | |
1144 | case 0xC0: case 0xC1: case 0xC2: case 0xC3: | |
1145 | case 0xC4: case 0xC5: case 0xC6: case 0xC7: | |
1146 | case 0xC8: case 0xC9: case 0xCA: case 0xCB: | |
1147 | case 0xCC: case 0xCD: case 0xCE: case 0xCF: /* ld.h */ | |
7eed1055 | 1148 | gr[RX] = rhat (gr[RD] + ((inst >> 3) & 0x001E)); |
2d514e6f SS |
1149 | memops++; |
1150 | break; | |
1151 | case 0xD0: case 0xD1: case 0xD2: case 0xD3: | |
1152 | case 0xD4: case 0xD5: case 0xD6: case 0xD7: | |
1153 | case 0xD8: case 0xD9: case 0xDA: case 0xDB: | |
1154 | case 0xDC: case 0xDD: case 0xDE: case 0xDF: /* st.h */ | |
7eed1055 | 1155 | what (gr[RD] + ((inst >> 3) & 0x001E), gr[RX]); |
2d514e6f SS |
1156 | memops++; |
1157 | break; | |
1158 | case 0xE8: case 0xE9: case 0xEA: case 0xEB: | |
ba14f941 | 1159 | case 0xEC: case 0xED: case 0xEE: case 0xEF: /* bf */ |
2d514e6f SS |
1160 | if (C_OFF()) |
1161 | { | |
1162 | int disp; | |
1163 | disp = inst & 0x03FF; | |
1164 | if (inst & 0x0400) | |
1165 | disp |= 0xFFFFFC00; | |
1166 | pc += disp<<1; | |
1167 | bonus_cycles++; | |
1168 | needfetch = 1; | |
1169 | } | |
1170 | break; | |
1171 | case 0xE0: case 0xE1: case 0xE2: case 0xE3: | |
1172 | case 0xE4: case 0xE5: case 0xE6: case 0xE7: /* bt */ | |
1173 | if (C_ON()) | |
1174 | { | |
1175 | int disp; | |
1176 | disp = inst & 0x03FF; | |
1177 | if (inst & 0x0400) | |
1178 | disp |= 0xFFFFFC00; | |
1179 | pc += disp<<1; | |
1180 | bonus_cycles++; | |
1181 | needfetch = 1; | |
1182 | } | |
1183 | break; | |
1184 | ||
1185 | case 0xF8: case 0xF9: case 0xFA: case 0xFB: | |
ba14f941 | 1186 | case 0xFC: case 0xFD: case 0xFE: case 0xFF: /* bsr */ |
7eed1055 | 1187 | gr[15] = pc; |
2d514e6f SS |
1188 | case 0xF0: case 0xF1: case 0xF2: case 0xF3: |
1189 | case 0xF4: case 0xF5: case 0xF6: case 0xF7: /* br */ | |
1190 | { | |
1191 | int disp; | |
1192 | disp = inst & 0x03FF; | |
1193 | if (inst & 0x0400) | |
1194 | disp |= 0xFFFFFC00; | |
1195 | pc += disp<<1; | |
1196 | bonus_cycles++; | |
1197 | needfetch = 1; | |
1198 | } | |
1199 | break; | |
1200 | ||
1201 | } | |
1202 | ||
1203 | if (tracing) | |
1204 | fprintf (stderr, "\n"); | |
cd0fc7c3 | 1205 | |
ba14f941 | 1206 | if (needfetch) |
2d514e6f | 1207 | { |
f63036b8 MF |
1208 | ibuf = rlat (pc & 0xFFFFFFFC); |
1209 | needfetch = 0; | |
2d514e6f SS |
1210 | } |
1211 | } | |
2d514e6f SS |
1212 | |
1213 | /* Hide away the things we've cached while executing. */ | |
7eed1055 MF |
1214 | CPU_PC_SET (cpu, pc); |
1215 | cpu->insts += insts; /* instructions done ... */ | |
1216 | cpu->cycles += insts; /* and each takes a cycle */ | |
1217 | cpu->cycles += bonus_cycles; /* and extra cycles for branches */ | |
1218 | cpu->cycles += memops * memcycles; /* and memop cycle delays */ | |
2d514e6f SS |
1219 | } |
1220 | ||
02962cd9 MF |
1221 | void |
1222 | sim_engine_run (SIM_DESC sd, | |
1223 | int next_cpu_nr, /* ignore */ | |
1224 | int nr_cpus, /* ignore */ | |
1225 | int siggnal) /* ignore */ | |
1226 | { | |
7eed1055 | 1227 | sim_cpu *cpu; |
02962cd9 MF |
1228 | |
1229 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
1230 | ||
7eed1055 | 1231 | cpu = STATE_CPU (sd, 0); |
02962cd9 MF |
1232 | |
1233 | while (1) | |
1234 | { | |
7eed1055 | 1235 | step_once (sd, cpu); |
02962cd9 MF |
1236 | if (sim_events_tick (sd)) |
1237 | sim_events_process (sd); | |
1238 | } | |
1239 | } | |
1240 | ||
9ef4651c | 1241 | static int |
7eed1055 | 1242 | mcore_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) |
2d514e6f | 1243 | { |
2d514e6f SS |
1244 | if (rn < NUM_MCORE_REGS && rn >= 0) |
1245 | { | |
1246 | if (length == 4) | |
1247 | { | |
2d514e6f | 1248 | long ival; |
ba14f941 | 1249 | |
cd0fc7c3 SS |
1250 | /* misalignment safe */ |
1251 | ival = mcore_extract_unsigned_integer (memory, 4); | |
7eed1055 | 1252 | cpu->asints[rn] = ival; |
2d514e6f SS |
1253 | } |
1254 | ||
1255 | return 4; | |
1256 | } | |
1257 | else | |
1258 | return 0; | |
1259 | } | |
1260 | ||
9ef4651c | 1261 | static int |
7eed1055 | 1262 | mcore_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) |
2d514e6f | 1263 | { |
2d514e6f SS |
1264 | if (rn < NUM_MCORE_REGS && rn >= 0) |
1265 | { | |
1266 | if (length == 4) | |
1267 | { | |
7eed1055 | 1268 | long ival = cpu->asints[rn]; |
cd0fc7c3 SS |
1269 | |
1270 | /* misalignment-safe */ | |
1271 | mcore_store_unsigned_integer (memory, 4, ival); | |
2d514e6f | 1272 | } |
ba14f941 | 1273 | |
2d514e6f SS |
1274 | return 4; |
1275 | } | |
1276 | else | |
1277 | return 0; | |
1278 | } | |
1279 | ||
2d514e6f | 1280 | void |
feb703b3 | 1281 | sim_info (SIM_DESC sd, int verbose) |
2d514e6f | 1282 | { |
7eed1055 | 1283 | SIM_CPU *cpu = STATE_CPU (sd, 0); |
2d514e6f SS |
1284 | #ifdef WATCHFUNCTIONS |
1285 | int w, wcyc; | |
1286 | #endif | |
7eed1055 | 1287 | double virttime = cpu->cycles / 36.0e6; |
ea6b7543 | 1288 | host_callback *callback = STATE_CALLBACK (sd); |
2d514e6f | 1289 | |
cd0fc7c3 | 1290 | callback->printf_filtered (callback, "\n\n# instructions executed %10d\n", |
7eed1055 | 1291 | cpu->insts); |
cd0fc7c3 | 1292 | callback->printf_filtered (callback, "# cycles %10d\n", |
7eed1055 | 1293 | cpu->cycles); |
cd0fc7c3 | 1294 | callback->printf_filtered (callback, "# pipeline stalls %10d\n", |
7eed1055 | 1295 | cpu->stalls); |
cd0fc7c3 SS |
1296 | callback->printf_filtered (callback, "# virtual time taken %10.4f\n", |
1297 | virttime); | |
2d514e6f SS |
1298 | |
1299 | #ifdef WATCHFUNCTIONS | |
cd0fc7c3 SS |
1300 | callback->printf_filtered (callback, "\nNumber of watched functions: %d\n", |
1301 | ENDWL); | |
2d514e6f SS |
1302 | |
1303 | wcyc = 0; | |
ba14f941 | 1304 | |
2d514e6f SS |
1305 | for (w = 1; w <= ENDWL; w++) |
1306 | { | |
1307 | callback->printf_filtered (callback, "WL = %s %8x\n",WLstr[w],WL[w]); | |
cd0fc7c3 SS |
1308 | callback->printf_filtered (callback, " calls = %d, cycles = %d\n", |
1309 | WLcnts[w],WLcyc[w]); | |
ba14f941 | 1310 | |
2d514e6f | 1311 | if (WLcnts[w] != 0) |
cd0fc7c3 SS |
1312 | callback->printf_filtered (callback, |
1313 | " maxcpc = %d, mincpc = %d, avecpc = %d\n", | |
1314 | WLmax[w],WLmin[w],WLcyc[w]/WLcnts[w]); | |
2d514e6f SS |
1315 | wcyc += WLcyc[w]; |
1316 | } | |
ba14f941 | 1317 | |
cd0fc7c3 SS |
1318 | callback->printf_filtered (callback, |
1319 | "Total cycles for watched functions: %d\n",wcyc); | |
2d514e6f SS |
1320 | #endif |
1321 | } | |
1322 | ||
4c0cab1e MF |
1323 | static sim_cia |
1324 | mcore_pc_get (sim_cpu *cpu) | |
1325 | { | |
7eed1055 | 1326 | return cpu->regs.pc; |
4c0cab1e MF |
1327 | } |
1328 | ||
1329 | static void | |
1330 | mcore_pc_set (sim_cpu *cpu, sim_cia pc) | |
1331 | { | |
7eed1055 | 1332 | cpu->regs.pc = pc; |
4c0cab1e MF |
1333 | } |
1334 | ||
ea6b7543 MF |
1335 | static void |
1336 | free_state (SIM_DESC sd) | |
1337 | { | |
1338 | if (STATE_MODULES (sd) != NULL) | |
1339 | sim_module_uninstall (sd); | |
1340 | sim_cpu_free_all (sd); | |
1341 | sim_state_free (sd); | |
1342 | } | |
1343 | ||
2d514e6f | 1344 | SIM_DESC |
2e3d4f4d MF |
1345 | sim_open (SIM_OPEN_KIND kind, host_callback *cb, |
1346 | struct bfd *abfd, char * const *argv) | |
2d514e6f | 1347 | { |
f63036b8 | 1348 | int i; |
ea6b7543 | 1349 | SIM_DESC sd = sim_state_alloc (kind, cb); |
ea6b7543 MF |
1350 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
1351 | ||
1352 | /* The cpu data is kept in a separately allocated chunk of memory. */ | |
d5a71b11 | 1353 | if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) |
ea6b7543 MF |
1354 | { |
1355 | free_state (sd); | |
1356 | return 0; | |
1357 | } | |
1358 | ||
1359 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
1360 | { | |
1361 | free_state (sd); | |
1362 | return 0; | |
1363 | } | |
1364 | ||
77cf2ef5 | 1365 | /* The parser will print an error message for us, so we silently return. */ |
ea6b7543 MF |
1366 | if (sim_parse_args (sd, argv) != SIM_RC_OK) |
1367 | { | |
1368 | free_state (sd); | |
1369 | return 0; | |
1370 | } | |
1371 | ||
1372 | /* Check for/establish the a reference program image. */ | |
1373 | if (sim_analyze_program (sd, | |
1374 | (STATE_PROG_ARGV (sd) != NULL | |
1375 | ? *STATE_PROG_ARGV (sd) | |
1376 | : NULL), abfd) != SIM_RC_OK) | |
1377 | { | |
1378 | free_state (sd); | |
1379 | return 0; | |
1380 | } | |
1381 | ||
1382 | /* Configure/verify the target byte order and other runtime | |
1383 | configuration options. */ | |
1384 | if (sim_config (sd) != SIM_RC_OK) | |
1385 | { | |
1386 | sim_module_uninstall (sd); | |
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
1391 | { | |
1392 | /* Uninstall the modules to avoid memory leaks, | |
1393 | file descriptor leaks, etc. */ | |
1394 | sim_module_uninstall (sd); | |
1395 | return 0; | |
1396 | } | |
1397 | ||
ea6b7543 MF |
1398 | /* CPU specific initialization. */ |
1399 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
1400 | { | |
1401 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
4c0cab1e | 1402 | |
9ef4651c MF |
1403 | CPU_REG_FETCH (cpu) = mcore_reg_fetch; |
1404 | CPU_REG_STORE (cpu) = mcore_reg_store; | |
4c0cab1e MF |
1405 | CPU_PC_FETCH (cpu) = mcore_pc_get; |
1406 | CPU_PC_STORE (cpu) = mcore_pc_set; | |
1407 | ||
ea6b7543 MF |
1408 | set_initial_gprs (cpu); /* Reset the GPR registers. */ |
1409 | } | |
ba14f941 | 1410 | |
f63036b8 MF |
1411 | /* Default to a 8 Mbyte (== 2^23) memory space. */ |
1412 | sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEMORY_SIZE); | |
1413 | ||
ea6b7543 | 1414 | return sd; |
2d514e6f SS |
1415 | } |
1416 | ||
2d514e6f | 1417 | SIM_RC |
2e3d4f4d MF |
1418 | sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, |
1419 | char * const *argv, char * const *env) | |
2d514e6f | 1420 | { |
7eed1055 | 1421 | SIM_CPU *cpu = STATE_CPU (sd, 0); |
91eea121 | 1422 | char * const *avp; |
2d514e6f SS |
1423 | int nargs = 0; |
1424 | int nenv = 0; | |
1425 | int s_length; | |
1426 | int l; | |
1427 | unsigned long strings; | |
1428 | unsigned long pointers; | |
1429 | unsigned long hi_stack; | |
1430 | ||
1431 | ||
1432 | /* Set the initial register set. */ | |
7eed1055 | 1433 | set_initial_gprs (cpu); |
ba14f941 | 1434 | |
f63036b8 | 1435 | hi_stack = DEFAULT_MEMORY_SIZE - 4; |
7eed1055 | 1436 | CPU_PC_SET (cpu, bfd_get_start_address (prog_bfd)); |
2d514e6f SS |
1437 | |
1438 | /* Calculate the argument and environment strings. */ | |
1439 | s_length = 0; | |
1440 | nargs = 0; | |
1441 | avp = argv; | |
1442 | while (avp && *avp) | |
1443 | { | |
1444 | l = strlen (*avp) + 1; /* include the null */ | |
1445 | s_length += (l + 3) & ~3; /* make it a 4 byte boundary */ | |
1446 | nargs++; avp++; | |
1447 | } | |
1448 | ||
1449 | nenv = 0; | |
1450 | avp = env; | |
1451 | while (avp && *avp) | |
1452 | { | |
1453 | l = strlen (*avp) + 1; /* include the null */ | |
1454 | s_length += (l + 3) & ~ 3;/* make it a 4 byte boundary */ | |
1455 | nenv++; avp++; | |
1456 | } | |
1457 | ||
1458 | /* Claim some memory for the pointers and strings. */ | |
1459 | pointers = hi_stack - sizeof(word) * (nenv+1+nargs+1); | |
1460 | pointers &= ~3; /* must be 4-byte aligned */ | |
7eed1055 | 1461 | gr[0] = pointers; |
2d514e6f | 1462 | |
7eed1055 | 1463 | strings = gr[0] - s_length; |
2d514e6f | 1464 | strings &= ~3; /* want to make it 4-byte aligned */ |
7eed1055 | 1465 | gr[0] = strings; |
2d514e6f | 1466 | /* dac fix, the stack address must be 8-byte aligned! */ |
7eed1055 | 1467 | gr[0] = gr[0] - gr[0] % 8; |
2d514e6f SS |
1468 | |
1469 | /* Loop through the arguments and fill them in. */ | |
7eed1055 | 1470 | gr[PARM1] = nargs; |
2d514e6f SS |
1471 | if (nargs == 0) |
1472 | { | |
1473 | /* No strings to fill in. */ | |
7eed1055 | 1474 | gr[PARM2] = 0; |
2d514e6f SS |
1475 | } |
1476 | else | |
1477 | { | |
7eed1055 | 1478 | gr[PARM2] = pointers; |
2d514e6f SS |
1479 | avp = argv; |
1480 | while (avp && *avp) | |
1481 | { | |
1482 | /* Save where we're putting it. */ | |
1483 | wlat (pointers, strings); | |
1484 | ||
1485 | /* Copy the string. */ | |
1486 | l = strlen (* avp) + 1; | |
7eed1055 | 1487 | sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l); |
2d514e6f SS |
1488 | |
1489 | /* Bump the pointers. */ | |
1490 | avp++; | |
1491 | pointers += 4; | |
1492 | strings += l+1; | |
1493 | } | |
ba14f941 | 1494 | |
2d514e6f SS |
1495 | /* A null to finish the list. */ |
1496 | wlat (pointers, 0); | |
1497 | pointers += 4; | |
1498 | } | |
1499 | ||
1500 | /* Now do the environment pointers. */ | |
1501 | if (nenv == 0) | |
1502 | { | |
1503 | /* No strings to fill in. */ | |
7eed1055 | 1504 | gr[PARM3] = 0; |
2d514e6f SS |
1505 | } |
1506 | else | |
1507 | { | |
7eed1055 | 1508 | gr[PARM3] = pointers; |
2d514e6f | 1509 | avp = env; |
ba14f941 | 1510 | |
2d514e6f SS |
1511 | while (avp && *avp) |
1512 | { | |
1513 | /* Save where we're putting it. */ | |
1514 | wlat (pointers, strings); | |
1515 | ||
1516 | /* Copy the string. */ | |
1517 | l = strlen (* avp) + 1; | |
7eed1055 | 1518 | sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l); |
2d514e6f SS |
1519 | |
1520 | /* Bump the pointers. */ | |
1521 | avp++; | |
1522 | pointers += 4; | |
1523 | strings += l+1; | |
1524 | } | |
ba14f941 | 1525 | |
2d514e6f SS |
1526 | /* A null to finish the list. */ |
1527 | wlat (pointers, 0); | |
1528 | pointers += 4; | |
1529 | } | |
ba14f941 | 1530 | |
2d514e6f SS |
1531 | return SIM_RC_OK; |
1532 | } |