projects / thirdparty / binutils-gdb.git / blame
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| bd30e45a ME |
1 | #ifndef MICROBLAZE_SIM_MAIN |
| 2 | #define MICROBLAZE_SIM_MAIN | |
| 3 | ||
| 7b6bb8da | 4 | /* Copyright 2009, 2010, 2011 Free Software Foundation, Inc. |
| bd30e45a ME |
5 | |
| 6 | This file is part of the Xilinx MicroBlaze simulator. | |
| 7 | ||
| 8 | This library is free software; you can redistribute it and/or modify | |
| 9 | it under the terms of the GNU General Public License as published by | |
| 10 | the Free Software Foundation; either version 3 of the License, or | |
| 11 | (at your option) any later version. | |
| 12 | ||
| 13 | This program is distributed in the hope that it will be useful, | |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | GNU General Public License for more details. | |
| 17 | ||
| 18 | You should have received a copy of the GNU General Public License | |
| 19 | along with this program; if not, write to the Free Software | |
| 20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, | |
| 21 | MA 02110-1301, USA. */ | |
| 22 | ||
| 23 | #include "microblaze.h" | |
| 24 | #include "sim-basics.h" | |
| 25 | typedef address_word sim_cia; | |
| 26 | #include "sim-base.h" | |
| 27 | ||
| 28 | /* The machine state. | |
| 29 | This state is maintained in host byte order. The | |
| 30 | fetch/store register functions must translate between host | |
| 31 | byte order and the target processor byte order. | |
| 32 | Keeping this data in target byte order simplifies the register | |
| 33 | read/write functions. Keeping this data in native order improves | |
| 34 | the performance of the simulator. Simulation speed is deemed more | |
| 35 | important. */ | |
| 36 | ||
| 37 | /* The ordering of the microblaze_regset structure is matched in the | |
| 38 | gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro. */ | |
| 39 | struct microblaze_regset | |
| 40 | { | |
| 41 | word regs[32]; /* primary registers */ | |
| 42 | word spregs[2]; /* pc + msr */ | |
| 43 | int cycles; | |
| 44 | int insts; | |
| 45 | int exception; | |
| 46 | unsigned long msize; | |
| 47 | unsigned char *memory; | |
| 48 | ubyte imm_enable; | |
| 49 | half imm_high; | |
| 50 | }; | |
| 51 | ||
| 52 | struct _sim_cpu { | |
| 53 | struct microblaze_regset microblaze_cpu; | |
| 54 | sim_cpu_base base; | |
| 55 | }; | |
| 56 | ||
| 57 | #define MAX_NR_PROCESSORS 1 | |
| 58 | struct sim_state { | |
| 59 | sim_cpu cpu[MAX_NR_PROCESSORS]; | |
| 60 | #define STATE_CPU(sd, n) (&(sd)->cpu[0]) | |
| 61 | sim_state_base base; | |
| 62 | }; | |
| 63 | #endif /* MICROBLAZE_SIM_MAIN */ | |
| 64 |