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sim: unify -Werror build settings
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
47ce766a
MF		 12021-06-18 Mike Frysinger <vapier@gentoo.org>
2
3 * aclocal.m4, configure: Regenerate.
4
982c3a65
MF		 52021-06-18 Mike Frysinger <vapier@gentoo.org>
6
7 * Makefile.in (SIM_WERROR_CFLAGS): New variable.
8 * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
9 * configure: Regenerate.
10
1fef66b0
MF		 112021-06-18 Mike Frysinger <vapier@gentoo.org>
12
13 * interp.c: Include sim-signal.h.
14
f9a4d543
MF		 152021-06-17 Mike Frysinger <vapier@gentoo.org>
16
17 * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
18 * aclocal.m4, configure: Regenerate.
19
b80d4475
MF		 202021-06-16 Mike Frysinger <vapier@gentoo.org>
21
22 * interp.c (dotrace): Make comment const.
23 * sim-main.h (dotrace): Likewise. Add ATTRIBUTE_PRINTF.
24
6828a302
MF		 252021-06-16 Mike Frysinger <vapier@gentoo.org>
26
27 * interp.c (sim_monitor): Change ap type to address_word*.
28 (_P, P): New macros. Rewrite dynamic printf logic to use these.
29
df32b446
MF		 302021-06-16 Mike Frysinger <vapier@gentoo.org>
31
32 * dv-tx3904sio.c (tx3904sio_fifo_push): Change next_buf to
33 unsigned_1.
34
7b2298cb
MF		 352021-06-16 Mike Frysinger <vapier@gentoo.org>
36
37 * dv-tx3904irc.c (tx3904irc_io_write_buffer): Initialize
38 register_value to 0.
39
a8a3d907
MF		 402021-06-16 Mike Frysinger <vapier@gentoo.org>
41
42 * configure: Regenerate.
43
dae666c9
MF		 442021-06-16 Mike Frysinger <vapier@gentoo.org>
45
46 * interp.c (sim_open): Change %lx to %x and PRIx macros.
47
52d37d2c
MF		 482021-06-16 Mike Frysinger <vapier@gentoo.org>
49
50 * configure: Regenerate.
51 * config.in: Removed.
52
bcaa61f7
MF		 532021-06-15 Mike Frysinger <vapier@gentoo.org>
54
55 * config.in, configure: Regenerate.
56
ba307cdd
MF		 572021-06-12 Mike Frysinger <vapier@gentoo.org>
58
59 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
60
dba333c1
MF		 612021-06-12 Mike Frysinger <vapier@gentoo.org>
62
63 * aclocal.m4, config.in, configure: Regenerate.
64
b15c5d7a
MF		 652021-06-12 Mike Frysinger <vapier@gentoo.org>
66
67 * configure.ac: Delete call to AC_CHECK_FUNCS.
68 * config.in, configure: Regenerate.
69
a55b92be
MF		 702021-06-08 Mike Frysinger <vapier@gentoo.org>
71
72 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
73 with $(IGEN).
74
8ea881d9
MF		 752021-05-29 Mike Frysinger <vapier@gentoo.org>
76
77 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
78
b312488f
FS		 792021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
80
168671c1
FS		 81 * interp.c (sim_open): Add shadow mappings from 32-bit
82 address space to 64-bit sign-extended address space.
83
842021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
85
b312488f
FS		 86 * interp.c (sim_create_inferior): Only truncate sign extension
87 bits for 32-bit target models.
88
f4fdd845
MF		 892021-05-17 Mike Frysinger <vapier@gentoo.org>
90
91 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
92
8ea7241c
MF		 932021-05-17 Mike Frysinger <vapier@gentoo.org>
94
95 * interp.c (sim_open): Switch to sim_state_alloc_extra.
96 * micromips.igen: Change SD to mips_sim_state.
97 * micromipsrun.c (sim_engine_run): Likewise.
98 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
99 (watch_options_install): Delete.
100 (struct swatch): Delete.
101 (struct sim_state): Delete.
102 (struct mips_sim_state): New struct.
103 (MIPS_SIM_STATE): Define.
104
6df01ab8
MF		 1052021-05-16 Mike Frysinger <vapier@gentoo.org>
106
107 * interp.c: Replace config.h include with defs.h.
108 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
109 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
110 Include defs.h.
111
79633c12
MF		 1122021-05-16 Mike Frysinger <vapier@gentoo.org>
113
114 * config.in, configure: Regenerate.
115
df68e12b
MF		 1162021-05-14 Mike Frysinger <vapier@gentoo.org>
117
118 * interp.c: Update include path.
119
77c0fdb7
MF		 1202021-05-04 Mike Frysinger <vapier@gentoo.org>
121
122 * dv-tx3904sio.c: Include stdlib.h.
123
9b1af85c
MF		 1242021-05-04 Mike Frysinger <vapier@gentoo.org>
125
126 * configure.ac (hw_extra_devices): Inline contents into
127 SIM_AC_OPTION_HARDWARE and delete.
128 * configure: Regenerate.
129
d97ba9c6
MF		 1302021-05-04 Mike Frysinger <vapier@gentoo.org>
131
132 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
133 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
134 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
135 * configure: Regenerate.
136
4df817de
MF		 1372021-05-04 Mike Frysinger <vapier@gentoo.org>
138
139 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
140
aa0fca16
MF		 1412021-05-04 Mike Frysinger <vapier@gentoo.org>
142
143 * configure: Regenerate.
144
adbaa7b8
MF		 1452021-05-01 Mike Frysinger <vapier@gentoo.org>
146
147 * cp1.c (store_fcr): Mark static.
148
fe348617
MF		 1492021-05-01 Mike Frysinger <vapier@gentoo.org>
150
151 * config.in, configure: Regenerate.
152
9d903352
MF		 1532021-04-23 Mike Frysinger <vapier@gentoo.org>
154
155 * configure.ac (hw_enabled): Delete.
156 (SIM_AC_OPTION_HARDWARE): Delete first two args.
157 * configure: Regenerate.
158
19f6a43c
TT		 1592021-04-22 Tom Tromey <tom@tromey.com>
160
161 * configure, config.in: Rebuild.
162
e7d8f1da
TT		 1632021-04-22 Tom Tromey <tom@tromey.com>
164
165 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
166 Remove.
167 (SIM_EXTRA_DEPS): New variable.
168
efd82ac7
TT		 1692021-04-22 Tom Tromey <tom@tromey.com>
170
171 * configure: Rebuild.
172
2662c237
MF		 1732021-04-21 Mike Frysinger <vapier@gentoo.org>
174
175 * aclocal.m4: Regenerate.
176
1f195bc3
SM		 1772021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
178
179 * configure: Regenerate.
180
37e9f182
MF		 1812021-04-18 Mike Frysinger <vapier@gentoo.org>
182
183 * configure: Regenerate.
184
d5a71b11
MF		 1852021-04-12 Mike Frysinger <vapier@gentoo.org>
186
187 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
188
2b8d134b
SM		 1892021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
190
191 * Makefile.in: Set ASAN_OPTIONS when running igen.
192
5c6f091a
FS		 1932021-04-04 Steve Ellcey <sellcey@mips.com>
194 Faraz Shahbazker <fshahbazker@wavecomp.com>
195
196 * interp.c (sim_monitor): Add switch entries for unlink (13),
197 lseek (14), and stat (15).
198
b6b1c790
MF		 1992021-04-02 Mike Frysinger <vapier@gentoo.org>
200
201 * Makefile.in (../igen/igen): Delete rule.
202 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
203
c2783492
MF		 2042021-04-02 Mike Frysinger <vapier@gentoo.org>
205
206 * aclocal.m4, configure: Regenerate.
207
ebe9564b
MF		 2082021-02-28 Mike Frysinger <vapier@gentoo.org>
209
210 * configure: Regenerate.
211
f8069d55
MF		 2122021-02-27 Mike Frysinger <vapier@gentoo.org>
213
214 * Makefile.in (SIM_EXTRA_ALL): Delete.
215 (all): New target.
216
760b3e8b
MF		 2172021-02-21 Mike Frysinger <vapier@gentoo.org>
218
219 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
220 * aclocal.m4, configure: Regenerate.
221
136da8cd
MF		 2222021-02-13 Mike Frysinger <vapier@gentoo.org>
223
224 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
225 * aclocal.m4, configure: Regenerate.
226
4c0d76b9
MF		 2272021-02-06 Mike Frysinger <vapier@gentoo.org>
228
229 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
230
aa09469f
MF		 2312021-02-06 Mike Frysinger <vapier@gentoo.org>
232
233 * configure: Regenerate.
234
d4e3adda
MF		 2352021-01-30 Mike Frysinger <vapier@gentoo.org>
236
237 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
238
68ed2854
MF		 2392021-01-11 Mike Frysinger <vapier@gentoo.org>
240
241 * config.in, configure: Regenerate.
242 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
243 and strings.h include.
244
50df264d
MF		 2452021-01-09 Mike Frysinger <vapier@gentoo.org>
246
247 * configure: Regenerate.
248
bf470982
MF		 2492021-01-09 Mike Frysinger <vapier@gentoo.org>
250
251 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
252 * configure: Regenerate.
253
46f900c0
MF		 2542021-01-08 Mike Frysinger <vapier@gentoo.org>
255
256 * configure: Regenerate.
257
dfb856ba
MF		 2582021-01-04 Mike Frysinger <vapier@gentoo.org>
259
260 * configure: Regenerate.
261
382bc56b
PK		 2622020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
263
264 * sim-main.c: Include <stdlib.h>.
265
ad9675dd
PK		 2662020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
267
268 * cp1.c: Include <stdlib.h>.
269
f693213d
SM		 2702020-07-29 Simon Marchi <simon.marchi@efficios.com>
271
272 * configure: Re-generate.
273
5c887dd5
JB		 2742017-09-06 John Baldwin <jhb@FreeBSD.org>
275
276 * configure: Regenerate.
277
91588b3a
MF		 2782016-11-11 Mike Frysinger <vapier@gentoo.org>
279
6cb2202b 280 PR sim/20808
91588b3a
MF		 281 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
282 and SD to sd.
283
e04659e8
MF		 2842016-11-11 Mike Frysinger <vapier@gentoo.org>
285
6cb2202b 286 PR sim/20809
e04659e8
MF		 287 * mips.igen (check_u64): Enable for `r3900'.
288
1554f758
MF		 2892016-02-05 Mike Frysinger <vapier@gentoo.org>
290
291 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
292 STATE_PROG_BFD (sd).
293 * configure: Regenerate.
294
3d304f48
AB		 2952016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
296 Maciej W. Rozycki <macro@imgtec.com>
297
298 PR sim/19441
299 * micromips.igen (delayslot_micromips): Enable for `micromips32',
300 `micromips64' and `micromipsdsp' only.
301 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
302 (do_micromips_jalr, do_micromips_jal): Likewise.
303 (compute_movep_src_reg): Likewise.
304 (compute_andi16_imm): Likewise.
305 (convert_fmt_micromips): Likewise.
306 (convert_fmt_micromips_cvt_d): Likewise.
307 (convert_fmt_micromips_cvt_s): Likewise.
308 (FMT_MICROMIPS): Likewise.
309 (FMT_MICROMIPS_CVT_D): Likewise.
310 (FMT_MICROMIPS_CVT_S): Likewise.
311
b36d953b
MF		 3122016-01-12 Mike Frysinger <vapier@gentoo.org>
313
314 * interp.c: Include elf-bfd.h.
315 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
316 ELFCLASS32.
317
ce39bd38
MF		 3182016-01-10 Mike Frysinger <vapier@gentoo.org>
319
320 * config.in, configure: Regenerate.
321
99d8e879
MF		 3222016-01-10 Mike Frysinger <vapier@gentoo.org>
323
324 * configure: Regenerate.
325
35656e95
MF		 3262016-01-10 Mike Frysinger <vapier@gentoo.org>
327
328 * configure: Regenerate.
329
16f7876d
MF		 3302016-01-10 Mike Frysinger <vapier@gentoo.org>
331
332 * configure: Regenerate.
333
e19418e0
MF		 3342016-01-10 Mike Frysinger <vapier@gentoo.org>
335
336 * configure: Regenerate.
337
6d90347b
MF		 3382016-01-10 Mike Frysinger <vapier@gentoo.org>
339
340 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
341 * configure: Regenerate.
342
347fe5bb
MF		 3432016-01-10 Mike Frysinger <vapier@gentoo.org>
344
345 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
346 * configure: Regenerate.
347
22be3fbe
MF		 3482016-01-10 Mike Frysinger <vapier@gentoo.org>
349
350 * configure: Regenerate.
351
0dc73ef7
MF		 3522016-01-10 Mike Frysinger <vapier@gentoo.org>
353
354 * configure: Regenerate.
355
936df756
MF		 3562016-01-09 Mike Frysinger <vapier@gentoo.org>
357
358 * config.in, configure: Regenerate.
359
2e3d4f4d
MF		 3602016-01-06 Mike Frysinger <vapier@gentoo.org>
361
362 * interp.c (sim_open): Mark argv const.
363 (sim_create_inferior): Mark argv and env const.
364
9bbf6f91
MF		 3652016-01-04 Mike Frysinger <vapier@gentoo.org>
366
367 * configure: Regenerate.
368
77cf2ef5
MF		 3692016-01-03 Mike Frysinger <vapier@gentoo.org>
370
371 * interp.c (sim_open): Update sim_parse_args comment.
372
0cb8d851
MF		 3732016-01-03 Mike Frysinger <vapier@gentoo.org>
374
375 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
376 * configure: Regenerate.
377
1ac72f06
MF		 3782016-01-02 Mike Frysinger <vapier@gentoo.org>
379
380 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
381 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
382 * configure: Regenerate.
383 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
384
d47f5b30
MF		 3852016-01-02 Mike Frysinger <vapier@gentoo.org>
386
387 * dv-tx3904cpu.c (CPU, SD): Delete.
388
e1211e55
MF		 3892015-12-30 Mike Frysinger <vapier@gentoo.org>
390
391 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
392 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
393 (sim_store_register): Rename to ...
394 (mips_reg_store): ... this. Delete local cpu var.
395 Update sim_io_eprintf calls.
396 (sim_fetch_register): Rename to ...
397 (mips_reg_fetch): ... this. Delete local cpu var.
398 Update sim_io_eprintf calls.
399
5e744ef8
MF		 4002015-12-27 Mike Frysinger <vapier@gentoo.org>
401
402 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
403
1b393626
MF		 4042015-12-26 Mike Frysinger <vapier@gentoo.org>
405
406 * config.in, configure: Regenerate.
407
26f8bf63
MF		 4082015-12-26 Mike Frysinger <vapier@gentoo.org>
409
410 * interp.c (sim_write, sim_read): Delete.
411 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
412 (load_word): Likewise.
413 * micromips.igen (cache): Likewise.
414 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
415 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
416 do_store_left, do_store_right, do_load_double, do_store_double):
417 Likewise.
418 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
419 (do_prefx): Likewise.
420 * sim-main.c (address_translation, prefetch): Delete.
421 (ifetch32, ifetch16): Delete call to AddressTranslation and set
422 paddr=vaddr.
423 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
424 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
425 (LoadMemory, StoreMemory): Delete CCA arg.
426
ef04e371
MF		 4272015-12-24 Mike Frysinger <vapier@gentoo.org>
428
429 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
430 * configure: Regenerated.
431
cb379ede
MF		 4322015-12-24 Mike Frysinger <vapier@gentoo.org>
433
434 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
435 * tconfig.h: Delete.
436
26936211
MF		 4372015-12-24 Mike Frysinger <vapier@gentoo.org>
438
439 * tconfig.h (SIM_HANDLES_LMA): Delete.
440
84e8e361
MF		 4412015-12-24 Mike Frysinger <vapier@gentoo.org>
442
443 * sim-main.h (WITH_WATCHPOINTS): Delete.
444
3cabaf66
MF		 4452015-12-24 Mike Frysinger <vapier@gentoo.org>
446
447 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
448
8abe6c66
MF		 4492015-12-24 Mike Frysinger <vapier@gentoo.org>
450
451 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
452
1d19cae7
DV		 4532015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
454
455 * micromips.igen (process_isa_mode): Fix left shift of negative
456 value.
457
cdf850e9
MF		 4582015-11-17 Mike Frysinger <vapier@gentoo.org>
459
460 * sim-main.h (WITH_MODULO_MEMORY): Delete.
461
797eee42
MF		 4622015-11-15 Mike Frysinger <vapier@gentoo.org>
463
464 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
465
6e4f085c
MF		 4662015-11-14 Mike Frysinger <vapier@gentoo.org>
467
468 * interp.c (sim_close): Rename to ...
469 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
470 sim_io_shutdown.
471 * sim-main.h (mips_sim_close): Declare.
472 (SIM_CLOSE_HOOK): Define.
473
8e394ffc
AB		 4742015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
475 Ali Lown <ali.lown@imgtec.com>
476
477 * Makefile.in (tmp-micromips): New rule.
478 (tmp-mach-multi): Add support for micromips.
479 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
480 that works for both mips64 and micromips64.
481 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
482 micromips32.
483 Add build support for micromips.
484 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
485 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
486 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
487 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
488 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
489 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
490 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
491 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
492 Refactored instruction code to use these functions.
493 * dsp2.igen: Refactored instruction code to use the new functions.
494 * interp.c (decode_coproc): Refactored to work with any instruction
495 encoding.
496 (isa_mode): New variable
497 (RSVD_INSTRUCTION): Changed to 0x00000039.
498 * m16.igen (BREAK16): Refactored instruction to use do_break16.
499 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
500 * micromips.dc: New file.
501 * micromips.igen: New file.
502 * micromips16.dc: New file.
503 * micromipsdsp.igen: New file.
504 * micromipsrun.c: New file.
505 * mips.igen (do_swc1): Changed to work with any instruction encoding.
506 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
507 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
508 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
509 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
510 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
511 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
512 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
513 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
514 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
515 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
516 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
517 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
518 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
519 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
520 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
521 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
522 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
523 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
524 instructions.
525 Refactored instruction code to use these functions.
526 (RSVD): Changed to use new reserved instruction.
527 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
528 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
529 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
530 do_store_double): Added micromips32 and micromips64 models.
531 Added include for micromips.igen and micromipsdsp.igen
532 Add micromips32 and micromips64 models.
533 (DecodeCoproc): Updated to use new macro definition.
534 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
535 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
536 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
537 Refactored instruction code to use these functions.
538 * sim-main.h (CP0_operation): New enum.
539 (DecodeCoproc): Updated macro.
540 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
541 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
542 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
543 ISA_MODE_MICROMIPS): New defines.
544 (sim_state): Add isa_mode field.
545
8d0978fb
MF		 5462015-06-23 Mike Frysinger <vapier@gentoo.org>
547
548 * configure: Regenerate.
549
306f4178
MF		 5502015-06-12 Mike Frysinger <vapier@gentoo.org>
551
552 * configure.ac: Change configure.in to configure.ac.
553 * configure: Regenerate.
554
a3487082
MF		 5552015-06-12 Mike Frysinger <vapier@gentoo.org>
556
557 * configure: Regenerate.
558
29bc024d
MF		 5592015-06-12 Mike Frysinger <vapier@gentoo.org>
560
561 * interp.c [TRACE]: Delete.
562 (TRACE): Change to WITH_TRACE_ANY_P.
563 [!WITH_TRACE_ANY_P] (open_trace): Define.
564 (mips_option_handler, open_trace, sim_close, dotrace):
565 Change defined(TRACE) to WITH_TRACE_ANY_P.
566 (sim_open): Delete TRACE ifdef check.
567 * sim-main.c (load_memory): Delete TRACE ifdef check.
568 (store_memory): Likewise.
569 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
570 [!WITH_TRACE_ANY_P] (dotrace): Define.
571
3ebe2863
MF		 5722015-04-18 Mike Frysinger <vapier@gentoo.org>
573
574 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
575 comments.
576
20bca71d
MF		 5772015-04-18 Mike Frysinger <vapier@gentoo.org>
578
579 * sim-main.h (SIM_CPU): Delete.
580
7e83aa92
MF		 5812015-04-18 Mike Frysinger <vapier@gentoo.org>
582
583 * sim-main.h (sim_cia): Delete.
584
034685f9
MF		 5852015-04-17 Mike Frysinger <vapier@gentoo.org>
586
587 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
588 PU_PC_GET.
589 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
590 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
591 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
592 CIA_SET to CPU_PC_SET.
593 * sim-main.h (CIA_GET, CIA_SET): Delete.
594
78e9aa70
MF		 5952015-04-15 Mike Frysinger <vapier@gentoo.org>
596
597 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
598 * sim-main.h (STATE_CPU): Delete.
599
bf12d44e
MF		 6002015-04-13 Mike Frysinger <vapier@gentoo.org>
601
602 * configure: Regenerate.
603
7bebb329
MF		 6042015-04-13 Mike Frysinger <vapier@gentoo.org>
605
606 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
607 * interp.c (mips_pc_get, mips_pc_set): New functions.
608 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
609 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
610 (sim_pc_get): Delete.
611 * sim-main.h (SIM_CPU): Define.
612 (struct sim_state): Change cpu to an array of pointers.
613 (STATE_CPU): Drop &.
614
8ac57fbd
MF		 6152015-04-13 Mike Frysinger <vapier@gentoo.org>
616
617 * interp.c (mips_option_handler, open_trace, sim_close,
618 sim_write, sim_read, sim_store_register, sim_fetch_register,
619 sim_create_inferior, pr_addr, pr_uword64): Convert old style
620 prototypes.
621 (sim_open): Convert old style prototype. Change casts with
622 sim_write to unsigned char *.
623 (fetch_str): Change null to unsigned char, and change cast to
624 unsigned char *.
625 (sim_monitor): Change c & ch to unsigned char. Change cast to
626 unsigned char *.
627
e787f858
MF		 6282015-04-12 Mike Frysinger <vapier@gentoo.org>
629
630 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
631
122bbfb5
MF		 6322015-04-06 Mike Frysinger <vapier@gentoo.org>
633
634 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
635
0fe84f3f
MF		 6362015-04-01 Mike Frysinger <vapier@gentoo.org>
637
638 * tconfig.h (SIM_HAVE_PROFILE): Delete.
639
aadc9410
MF		 6402015-03-31 Mike Frysinger <vapier@gentoo.org>
641
642 * config.in, configure: Regenerate.
643
05f53ed6
MF		 6442015-03-24 Mike Frysinger <vapier@gentoo.org>
645
646 * interp.c (sim_pc_get): New function.
647
c0931f26
MF		 6482015-03-24 Mike Frysinger <vapier@gentoo.org>
649
650 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
651 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
652
30452bbe
MF		 6532015-03-24 Mike Frysinger <vapier@gentoo.org>
654
655 * configure: Regenerate.
656
64dd13df
MF		 6572015-03-23 Mike Frysinger <vapier@gentoo.org>
658
659 * configure: Regenerate.
660
49cd1634
MF		 6612015-03-23 Mike Frysinger <vapier@gentoo.org>
662
663 * configure: Regenerate.
664 * configure.ac (mips_extra_objs): Delete.
665 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
666 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
667
3649cb06
MF		 6682015-03-23 Mike Frysinger <vapier@gentoo.org>
669
670 * configure: Regenerate.
671 * configure.ac: Delete sim_hw checks for dv-sockser.
672
ae7d0cac
MF		 6732015-03-16 Mike Frysinger <vapier@gentoo.org>
674
675 * config.in, configure: Regenerate.
676 * tconfig.in: Rename file ...
677 * tconfig.h: ... here.
678
8406bb59
MF		 6792015-03-15 Mike Frysinger <vapier@gentoo.org>
680
681 * tconfig.in: Delete includes.
682 [HAVE_DV_SOCKSER]: Delete.
683
465fb143
MF		 6842015-03-14 Mike Frysinger <vapier@gentoo.org>
685
686 * Makefile.in (SIM_RUN_OBJS): Delete.
687
5cddc23a
MF		 6882015-03-14 Mike Frysinger <vapier@gentoo.org>
689
690 * configure.ac (AC_CHECK_HEADERS): Delete.
691 * aclocal.m4, configure: Regenerate.
692
2974be62
AM		 6932014-08-19 Alan Modra <amodra@gmail.com>
694
695 * configure: Regenerate.
696
faa743bb
RM		 6972014-08-15 Roland McGrath <mcgrathr@google.com>
698
699 * configure: Regenerate.
700 * config.in: Regenerate.
701
1a8a700e
MF		 7022014-03-04 Mike Frysinger <vapier@gentoo.org>
703
704 * configure: Regenerate.
705
bf3d9781
AM		 7062013-09-23 Alan Modra <amodra@gmail.com>
707
708 * configure: Regenerate.
709
31e6ad7d
MF		 7102013-06-03 Mike Frysinger <vapier@gentoo.org>
711
712 * aclocal.m4, configure: Regenerate.
713
d3685d60
TT		 7142013-05-10 Freddie Chopin <freddie_chopin@op.pl>
715
716 * configure: Rebuild.
717
1517bd27
MF		 7182013-03-26 Mike Frysinger <vapier@gentoo.org>
719
720 * configure: Regenerate.
721
3be31516
JS		 7222013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
723
724 * configure.ac: Address use of dv-sockser.o.
725 * tconfig.in: Conditionalize use of dv_sockser_install.
726 * configure: Regenerated.
727 * config.in: Regenerated.
728
37cb8f8e
SE		 7292012-10-04 Chao-ying Fu <fu@mips.com>
730 Steve Ellcey <sellcey@mips.com>
731
732 * mips/mips3264r2.igen (rdhwr): New.
733
87c8644f
JS		 7342012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
735
736 * configure.ac: Always link against dv-sockser.o.
737 * configure: Regenerate.
738
5f3ef9d0
JB		 7392012-06-15 Joel Brobecker <brobecker@adacore.com>
740
741 * config.in, configure: Regenerate.
742
a6ff997c
NC		 7432012-05-18 Nick Clifton <nickc@redhat.com>
744
745 PR 14072
746 * interp.c: Include config.h before system header files.
747
2232061b
MF		 7482012-03-24 Mike Frysinger <vapier@gentoo.org>
749
750 * aclocal.m4, config.in, configure: Regenerate.
751
db2e4d67
MF		 7522011-12-03 Mike Frysinger <vapier@gentoo.org>
753
754 * aclocal.m4: New file.
755 * configure: Regenerate.
756
4399a56b
MF		 7572011-10-19 Mike Frysinger <vapier@gentoo.org>
758
759 * configure: Regenerate after common/acinclude.m4 update.
760
9c082ca8
MF		 7612011-10-17 Mike Frysinger <vapier@gentoo.org>
762
763 * configure.ac: Change include to common/acinclude.m4.
764
6ffe910a
MF		 7652011-10-17 Mike Frysinger <vapier@gentoo.org>
766
767 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
768 call. Replace common.m4 include with SIM_AC_COMMON.
769 * configure: Regenerate.
770
31b28250
HPN		 7712011-07-08 Hans-Peter Nilsson <hp@axis.com>
772
3faa01e3
HPN		 773 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
774 $(SIM_EXTRA_DEPS).
775 (tmp-mach-multi): Exit early when igen fails.
31b28250 776
2419798b
MF		 7772011-07-05 Mike Frysinger <vapier@gentoo.org>
778
779 * interp.c (sim_do_command): Delete.
780
d79fe0d6
MF		 7812011-02-14 Mike Frysinger <vapier@gentoo.org>
782
783 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
784 (tx3904sio_fifo_reset): Likewise.
785 * interp.c (sim_monitor): Likewise.
786
5558e7e6
MF		 7872010-04-14 Mike Frysinger <vapier@gentoo.org>
788
789 * interp.c (sim_write): Add const to buffer arg.
790
35aafff4
JB		 7912010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
792
793 * interp.c: Don't include sysdep.h
794
3725885a
RW		 7952010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
796
797 * configure: Regenerate.
798
d6416cdc
RW		 7992009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
800
81ecdfbb
RW		 801 * config.in: Regenerate.
802 * configure: Likewise.
803
d6416cdc
RW		 804 * configure: Regenerate.
805
b5bd9624
HPN		 8062008-07-11 Hans-Peter Nilsson <hp@axis.com>
807
808 * configure: Regenerate to track ../common/common.m4 changes.
809 * config.in: Ditto.
810
6efef468 8112008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 812 Daniel Jacobowitz <dan@codesourcery.com>
813 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 814
815 * configure: Regenerate.
816
60dc88db
RS		 8172007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
818
819 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
820 that unconditionally allows fmt_ps.
821 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
822 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
823 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
824 filter from 64,f to 32,f.
825 (PREFX): Change filter from 64 to 32.
826 (LDXC1, LUXC1): Provide separate mips32r2 implementations
827 that use do_load_double instead of do_load. Make both LUXC1
828 versions unpredictable if SizeFGR () != 64.
829 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
830 instead of do_store. Remove unused variable. Make both SUXC1
831 versions unpredictable if SizeFGR () != 64.
832
599ca73e
RS		 8332007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
834
835 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
836 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
837 shifts for that case.
838
2525df03
NC		 8392007-09-04 Nick Clifton <nickc@redhat.com>
840
841 * interp.c (options enum): Add OPTION_INFO_MEMORY.
842 (display_mem_info): New static variable.
843 (mips_option_handler): Handle OPTION_INFO_MEMORY.
844 (mips_options): Add info-memory and memory-info.
845 (sim_open): After processing the command line and board
846 specification, check display_mem_info. If it is set then
847 call the real handler for the --memory-info command line
848 switch.
849
35ee6e1e
JB		 8502007-08-24 Joel Brobecker <brobecker@adacore.com>
851
852 * configure.ac: Change license of multi-run.c to GPL version 3.
853 * configure: Regenerate.
854
d5fb0879
RS		 8552007-06-28 Richard Sandiford <richard@codesourcery.com>
856
857 * configure.ac, configure: Revert last patch.
858
2a2ce21b
RS		 8592007-06-26 Richard Sandiford <richard@codesourcery.com>
860
861 * configure.ac (sim_mipsisa3264_configs): New variable.
862 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
863 every configuration support all four targets, using the triplet to
864 determine the default.
865 * configure: Regenerate.
866
efdcccc9
RS		 8672007-06-25 Richard Sandiford <richard@codesourcery.com>
868
0a7692b2 869 * Makefile.in (m16run.o): New rule.
efdcccc9 870
f532a356
TS		 8712007-05-15 Thiemo Seufer <ths@mips.com>
872
873 * mips3264r2.igen (DSHD): Fix compile warning.
874
bfe9c90b
TS		 8752007-05-14 Thiemo Seufer <ths@mips.com>
876
877 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
878 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
879 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
880 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
881 for mips32r2.
882
53f4826b
TS		 8832007-03-01 Thiemo Seufer <ths@mips.com>
884
885 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
886 and mips64.
887
8bf3ddc8
TS		 8882007-02-20 Thiemo Seufer <ths@mips.com>
889
890 * dsp.igen: Update copyright notice.
891 * dsp2.igen: Fix copyright notice.
892
8b082fb1 8932007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 894 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 895
896 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
897 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
898 Add dsp2 to sim_igen_machine.
899 * configure: Regenerate.
900 * dsp.igen (do_ph_op): Add MUL support when op = 2.
901 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
902 (mulq_rs.ph): Use do_ph_mulq.
903 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
904 * mips.igen: Add dsp2 model and include dsp2.igen.
905 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
906 for *mips32r2, *mips64r2, *dsp.
907 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
908 for *mips32r2, *mips64r2, *dsp2.
909 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
910
b1004875 9112007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 912 Nigel Stephens <nigel@mips.com>
b1004875
TS		 913
914 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
915 jumps with hazard barrier.
916
f8df4c77 9172007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 918 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 919
920 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
921 after each call to sim_io_write.
922
b1004875 9232007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 924 Nigel Stephens <nigel@mips.com>
b1004875
TS		 925
926 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
927 supported by this simulator.
07802d98
TS		 928 (decode_coproc): Recognise additional CP0 Config registers
929 correctly.
930
14fb6c5a 9312007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 932 Nigel Stephens <nigel@mips.com>
933 David Ung <davidu@mips.com>
14fb6c5a
TS		 934
935 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
936 uninterpreted formats. If fmt is one of the uninterpreted types
937 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
938 fmt_word, and fmt_uninterpreted_64 like fmt_long.
939 (store_fpr): When writing an invalid odd register, set the
940 matching even register to fmt_unknown, not the following register.
941 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
942 the the memory window at offset 0 set by --memory-size command
943 line option.
944 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
945 point register.
946 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
947 register.
948 (sim_monitor): When returning the memory size to the MIPS
949 application, use the value in STATE_MEM_SIZE, not an arbitrary
950 hardcoded value.
951 (cop_lw): Don' mess around with FPR_STATE, just pass
952 fmt_uninterpreted_32 to StoreFPR.
953 (cop_sw): Similarly.
954 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
955 (cop_sd): Similarly.
956 * mips.igen (not_word_value): Single version for mips32, mips64
957 and mips16.
958
c8847145 9592007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 960 Nigel Stephens <nigel@mips.com>
c8847145
TS		 961
962 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
963 MBytes.
964
4b5d35ee
TS		 9652007-02-17 Thiemo Seufer <ths@mips.com>
966
967 * configure.ac (mips*-sde-elf*): Move in front of generic machine
968 configuration.
969 * configure: Regenerate.
970
3669427c
TS		 9712007-02-17 Thiemo Seufer <ths@mips.com>
972
973 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
974 Add mdmx to sim_igen_machine.
975 (mipsisa64*-*-*): Likewise. Remove dsp.
976 (mipsisa32*-*-*): Remove dsp.
977 * configure: Regenerate.
978
109ad085
TS		 9792007-02-13 Thiemo Seufer <ths@mips.com>
980
981 * configure.ac: Add mips*-sde-elf* target.
982 * configure: Regenerate.
983
921d7ad3
HPN		 9842006-12-21 Hans-Peter Nilsson <hp@axis.com>
985
986 * acconfig.h: Remove.
987 * config.in, configure: Regenerate.
988
02f97da7
TS		 9892006-11-07 Thiemo Seufer <ths@mips.com>
990
991 * dsp.igen (do_w_op): Fix compiler warning.
992
2d2733fc 9932006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 994 David Ung <davidu@mips.com>
2d2733fc
TS		 995
996 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
997 sim_igen_machine.
998 * configure: Regenerate.
999 * mips.igen (model): Add smartmips.
1000 (MADDU): Increment ACX if carry.
1001 (do_mult): Clear ACX.
1002 (ROR,RORV): Add smartmips.
72f4393d 1003 (include): Include smartmips.igen.
2d2733fc
TS		 1004 * sim-main.h (ACX): Set to REGISTERS[89].
1005 * smartmips.igen: New file.
1006
d85c3a10 10072006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 1008 David Ung <davidu@mips.com>
d85c3a10
TS		 1009
1010 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
1011 mips3264r2.igen. Add missing dependency rules.
1012 * m16e.igen: Support for mips16e save/restore instructions.
1013
e85e3205
RE		 10142006-06-13 Richard Earnshaw <rearnsha@arm.com>
1015
1016 * configure: Regenerated.
1017
2f0122dc
DJ		 10182006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
1019
1020 * configure: Regenerated.
1021
20e95c23
DJ		 10222006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
1023
1024 * configure: Regenerated.
1025
69088b17
CF		 10262006-05-15 Chao-ying Fu <fu@mips.com>
1027
1028 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
1029
0275de4e
NC		 10302006-04-18 Nick Clifton <nickc@redhat.com>
1031
1032 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
1033 statement.
1034
b3a3ffef
HPN		 10352006-03-29 Hans-Peter Nilsson <hp@axis.com>
1036
1037 * configure: Regenerate.
1038
40a5538e
CF		 10392005-12-14 Chao-ying Fu <fu@mips.com>
1040
1041 * Makefile.in (SIM_OBJS): Add dsp.o.
1042 (dsp.o): New dependency.
1043 (IGEN_INCLUDE): Add dsp.igen.
1044 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
1045 mipsisa64*-*-*): Add dsp to sim_igen_machine.
1046 * configure: Regenerate.
1047 * mips.igen: Add dsp model and include dsp.igen.
1048 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1049 because these instructions are extended in DSP ASE.
1050 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1051 adding 6 DSP accumulator registers and 1 DSP control register.
1052 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1053 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1054 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1055 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1056 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1057 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1058 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1059 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1060 DSPCR_CCOND_SMASK): New define.
1061 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1062 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1063
21d14896
ILT		 10642005-07-08 Ian Lance Taylor <ian@airs.com>
1065
1066 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1067
b16d63da 10682005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1069 Nigel Stephens <nigel@mips.com>
1070
1071 * mips.igen: New mips16e model and include m16e.igen.
1072 (check_u64): Add mips16e tag.
1073 * m16e.igen: New file for MIPS16e instructions.
1074 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1075 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1076 models.
1077 * configure: Regenerate.
b16d63da 1078
e70cb6cd 10792005-05-26 David Ung <davidu@mips.com>
72f4393d 1080
e70cb6cd
CD		 1081 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1082 tags to all instructions which are applicable to the new ISAs.
1083 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1084 vr.igen.
1085 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1086 instructions.
e70cb6cd
CD		 1087 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1088 to mips.igen.
1089 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1090 * configure: Regenerate.
72f4393d 1091
2b193c4a
MK		 10922005-03-23 Mark Kettenis <kettenis@gnu.org>
1093
1094 * configure: Regenerate.
1095
35695fd6
AC		 10962005-01-14 Andrew Cagney <cagney@gnu.org>
1097
1098 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1099 explicit call to AC_CONFIG_HEADER.
1100 * configure: Regenerate.
1101
f0569246
AC		 11022005-01-12 Andrew Cagney <cagney@gnu.org>
1103
1104 * configure.ac: Update to use ../common/common.m4.
1105 * configure: Re-generate.
1106
38f48d72
AC		 11072005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1108
1109 * configure: Regenerated to track ../common/aclocal.m4 changes.
1110
b7026657
AC		 11112005-01-07 Andrew Cagney <cagney@gnu.org>
1112
1113 * configure.ac: Rename configure.in, require autoconf 2.59.
1114 * configure: Re-generate.
1115
379832de
HPN		 11162004-12-08 Hans-Peter Nilsson <hp@axis.com>
1117
1118 * configure: Regenerate for ../common/aclocal.m4 update.
1119
cd62154c 11202004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1121
cd62154c
AC		 1122 Committed by Andrew Cagney.
1123 * m16.igen (CMP, CMPI): Fix assembler.
1124
e5da76ec
CD		 11252004-08-18 Chris Demetriou <cgd@broadcom.com>
1126
1127 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1128 * configure: Regenerate.
1129
139181c8
CD		 11302004-06-25 Chris Demetriou <cgd@broadcom.com>
1131
1132 * configure.in (sim_m16_machine): Include mipsIII.
1133 * configure: Regenerate.
1134
1a27f959
CD		 11352004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1136
72f4393d 1137 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1138 from COP0_BADVADDR.
1139 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1140
5dbb7b5a
CD		 11412004-04-10 Chris Demetriou <cgd@broadcom.com>
1142
1143 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1144
14234056
CD		 11452004-04-09 Chris Demetriou <cgd@broadcom.com>
1146
1147 * mips.igen (check_fmt): Remove.
1148 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1149 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1150 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1151 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1152 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1153 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1154 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1155 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1156 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1157 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1158
c6f9085c
CD		 11592004-04-09 Chris Demetriou <cgd@broadcom.com>
1160
1161 * sb1.igen (check_sbx): New function.
1162 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1163
11d66e66 11642004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1165 Richard Sandiford <rsandifo@redhat.com>
1166
1167 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1168 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1169 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1170 separate implementations for mipsIV and mipsV. Use new macros to
1171 determine whether the restrictions apply.
1172
b3208fb8
CD		 11732004-01-19 Chris Demetriou <cgd@broadcom.com>
1174
1175 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1176 (check_mult_hilo): Improve comments.
1177 (check_div_hilo): Likewise. Also, fork off a new version
1178 to handle mips32/mips64 (since there are no hazards to check
1179 in MIPS32/MIPS64).
1180
9a1d84fb
CD		 11812003-06-17 Richard Sandiford <rsandifo@redhat.com>
1182
1183 * mips.igen (do_dmultx): Fix check for negative operands.
1184
ae451ac6
ILT		 11852003-05-16 Ian Lance Taylor <ian@airs.com>
1186
1187 * Makefile.in (SHELL): Make sure this is defined.
1188 (various): Use $(SHELL) whenever we invoke move-if-change.
1189
dd69d292
CD		 11902003-05-03 Chris Demetriou <cgd@broadcom.com>
1191
1192 * cp1.c: Tweak attribution slightly.
1193 * cp1.h: Likewise.
1194 * mdmx.c: Likewise.
1195 * mdmx.igen: Likewise.
1196 * mips3d.igen: Likewise.
1197 * sb1.igen: Likewise.
1198
bcd0068e
CD		 11992003-04-15 Richard Sandiford <rsandifo@redhat.com>
1200
1201 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1202 unsigned operands.
1203
6b4a8935
AC		 12042003-02-27 Andrew Cagney <cagney@redhat.com>
1205
601da316
AC		 1206 * interp.c (sim_open): Rename _bfd to bfd.
1207 (sim_create_inferior): Ditto.
6b4a8935 1208
d29e330f
CD		 12092003-01-14 Chris Demetriou <cgd@broadcom.com>
1210
1211 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1212
a2353a08
CD		 12132003-01-14 Chris Demetriou <cgd@broadcom.com>
1214
1215 * mips.igen (EI, DI): Remove.
1216
80551777
CD		 12172003-01-05 Richard Sandiford <rsandifo@redhat.com>
1218
1219 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1220
4c54fc26
CD		 12212003-01-04 Richard Sandiford <rsandifo@redhat.com>
1222 Andrew Cagney <ac131313@redhat.com>
1223 Gavin Romig-Koch <gavin@redhat.com>
1224 Graydon Hoare <graydon@redhat.com>
1225 Aldy Hernandez <aldyh@redhat.com>
1226 Dave Brolley <brolley@redhat.com>
1227 Chris Demetriou <cgd@broadcom.com>
1228
1229 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1230 (sim_mach_default): New variable.
1231 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1232 Add a new simulator generator, MULTI.
1233 * configure: Regenerate.
1234 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1235 (multi-run.o): New dependency.
1236 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1237 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1238 (tmp-multi): Combine them.
1239 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1240 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1241 (distclean-extra): New rule.
1242 * sim-main.h: Include bfd.h.
1243 (MIPS_MACH): New macro.
1244 * mips.igen (vr4120, vr5400, vr5500): New models.
1245 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1246 * vr.igen: Replace with new version.
1247
e6c674b8
CD		 12482003-01-04 Chris Demetriou <cgd@broadcom.com>
1249
1250 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1251 * configure: Regenerate.
1252
28f50ac8
CD		 12532002-12-31 Chris Demetriou <cgd@broadcom.com>
1254
1255 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1256 * mips.igen: Remove all invocations of check_branch_bug and
1257 mark_branch_bug.
1258
5071ffe6
CD		 12592002-12-16 Chris Demetriou <cgd@broadcom.com>
1260
72f4393d 1261 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1262
06e7837e
CD		 12632002-07-30 Chris Demetriou <cgd@broadcom.com>
1264
1265 * mips.igen (do_load_double, do_store_double): New functions.
1266 (LDC1, SDC1): Rename to...
1267 (LDC1b, SDC1b): respectively.
1268 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1269
2265c243
MS		 12702002-07-29 Michael Snyder <msnyder@redhat.com>
1271
1272 * cp1.c (fp_recip2): Modify initialization expression so that
1273 GCC will recognize it as constant.
1274
a2f8b4f3
CD		 12752002-06-18 Chris Demetriou <cgd@broadcom.com>
1276
1277 * mdmx.c (SD_): Delete.
1278 (Unpredictable): Re-define, for now, to directly invoke
1279 unpredictable_action().
1280 (mdmx_acc_op): Fix error in .ob immediate handling.
1281
b4b6c939
AC		 12822002-06-18 Andrew Cagney <cagney@redhat.com>
1283
1284 * interp.c (sim_firmware_command): Initialize `address'.
1285
c8cca39f
AC		 12862002-06-16 Andrew Cagney <ac131313@redhat.com>
1287
1288 * configure: Regenerated to track ../common/aclocal.m4 changes.
1289
e7e81181 12902002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1291 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1292
1293 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1294 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1295 * mips.igen: Include mips3d.igen.
1296 (mips3d): New model name for MIPS-3D ASE instructions.
1297 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1298 instructions.
e7e81181
CD		 1299 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1300 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1301 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1302 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1303 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1304 (RSquareRoot1, RSquareRoot2): New macros.
1305 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1306 (fp_rsqrt2): New functions.
1307 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1308 * configure: Regenerate.
1309
3a2b820e 13102002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1311 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1312
1313 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1314 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1315 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1316 (convert): Note that this function is not used for paired-single
1317 format conversions.
1318 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1319 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1320 (check_fmt_p): Enable paired-single support.
1321 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1322 (PUU.PS): New instructions.
1323 (CVT.S.fmt): Don't use this instruction for paired-single format
1324 destinations.
1325 * sim-main.h (FP_formats): New value 'fmt_ps.'
1326 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1327 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1328
d18ea9c2
CD		 13292002-06-12 Chris Demetriou <cgd@broadcom.com>
1330
1331 * mips.igen: Fix formatting of function calls in
1332 many FP operations.
1333
95fd5cee
CD		 13342002-06-12 Chris Demetriou <cgd@broadcom.com>
1335
1336 * mips.igen (MOVN, MOVZ): Trace result.
1337 (TNEI): Print "tnei" as the opcode name in traces.
1338 (CEIL.W): Add disassembly string for traces.
1339 (RSQRT.fmt): Make location of disassembly string consistent
1340 with other instructions.
1341
4f0d55ae
CD		 13422002-06-12 Chris Demetriou <cgd@broadcom.com>
1343
1344 * mips.igen (X): Delete unused function.
1345
3c25f8c7
AC		 13462002-06-08 Andrew Cagney <cagney@redhat.com>
1347
1348 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1349
f3c08b7e 13502002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1351 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1352
1353 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1354 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1355 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1356 (fp_nmsub): New prototypes.
1357 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1358 (NegMultiplySub): New defines.
1359 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1360 (MADD.D, MADD.S): Replace with...
1361 (MADD.fmt): New instruction.
1362 (MSUB.D, MSUB.S): Replace with...
1363 (MSUB.fmt): New instruction.
1364 (NMADD.D, NMADD.S): Replace with...
1365 (NMADD.fmt): New instruction.
1366 (NMSUB.D, MSUB.S): Replace with...
1367 (NMSUB.fmt): New instruction.
1368
52714ff9 13692002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1370 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1371
1372 * cp1.c: Fix more comment spelling and formatting.
1373 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1374 (denorm_mode): New function.
1375 (fpu_unary, fpu_binary): Round results after operation, collect
1376 status from rounding operations, and update the FCSR.
1377 (convert): Collect status from integer conversions and rounding
1378 operations, and update the FCSR. Adjust NaN values that result
1379 from conversions. Convert to use sim_io_eprintf rather than
1380 fprintf, and remove some debugging code.
1381 * cp1.h (fenr_FS): New define.
1382
577d8c4b
CD		 13832002-06-07 Chris Demetriou <cgd@broadcom.com>
1384
1385 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1386 rounding mode to sim FP rounding mode flag conversion code into...
1387 (rounding_mode): New function.
1388
196496ed
CD		 13892002-06-07 Chris Demetriou <cgd@broadcom.com>
1390
1391 * cp1.c: Clean up formatting of a few comments.
1392 (value_fpr): Reformat switch statement.
1393
cfe9ea23 13942002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1395 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1396
1397 * cp1.h: New file.
1398 * sim-main.h: Include cp1.h.
1399 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1400 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1401 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1402 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1403 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1404 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1405 * cp1.c: Don't include sim-fpu.h; already included by
1406 sim-main.h. Clean up formatting of some comments.
1407 (NaN, Equal, Less): Remove.
1408 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1409 (fp_cmp): New functions.
1410 * mips.igen (do_c_cond_fmt): Remove.
1411 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1412 Compare. Add result tracing.
1413 (CxC1): Remove, replace with...
1414 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1415 (DMxC1): Remove, replace with...
1416 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1417 (MxC1): Remove, replace with...
1418 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1419
ee7254b0
CD		 14202002-06-04 Chris Demetriou <cgd@broadcom.com>
1421
1422 * sim-main.h (FGRIDX): Remove, replace all uses with...
1423 (FGR_BASE): New macro.
1424 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1425 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1426 (NR_FGR, FGR): Likewise.
1427 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1428 * mips.igen: Likewise.
1429
d3eb724f
CD		 14302002-06-04 Chris Demetriou <cgd@broadcom.com>
1431
1432 * cp1.c: Add an FSF Copyright notice to this file.
1433
ba46ddd0 14342002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1435 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1436
1437 * cp1.c (Infinity): Remove.
1438 * sim-main.h (Infinity): Likewise.
1439
1440 * cp1.c (fp_unary, fp_binary): New functions.
1441 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1442 (fp_sqrt): New functions, implemented in terms of the above.
1443 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1444 (Recip, SquareRoot): Remove (replaced by functions above).
1445 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1446 (fp_recip, fp_sqrt): New prototypes.
1447 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1448 (Recip, SquareRoot): Replace prototypes with #defines which
1449 invoke the functions above.
72f4393d 1450
18d8a52d
CD		 14512002-06-03 Chris Demetriou <cgd@broadcom.com>
1452
1453 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1454 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1455 file, remove PARAMS from prototypes.
1456 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1457 simulator state arguments.
1458 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1459 pass simulator state arguments.
1460 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1461 (store_fpr, convert): Remove 'sd' argument.
1462 (value_fpr): Likewise. Convert to use 'SD' instead.
1463
0f154cbd
CD		 14642002-06-03 Chris Demetriou <cgd@broadcom.com>
1465
1466 * cp1.c (Min, Max): Remove #if 0'd functions.
1467 * sim-main.h (Min, Max): Remove.
1468
e80fc152
CD		 14692002-06-03 Chris Demetriou <cgd@broadcom.com>
1470
1471 * cp1.c: fix formatting of switch case and default labels.
1472 * interp.c: Likewise.
1473 * sim-main.c: Likewise.
1474
bad673a9
CD		 14752002-06-03 Chris Demetriou <cgd@broadcom.com>
1476
1477 * cp1.c: Clean up comments which describe FP formats.
1478 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1479
7cbea089 14802002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1481 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1482
1483 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1484 Broadcom SiByte SB-1 processor configurations.
1485 * configure: Regenerate.
1486 * sb1.igen: New file.
1487 * mips.igen: Include sb1.igen.
1488 (sb1): New model.
1489 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1490 * mdmx.igen: Add "sb1" model to all appropriate functions and
1491 instructions.
1492 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1493 (ob_func, ob_acc): Reference the above.
1494 (qh_acc): Adjust to keep the same size as ob_acc.
1495 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1496 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1497
909daa82
CD		 14982002-06-03 Chris Demetriou <cgd@broadcom.com>
1499
1500 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1501
f4f1b9f1 15022002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1503 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1504
1505 * mips.igen (mdmx): New (pseudo-)model.
1506 * mdmx.c, mdmx.igen: New files.
1507 * Makefile.in (SIM_OBJS): Add mdmx.o.
1508 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1509 New typedefs.
1510 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1511 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1512 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1513 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1514 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1515 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1516 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1517 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1518 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1519 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1520 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1521 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1522 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1523 (qh_fmtsel): New macros.
1524 (_sim_cpu): New member "acc".
1525 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1526 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1527
5accf1ff
CD		 15282002-05-01 Chris Demetriou <cgd@broadcom.com>
1529
1530 * interp.c: Use 'deprecated' rather than 'depreciated.'
1531 * sim-main.h: Likewise.
1532
402586aa
CD		 15332002-05-01 Chris Demetriou <cgd@broadcom.com>
1534
1535 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1536 which wouldn't compile anyway.
1537 * sim-main.h (unpredictable_action): New function prototype.
1538 (Unpredictable): Define to call igen function unpredictable().
1539 (NotWordValue): New macro to call igen function not_word_value().
1540 (UndefinedResult): Remove.
1541 * interp.c (undefined_result): Remove.
1542 (unpredictable_action): New function.
1543 * mips.igen (not_word_value, unpredictable): New functions.
1544 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1545 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1546 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1547 NotWordValue() to check for unpredictable inputs, then
1548 Unpredictable() to handle them.
1549
c9b9995a
CD		 15502002-02-24 Chris Demetriou <cgd@broadcom.com>
1551
1552 * mips.igen: Fix formatting of calls to Unpredictable().
1553
e1015982
AC		 15542002-04-20 Andrew Cagney <ac131313@redhat.com>
1555
1556 * interp.c (sim_open): Revert previous change.
1557
b882a66b
AO		 15582002-04-18 Alexandre Oliva <aoliva@redhat.com>
1559
1560 * interp.c (sim_open): Disable chunk of code that wrote code in
1561 vector table entries.
1562
c429b7dd
CD		 15632002-03-19 Chris Demetriou <cgd@broadcom.com>
1564
1565 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1566 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1567 unused definitions.
1568
37d146fa
CD		 15692002-03-19 Chris Demetriou <cgd@broadcom.com>
1570
1571 * cp1.c: Fix many formatting issues.
1572
07892c0b
CD		 15732002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1574
1575 * cp1.c (fpu_format_name): New function to replace...
1576 (DOFMT): This. Delete, and update all callers.
1577 (fpu_rounding_mode_name): New function to replace...
1578 (RMMODE): This. Delete, and update all callers.
1579
487f79b7
CD		 15802002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1581
1582 * interp.c: Move FPU support routines from here to...
1583 * cp1.c: Here. New file.
1584 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1585 (cp1.o): New target.
1586
1e799e28
CD		 15872002-03-12 Chris Demetriou <cgd@broadcom.com>
1588
1589 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1590 * mips.igen (mips32, mips64): New models, add to all instructions
1591 and functions as appropriate.
1592 (loadstore_ea, check_u64): New variant for model mips64.
1593 (check_fmt_p): New variant for models mipsV and mips64, remove
1594 mipsV model marking fro other variant.
1595 (SLL) Rename to...
1596 (SLLa) this.
1597 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1598 for mips32 and mips64.
1599 (DCLO, DCLZ): New instructions for mips64.
1600
82f728db
CD		 16012002-03-07 Chris Demetriou <cgd@broadcom.com>
1602
1603 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1604 immediate or code as a hex value with the "%#lx" format.
1605 (ANDI): Likewise, and fix printed instruction name.
1606
b96e7ef1
CD		 16072002-03-05 Chris Demetriou <cgd@broadcom.com>
1608
1609 * sim-main.h (UndefinedResult, Unpredictable): New macros
1610 which currently do nothing.
1611
d35d4f70
CD		 16122002-03-05 Chris Demetriou <cgd@broadcom.com>
1613
1614 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1615 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1616 (status_CU3): New definitions.
1617
1618 * sim-main.h (ExceptionCause): Add new values for MIPS32
1619 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1620 for DebugBreakPoint and NMIReset to note their status in
1621 MIPS32 and MIPS64.
1622 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1623 (SignalExceptionCacheErr): New exception macros.
1624
3ad6f714
CD		 16252002-03-05 Chris Demetriou <cgd@broadcom.com>
1626
1627 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1628 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1629 is always enabled.
1630 (SignalExceptionCoProcessorUnusable): Take as argument the
1631 unusable coprocessor number.
1632
86b77b47
CD		 16332002-03-05 Chris Demetriou <cgd@broadcom.com>
1634
1635 * mips.igen: Fix formatting of all SignalException calls.
1636
97a88e93 16372002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1638
1639 * sim-main.h (SIGNEXTEND): Remove.
1640
97a88e93 16412002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1642
1643 * mips.igen: Remove gencode comment from top of file, fix
1644 spelling in another comment.
1645
97a88e93 16462002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1647
1648 * mips.igen (check_fmt, check_fmt_p): New functions to check
1649 whether specific floating point formats are usable.
1650 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1651 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1652 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1653 Use the new functions.
1654 (do_c_cond_fmt): Remove format checks...
1655 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1656
97a88e93 16572002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1658
1659 * mips.igen: Fix formatting of check_fpu calls.
1660
41774c9d
CD		 16612002-03-03 Chris Demetriou <cgd@broadcom.com>
1662
1663 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1664
4a0bd876
CD		 16652002-03-03 Chris Demetriou <cgd@broadcom.com>
1666
1667 * mips.igen: Remove whitespace at end of lines.
1668
09297648
CD		 16692002-03-02 Chris Demetriou <cgd@broadcom.com>
1670
1671 * mips.igen (loadstore_ea): New function to do effective
1672 address calculations.
1673 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1674 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1675 CACHE): Use loadstore_ea to do effective address computations.
1676
043b7057
CD		 16772002-03-02 Chris Demetriou <cgd@broadcom.com>
1678
1679 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1680 * mips.igen (LL, CxC1, MxC1): Likewise.
1681
c1e8ada4
CD		 16822002-03-02 Chris Demetriou <cgd@broadcom.com>
1683
1684 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1685 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1686 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1687 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1688 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1689 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1690 Don't split opcode fields by hand, use the opcode field values
1691 provided by igen.
1692
3e1dca16
CD		 16932002-03-01 Chris Demetriou <cgd@broadcom.com>
1694
1695 * mips.igen (do_divu): Fix spacing.
1696
1697 * mips.igen (do_dsllv): Move to be right before DSLLV,
1698 to match the rest of the do_<shift> functions.
1699
fff8d27d
CD		 17002002-03-01 Chris Demetriou <cgd@broadcom.com>
1701
1702 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1703 DSRL32, do_dsrlv): Trace inputs and results.
1704
0d3e762b
CD		 17052002-03-01 Chris Demetriou <cgd@broadcom.com>
1706
1707 * mips.igen (CACHE): Provide instruction-printing string.
1708
1709 * interp.c (signal_exception): Comment tokens after #endif.
1710
eb5fcf93
CD		 17112002-02-28 Chris Demetriou <cgd@broadcom.com>
1712
1713 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1714 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1715 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1716 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1717 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1718 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1719 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1720 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1721
bb22bd7d
CD		 17222002-02-28 Chris Demetriou <cgd@broadcom.com>
1723
1724 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1725 instruction-printing string.
1726 (LWU): Use '64' as the filter flag.
1727
91a177cf
CD		 17282002-02-28 Chris Demetriou <cgd@broadcom.com>
1729
1730 * mips.igen (SDXC1): Fix instruction-printing string.
1731
387f484a
CD		 17322002-02-28 Chris Demetriou <cgd@broadcom.com>
1733
1734 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1735 filter flags "32,f".
1736
3d81f391
CD		 17372002-02-27 Chris Demetriou <cgd@broadcom.com>
1738
1739 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1740 as the filter flag.
1741
af5107af
CD		 17422002-02-27 Chris Demetriou <cgd@broadcom.com>
1743
1744 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1745 add a comma) so that it more closely match the MIPS ISA
1746 documentation opcode partitioning.
1747 (PREF): Put useful names on opcode fields, and include
1748 instruction-printing string.
1749
ca971540
CD		 17502002-02-27 Chris Demetriou <cgd@broadcom.com>
1751
1752 * mips.igen (check_u64): New function which in the future will
1753 check whether 64-bit instructions are usable and signal an
1754 exception if not. Currently a no-op.
1755 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1756 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1757 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1758 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1759
1760 * mips.igen (check_fpu): New function which in the future will
1761 check whether FPU instructions are usable and signal an exception
1762 if not. Currently a no-op.
1763 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1764 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1765 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1766 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1767 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1768 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1769 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1770 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1771
1c47a468
CD		 17722002-02-27 Chris Demetriou <cgd@broadcom.com>
1773
1774 * mips.igen (do_load_left, do_load_right): Move to be immediately
1775 following do_load.
1776 (do_store_left, do_store_right): Move to be immediately following
1777 do_store.
1778
603a98e7
CD		 17792002-02-27 Chris Demetriou <cgd@broadcom.com>
1780
1781 * mips.igen (mipsV): New model name. Also, add it to
1782 all instructions and functions where it is appropriate.
1783
c5d00cc7
CD		 17842002-02-18 Chris Demetriou <cgd@broadcom.com>
1785
1786 * mips.igen: For all functions and instructions, list model
1787 names that support that instruction one per line.
1788
074e9cb8
CD		 17892002-02-11 Chris Demetriou <cgd@broadcom.com>
1790
1791 * mips.igen: Add some additional comments about supported
1792 models, and about which instructions go where.
1793 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1794 order as is used in the rest of the file.
1795
9805e229
CD		 17962002-02-11 Chris Demetriou <cgd@broadcom.com>
1797
1798 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1799 indicating that ALU32_END or ALU64_END are there to check
1800 for overflow.
1801 (DADD): Likewise, but also remove previous comment about
1802 overflow checking.
1803
f701dad2
CD		 18042002-02-10 Chris Demetriou <cgd@broadcom.com>
1805
1806 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1807 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1808 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1809 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1810 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1811 fields (i.e., add and move commas) so that they more closely
1812 match the MIPS ISA documentation opcode partitioning.
1813
18142002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1815
72f4393d
L		 1816 * mips.igen (ADDI): Print immediate value.
1817 (BREAK): Print code.
1818 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1819 (SLL): Print "nop" specially, and don't run the code
1820 that does the shift for the "nop" case.
20ae0098 1821
9e52972e
FF		 18222001-11-17 Fred Fish <fnf@redhat.com>
1823
1824 * sim-main.h (float_operation): Move enum declaration outside
1825 of _sim_cpu struct declaration.
1826
c0efbca4
JB		 18272001-04-12 Jim Blandy <jimb@redhat.com>
1828
1829 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1830 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1831 set of the FCSR.
1832 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1833 PENDING_FILL, and you can get the intended effect gracefully by
1834 calling PENDING_SCHED directly.
1835
fb891446
BE		 18362001-02-23 Ben Elliston <bje@redhat.com>
1837
1838 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1839 already defined elsewhere.
1840
8030f857
BE		 18412001-02-19 Ben Elliston <bje@redhat.com>
1842
1843 * sim-main.h (sim_monitor): Return an int.
1844 * interp.c (sim_monitor): Add return values.
1845 (signal_exception): Handle error conditions from sim_monitor.
1846
56b48a7a
CD		 18472001-02-08 Ben Elliston <bje@redhat.com>
1848
1849 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1850 (store_memory): Likewise, pass cia to sim_core_write*.
1851
d3ee60d9
FCE		 18522000-10-19 Frank Ch. Eigler <fche@redhat.com>
1853
1854 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1855 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1856
071da002
AC		 1857Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1858
1859 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1860 * Makefile.in: Don't delete *.igen when cleaning directory.
1861
a28c02cd
AC		 1862Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1863
1864 * m16.igen (break): Call SignalException not sim_engine_halt.
1865
80ee11fa
AC		 1866Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1867
1868 From Jason Eckhardt:
1869 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1870
673388c0
AC		 1871Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1872
1873 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1874
4c0deff4
NC		 18752000-05-24 Michael Hayes <mhayes@cygnus.com>
1876
1877 * mips.igen (do_dmultx): Fix typo.
1878
eb2d80b4
AC		 1879Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1880
1881 * configure: Regenerated to track ../common/aclocal.m4 changes.
1882
dd37a34b
AC		 1883Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1884
1885 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1886
4c0deff4
NC		 18872000-04-12 Frank Ch. Eigler <fche@redhat.com>
1888
1889 * sim-main.h (GPR_CLEAR): Define macro.
1890
e30db738
AC		 1891Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1892
1893 * interp.c (decode_coproc): Output long using %lx and not %s.
1894
cb7450ea
FCE		 18952000-03-21 Frank Ch. Eigler <fche@redhat.com>
1896
1897 * interp.c (sim_open): Sort & extend dummy memory regions for
1898 --board=jmr3904 for eCos.
1899
a3027dd7
FCE		 19002000-03-02 Frank Ch. Eigler <fche@redhat.com>
1901
1902 * configure: Regenerated.
1903
1904Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1905
1906 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1907 calls, conditional on the simulator being in verbose mode.
1908
dfcd3bfb
JM		 1909Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1910
1911 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1912 cache don't get ReservedInstruction traps.
1913
c2d11a7d
JM		 19141999-11-29 Mark Salter <msalter@cygnus.com>
1915
1916 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1917 to clear status bits in sdisr register. This is how the hardware works.
1918
1919 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1920 being used by cygmon.
1921
4ce44c66
JM		 19221999-11-11 Andrew Haley <aph@cygnus.com>
1923
1924 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1925 instructions.
1926
cff3e48b
JM		 1927Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1928
1929 * mips.igen (MULT): Correct previous mis-applied patch.
1930
d4f3574e
SS		 1931Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1932
1933 * mips.igen (delayslot32): Handle sequence like
1934 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1935 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1936 (MULT): Actually pass the third register...
1937
19381999-09-03 Mark Salter <msalter@cygnus.com>
1939
1940 * interp.c (sim_open): Added more memory aliases for additional
1941 hardware being touched by cygmon on jmr3904 board.
1942
1943Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1944
1945 * configure: Regenerated to track ../common/aclocal.m4 changes.
1946
a0b3c4fd
JM		 1947Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1948
1949 * interp.c (sim_store_register): Handle case where client - GDB -
1950 specifies that a 4 byte register is 8 bytes in size.
1951 (sim_fetch_register): Ditto.
72f4393d 1952
adf40b2e
JM		 19531999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1954
1955 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1956 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1957 (idt_monitor_base): Base address for IDT monitor traps.
1958 (pmon_monitor_base): Ditto for PMON.
1959 (lsipmon_monitor_base): Ditto for LSI PMON.
1960 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1961 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1962 (sim_firmware_command): New function.
1963 (mips_option_handler): Call it for OPTION_FIRMWARE.
1964 (sim_open): Allocate memory for idt_monitor region. If "--board"
1965 option was given, add no monitor by default. Add BREAK hooks only if
1966 monitors are also there.
72f4393d 1967
43e526b9
JM		 1968Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1969
1970 * interp.c (sim_monitor): Flush output before reading input.
1971
1972Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1973
1974 * tconfig.in (SIM_HANDLES_LMA): Always define.
1975
1976Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1977
1978 From Mark Salter <msalter@cygnus.com>:
1979 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1980 (sim_open): Add setup for BSP board.
1981
9846de1b
JM		 1982Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1983
1984 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1985 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1986 them as unimplemented.
1987
cd0fc7c3
SS		 19881999-05-08 Felix Lee <flee@cygnus.com>
1989
1990 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1991
7a292a7a
SS		 19921999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1993
1994 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1995
1996Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1997
1998 * configure.in: Any mips64vr5*-*-* target should have
1999 -DTARGET_ENABLE_FR=1.
2000 (default_endian): Any mips64vr*el-*-* target should default to
2001 LITTLE_ENDIAN.
2002 * configure: Re-generate.
2003
20041999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
2005
2006 * mips.igen (ldl): Extend from _16_, not 32.
2007
2008Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
2009
2010 * interp.c (sim_store_register): Force registers written to by GDB
2011 into an un-interpreted state.
2012
c906108c
SS		 20131999-02-05 Frank Ch. Eigler <fche@cygnus.com>
2014
2015 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
2016 CPU, start periodic background I/O polls.
72f4393d 2017 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 2018
20191998-12-30 Frank Ch. Eigler <fche@cygnus.com>
2020
2021 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 2022
c906108c
SS		 2023Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
2024
2025 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
2026 case statement.
2027
20281998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 2029
2030 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 2031 (load_word): Call SIM_CORE_SIGNAL hook on error.
2032 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
2033 starting. For exception dispatching, pass PC instead of NULL_CIA.
2034 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 2035 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 2036 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
2037 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 2038 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 2039 * mips.igen (*): Replace memory-related SignalException* calls
2040 with references to SIM_CORE_SIGNAL hook.
72f4393d 2041
c906108c
SS		 2042 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
2043 fix.
2044 * sim-main.c (*): Minor warning cleanups.
72f4393d 2045
c906108c
SS		 20461998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2047
2048 * m16.igen (DADDIU5): Correct type-o.
2049
2050Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2051
2052 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2053 variables.
2054
2055Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2056
2057 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2058 to include path.
2059 (interp.o): Add dependency on itable.h
2060 (oengine.c, gencode): Delete remaining references.
2061 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2062
c906108c 20631998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2064
c906108c
SS		 2065 * vr4run.c: New.
2066 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2067 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2068 tmp-run-hack) : New.
2069 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2070 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2071 Drop the "64" qualifier to get the HACK generator working.
2072 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2073 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2074 qualifier to get the hack generator working.
2075 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2076 (DSLL): Use do_dsll.
2077 (DSLLV): Use do_dsllv.
2078 (DSRA): Use do_dsra.
2079 (DSRL): Use do_dsrl.
2080 (DSRLV): Use do_dsrlv.
2081 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2082 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2083 get the HACK generator working.
2084 (MACC) Rename to get the HACK generator working.
2085 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2086
c906108c
SS		 20871998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2088
2089 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2090 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2091
c906108c
SS		 20921998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2093
2094 * mips/interp.c (DEBUG): Cleanups.
2095
20961998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2097
2098 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2099 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2100
c906108c
SS		 21011998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2102
2103 * interp.c (sim_close): Uninstall modules.
2104
2105Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2106
2107 * sim-main.h, interp.c (sim_monitor): Change to global
2108 function.
2109
2110Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2111
2112 * configure.in (vr4100): Only include vr4100 instructions in
2113 simulator.
2114 * configure: Re-generate.
2115 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2116
2117Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2118
2119 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2120 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2121 true alternative.
2122
2123 * configure.in (sim_default_gen, sim_use_gen): Replace with
2124 sim_gen.
2125 (--enable-sim-igen): Delete config option. Always using IGEN.
2126 * configure: Re-generate.
72f4393d 2127
c906108c
SS		 2128 * Makefile.in (gencode): Kill, kill, kill.
2129 * gencode.c: Ditto.
72f4393d 2130
c906108c
SS		 2131Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2132
2133 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2134 bit mips16 igen simulator.
2135 * configure: Re-generate.
2136
2137 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2138 as part of vr4100 ISA.
2139 * vr.igen: Mark all instructions as 64 bit only.
2140
2141Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2142
2143 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2144 Pacify GCC.
2145
2146Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2147
2148 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2149 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2150 * configure: Re-generate.
2151
2152 * m16.igen (BREAK): Define breakpoint instruction.
2153 (JALX32): Mark instruction as mips16 and not r3900.
2154 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2155
2156 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2157
2158Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2159
2160 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2161 insn as a debug breakpoint.
2162
2163 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2164 pending.slot_size.
2165 (PENDING_SCHED): Clean up trace statement.
2166 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2167 (PENDING_FILL): Delay write by only one cycle.
2168 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2169
2170 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2171 of pending writes.
2172 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2173 32 & 64.
2174 (pending_tick): Move incrementing of index to FOR statement.
2175 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2176
c906108c
SS		 2177 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2178 build simulator.
2179 * configure: Re-generate.
72f4393d 2180
c906108c
SS		 2181 * interp.c (sim_engine_run OLD): Delete explicit call to
2182 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2183
c906108c
SS		 2184Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2185
2186 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2187 interrupt level number to match changed SignalExceptionInterrupt
2188 macro.
2189
2190Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2191
2192 * interp.c: #include "itable.h" if WITH_IGEN.
2193 (get_insn_name): New function.
2194 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2195 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2196
2197Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2198
2199 * configure: Rebuilt to inhale new common/aclocal.m4.
2200
2201Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2202
2203 * dv-tx3904sio.c: Include sim-assert.h.
2204
2205Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2206
2207 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2208 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2209 Reorganize target-specific sim-hardware checks.
2210 * configure: rebuilt.
2211 * interp.c (sim_open): For tx39 target boards, set
2212 OPERATING_ENVIRONMENT, add tx3904sio devices.
2213 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2214 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2215
c906108c
SS		 2216 * dv-tx3904irc.c: Compiler warning clean-up.
2217 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2218 frequent hw-trace messages.
2219
2220Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2221
2222 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2223
2224Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2225
2226 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2227
2228 * vr.igen: New file.
2229 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2230 * mips.igen: Define vr4100 model. Include vr.igen.
2231Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2232
2233 * mips.igen (check_mf_hilo): Correct check.
2234
2235Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2236
2237 * sim-main.h (interrupt_event): Add prototype.
2238
2239 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2240 register_ptr, register_value.
2241 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2242
2243 * sim-main.h (tracefh): Make extern.
2244
2245Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2246
2247 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2248 Reduce unnecessarily high timer event frequency.
c906108c 2249 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2250
c906108c
SS		 2251Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2252
2253 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2254 to allay warnings.
2255 (interrupt_event): Made non-static.
72f4393d 2256
c906108c
SS		 2257 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2258 interchange of configuration values for external vs. internal
2259 clock dividers.
72f4393d 2260
c906108c
SS		 2261Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2262
72f4393d 2263 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2264 simulator-reserved break instructions.
2265 * gencode.c (build_instruction): Ditto.
2266 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2267 reserved instructions now use exception vector, rather
c906108c
SS		 2268 than halting sim.
2269 * sim-main.h: Moved magic constants to here.
2270
2271Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2272
2273 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2274 register upon non-zero interrupt event level, clear upon zero
2275 event value.
2276 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2277 by passing zero event value.
2278 (*_io_{read,write}_buffer): Endianness fixes.
2279 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2280 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2281
2282 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2283 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2284
c906108c
SS		 2285Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2286
72f4393d 2287 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2288 and BigEndianCPU.
2289
2290Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2291
2292 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2293 parts.
2294 * configure: Update.
2295
2296Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2297
2298 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2299 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2300 * configure.in: Include tx3904tmr in hw_device list.
2301 * configure: Rebuilt.
2302 * interp.c (sim_open): Instantiate three timer instances.
2303 Fix address typo of tx3904irc instance.
2304
2305Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2306
2307 * interp.c (signal_exception): SystemCall exception now uses
2308 the exception vector.
2309
2310Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2311
2312 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2313 to allay warnings.
2314
2315Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2316
2317 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2318
2319Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2320
2321 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2322
2323 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2324 sim-main.h. Declare a struct hw_descriptor instead of struct
2325 hw_device_descriptor.
2326
2327Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2328
2329 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2330 right bits and then re-align left hand bytes to correct byte
2331 lanes. Fix incorrect computation in do_store_left when loading
2332 bytes from second word.
2333
2334Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2335
2336 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2337 * interp.c (sim_open): Only create a device tree when HW is
2338 enabled.
2339
2340 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2341 * interp.c (signal_exception): Ditto.
2342
2343Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2344
2345 * gencode.c: Mark BEGEZALL as LIKELY.
2346
2347Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2348
2349 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2350 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2351
c906108c
SS		 2352Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2353
2354 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2355 modules. Recognize TX39 target with "mips*tx39" pattern.
2356 * configure: Rebuilt.
2357 * sim-main.h (*): Added many macros defining bits in
2358 TX39 control registers.
2359 (SignalInterrupt): Send actual PC instead of NULL.
2360 (SignalNMIReset): New exception type.
2361 * interp.c (board): New variable for future use to identify
2362 a particular board being simulated.
2363 (mips_option_handler,mips_options): Added "--board" option.
2364 (interrupt_event): Send actual PC.
2365 (sim_open): Make memory layout conditional on board setting.
2366 (signal_exception): Initial implementation of hardware interrupt
2367 handling. Accept another break instruction variant for simulator
2368 exit.
2369 (decode_coproc): Implement RFE instruction for TX39.
2370 (mips.igen): Decode RFE instruction as such.
2371 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2372 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2373 bbegin to implement memory map.
2374 * dv-tx3904cpu.c: New file.
2375 * dv-tx3904irc.c: New file.
2376
2377Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2378
2379 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2380
2381Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2382
2383 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2384 with calls to check_div_hilo.
2385
2386Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2387
2388 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2389 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2390 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2391 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2392 with calls to check_mult_hilo.
2393 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2394 with calls to check_div_hilo.
2395
2396Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2397
2398 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2399 Document a replacement.
2400
2401Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2402
2403 * interp.c (sim_monitor): Make mon_printf work.
2404
2405Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2406
2407 * sim-main.h (INSN_NAME): New arg `cpu'.
2408
2409Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2410
72f4393d 2411 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2412
2413Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2414
2415 * configure: Regenerated to track ../common/aclocal.m4 changes.
2416 * config.in: Ditto.
2417
2418Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2419
2420 * acconfig.h: New file.
2421 * configure.in: Reverted change of Apr 24; use sinclude again.
2422
2423Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2424
2425 * configure: Regenerated to track ../common/aclocal.m4 changes.
2426 * config.in: Ditto.
2427
2428Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2429
2430 * configure.in: Don't call sinclude.
2431
2432Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2433
2434 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2435
2436Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2437
2438 * mips.igen (ERET): Implement.
2439
2440 * interp.c (decode_coproc): Return sign-extended EPC.
2441
2442 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2443
2444 * interp.c (signal_exception): Do not ignore Trap.
2445 (signal_exception): On TRAP, restart at exception address.
2446 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2447 (signal_exception): Update.
2448 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2449 so that TRAP instructions are caught.
2450
2451Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2452
2453 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2454 contains HI/LO access history.
2455 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2456 (HIACCESS, LOACCESS): Delete, replace with
2457 (HIHISTORY, LOHISTORY): New macros.
2458 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2459
c906108c
SS		 2460 * gencode.c (build_instruction): Do not generate checks for
2461 correct HI/LO register usage.
2462
2463 * interp.c (old_engine_run): Delete checks for correct HI/LO
2464 register usage.
2465
2466 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2467 check_mf_cycles): New functions.
2468 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2469 do_divu, domultx, do_mult, do_multu): Use.
2470
2471 * tx.igen ("madd", "maddu"): Use.
72f4393d 2472
c906108c
SS		 2473Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2474
2475 * mips.igen (DSRAV): Use function do_dsrav.
2476 (SRAV): Use new function do_srav.
2477
2478 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2479 (B): Sign extend 11 bit immediate.
2480 (EXT-B*): Shift 16 bit immediate left by 1.
2481 (ADDIU*): Don't sign extend immediate value.
2482
2483Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2484
2485 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2486
2487 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2488 functions.
2489
2490 * mips.igen (delayslot32, nullify_next_insn): New functions.
2491 (m16.igen): Always include.
2492 (do_*): Add more tracing.
2493
2494 * m16.igen (delayslot16): Add NIA argument, could be called by a
2495 32 bit MIPS16 instruction.
72f4393d 2496
c906108c
SS		 2497 * interp.c (ifetch16): Move function from here.
2498 * sim-main.c (ifetch16): To here.
72f4393d 2499
c906108c
SS		 2500 * sim-main.c (ifetch16, ifetch32): Update to match current
2501 implementations of LH, LW.
2502 (signal_exception): Don't print out incorrect hex value of illegal
2503 instruction.
2504
2505Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2506
2507 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2508 instruction.
2509
2510 * m16.igen: Implement MIPS16 instructions.
72f4393d 2511
c906108c
SS		 2512 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2513 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2514 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2515 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2516 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2517 bodies of corresponding code from 32 bit insn to these. Also used
2518 by MIPS16 versions of functions.
72f4393d 2519
c906108c
SS		 2520 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2521 (IMEM16): Drop NR argument from macro.
2522
2523Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2524
2525 * Makefile.in (SIM_OBJS): Add sim-main.o.
2526
2527 * sim-main.h (address_translation, load_memory, store_memory,
2528 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2529 as INLINE_SIM_MAIN.
2530 (pr_addr, pr_uword64): Declare.
2531 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2532
c906108c
SS		 2533 * interp.c (address_translation, load_memory, store_memory,
2534 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2535 from here.
2536 * sim-main.c: To here. Fix compilation problems.
72f4393d 2537
c906108c
SS		 2538 * configure.in: Enable inlining.
2539 * configure: Re-config.
2540
2541Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2542
2543 * configure: Regenerated to track ../common/aclocal.m4 changes.
2544
2545Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2546
2547 * mips.igen: Include tx.igen.
2548 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2549 * tx.igen: New file, contains MADD and MADDU.
2550
2551 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2552 the hardwired constant `7'.
2553 (store_memory): Ditto.
2554 (LOADDRMASK): Move definition to sim-main.h.
2555
2556 mips.igen (MTC0): Enable for r3900.
2557 (ADDU): Add trace.
2558
2559 mips.igen (do_load_byte): Delete.
2560 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2561 do_store_right): New functions.
2562 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2563
2564 configure.in: Let the tx39 use igen again.
2565 configure: Update.
72f4393d 2566
c906108c
SS		 2567Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2568
2569 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2570 not an address sized quantity. Return zero for cache sizes.
2571
2572Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2573
2574 * mips.igen (r3900): r3900 does not support 64 bit integer
2575 operations.
2576
2577Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2578
2579 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2580 than igen one.
2581 * configure : Rebuild.
72f4393d 2582
c906108c
SS		 2583Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2584
2585 * configure: Regenerated to track ../common/aclocal.m4 changes.
2586
2587Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2588
2589 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2590
2591Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2592
2593 * configure: Regenerated to track ../common/aclocal.m4 changes.
2594 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2595
2596Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2597
2598 * configure: Regenerated to track ../common/aclocal.m4 changes.
2599
2600Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2601
2602 * interp.c (Max, Min): Comment out functions. Not yet used.
2603
2604Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2605
2606 * configure: Regenerated to track ../common/aclocal.m4 changes.
2607
2608Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2609
2610 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2611 configurable settings for stand-alone simulator.
72f4393d 2612
c906108c 2613 * configure.in: Added X11 search, just in case.
72f4393d 2614
c906108c
SS		 2615 * configure: Regenerated.
2616
2617Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2618
2619 * interp.c (sim_write, sim_read, load_memory, store_memory):
2620 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2621
2622Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2623
2624 * sim-main.h (GETFCC): Return an unsigned value.
2625
2626Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2627
2628 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2629 (DADD): Result destination is RD not RT.
2630
2631Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * sim-main.h (HIACCESS, LOACCESS): Always define.
2634
2635 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2636
2637 * interp.c (sim_info): Delete.
2638
2639Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2640
2641 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2642 (mips_option_handler): New argument `cpu'.
2643 (sim_open): Update call to sim_add_option_table.
2644
2645Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2646
2647 * mips.igen (CxC1): Add tracing.
2648
2649Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2650
2651 * sim-main.h (Max, Min): Declare.
2652
2653 * interp.c (Max, Min): New functions.
2654
2655 * mips.igen (BC1): Add tracing.
72f4393d 2656
c906108c 2657Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2658
c906108c 2659 * interp.c Added memory map for stack in vr4100
72f4393d 2660
c906108c
SS		 2661Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2662
2663 * interp.c (load_memory): Add missing "break"'s.
2664
2665Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2666
2667 * interp.c (sim_store_register, sim_fetch_register): Pass in
2668 length parameter. Return -1.
2669
2670Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2671
2672 * interp.c: Added hardware init hook, fixed warnings.
2673
2674Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2675
2676 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2677
2678Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2679
2680 * interp.c (ifetch16): New function.
2681
2682 * sim-main.h (IMEM32): Rename IMEM.
2683 (IMEM16_IMMED): Define.
2684 (IMEM16): Define.
2685 (DELAY_SLOT): Update.
72f4393d 2686
c906108c 2687 * m16run.c (sim_engine_run): New file.
72f4393d 2688
c906108c
SS		 2689 * m16.igen: All instructions except LB.
2690 (LB): Call do_load_byte.
2691 * mips.igen (do_load_byte): New function.
2692 (LB): Call do_load_byte.
2693
2694 * mips.igen: Move spec for insn bit size and high bit from here.
2695 * Makefile.in (tmp-igen, tmp-m16): To here.
2696
2697 * m16.dc: New file, decode mips16 instructions.
2698
2699 * Makefile.in (SIM_NO_ALL): Define.
2700 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2701
2702Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2703
2704 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2705 point unit to 32 bit registers.
2706 * configure: Re-generate.
2707
2708Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2709
2710 * configure.in (sim_use_gen): Make IGEN the default simulator
2711 generator for generic 32 and 64 bit mips targets.
2712 * configure: Re-generate.
2713
2714Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2715
2716 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2717 bitsize.
2718
2719 * interp.c (sim_fetch_register, sim_store_register): Read/write
2720 FGR from correct location.
2721 (sim_open): Set size of FGR's according to
2722 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2723
c906108c
SS		 2724 * sim-main.h (FGR): Store floating point registers in a separate
2725 array.
2726
2727Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2728
2729 * configure: Regenerated to track ../common/aclocal.m4 changes.
2730
2731Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2732
2733 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2734
2735 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2736
2737 * interp.c (pending_tick): New function. Deliver pending writes.
2738
2739 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2740 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2741 it can handle mixed sized quantites and single bits.
72f4393d 2742
c906108c
SS		 2743Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2744
2745 * interp.c (oengine.h): Do not include when building with IGEN.
2746 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2747 (sim_info): Ditto for PROCESSOR_64BIT.
2748 (sim_monitor): Replace ut_reg with unsigned_word.
2749 (*): Ditto for t_reg.
2750 (LOADDRMASK): Define.
2751 (sim_open): Remove defunct check that host FP is IEEE compliant,
2752 using software to emulate floating point.
2753 (value_fpr, ...): Always compile, was conditional on HASFPU.
2754
2755Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2756
2757 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2758 size.
2759
2760 * interp.c (SD, CPU): Define.
2761 (mips_option_handler): Set flags in each CPU.
2762 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2763 (sim_close): Do not clear STATE, deleted anyway.
2764 (sim_write, sim_read): Assume CPU zero's vm should be used for
2765 data transfers.
2766 (sim_create_inferior): Set the PC for all processors.
2767 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2768 argument.
2769 (mips16_entry): Pass correct nr of args to store_word, load_word.
2770 (ColdReset): Cold reset all cpu's.
2771 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2772 (sim_monitor, load_memory, store_memory, signal_exception): Use
2773 `CPU' instead of STATE_CPU.
2774
2775
2776 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2777 SD or CPU_.
72f4393d 2778
c906108c
SS		 2779 * sim-main.h (signal_exception): Add sim_cpu arg.
2780 (SignalException*): Pass both SD and CPU to signal_exception.
2781 * interp.c (signal_exception): Update.
72f4393d 2782
c906108c
SS		 2783 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2784 Ditto
2785 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2786 address_translation): Ditto
2787 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2788
c906108c
SS		 2789Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2790
2791 * configure: Regenerated to track ../common/aclocal.m4 changes.
2792
2793Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2794
2795 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2796
72f4393d 2797 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2798
2799 * sim-main.h (CPU_CIA): Delete.
2800 (SET_CIA, GET_CIA): Define
2801
2802Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2803
2804 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2805 regiser.
2806
2807 * configure.in (default_endian): Configure a big-endian simulator
2808 by default.
2809 * configure: Re-generate.
72f4393d 2810
c906108c
SS		 2811Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2812
2813 * configure: Regenerated to track ../common/aclocal.m4 changes.
2814
2815Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2816
2817 * interp.c (sim_monitor): Handle Densan monitor outbyte
2818 and inbyte functions.
2819
28201997-12-29 Felix Lee <flee@cygnus.com>
2821
2822 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2823
2824Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2825
2826 * Makefile.in (tmp-igen): Arrange for $zero to always be
2827 reset to zero after every instruction.
2828
2829Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2830
2831 * configure: Regenerated to track ../common/aclocal.m4 changes.
2832 * config.in: Ditto.
2833
2834Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2835
2836 * mips.igen (MSUB): Fix to work like MADD.
2837 * gencode.c (MSUB): Similarly.
2838
2839Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2840
2841 * configure: Regenerated to track ../common/aclocal.m4 changes.
2842
2843Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2844
2845 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2846
2847Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2848
2849 * sim-main.h (sim-fpu.h): Include.
2850
2851 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2852 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2853 using host independant sim_fpu module.
2854
2855Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2856
2857 * interp.c (signal_exception): Report internal errors with SIGABRT
2858 not SIGQUIT.
2859
2860 * sim-main.h (C0_CONFIG): New register.
2861 (signal.h): No longer include.
2862
2863 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2864
2865Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2866
2867 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2868
2869Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2870
2871 * mips.igen: Tag vr5000 instructions.
2872 (ANDI): Was missing mipsIV model, fix assembler syntax.
2873 (do_c_cond_fmt): New function.
2874 (C.cond.fmt): Handle mips I-III which do not support CC field
2875 separatly.
2876 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2877 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2878 in IV3.2 spec.
2879 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2880 vr5000 which saves LO in a GPR separatly.
72f4393d 2881
c906108c
SS		 2882 * configure.in (enable-sim-igen): For vr5000, select vr5000
2883 specific instructions.
2884 * configure: Re-generate.
72f4393d 2885
c906108c
SS		 2886Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2887
2888 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2889
2890 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2891 fmt_uninterpreted_64 bit cases to switch. Convert to
2892 fmt_formatted,
2893
2894 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2895
2896 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2897 as specified in IV3.2 spec.
2898 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2899
2900Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2901
2902 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2903 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2904 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2905 PENDING_FILL versions of instructions. Simplify.
2906 (X): New function.
2907 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2908 instructions.
2909 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2910 a signed value.
2911 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2912
c906108c
SS		 2913 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2914 global.
2915 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2916
2917Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2918
2919 * gencode.c (build_mips16_operands): Replace IPC with cia.
2920
2921 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2922 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2923 IPC to `cia'.
2924 (UndefinedResult): Replace function with macro/function
2925 combination.
2926 (sim_engine_run): Don't save PC in IPC.
2927
2928 * sim-main.h (IPC): Delete.
2929
2930
2931 * interp.c (signal_exception, store_word, load_word,
2932 address_translation, load_memory, store_memory, cache_op,
2933 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2934 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2935 current instruction address - cia - argument.
2936 (sim_read, sim_write): Call address_translation directly.
2937 (sim_engine_run): Rename variable vaddr to cia.
2938 (signal_exception): Pass cia to sim_monitor
72f4393d 2939
c906108c
SS		 2940 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2941 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2942 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2943
2944 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2945 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2946 SIM_ASSERT.
72f4393d 2947
c906108c
SS		 2948 * interp.c (signal_exception): Pass restart address to
2949 sim_engine_restart.
2950
2951 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2952 idecode.o): Add dependency.
2953
2954 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2955 Delete definitions
2956 (DELAY_SLOT): Update NIA not PC with branch address.
2957 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2958
2959 * mips.igen: Use CIA not PC in branch calculations.
2960 (illegal): Call SignalException.
2961 (BEQ, ADDIU): Fix assembler.
2962
2963Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2964
2965 * m16.igen (JALX): Was missing.
2966
2967 * configure.in (enable-sim-igen): New configuration option.
2968 * configure: Re-generate.
72f4393d 2969
c906108c
SS		 2970 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2971
2972 * interp.c (load_memory, store_memory): Delete parameter RAW.
2973 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2974 bypassing {load,store}_memory.
2975
2976 * sim-main.h (ByteSwapMem): Delete definition.
2977
2978 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2979
2980 * interp.c (sim_do_command, sim_commands): Delete mips specific
2981 commands. Handled by module sim-options.
72f4393d 2982
c906108c
SS		 2983 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2984 (WITH_MODULO_MEMORY): Define.
2985
2986 * interp.c (sim_info): Delete code printing memory size.
2987
2988 * interp.c (mips_size): Nee sim_size, delete function.
2989 (power2): Delete.
2990 (monitor, monitor_base, monitor_size): Delete global variables.
2991 (sim_open, sim_close): Delete code creating monitor and other
2992 memory regions. Use sim-memopts module, via sim_do_commandf, to
2993 manage memory regions.
2994 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2995
c906108c
SS		 2996 * interp.c (address_translation): Delete all memory map code
2997 except line forcing 32 bit addresses.
2998
2999Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
3000
3001 * sim-main.h (WITH_TRACE): Delete definition. Enables common
3002 trace options.
3003
3004 * interp.c (logfh, logfile): Delete globals.
3005 (sim_open, sim_close): Delete code opening & closing log file.
3006 (mips_option_handler): Delete -l and -n options.
3007 (OPTION mips_options): Ditto.
3008
3009 * interp.c (OPTION mips_options): Rename option trace to dinero.
3010 (mips_option_handler): Update.
3011
3012Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3013
3014 * interp.c (fetch_str): New function.
3015 (sim_monitor): Rewrite using sim_read & sim_write.
3016 (sim_open): Check magic number.
3017 (sim_open): Write monitor vectors into memory using sim_write.
3018 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
3019 (sim_read, sim_write): Simplify - transfer data one byte at a
3020 time.
3021 (load_memory, store_memory): Clarify meaning of parameter RAW.
3022
3023 * sim-main.h (isHOST): Defete definition.
3024 (isTARGET): Mark as depreciated.
3025 (address_translation): Delete parameter HOST.
3026
3027 * interp.c (address_translation): Delete parameter HOST.
3028
3029Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3030
72f4393d 3031 * mips.igen:
c906108c
SS		 3032
3033 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
3034 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
3035
3036Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
3037
3038 * mips.igen: Add model filter field to records.
3039
3040Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3041
3042 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 3043
c906108c
SS		 3044 interp.c (sim_engine_run): Do not compile function sim_engine_run
3045 when WITH_IGEN == 1.
3046
3047 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3048 target architecture.
3049
3050 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3051 igen. Replace with configuration variables sim_igen_flags /
3052 sim_m16_flags.
3053
3054 * m16.igen: New file. Copy mips16 insns here.
3055 * mips.igen: From here.
3056
3057Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3058
3059 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3060 to top.
3061 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3062
3063Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3064
3065 * gencode.c (build_instruction): Follow sim_write's lead in using
3066 BigEndianMem instead of !ByteSwapMem.
3067
3068Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3069
3070 * configure.in (sim_gen): Dependent on target, select type of
3071 generator. Always select old style generator.
3072
3073 configure: Re-generate.
3074
3075 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3076 targets.
3077 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3078 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3079 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3080 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3081 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3082
c906108c
SS		 3083Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3084
3085 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3086
3087 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3088 CURRENT_FLOATING_POINT instead.
3089
3090 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3091 (address_translation): Raise exception InstructionFetch when
3092 translation fails and isINSTRUCTION.
72f4393d 3093
c906108c
SS		 3094 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3095 sim_engine_run): Change type of of vaddr and paddr to
3096 address_word.
3097 (address_translation, prefetch, load_memory, store_memory,
3098 cache_op): Change type of vAddr and pAddr to address_word.
3099
3100 * gencode.c (build_instruction): Change type of vaddr and paddr to
3101 address_word.
3102
3103Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3104
3105 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3106 macro to obtain result of ALU op.
3107
3108Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3109
3110 * interp.c (sim_info): Call profile_print.
3111
3112Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3113
3114 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3115
3116 * sim-main.h (WITH_PROFILE): Do not define, defined in
3117 common/sim-config.h. Use sim-profile module.
3118 (simPROFILE): Delete defintion.
3119
3120 * interp.c (PROFILE): Delete definition.
3121 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3122 (sim_close): Delete code writing profile histogram.
3123 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3124 Delete.
3125 (sim_engine_run): Delete code profiling the PC.
3126
3127Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3128
3129 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3130
3131 * interp.c (sim_monitor): Make register pointers of type
3132 unsigned_word*.
3133
3134 * sim-main.h: Make registers of type unsigned_word not
3135 signed_word.
3136
3137Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3138
3139 * interp.c (sync_operation): Rename from SyncOperation, make
3140 global, add SD argument.
3141 (prefetch): Rename from Prefetch, make global, add SD argument.
3142 (decode_coproc): Make global.
3143
3144 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3145
3146 * gencode.c (build_instruction): Generate DecodeCoproc not
3147 decode_coproc calls.
3148
3149 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3150 (SizeFGR): Move to sim-main.h
3151 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3152 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3153 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3154 sim-main.h.
3155 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3156 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3157 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3158 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3159 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3160 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3161
c906108c
SS		 3162 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3163 exception.
3164 (sim-alu.h): Include.
3165 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3166 (sim_cia): Typedef to instruction_address.
72f4393d 3167
c906108c
SS		 3168Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3169
3170 * Makefile.in (interp.o): Rename generated file engine.c to
3171 oengine.c.
72f4393d 3172
c906108c 3173 * interp.c: Update.
72f4393d 3174
c906108c
SS		 3175Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3176
3177 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3178
c906108c
SS		 3179Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3180
3181 * gencode.c (build_instruction): For "FPSQRT", output correct
3182 number of arguments to Recip.
72f4393d 3183
c906108c
SS		 3184Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3185
3186 * Makefile.in (interp.o): Depends on sim-main.h
3187
3188 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3189
3190 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3191 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3192 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3193 STATE, DSSTATE): Define
3194 (GPR, FGRIDX, ..): Define.
3195
3196 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3197 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3198 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3199
c906108c 3200 * interp.c: Update names to match defines from sim-main.h
72f4393d 3201
c906108c
SS		 3202Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3203
3204 * interp.c (sim_monitor): Add SD argument.
3205 (sim_warning): Delete. Replace calls with calls to
3206 sim_io_eprintf.
3207 (sim_error): Delete. Replace calls with sim_io_error.
3208 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3209 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3210 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3211 argument.
3212 (mips_size): Rename from sim_size. Add SD argument.
3213
3214 * interp.c (simulator): Delete global variable.
3215 (callback): Delete global variable.
3216 (mips_option_handler, sim_open, sim_write, sim_read,
3217 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3218 sim_size,sim_monitor): Use sim_io_* not callback->*.
3219 (sim_open): ZALLOC simulator struct.
3220 (PROFILE): Do not define.
3221
3222Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3223
3224 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3225 support.h with corresponding code.
3226
3227 * sim-main.h (word64, uword64), support.h: Move definition to
3228 sim-main.h.
3229 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3230
3231 * support.h: Delete
3232 * Makefile.in: Update dependencies
3233 * interp.c: Do not include.
72f4393d 3234
c906108c
SS		 3235Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3236
3237 * interp.c (address_translation, load_memory, store_memory,
3238 cache_op): Rename to from AddressTranslation et.al., make global,
3239 add SD argument
72f4393d 3240
c906108c
SS		 3241 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3242 CacheOp): Define.
72f4393d 3243
c906108c
SS		 3244 * interp.c (SignalException): Rename to signal_exception, make
3245 global.
3246
3247 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3248
c906108c
SS		 3249 * sim-main.h (SignalException, SignalExceptionInterrupt,
3250 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3251 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3252 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3253 Define.
72f4393d 3254
c906108c 3255 * interp.c, support.h: Use.
72f4393d 3256
c906108c
SS		 3257Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3258
3259 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3260 to value_fpr / store_fpr. Add SD argument.
3261 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3262 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3263
3264 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3265
c906108c
SS		 3266Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3267
3268 * interp.c (sim_engine_run): Check consistency between configure
3269 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3270 and HASFPU.
3271
3272 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3273 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3274 (mips_endian): Configure WITH_TARGET_ENDIAN.
3275 * configure: Update.
3276
3277Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3278
3279 * configure: Regenerated to track ../common/aclocal.m4 changes.
3280
3281Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3282
3283 * configure: Regenerated.
3284
3285Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3286
3287 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3288
3289Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3290
3291 * gencode.c (print_igen_insn_models): Assume certain architectures
3292 include all mips* instructions.
3293 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3294 instruction.
3295
3296 * Makefile.in (tmp.igen): Add target. Generate igen input from
3297 gencode file.
3298
3299 * gencode.c (FEATURE_IGEN): Define.
3300 (main): Add --igen option. Generate output in igen format.
3301 (process_instructions): Format output according to igen option.
3302 (print_igen_insn_format): New function.
3303 (print_igen_insn_models): New function.
3304 (process_instructions): Only issue warnings and ignore
3305 instructions when no FEATURE_IGEN.
3306
3307Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3308
3309 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3310 MIPS targets.
3311
3312Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3313
3314 * configure: Regenerated to track ../common/aclocal.m4 changes.
3315
3316Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3317
3318 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3319 SIM_RESERVED_BITS): Delete, moved to common.
3320 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3321
c906108c
SS		 3322Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3323
3324 * configure.in: Configure non-strict memory alignment.
3325 * configure: Regenerated to track ../common/aclocal.m4 changes.
3326
3327Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3328
3329 * configure: Regenerated to track ../common/aclocal.m4 changes.
3330
3331Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3332
3333 * gencode.c (SDBBP,DERET): Added (3900) insns.
3334 (RFE): Turn on for 3900.
3335 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3336 (dsstate): Made global.
3337 (SUBTARGET_R3900): Added.
3338 (CANCELDELAYSLOT): New.
3339 (SignalException): Ignore SystemCall rather than ignore and
3340 terminate. Add DebugBreakPoint handling.
3341 (decode_coproc): New insns RFE, DERET; and new registers Debug
3342 and DEPC protected by SUBTARGET_R3900.
3343 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3344 bits explicitly.
3345 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3346 * configure: Update.
c906108c
SS		 3347
3348Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3349
3350 * gencode.c: Add r3900 (tx39).
72f4393d 3351
c906108c
SS		 3352
3353Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3354
3355 * gencode.c (build_instruction): Don't need to subtract 4 for
3356 JALR, just 2.
3357
3358Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3359
3360 * interp.c: Correct some HASFPU problems.
3361
3362Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3363
3364 * configure: Regenerated to track ../common/aclocal.m4 changes.
3365
3366Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3367
3368 * interp.c (mips_options): Fix samples option short form, should
3369 be `x'.
3370
3371Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3372
3373 * interp.c (sim_info): Enable info code. Was just returning.
3374
3375Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3376
3377 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3378 MFC0.
3379
3380Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3381
3382 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3383 constants.
3384 (build_instruction): Ditto for LL.
3385
3386Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3387
3388 * configure: Regenerated to track ../common/aclocal.m4 changes.
3389
3390Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3391
3392 * configure: Regenerated to track ../common/aclocal.m4 changes.
3393 * config.in: Ditto.
3394
3395Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3396
3397 * interp.c (sim_open): Add call to sim_analyze_program, update
3398 call to sim_config.
3399
3400Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3401
3402 * interp.c (sim_kill): Delete.
3403 (sim_create_inferior): Add ABFD argument. Set PC from same.
3404 (sim_load): Move code initializing trap handlers from here.
3405 (sim_open): To here.
3406 (sim_load): Delete, use sim-hload.c.
3407
3408 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3409
3410Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3411
3412 * configure: Regenerated to track ../common/aclocal.m4 changes.
3413 * config.in: Ditto.
3414
3415Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3416
3417 * interp.c (sim_open): Add ABFD argument.
3418 (sim_load): Move call to sim_config from here.
3419 (sim_open): To here. Check return status.
3420
3421Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3422
c906108c
SS		 3423 * gencode.c (build_instruction): Two arg MADD should
3424 not assign result to $0.
72f4393d 3425
c906108c
SS		 3426Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3427
3428 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3429 * sim/mips/configure.in: Regenerate.
3430
3431Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3432
3433 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3434 signed8, unsigned8 et.al. types.
3435
3436 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3437 hosts when selecting subreg.
3438
3439Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3440
3441 * interp.c (sim_engine_run): Reset the ZERO register to zero
3442 regardless of FEATURE_WARN_ZERO.
3443 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3444
3445Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3446
3447 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3448 (SignalException): For BreakPoints ignore any mode bits and just
3449 save the PC.
3450 (SignalException): Always set the CAUSE register.
3451
3452Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3453
3454 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3455 exception has been taken.
3456
3457 * interp.c: Implement the ERET and mt/f sr instructions.
3458
3459Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3460
3461 * interp.c (SignalException): Don't bother restarting an
3462 interrupt.
3463
3464Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3465
3466 * interp.c (SignalException): Really take an interrupt.
3467 (interrupt_event): Only deliver interrupts when enabled.
3468
3469Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3470
3471 * interp.c (sim_info): Only print info when verbose.
3472 (sim_info) Use sim_io_printf for output.
72f4393d 3473
c906108c
SS		 3474Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3475
3476 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3477 mips architectures.
3478
3479Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3480
3481 * interp.c (sim_do_command): Check for common commands if a
3482 simulator specific command fails.
3483
3484Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3485
3486 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3487 and simBE when DEBUG is defined.
3488
3489Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3490
3491 * interp.c (interrupt_event): New function. Pass exception event
3492 onto exception handler.
3493
3494 * configure.in: Check for stdlib.h.
3495 * configure: Regenerate.
3496
3497 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3498 variable declaration.
3499 (build_instruction): Initialize memval1.
3500 (build_instruction): Add UNUSED attribute to byte, bigend,
3501 reverse.
3502 (build_operands): Ditto.
3503
3504 * interp.c: Fix GCC warnings.
3505 (sim_get_quit_code): Delete.
3506
3507 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3508 * Makefile.in: Ditto.
3509 * configure: Re-generate.
72f4393d 3510
c906108c
SS		 3511 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3512
3513Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3514
3515 * interp.c (mips_option_handler): New function parse argumes using
3516 sim-options.
3517 (myname): Replace with STATE_MY_NAME.
3518 (sim_open): Delete check for host endianness - performed by
3519 sim_config.
3520 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3521 (sim_open): Move much of the initialization from here.
3522 (sim_load): To here. After the image has been loaded and
3523 endianness set.
3524 (sim_open): Move ColdReset from here.
3525 (sim_create_inferior): To here.
3526 (sim_open): Make FP check less dependant on host endianness.
3527
3528 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3529 run.
3530 * interp.c (sim_set_callbacks): Delete.
3531
3532 * interp.c (membank, membank_base, membank_size): Replace with
3533 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3534 (sim_open): Remove call to callback->init. gdb/run do this.
3535
3536 * interp.c: Update
3537
3538 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3539
3540 * interp.c (big_endian_p): Delete, replaced by
3541 current_target_byte_order.
3542
3543Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3544
3545 * interp.c (host_read_long, host_read_word, host_swap_word,
3546 host_swap_long): Delete. Using common sim-endian.
3547 (sim_fetch_register, sim_store_register): Use H2T.
3548 (pipeline_ticks): Delete. Handled by sim-events.
3549 (sim_info): Update.
3550 (sim_engine_run): Update.
3551
3552Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3553
3554 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3555 reason from here.
3556 (SignalException): To here. Signal using sim_engine_halt.
3557 (sim_stop_reason): Delete, moved to common.
72f4393d 3558
c906108c
SS		 3559Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3560
3561 * interp.c (sim_open): Add callback argument.
3562 (sim_set_callbacks): Delete SIM_DESC argument.
3563 (sim_size): Ditto.
3564
3565Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3566
3567 * Makefile.in (SIM_OBJS): Add common modules.
3568
3569 * interp.c (sim_set_callbacks): Also set SD callback.
3570 (set_endianness, xfer_*, swap_*): Delete.
3571 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3572 Change to functions using sim-endian macros.
3573 (control_c, sim_stop): Delete, use common version.
3574 (simulate): Convert into.
3575 (sim_engine_run): This function.
3576 (sim_resume): Delete.
72f4393d 3577
c906108c
SS		 3578 * interp.c (simulation): New variable - the simulator object.
3579 (sim_kind): Delete global - merged into simulation.
3580 (sim_load): Cleanup. Move PC assignment from here.
3581 (sim_create_inferior): To here.
3582
3583 * sim-main.h: New file.
3584 * interp.c (sim-main.h): Include.
72f4393d 3585
c906108c
SS		 3586Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3587
3588 * configure: Regenerated to track ../common/aclocal.m4 changes.
3589
3590Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3591
3592 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3593
3594Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3595
72f4393d
L		 3596 * gencode.c (build_instruction): DIV instructions: check
3597 for division by zero and integer overflow before using
c906108c
SS		 3598 host's division operation.
3599
3600Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3601
3602 * Makefile.in (SIM_OBJS): Add sim-load.o.
3603 * interp.c: #include bfd.h.
3604 (target_byte_order): Delete.
3605 (sim_kind, myname, big_endian_p): New static locals.
3606 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3607 after argument parsing. Recognize -E arg, set endianness accordingly.
3608 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3609 load file into simulator. Set PC from bfd.
3610 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3611 (set_endianness): Use big_endian_p instead of target_byte_order.
3612
3613Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3614
3615 * interp.c (sim_size): Delete prototype - conflicts with
3616 definition in remote-sim.h. Correct definition.
3617
3618Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3619
3620 * configure: Regenerated to track ../common/aclocal.m4 changes.
3621 * config.in: Ditto.
3622
3623Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3624
3625 * interp.c (sim_open): New arg `kind'.
3626
3627 * configure: Regenerated to track ../common/aclocal.m4 changes.
3628
3629Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3630
3631 * configure: Regenerated to track ../common/aclocal.m4 changes.
3632
3633Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3634
3635 * interp.c (sim_open): Set optind to 0 before calling getopt.
3636
3637Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3638
3639 * configure: Regenerated to track ../common/aclocal.m4 changes.
3640
3641Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3642
3643 * interp.c : Replace uses of pr_addr with pr_uword64
3644 where the bit length is always 64 independent of SIM_ADDR.
3645 (pr_uword64) : added.
3646
3647Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3648
3649 * configure: Re-generate.
3650
3651Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3652
3653 * configure: Regenerate to track ../common/aclocal.m4 changes.
3654
3655Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3656
3657 * interp.c (sim_open): New SIM_DESC result. Argument is now
3658 in argv form.
3659 (other sim_*): New SIM_DESC argument.
3660
3661Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3662
3663 * interp.c: Fix printing of addresses for non-64-bit targets.
3664 (pr_addr): Add function to print address based on size.
3665
3666Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3667
3668 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3669
3670Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3671
3672 * gencode.c (build_mips16_operands): Correct computation of base
3673 address for extended PC relative instruction.
3674
3675Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3676
3677 * interp.c (mips16_entry): Add support for floating point cases.
3678 (SignalException): Pass floating point cases to mips16_entry.
3679 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3680 registers.
3681 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3682 or fmt_word.
3683 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3684 and then set the state to fmt_uninterpreted.
3685 (COP_SW): Temporarily set the state to fmt_word while calling
3686 ValueFPR.
3687
3688Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3689
3690 * gencode.c (build_instruction): The high order may be set in the
3691 comparison flags at any ISA level, not just ISA 4.
3692
3693Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3694
3695 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3696 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3697 * configure.in: sinclude ../common/aclocal.m4.
3698 * configure: Regenerated.
3699
3700Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3701
3702 * configure: Rebuild after change to aclocal.m4.
3703
3704Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3705
3706 * configure configure.in Makefile.in: Update to new configure
3707 scheme which is more compatible with WinGDB builds.
3708 * configure.in: Improve comment on how to run autoconf.
3709 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3710 * Makefile.in: Use autoconf substitution to install common
3711 makefile fragment.
3712
3713Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3714
3715 * gencode.c (build_instruction): Use BigEndianCPU instead of
3716 ByteSwapMem.
3717
3718Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3719
3720 * interp.c (sim_monitor): Make output to stdout visible in
3721 wingdb's I/O log window.
3722
3723Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3724
3725 * support.h: Undo previous change to SIGTRAP
3726 and SIGQUIT values.
3727
3728Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3729
3730 * interp.c (store_word, load_word): New static functions.
3731 (mips16_entry): New static function.
3732 (SignalException): Look for mips16 entry and exit instructions.
3733 (simulate): Use the correct index when setting fpr_state after
3734 doing a pending move.
3735
3736Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3737
3738 * interp.c: Fix byte-swapping code throughout to work on
3739 both little- and big-endian hosts.
3740
3741Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3742
3743 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3744 with gdb/config/i386/xm-windows.h.
3745
3746Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3747
3748 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3749 that messes up arithmetic shifts.
3750
3751Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3752
3753 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3754 SIGTRAP and SIGQUIT for _WIN32.
3755
3756Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3757
3758 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3759 force a 64 bit multiplication.
3760 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3761 destination register is 0, since that is the default mips16 nop
3762 instruction.
3763
3764Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3765
3766 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3767 (build_endian_shift): Don't check proc64.
3768 (build_instruction): Always set memval to uword64. Cast op2 to
3769 uword64 when shifting it left in memory instructions. Always use
3770 the same code for stores--don't special case proc64.
3771
3772 * gencode.c (build_mips16_operands): Fix base PC value for PC
3773 relative operands.
3774 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3775 jal instruction.
3776 * interp.c (simJALDELAYSLOT): Define.
3777 (JALDELAYSLOT): Define.
3778 (INDELAYSLOT, INJALDELAYSLOT): Define.
3779 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3780
3781Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3782
3783 * interp.c (sim_open): add flush_cache as a PMON routine
3784 (sim_monitor): handle flush_cache by ignoring it
3785
3786Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3787
3788 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3789 BigEndianMem.
3790 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3791 (BigEndianMem): Rename to ByteSwapMem and change sense.
3792 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3793 BigEndianMem references to !ByteSwapMem.
3794 (set_endianness): New function, with prototype.
3795 (sim_open): Call set_endianness.
3796 (sim_info): Use simBE instead of BigEndianMem.
3797 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3798 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3799 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3800 ifdefs, keeping the prototype declaration.
3801 (swap_word): Rewrite correctly.
3802 (ColdReset): Delete references to CONFIG. Delete endianness related
3803 code; moved to set_endianness.
72f4393d 3804
c906108c
SS		 3805Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3806
3807 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3808 * interp.c (CHECKHILO): Define away.
3809 (simSIGINT): New macro.
3810 (membank_size): Increase from 1MB to 2MB.
3811 (control_c): New function.
3812 (sim_resume): Rename parameter signal to signal_number. Add local
3813 variable prev. Call signal before and after simulate.
3814 (sim_stop_reason): Add simSIGINT support.
3815 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3816 functions always.
3817 (sim_warning): Delete call to SignalException. Do call printf_filtered
3818 if logfh is NULL.
3819 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3820 a call to sim_warning.
3821
3822Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3823
3824 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3825 16 bit instructions.
3826
3827Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3828
3829 Add support for mips16 (16 bit MIPS implementation):
3830 * gencode.c (inst_type): Add mips16 instruction encoding types.
3831 (GETDATASIZEINSN): Define.
3832 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3833 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3834 mtlo.
3835 (MIPS16_DECODE): New table, for mips16 instructions.
3836 (bitmap_val): New static function.
3837 (struct mips16_op): Define.
3838 (mips16_op_table): New table, for mips16 operands.
3839 (build_mips16_operands): New static function.
3840 (process_instructions): If PC is odd, decode a mips16
3841 instruction. Break out instruction handling into new
3842 build_instruction function.
3843 (build_instruction): New static function, broken out of
3844 process_instructions. Check modifiers rather than flags for SHIFT
3845 bit count and m[ft]{hi,lo} direction.
3846 (usage): Pass program name to fprintf.
3847 (main): Remove unused variable this_option_optind. Change
3848 ``*loptarg++'' to ``loptarg++''.
3849 (my_strtoul): Parenthesize && within ||.
3850 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3851 (simulate): If PC is odd, fetch a 16 bit instruction, and
3852 increment PC by 2 rather than 4.
3853 * configure.in: Add case for mips16*-*-*.
3854 * configure: Rebuild.
3855
3856Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3857
3858 * interp.c: Allow -t to enable tracing in standalone simulator.
3859 Fix garbage output in trace file and error messages.
3860
3861Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3862
3863 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3864 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3865 * configure.in: Simplify using macros in ../common/aclocal.m4.
3866 * configure: Regenerated.
3867 * tconfig.in: New file.
3868
3869Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3870
3871 * interp.c: Fix bugs in 64-bit port.
3872 Use ansi function declarations for msvc compiler.
3873 Initialize and test file pointer in trace code.
3874 Prevent duplicate definition of LAST_EMED_REGNUM.
3875
3876Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3877
3878 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3879
3880Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3881
3882 * interp.c (SignalException): Check for explicit terminating
3883 breakpoint value.
3884 * gencode.c: Pass instruction value through SignalException()
3885 calls for Trap, Breakpoint and Syscall.
3886
3887Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3888
3889 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3890 only used on those hosts that provide it.
3891 * configure.in: Add sqrt() to list of functions to be checked for.
3892 * config.in: Re-generated.
3893 * configure: Re-generated.
3894
3895Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3896
3897 * gencode.c (process_instructions): Call build_endian_shift when
3898 expanding STORE RIGHT, to fix swr.
3899 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3900 clear the high bits.
3901 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3902 Fix float to int conversions to produce signed values.
3903
3904Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3905
3906 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3907 (process_instructions): Correct handling of nor instruction.
3908 Correct shift count for 32 bit shift instructions. Correct sign
3909 extension for arithmetic shifts to not shift the number of bits in
3910 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3911 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3912 Fix madd.
3913 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3914 It's OK to have a mult follow a mult. What's not OK is to have a
3915 mult follow an mfhi.
3916 (Convert): Comment out incorrect rounding code.
3917
3918Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3919
3920 * interp.c (sim_monitor): Improved monitor printf
3921 simulation. Tidied up simulator warnings, and added "--log" option
3922 for directing warning message output.
3923 * gencode.c: Use sim_warning() rather than WARNING macro.
3924
3925Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3926
3927 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3928 getopt1.o, rather than on gencode.c. Link objects together.
3929 Don't link against -liberty.
3930 (gencode.o, getopt.o, getopt1.o): New targets.
3931 * gencode.c: Include <ctype.h> and "ansidecl.h".
3932 (AND): Undefine after including "ansidecl.h".
3933 (ULONG_MAX): Define if not defined.
3934 (OP_*): Don't define macros; now defined in opcode/mips.h.
3935 (main): Call my_strtoul rather than strtoul.
3936 (my_strtoul): New static function.
3937
3938Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3939
3940 * gencode.c (process_instructions): Generate word64 and uword64
3941 instead of `long long' and `unsigned long long' data types.
3942 * interp.c: #include sysdep.h to get signals, and define default
3943 for SIGBUS.
3944 * (Convert): Work around for Visual-C++ compiler bug with type
3945 conversion.
3946 * support.h: Make things compile under Visual-C++ by using
3947 __int64 instead of `long long'. Change many refs to long long
3948 into word64/uword64 typedefs.
3949
3950Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3951
72f4393d
L		 3952 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3953 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3954 (docdir): Removed.
3955 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3956 (AC_PROG_INSTALL): Added.
c906108c 3957 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3958 * configure: Rebuilt.
3959
c906108c
SS		 3960Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3961
3962 * configure.in: Define @SIMCONF@ depending on mips target.
3963 * configure: Rebuild.
3964 * Makefile.in (run): Add @SIMCONF@ to control simulator
3965 construction.
3966 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3967 * interp.c: Remove some debugging, provide more detailed error
3968 messages, update memory accesses to use LOADDRMASK.
72f4393d 3969
c906108c
SS		 3970Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3971
3972 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3973 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3974 stamp-h.
3975 * configure: Rebuild.
3976 * config.in: New file, generated by autoheader.
3977 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3978 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3979 HAVE_ANINT and HAVE_AINT, as appropriate.
3980 * Makefile.in (run): Use @LIBS@ rather than -lm.
3981 (interp.o): Depend upon config.h.
3982 (Makefile): Just rebuild Makefile.
3983 (clean): Remove stamp-h.
3984 (mostlyclean): Make the same as clean, not as distclean.
3985 (config.h, stamp-h): New targets.
3986
3987Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3988
3989 * interp.c (ColdReset): Fix boolean test. Make all simulator
3990 globals static.
3991
3992Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3993
3994 * interp.c (xfer_direct_word, xfer_direct_long,
3995 swap_direct_word, swap_direct_long, xfer_big_word,
3996 xfer_big_long, xfer_little_word, xfer_little_long,
3997 swap_word,swap_long): Added.
3998 * interp.c (ColdReset): Provide function indirection to
3999 host<->simulated_target transfer routines.
4000 * interp.c (sim_store_register, sim_fetch_register): Updated to
4001 make use of indirected transfer routines.
4002
4003Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
4004
4005 * gencode.c (process_instructions): Ensure FP ABS instruction
4006 recognised.
4007 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
4008 system call support.
4009
4010Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
4011
4012 * interp.c (sim_do_command): Complain if callback structure not
4013 initialised.
4014
4015Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
4016
4017 * interp.c (Convert): Provide round-to-nearest and round-to-zero
4018 support for Sun hosts.
4019 * Makefile.in (gencode): Ensure the host compiler and libraries
4020 used for cross-hosted build.
4021
4022Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
4023
4024 * interp.c, gencode.c: Some more (TODO) tidying.
4025
4026Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
4027
4028 * gencode.c, interp.c: Replaced explicit long long references with
4029 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
4030 * support.h (SET64LO, SET64HI): Macros added.
4031
4032Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
4033
4034 * configure: Regenerate with autoconf 2.7.
4035
4036Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
4037
4038 * interp.c (LoadMemory): Enclose text following #endif in /* */.
4039 * support.h: Remove superfluous "1" from #if.
4040 * support.h (CHECKSIM): Remove stray 'a' at end of line.
4041
4042Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
4043
4044 * interp.c (StoreFPR): Control UndefinedResult() call on
4045 WARN_RESULT manifest.
4046
4047Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4048
4049 * gencode.c: Tidied instruction decoding, and added FP instruction
4050 support.
4051
4052 * interp.c: Added dineroIII, and BSD profiling support. Also
4053 run-time FP handling.
4054
4055Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4056
4057 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4058 gencode.c, interp.c, support.h: created.
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