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sim: move -Werror disabling to Makefile
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
982c3a65
MF		 12021-06-18 Mike Frysinger <vapier@gentoo.org>
2
3 * Makefile.in (SIM_WERROR_CFLAGS): New variable.
4 * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
5 * configure: Regenerate.
6
1fef66b0
MF		 72021-06-18 Mike Frysinger <vapier@gentoo.org>
8
9 * interp.c: Include sim-signal.h.
10
f9a4d543
MF		 112021-06-17 Mike Frysinger <vapier@gentoo.org>
12
13 * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
14 * aclocal.m4, configure: Regenerate.
15
b80d4475
MF		 162021-06-16 Mike Frysinger <vapier@gentoo.org>
17
18 * interp.c (dotrace): Make comment const.
19 * sim-main.h (dotrace): Likewise. Add ATTRIBUTE_PRINTF.
20
6828a302
MF		 212021-06-16 Mike Frysinger <vapier@gentoo.org>
22
23 * interp.c (sim_monitor): Change ap type to address_word*.
24 (_P, P): New macros. Rewrite dynamic printf logic to use these.
25
df32b446
MF		 262021-06-16 Mike Frysinger <vapier@gentoo.org>
27
28 * dv-tx3904sio.c (tx3904sio_fifo_push): Change next_buf to
29 unsigned_1.
30
7b2298cb
MF		 312021-06-16 Mike Frysinger <vapier@gentoo.org>
32
33 * dv-tx3904irc.c (tx3904irc_io_write_buffer): Initialize
34 register_value to 0.
35
a8a3d907
MF		 362021-06-16 Mike Frysinger <vapier@gentoo.org>
37
38 * configure: Regenerate.
39
dae666c9
MF		 402021-06-16 Mike Frysinger <vapier@gentoo.org>
41
42 * interp.c (sim_open): Change %lx to %x and PRIx macros.
43
52d37d2c
MF		 442021-06-16 Mike Frysinger <vapier@gentoo.org>
45
46 * configure: Regenerate.
47 * config.in: Removed.
48
bcaa61f7
MF		 492021-06-15 Mike Frysinger <vapier@gentoo.org>
50
51 * config.in, configure: Regenerate.
52
ba307cdd
MF		 532021-06-12 Mike Frysinger <vapier@gentoo.org>
54
55 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
56
dba333c1
MF		 572021-06-12 Mike Frysinger <vapier@gentoo.org>
58
59 * aclocal.m4, config.in, configure: Regenerate.
60
b15c5d7a
MF		 612021-06-12 Mike Frysinger <vapier@gentoo.org>
62
63 * configure.ac: Delete call to AC_CHECK_FUNCS.
64 * config.in, configure: Regenerate.
65
a55b92be
MF		 662021-06-08 Mike Frysinger <vapier@gentoo.org>
67
68 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
69 with $(IGEN).
70
8ea881d9
MF		 712021-05-29 Mike Frysinger <vapier@gentoo.org>
72
73 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
74
b312488f
FS		 752021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
76
168671c1
FS		 77 * interp.c (sim_open): Add shadow mappings from 32-bit
78 address space to 64-bit sign-extended address space.
79
802021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
81
b312488f
FS		 82 * interp.c (sim_create_inferior): Only truncate sign extension
83 bits for 32-bit target models.
84
f4fdd845
MF		 852021-05-17 Mike Frysinger <vapier@gentoo.org>
86
87 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
88
8ea7241c
MF		 892021-05-17 Mike Frysinger <vapier@gentoo.org>
90
91 * interp.c (sim_open): Switch to sim_state_alloc_extra.
92 * micromips.igen: Change SD to mips_sim_state.
93 * micromipsrun.c (sim_engine_run): Likewise.
94 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
95 (watch_options_install): Delete.
96 (struct swatch): Delete.
97 (struct sim_state): Delete.
98 (struct mips_sim_state): New struct.
99 (MIPS_SIM_STATE): Define.
100
6df01ab8
MF		 1012021-05-16 Mike Frysinger <vapier@gentoo.org>
102
103 * interp.c: Replace config.h include with defs.h.
104 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
105 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
106 Include defs.h.
107
79633c12
MF		 1082021-05-16 Mike Frysinger <vapier@gentoo.org>
109
110 * config.in, configure: Regenerate.
111
df68e12b
MF		 1122021-05-14 Mike Frysinger <vapier@gentoo.org>
113
114 * interp.c: Update include path.
115
77c0fdb7
MF		 1162021-05-04 Mike Frysinger <vapier@gentoo.org>
117
118 * dv-tx3904sio.c: Include stdlib.h.
119
9b1af85c
MF		 1202021-05-04 Mike Frysinger <vapier@gentoo.org>
121
122 * configure.ac (hw_extra_devices): Inline contents into
123 SIM_AC_OPTION_HARDWARE and delete.
124 * configure: Regenerate.
125
d97ba9c6
MF		 1262021-05-04 Mike Frysinger <vapier@gentoo.org>
127
128 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
129 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
130 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
131 * configure: Regenerate.
132
4df817de
MF		 1332021-05-04 Mike Frysinger <vapier@gentoo.org>
134
135 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
136
aa0fca16
MF		 1372021-05-04 Mike Frysinger <vapier@gentoo.org>
138
139 * configure: Regenerate.
140
adbaa7b8
MF		 1412021-05-01 Mike Frysinger <vapier@gentoo.org>
142
143 * cp1.c (store_fcr): Mark static.
144
fe348617
MF		 1452021-05-01 Mike Frysinger <vapier@gentoo.org>
146
147 * config.in, configure: Regenerate.
148
9d903352
MF		 1492021-04-23 Mike Frysinger <vapier@gentoo.org>
150
151 * configure.ac (hw_enabled): Delete.
152 (SIM_AC_OPTION_HARDWARE): Delete first two args.
153 * configure: Regenerate.
154
19f6a43c
TT		 1552021-04-22 Tom Tromey <tom@tromey.com>
156
157 * configure, config.in: Rebuild.
158
e7d8f1da
TT		 1592021-04-22 Tom Tromey <tom@tromey.com>
160
161 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
162 Remove.
163 (SIM_EXTRA_DEPS): New variable.
164
efd82ac7
TT		 1652021-04-22 Tom Tromey <tom@tromey.com>
166
167 * configure: Rebuild.
168
2662c237
MF		 1692021-04-21 Mike Frysinger <vapier@gentoo.org>
170
171 * aclocal.m4: Regenerate.
172
1f195bc3
SM		 1732021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
174
175 * configure: Regenerate.
176
37e9f182
MF		 1772021-04-18 Mike Frysinger <vapier@gentoo.org>
178
179 * configure: Regenerate.
180
d5a71b11
MF		 1812021-04-12 Mike Frysinger <vapier@gentoo.org>
182
183 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
184
2b8d134b
SM		 1852021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
186
187 * Makefile.in: Set ASAN_OPTIONS when running igen.
188
5c6f091a
FS		 1892021-04-04 Steve Ellcey <sellcey@mips.com>
190 Faraz Shahbazker <fshahbazker@wavecomp.com>
191
192 * interp.c (sim_monitor): Add switch entries for unlink (13),
193 lseek (14), and stat (15).
194
b6b1c790
MF		 1952021-04-02 Mike Frysinger <vapier@gentoo.org>
196
197 * Makefile.in (../igen/igen): Delete rule.
198 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
199
c2783492
MF		 2002021-04-02 Mike Frysinger <vapier@gentoo.org>
201
202 * aclocal.m4, configure: Regenerate.
203
ebe9564b
MF		 2042021-02-28 Mike Frysinger <vapier@gentoo.org>
205
206 * configure: Regenerate.
207
f8069d55
MF		 2082021-02-27 Mike Frysinger <vapier@gentoo.org>
209
210 * Makefile.in (SIM_EXTRA_ALL): Delete.
211 (all): New target.
212
760b3e8b
MF		 2132021-02-21 Mike Frysinger <vapier@gentoo.org>
214
215 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
216 * aclocal.m4, configure: Regenerate.
217
136da8cd
MF		 2182021-02-13 Mike Frysinger <vapier@gentoo.org>
219
220 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
221 * aclocal.m4, configure: Regenerate.
222
4c0d76b9
MF		 2232021-02-06 Mike Frysinger <vapier@gentoo.org>
224
225 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
226
aa09469f
MF		 2272021-02-06 Mike Frysinger <vapier@gentoo.org>
228
229 * configure: Regenerate.
230
d4e3adda
MF		 2312021-01-30 Mike Frysinger <vapier@gentoo.org>
232
233 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
234
68ed2854
MF		 2352021-01-11 Mike Frysinger <vapier@gentoo.org>
236
237 * config.in, configure: Regenerate.
238 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
239 and strings.h include.
240
50df264d
MF		 2412021-01-09 Mike Frysinger <vapier@gentoo.org>
242
243 * configure: Regenerate.
244
bf470982
MF		 2452021-01-09 Mike Frysinger <vapier@gentoo.org>
246
247 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
248 * configure: Regenerate.
249
46f900c0
MF		 2502021-01-08 Mike Frysinger <vapier@gentoo.org>
251
252 * configure: Regenerate.
253
dfb856ba
MF		 2542021-01-04 Mike Frysinger <vapier@gentoo.org>
255
256 * configure: Regenerate.
257
382bc56b
PK		 2582020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
259
260 * sim-main.c: Include <stdlib.h>.
261
ad9675dd
PK		 2622020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
263
264 * cp1.c: Include <stdlib.h>.
265
f693213d
SM		 2662020-07-29 Simon Marchi <simon.marchi@efficios.com>
267
268 * configure: Re-generate.
269
5c887dd5
JB		 2702017-09-06 John Baldwin <jhb@FreeBSD.org>
271
272 * configure: Regenerate.
273
91588b3a
MF		 2742016-11-11 Mike Frysinger <vapier@gentoo.org>
275
6cb2202b 276 PR sim/20808
91588b3a
MF		 277 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
278 and SD to sd.
279
e04659e8
MF		 2802016-11-11 Mike Frysinger <vapier@gentoo.org>
281
6cb2202b 282 PR sim/20809
e04659e8
MF		 283 * mips.igen (check_u64): Enable for `r3900'.
284
1554f758
MF		 2852016-02-05 Mike Frysinger <vapier@gentoo.org>
286
287 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
288 STATE_PROG_BFD (sd).
289 * configure: Regenerate.
290
3d304f48
AB		 2912016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
292 Maciej W. Rozycki <macro@imgtec.com>
293
294 PR sim/19441
295 * micromips.igen (delayslot_micromips): Enable for `micromips32',
296 `micromips64' and `micromipsdsp' only.
297 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
298 (do_micromips_jalr, do_micromips_jal): Likewise.
299 (compute_movep_src_reg): Likewise.
300 (compute_andi16_imm): Likewise.
301 (convert_fmt_micromips): Likewise.
302 (convert_fmt_micromips_cvt_d): Likewise.
303 (convert_fmt_micromips_cvt_s): Likewise.
304 (FMT_MICROMIPS): Likewise.
305 (FMT_MICROMIPS_CVT_D): Likewise.
306 (FMT_MICROMIPS_CVT_S): Likewise.
307
b36d953b
MF		 3082016-01-12 Mike Frysinger <vapier@gentoo.org>
309
310 * interp.c: Include elf-bfd.h.
311 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
312 ELFCLASS32.
313
ce39bd38
MF		 3142016-01-10 Mike Frysinger <vapier@gentoo.org>
315
316 * config.in, configure: Regenerate.
317
99d8e879
MF		 3182016-01-10 Mike Frysinger <vapier@gentoo.org>
319
320 * configure: Regenerate.
321
35656e95
MF		 3222016-01-10 Mike Frysinger <vapier@gentoo.org>
323
324 * configure: Regenerate.
325
16f7876d
MF		 3262016-01-10 Mike Frysinger <vapier@gentoo.org>
327
328 * configure: Regenerate.
329
e19418e0
MF		 3302016-01-10 Mike Frysinger <vapier@gentoo.org>
331
332 * configure: Regenerate.
333
6d90347b
MF		 3342016-01-10 Mike Frysinger <vapier@gentoo.org>
335
336 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
337 * configure: Regenerate.
338
347fe5bb
MF		 3392016-01-10 Mike Frysinger <vapier@gentoo.org>
340
341 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
342 * configure: Regenerate.
343
22be3fbe
MF		 3442016-01-10 Mike Frysinger <vapier@gentoo.org>
345
346 * configure: Regenerate.
347
0dc73ef7
MF		 3482016-01-10 Mike Frysinger <vapier@gentoo.org>
349
350 * configure: Regenerate.
351
936df756
MF		 3522016-01-09 Mike Frysinger <vapier@gentoo.org>
353
354 * config.in, configure: Regenerate.
355
2e3d4f4d
MF		 3562016-01-06 Mike Frysinger <vapier@gentoo.org>
357
358 * interp.c (sim_open): Mark argv const.
359 (sim_create_inferior): Mark argv and env const.
360
9bbf6f91
MF		 3612016-01-04 Mike Frysinger <vapier@gentoo.org>
362
363 * configure: Regenerate.
364
77cf2ef5
MF		 3652016-01-03 Mike Frysinger <vapier@gentoo.org>
366
367 * interp.c (sim_open): Update sim_parse_args comment.
368
0cb8d851
MF		 3692016-01-03 Mike Frysinger <vapier@gentoo.org>
370
371 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
372 * configure: Regenerate.
373
1ac72f06
MF		 3742016-01-02 Mike Frysinger <vapier@gentoo.org>
375
376 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
377 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
378 * configure: Regenerate.
379 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
380
d47f5b30
MF		 3812016-01-02 Mike Frysinger <vapier@gentoo.org>
382
383 * dv-tx3904cpu.c (CPU, SD): Delete.
384
e1211e55
MF		 3852015-12-30 Mike Frysinger <vapier@gentoo.org>
386
387 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
388 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
389 (sim_store_register): Rename to ...
390 (mips_reg_store): ... this. Delete local cpu var.
391 Update sim_io_eprintf calls.
392 (sim_fetch_register): Rename to ...
393 (mips_reg_fetch): ... this. Delete local cpu var.
394 Update sim_io_eprintf calls.
395
5e744ef8
MF		 3962015-12-27 Mike Frysinger <vapier@gentoo.org>
397
398 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
399
1b393626
MF		 4002015-12-26 Mike Frysinger <vapier@gentoo.org>
401
402 * config.in, configure: Regenerate.
403
26f8bf63
MF		 4042015-12-26 Mike Frysinger <vapier@gentoo.org>
405
406 * interp.c (sim_write, sim_read): Delete.
407 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
408 (load_word): Likewise.
409 * micromips.igen (cache): Likewise.
410 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
411 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
412 do_store_left, do_store_right, do_load_double, do_store_double):
413 Likewise.
414 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
415 (do_prefx): Likewise.
416 * sim-main.c (address_translation, prefetch): Delete.
417 (ifetch32, ifetch16): Delete call to AddressTranslation and set
418 paddr=vaddr.
419 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
420 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
421 (LoadMemory, StoreMemory): Delete CCA arg.
422
ef04e371
MF		 4232015-12-24 Mike Frysinger <vapier@gentoo.org>
424
425 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
426 * configure: Regenerated.
427
cb379ede
MF		 4282015-12-24 Mike Frysinger <vapier@gentoo.org>
429
430 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
431 * tconfig.h: Delete.
432
26936211
MF		 4332015-12-24 Mike Frysinger <vapier@gentoo.org>
434
435 * tconfig.h (SIM_HANDLES_LMA): Delete.
436
84e8e361
MF		 4372015-12-24 Mike Frysinger <vapier@gentoo.org>
438
439 * sim-main.h (WITH_WATCHPOINTS): Delete.
440
3cabaf66
MF		 4412015-12-24 Mike Frysinger <vapier@gentoo.org>
442
443 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
444
8abe6c66
MF		 4452015-12-24 Mike Frysinger <vapier@gentoo.org>
446
447 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
448
1d19cae7
DV		 4492015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
450
451 * micromips.igen (process_isa_mode): Fix left shift of negative
452 value.
453
cdf850e9
MF		 4542015-11-17 Mike Frysinger <vapier@gentoo.org>
455
456 * sim-main.h (WITH_MODULO_MEMORY): Delete.
457
797eee42
MF		 4582015-11-15 Mike Frysinger <vapier@gentoo.org>
459
460 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
461
6e4f085c
MF		 4622015-11-14 Mike Frysinger <vapier@gentoo.org>
463
464 * interp.c (sim_close): Rename to ...
465 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
466 sim_io_shutdown.
467 * sim-main.h (mips_sim_close): Declare.
468 (SIM_CLOSE_HOOK): Define.
469
8e394ffc
AB		 4702015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
471 Ali Lown <ali.lown@imgtec.com>
472
473 * Makefile.in (tmp-micromips): New rule.
474 (tmp-mach-multi): Add support for micromips.
475 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
476 that works for both mips64 and micromips64.
477 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
478 micromips32.
479 Add build support for micromips.
480 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
481 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
482 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
483 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
484 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
485 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
486 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
487 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
488 Refactored instruction code to use these functions.
489 * dsp2.igen: Refactored instruction code to use the new functions.
490 * interp.c (decode_coproc): Refactored to work with any instruction
491 encoding.
492 (isa_mode): New variable
493 (RSVD_INSTRUCTION): Changed to 0x00000039.
494 * m16.igen (BREAK16): Refactored instruction to use do_break16.
495 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
496 * micromips.dc: New file.
497 * micromips.igen: New file.
498 * micromips16.dc: New file.
499 * micromipsdsp.igen: New file.
500 * micromipsrun.c: New file.
501 * mips.igen (do_swc1): Changed to work with any instruction encoding.
502 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
503 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
504 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
505 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
506 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
507 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
508 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
509 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
510 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
511 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
512 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
513 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
514 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
515 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
516 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
517 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
518 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
519 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
520 instructions.
521 Refactored instruction code to use these functions.
522 (RSVD): Changed to use new reserved instruction.
523 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
524 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
525 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
526 do_store_double): Added micromips32 and micromips64 models.
527 Added include for micromips.igen and micromipsdsp.igen
528 Add micromips32 and micromips64 models.
529 (DecodeCoproc): Updated to use new macro definition.
530 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
531 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
532 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
533 Refactored instruction code to use these functions.
534 * sim-main.h (CP0_operation): New enum.
535 (DecodeCoproc): Updated macro.
536 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
537 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
538 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
539 ISA_MODE_MICROMIPS): New defines.
540 (sim_state): Add isa_mode field.
541
8d0978fb
MF		 5422015-06-23 Mike Frysinger <vapier@gentoo.org>
543
544 * configure: Regenerate.
545
306f4178
MF		 5462015-06-12 Mike Frysinger <vapier@gentoo.org>
547
548 * configure.ac: Change configure.in to configure.ac.
549 * configure: Regenerate.
550
a3487082
MF		 5512015-06-12 Mike Frysinger <vapier@gentoo.org>
552
553 * configure: Regenerate.
554
29bc024d
MF		 5552015-06-12 Mike Frysinger <vapier@gentoo.org>
556
557 * interp.c [TRACE]: Delete.
558 (TRACE): Change to WITH_TRACE_ANY_P.
559 [!WITH_TRACE_ANY_P] (open_trace): Define.
560 (mips_option_handler, open_trace, sim_close, dotrace):
561 Change defined(TRACE) to WITH_TRACE_ANY_P.
562 (sim_open): Delete TRACE ifdef check.
563 * sim-main.c (load_memory): Delete TRACE ifdef check.
564 (store_memory): Likewise.
565 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
566 [!WITH_TRACE_ANY_P] (dotrace): Define.
567
3ebe2863
MF		 5682015-04-18 Mike Frysinger <vapier@gentoo.org>
569
570 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
571 comments.
572
20bca71d
MF		 5732015-04-18 Mike Frysinger <vapier@gentoo.org>
574
575 * sim-main.h (SIM_CPU): Delete.
576
7e83aa92
MF		 5772015-04-18 Mike Frysinger <vapier@gentoo.org>
578
579 * sim-main.h (sim_cia): Delete.
580
034685f9
MF		 5812015-04-17 Mike Frysinger <vapier@gentoo.org>
582
583 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
584 PU_PC_GET.
585 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
586 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
587 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
588 CIA_SET to CPU_PC_SET.
589 * sim-main.h (CIA_GET, CIA_SET): Delete.
590
78e9aa70
MF		 5912015-04-15 Mike Frysinger <vapier@gentoo.org>
592
593 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
594 * sim-main.h (STATE_CPU): Delete.
595
bf12d44e
MF		 5962015-04-13 Mike Frysinger <vapier@gentoo.org>
597
598 * configure: Regenerate.
599
7bebb329
MF		 6002015-04-13 Mike Frysinger <vapier@gentoo.org>
601
602 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
603 * interp.c (mips_pc_get, mips_pc_set): New functions.
604 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
605 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
606 (sim_pc_get): Delete.
607 * sim-main.h (SIM_CPU): Define.
608 (struct sim_state): Change cpu to an array of pointers.
609 (STATE_CPU): Drop &.
610
8ac57fbd
MF		 6112015-04-13 Mike Frysinger <vapier@gentoo.org>
612
613 * interp.c (mips_option_handler, open_trace, sim_close,
614 sim_write, sim_read, sim_store_register, sim_fetch_register,
615 sim_create_inferior, pr_addr, pr_uword64): Convert old style
616 prototypes.
617 (sim_open): Convert old style prototype. Change casts with
618 sim_write to unsigned char *.
619 (fetch_str): Change null to unsigned char, and change cast to
620 unsigned char *.
621 (sim_monitor): Change c & ch to unsigned char. Change cast to
622 unsigned char *.
623
e787f858
MF		 6242015-04-12 Mike Frysinger <vapier@gentoo.org>
625
626 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
627
122bbfb5
MF		 6282015-04-06 Mike Frysinger <vapier@gentoo.org>
629
630 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
631
0fe84f3f
MF		 6322015-04-01 Mike Frysinger <vapier@gentoo.org>
633
634 * tconfig.h (SIM_HAVE_PROFILE): Delete.
635
aadc9410
MF		 6362015-03-31 Mike Frysinger <vapier@gentoo.org>
637
638 * config.in, configure: Regenerate.
639
05f53ed6
MF		 6402015-03-24 Mike Frysinger <vapier@gentoo.org>
641
642 * interp.c (sim_pc_get): New function.
643
c0931f26
MF		 6442015-03-24 Mike Frysinger <vapier@gentoo.org>
645
646 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
647 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
648
30452bbe
MF		 6492015-03-24 Mike Frysinger <vapier@gentoo.org>
650
651 * configure: Regenerate.
652
64dd13df
MF		 6532015-03-23 Mike Frysinger <vapier@gentoo.org>
654
655 * configure: Regenerate.
656
49cd1634
MF		 6572015-03-23 Mike Frysinger <vapier@gentoo.org>
658
659 * configure: Regenerate.
660 * configure.ac (mips_extra_objs): Delete.
661 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
662 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
663
3649cb06
MF		 6642015-03-23 Mike Frysinger <vapier@gentoo.org>
665
666 * configure: Regenerate.
667 * configure.ac: Delete sim_hw checks for dv-sockser.
668
ae7d0cac
MF		 6692015-03-16 Mike Frysinger <vapier@gentoo.org>
670
671 * config.in, configure: Regenerate.
672 * tconfig.in: Rename file ...
673 * tconfig.h: ... here.
674
8406bb59
MF		 6752015-03-15 Mike Frysinger <vapier@gentoo.org>
676
677 * tconfig.in: Delete includes.
678 [HAVE_DV_SOCKSER]: Delete.
679
465fb143
MF		 6802015-03-14 Mike Frysinger <vapier@gentoo.org>
681
682 * Makefile.in (SIM_RUN_OBJS): Delete.
683
5cddc23a
MF		 6842015-03-14 Mike Frysinger <vapier@gentoo.org>
685
686 * configure.ac (AC_CHECK_HEADERS): Delete.
687 * aclocal.m4, configure: Regenerate.
688
2974be62
AM		 6892014-08-19 Alan Modra <amodra@gmail.com>
690
691 * configure: Regenerate.
692
faa743bb
RM		 6932014-08-15 Roland McGrath <mcgrathr@google.com>
694
695 * configure: Regenerate.
696 * config.in: Regenerate.
697
1a8a700e
MF		 6982014-03-04 Mike Frysinger <vapier@gentoo.org>
699
700 * configure: Regenerate.
701
bf3d9781
AM		 7022013-09-23 Alan Modra <amodra@gmail.com>
703
704 * configure: Regenerate.
705
31e6ad7d
MF		 7062013-06-03 Mike Frysinger <vapier@gentoo.org>
707
708 * aclocal.m4, configure: Regenerate.
709
d3685d60
TT		 7102013-05-10 Freddie Chopin <freddie_chopin@op.pl>
711
712 * configure: Rebuild.
713
1517bd27
MF		 7142013-03-26 Mike Frysinger <vapier@gentoo.org>
715
716 * configure: Regenerate.
717
3be31516
JS		 7182013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
719
720 * configure.ac: Address use of dv-sockser.o.
721 * tconfig.in: Conditionalize use of dv_sockser_install.
722 * configure: Regenerated.
723 * config.in: Regenerated.
724
37cb8f8e
SE		 7252012-10-04 Chao-ying Fu <fu@mips.com>
726 Steve Ellcey <sellcey@mips.com>
727
728 * mips/mips3264r2.igen (rdhwr): New.
729
87c8644f
JS		 7302012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
731
732 * configure.ac: Always link against dv-sockser.o.
733 * configure: Regenerate.
734
5f3ef9d0
JB		 7352012-06-15 Joel Brobecker <brobecker@adacore.com>
736
737 * config.in, configure: Regenerate.
738
a6ff997c
NC		 7392012-05-18 Nick Clifton <nickc@redhat.com>
740
741 PR 14072
742 * interp.c: Include config.h before system header files.
743
2232061b
MF		 7442012-03-24 Mike Frysinger <vapier@gentoo.org>
745
746 * aclocal.m4, config.in, configure: Regenerate.
747
db2e4d67
MF		 7482011-12-03 Mike Frysinger <vapier@gentoo.org>
749
750 * aclocal.m4: New file.
751 * configure: Regenerate.
752
4399a56b
MF		 7532011-10-19 Mike Frysinger <vapier@gentoo.org>
754
755 * configure: Regenerate after common/acinclude.m4 update.
756
9c082ca8
MF		 7572011-10-17 Mike Frysinger <vapier@gentoo.org>
758
759 * configure.ac: Change include to common/acinclude.m4.
760
6ffe910a
MF		 7612011-10-17 Mike Frysinger <vapier@gentoo.org>
762
763 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
764 call. Replace common.m4 include with SIM_AC_COMMON.
765 * configure: Regenerate.
766
31b28250
HPN		 7672011-07-08 Hans-Peter Nilsson <hp@axis.com>
768
3faa01e3
HPN		 769 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
770 $(SIM_EXTRA_DEPS).
771 (tmp-mach-multi): Exit early when igen fails.
31b28250 772
2419798b
MF		 7732011-07-05 Mike Frysinger <vapier@gentoo.org>
774
775 * interp.c (sim_do_command): Delete.
776
d79fe0d6
MF		 7772011-02-14 Mike Frysinger <vapier@gentoo.org>
778
779 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
780 (tx3904sio_fifo_reset): Likewise.
781 * interp.c (sim_monitor): Likewise.
782
5558e7e6
MF		 7832010-04-14 Mike Frysinger <vapier@gentoo.org>
784
785 * interp.c (sim_write): Add const to buffer arg.
786
35aafff4
JB		 7872010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
788
789 * interp.c: Don't include sysdep.h
790
3725885a
RW		 7912010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
792
793 * configure: Regenerate.
794
d6416cdc
RW		 7952009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
796
81ecdfbb
RW		 797 * config.in: Regenerate.
798 * configure: Likewise.
799
d6416cdc
RW		 800 * configure: Regenerate.
801
b5bd9624
HPN		 8022008-07-11 Hans-Peter Nilsson <hp@axis.com>
803
804 * configure: Regenerate to track ../common/common.m4 changes.
805 * config.in: Ditto.
806
6efef468 8072008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 808 Daniel Jacobowitz <dan@codesourcery.com>
809 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 810
811 * configure: Regenerate.
812
60dc88db
RS		 8132007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
814
815 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
816 that unconditionally allows fmt_ps.
817 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
818 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
819 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
820 filter from 64,f to 32,f.
821 (PREFX): Change filter from 64 to 32.
822 (LDXC1, LUXC1): Provide separate mips32r2 implementations
823 that use do_load_double instead of do_load. Make both LUXC1
824 versions unpredictable if SizeFGR () != 64.
825 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
826 instead of do_store. Remove unused variable. Make both SUXC1
827 versions unpredictable if SizeFGR () != 64.
828
599ca73e
RS		 8292007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
830
831 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
832 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
833 shifts for that case.
834
2525df03
NC		 8352007-09-04 Nick Clifton <nickc@redhat.com>
836
837 * interp.c (options enum): Add OPTION_INFO_MEMORY.
838 (display_mem_info): New static variable.
839 (mips_option_handler): Handle OPTION_INFO_MEMORY.
840 (mips_options): Add info-memory and memory-info.
841 (sim_open): After processing the command line and board
842 specification, check display_mem_info. If it is set then
843 call the real handler for the --memory-info command line
844 switch.
845
35ee6e1e
JB		 8462007-08-24 Joel Brobecker <brobecker@adacore.com>
847
848 * configure.ac: Change license of multi-run.c to GPL version 3.
849 * configure: Regenerate.
850
d5fb0879
RS		 8512007-06-28 Richard Sandiford <richard@codesourcery.com>
852
853 * configure.ac, configure: Revert last patch.
854
2a2ce21b
RS		 8552007-06-26 Richard Sandiford <richard@codesourcery.com>
856
857 * configure.ac (sim_mipsisa3264_configs): New variable.
858 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
859 every configuration support all four targets, using the triplet to
860 determine the default.
861 * configure: Regenerate.
862
efdcccc9
RS		 8632007-06-25 Richard Sandiford <richard@codesourcery.com>
864
0a7692b2 865 * Makefile.in (m16run.o): New rule.
efdcccc9 866
f532a356
TS		 8672007-05-15 Thiemo Seufer <ths@mips.com>
868
869 * mips3264r2.igen (DSHD): Fix compile warning.
870
bfe9c90b
TS		 8712007-05-14 Thiemo Seufer <ths@mips.com>
872
873 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
874 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
875 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
876 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
877 for mips32r2.
878
53f4826b
TS		 8792007-03-01 Thiemo Seufer <ths@mips.com>
880
881 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
882 and mips64.
883
8bf3ddc8
TS		 8842007-02-20 Thiemo Seufer <ths@mips.com>
885
886 * dsp.igen: Update copyright notice.
887 * dsp2.igen: Fix copyright notice.
888
8b082fb1 8892007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 890 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 891
892 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
893 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
894 Add dsp2 to sim_igen_machine.
895 * configure: Regenerate.
896 * dsp.igen (do_ph_op): Add MUL support when op = 2.
897 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
898 (mulq_rs.ph): Use do_ph_mulq.
899 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
900 * mips.igen: Add dsp2 model and include dsp2.igen.
901 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
902 for *mips32r2, *mips64r2, *dsp.
903 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
904 for *mips32r2, *mips64r2, *dsp2.
905 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
906
b1004875 9072007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 908 Nigel Stephens <nigel@mips.com>
b1004875
TS		 909
910 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
911 jumps with hazard barrier.
912
f8df4c77 9132007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 914 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 915
916 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
917 after each call to sim_io_write.
918
b1004875 9192007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 920 Nigel Stephens <nigel@mips.com>
b1004875
TS		 921
922 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
923 supported by this simulator.
07802d98
TS		 924 (decode_coproc): Recognise additional CP0 Config registers
925 correctly.
926
14fb6c5a 9272007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 928 Nigel Stephens <nigel@mips.com>
929 David Ung <davidu@mips.com>
14fb6c5a
TS		 930
931 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
932 uninterpreted formats. If fmt is one of the uninterpreted types
933 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
934 fmt_word, and fmt_uninterpreted_64 like fmt_long.
935 (store_fpr): When writing an invalid odd register, set the
936 matching even register to fmt_unknown, not the following register.
937 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
938 the the memory window at offset 0 set by --memory-size command
939 line option.
940 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
941 point register.
942 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
943 register.
944 (sim_monitor): When returning the memory size to the MIPS
945 application, use the value in STATE_MEM_SIZE, not an arbitrary
946 hardcoded value.
947 (cop_lw): Don' mess around with FPR_STATE, just pass
948 fmt_uninterpreted_32 to StoreFPR.
949 (cop_sw): Similarly.
950 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
951 (cop_sd): Similarly.
952 * mips.igen (not_word_value): Single version for mips32, mips64
953 and mips16.
954
c8847145 9552007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 956 Nigel Stephens <nigel@mips.com>
c8847145
TS		 957
958 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
959 MBytes.
960
4b5d35ee
TS		 9612007-02-17 Thiemo Seufer <ths@mips.com>
962
963 * configure.ac (mips*-sde-elf*): Move in front of generic machine
964 configuration.
965 * configure: Regenerate.
966
3669427c
TS		 9672007-02-17 Thiemo Seufer <ths@mips.com>
968
969 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
970 Add mdmx to sim_igen_machine.
971 (mipsisa64*-*-*): Likewise. Remove dsp.
972 (mipsisa32*-*-*): Remove dsp.
973 * configure: Regenerate.
974
109ad085
TS		 9752007-02-13 Thiemo Seufer <ths@mips.com>
976
977 * configure.ac: Add mips*-sde-elf* target.
978 * configure: Regenerate.
979
921d7ad3
HPN		 9802006-12-21 Hans-Peter Nilsson <hp@axis.com>
981
982 * acconfig.h: Remove.
983 * config.in, configure: Regenerate.
984
02f97da7
TS		 9852006-11-07 Thiemo Seufer <ths@mips.com>
986
987 * dsp.igen (do_w_op): Fix compiler warning.
988
2d2733fc 9892006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 990 David Ung <davidu@mips.com>
2d2733fc
TS		 991
992 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
993 sim_igen_machine.
994 * configure: Regenerate.
995 * mips.igen (model): Add smartmips.
996 (MADDU): Increment ACX if carry.
997 (do_mult): Clear ACX.
998 (ROR,RORV): Add smartmips.
72f4393d 999 (include): Include smartmips.igen.
2d2733fc
TS		 1000 * sim-main.h (ACX): Set to REGISTERS[89].
1001 * smartmips.igen: New file.
1002
d85c3a10 10032006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 1004 David Ung <davidu@mips.com>
d85c3a10
TS		 1005
1006 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
1007 mips3264r2.igen. Add missing dependency rules.
1008 * m16e.igen: Support for mips16e save/restore instructions.
1009
e85e3205
RE		 10102006-06-13 Richard Earnshaw <rearnsha@arm.com>
1011
1012 * configure: Regenerated.
1013
2f0122dc
DJ		 10142006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
1015
1016 * configure: Regenerated.
1017
20e95c23
DJ		 10182006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
1019
1020 * configure: Regenerated.
1021
69088b17
CF		 10222006-05-15 Chao-ying Fu <fu@mips.com>
1023
1024 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
1025
0275de4e
NC		 10262006-04-18 Nick Clifton <nickc@redhat.com>
1027
1028 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
1029 statement.
1030
b3a3ffef
HPN		 10312006-03-29 Hans-Peter Nilsson <hp@axis.com>
1032
1033 * configure: Regenerate.
1034
40a5538e
CF		 10352005-12-14 Chao-ying Fu <fu@mips.com>
1036
1037 * Makefile.in (SIM_OBJS): Add dsp.o.
1038 (dsp.o): New dependency.
1039 (IGEN_INCLUDE): Add dsp.igen.
1040 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
1041 mipsisa64*-*-*): Add dsp to sim_igen_machine.
1042 * configure: Regenerate.
1043 * mips.igen: Add dsp model and include dsp.igen.
1044 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1045 because these instructions are extended in DSP ASE.
1046 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1047 adding 6 DSP accumulator registers and 1 DSP control register.
1048 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1049 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1050 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1051 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1052 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1053 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1054 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1055 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1056 DSPCR_CCOND_SMASK): New define.
1057 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1058 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1059
21d14896
ILT		 10602005-07-08 Ian Lance Taylor <ian@airs.com>
1061
1062 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1063
b16d63da 10642005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1065 Nigel Stephens <nigel@mips.com>
1066
1067 * mips.igen: New mips16e model and include m16e.igen.
1068 (check_u64): Add mips16e tag.
1069 * m16e.igen: New file for MIPS16e instructions.
1070 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1071 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1072 models.
1073 * configure: Regenerate.
b16d63da 1074
e70cb6cd 10752005-05-26 David Ung <davidu@mips.com>
72f4393d 1076
e70cb6cd
CD		 1077 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1078 tags to all instructions which are applicable to the new ISAs.
1079 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1080 vr.igen.
1081 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1082 instructions.
e70cb6cd
CD		 1083 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1084 to mips.igen.
1085 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1086 * configure: Regenerate.
72f4393d 1087
2b193c4a
MK		 10882005-03-23 Mark Kettenis <kettenis@gnu.org>
1089
1090 * configure: Regenerate.
1091
35695fd6
AC		 10922005-01-14 Andrew Cagney <cagney@gnu.org>
1093
1094 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1095 explicit call to AC_CONFIG_HEADER.
1096 * configure: Regenerate.
1097
f0569246
AC		 10982005-01-12 Andrew Cagney <cagney@gnu.org>
1099
1100 * configure.ac: Update to use ../common/common.m4.
1101 * configure: Re-generate.
1102
38f48d72
AC		 11032005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1104
1105 * configure: Regenerated to track ../common/aclocal.m4 changes.
1106
b7026657
AC		 11072005-01-07 Andrew Cagney <cagney@gnu.org>
1108
1109 * configure.ac: Rename configure.in, require autoconf 2.59.
1110 * configure: Re-generate.
1111
379832de
HPN		 11122004-12-08 Hans-Peter Nilsson <hp@axis.com>
1113
1114 * configure: Regenerate for ../common/aclocal.m4 update.
1115
cd62154c 11162004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1117
cd62154c
AC		 1118 Committed by Andrew Cagney.
1119 * m16.igen (CMP, CMPI): Fix assembler.
1120
e5da76ec
CD		 11212004-08-18 Chris Demetriou <cgd@broadcom.com>
1122
1123 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1124 * configure: Regenerate.
1125
139181c8
CD		 11262004-06-25 Chris Demetriou <cgd@broadcom.com>
1127
1128 * configure.in (sim_m16_machine): Include mipsIII.
1129 * configure: Regenerate.
1130
1a27f959
CD		 11312004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1132
72f4393d 1133 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1134 from COP0_BADVADDR.
1135 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1136
5dbb7b5a
CD		 11372004-04-10 Chris Demetriou <cgd@broadcom.com>
1138
1139 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1140
14234056
CD		 11412004-04-09 Chris Demetriou <cgd@broadcom.com>
1142
1143 * mips.igen (check_fmt): Remove.
1144 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1145 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1146 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1147 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1148 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1149 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1150 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1151 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1152 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1153 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1154
c6f9085c
CD		 11552004-04-09 Chris Demetriou <cgd@broadcom.com>
1156
1157 * sb1.igen (check_sbx): New function.
1158 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1159
11d66e66 11602004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1161 Richard Sandiford <rsandifo@redhat.com>
1162
1163 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1164 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1165 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1166 separate implementations for mipsIV and mipsV. Use new macros to
1167 determine whether the restrictions apply.
1168
b3208fb8
CD		 11692004-01-19 Chris Demetriou <cgd@broadcom.com>
1170
1171 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1172 (check_mult_hilo): Improve comments.
1173 (check_div_hilo): Likewise. Also, fork off a new version
1174 to handle mips32/mips64 (since there are no hazards to check
1175 in MIPS32/MIPS64).
1176
9a1d84fb
CD		 11772003-06-17 Richard Sandiford <rsandifo@redhat.com>
1178
1179 * mips.igen (do_dmultx): Fix check for negative operands.
1180
ae451ac6
ILT		 11812003-05-16 Ian Lance Taylor <ian@airs.com>
1182
1183 * Makefile.in (SHELL): Make sure this is defined.
1184 (various): Use $(SHELL) whenever we invoke move-if-change.
1185
dd69d292
CD		 11862003-05-03 Chris Demetriou <cgd@broadcom.com>
1187
1188 * cp1.c: Tweak attribution slightly.
1189 * cp1.h: Likewise.
1190 * mdmx.c: Likewise.
1191 * mdmx.igen: Likewise.
1192 * mips3d.igen: Likewise.
1193 * sb1.igen: Likewise.
1194
bcd0068e
CD		 11952003-04-15 Richard Sandiford <rsandifo@redhat.com>
1196
1197 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1198 unsigned operands.
1199
6b4a8935
AC		 12002003-02-27 Andrew Cagney <cagney@redhat.com>
1201
601da316
AC		 1202 * interp.c (sim_open): Rename _bfd to bfd.
1203 (sim_create_inferior): Ditto.
6b4a8935 1204
d29e330f
CD		 12052003-01-14 Chris Demetriou <cgd@broadcom.com>
1206
1207 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1208
a2353a08
CD		 12092003-01-14 Chris Demetriou <cgd@broadcom.com>
1210
1211 * mips.igen (EI, DI): Remove.
1212
80551777
CD		 12132003-01-05 Richard Sandiford <rsandifo@redhat.com>
1214
1215 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1216
4c54fc26
CD		 12172003-01-04 Richard Sandiford <rsandifo@redhat.com>
1218 Andrew Cagney <ac131313@redhat.com>
1219 Gavin Romig-Koch <gavin@redhat.com>
1220 Graydon Hoare <graydon@redhat.com>
1221 Aldy Hernandez <aldyh@redhat.com>
1222 Dave Brolley <brolley@redhat.com>
1223 Chris Demetriou <cgd@broadcom.com>
1224
1225 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1226 (sim_mach_default): New variable.
1227 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1228 Add a new simulator generator, MULTI.
1229 * configure: Regenerate.
1230 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1231 (multi-run.o): New dependency.
1232 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1233 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1234 (tmp-multi): Combine them.
1235 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1236 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1237 (distclean-extra): New rule.
1238 * sim-main.h: Include bfd.h.
1239 (MIPS_MACH): New macro.
1240 * mips.igen (vr4120, vr5400, vr5500): New models.
1241 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1242 * vr.igen: Replace with new version.
1243
e6c674b8
CD		 12442003-01-04 Chris Demetriou <cgd@broadcom.com>
1245
1246 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1247 * configure: Regenerate.
1248
28f50ac8
CD		 12492002-12-31 Chris Demetriou <cgd@broadcom.com>
1250
1251 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1252 * mips.igen: Remove all invocations of check_branch_bug and
1253 mark_branch_bug.
1254
5071ffe6
CD		 12552002-12-16 Chris Demetriou <cgd@broadcom.com>
1256
72f4393d 1257 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1258
06e7837e
CD		 12592002-07-30 Chris Demetriou <cgd@broadcom.com>
1260
1261 * mips.igen (do_load_double, do_store_double): New functions.
1262 (LDC1, SDC1): Rename to...
1263 (LDC1b, SDC1b): respectively.
1264 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1265
2265c243
MS		 12662002-07-29 Michael Snyder <msnyder@redhat.com>
1267
1268 * cp1.c (fp_recip2): Modify initialization expression so that
1269 GCC will recognize it as constant.
1270
a2f8b4f3
CD		 12712002-06-18 Chris Demetriou <cgd@broadcom.com>
1272
1273 * mdmx.c (SD_): Delete.
1274 (Unpredictable): Re-define, for now, to directly invoke
1275 unpredictable_action().
1276 (mdmx_acc_op): Fix error in .ob immediate handling.
1277
b4b6c939
AC		 12782002-06-18 Andrew Cagney <cagney@redhat.com>
1279
1280 * interp.c (sim_firmware_command): Initialize `address'.
1281
c8cca39f
AC		 12822002-06-16 Andrew Cagney <ac131313@redhat.com>
1283
1284 * configure: Regenerated to track ../common/aclocal.m4 changes.
1285
e7e81181 12862002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1287 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1288
1289 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1290 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1291 * mips.igen: Include mips3d.igen.
1292 (mips3d): New model name for MIPS-3D ASE instructions.
1293 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1294 instructions.
e7e81181
CD		 1295 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1296 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1297 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1298 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1299 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1300 (RSquareRoot1, RSquareRoot2): New macros.
1301 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1302 (fp_rsqrt2): New functions.
1303 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1304 * configure: Regenerate.
1305
3a2b820e 13062002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1307 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1308
1309 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1310 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1311 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1312 (convert): Note that this function is not used for paired-single
1313 format conversions.
1314 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1315 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1316 (check_fmt_p): Enable paired-single support.
1317 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1318 (PUU.PS): New instructions.
1319 (CVT.S.fmt): Don't use this instruction for paired-single format
1320 destinations.
1321 * sim-main.h (FP_formats): New value 'fmt_ps.'
1322 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1323 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1324
d18ea9c2
CD		 13252002-06-12 Chris Demetriou <cgd@broadcom.com>
1326
1327 * mips.igen: Fix formatting of function calls in
1328 many FP operations.
1329
95fd5cee
CD		 13302002-06-12 Chris Demetriou <cgd@broadcom.com>
1331
1332 * mips.igen (MOVN, MOVZ): Trace result.
1333 (TNEI): Print "tnei" as the opcode name in traces.
1334 (CEIL.W): Add disassembly string for traces.
1335 (RSQRT.fmt): Make location of disassembly string consistent
1336 with other instructions.
1337
4f0d55ae
CD		 13382002-06-12 Chris Demetriou <cgd@broadcom.com>
1339
1340 * mips.igen (X): Delete unused function.
1341
3c25f8c7
AC		 13422002-06-08 Andrew Cagney <cagney@redhat.com>
1343
1344 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1345
f3c08b7e 13462002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1347 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1348
1349 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1350 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1351 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1352 (fp_nmsub): New prototypes.
1353 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1354 (NegMultiplySub): New defines.
1355 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1356 (MADD.D, MADD.S): Replace with...
1357 (MADD.fmt): New instruction.
1358 (MSUB.D, MSUB.S): Replace with...
1359 (MSUB.fmt): New instruction.
1360 (NMADD.D, NMADD.S): Replace with...
1361 (NMADD.fmt): New instruction.
1362 (NMSUB.D, MSUB.S): Replace with...
1363 (NMSUB.fmt): New instruction.
1364
52714ff9 13652002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1366 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1367
1368 * cp1.c: Fix more comment spelling and formatting.
1369 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1370 (denorm_mode): New function.
1371 (fpu_unary, fpu_binary): Round results after operation, collect
1372 status from rounding operations, and update the FCSR.
1373 (convert): Collect status from integer conversions and rounding
1374 operations, and update the FCSR. Adjust NaN values that result
1375 from conversions. Convert to use sim_io_eprintf rather than
1376 fprintf, and remove some debugging code.
1377 * cp1.h (fenr_FS): New define.
1378
577d8c4b
CD		 13792002-06-07 Chris Demetriou <cgd@broadcom.com>
1380
1381 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1382 rounding mode to sim FP rounding mode flag conversion code into...
1383 (rounding_mode): New function.
1384
196496ed
CD		 13852002-06-07 Chris Demetriou <cgd@broadcom.com>
1386
1387 * cp1.c: Clean up formatting of a few comments.
1388 (value_fpr): Reformat switch statement.
1389
cfe9ea23 13902002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1391 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1392
1393 * cp1.h: New file.
1394 * sim-main.h: Include cp1.h.
1395 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1396 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1397 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1398 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1399 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1400 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1401 * cp1.c: Don't include sim-fpu.h; already included by
1402 sim-main.h. Clean up formatting of some comments.
1403 (NaN, Equal, Less): Remove.
1404 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1405 (fp_cmp): New functions.
1406 * mips.igen (do_c_cond_fmt): Remove.
1407 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1408 Compare. Add result tracing.
1409 (CxC1): Remove, replace with...
1410 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1411 (DMxC1): Remove, replace with...
1412 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1413 (MxC1): Remove, replace with...
1414 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1415
ee7254b0
CD		 14162002-06-04 Chris Demetriou <cgd@broadcom.com>
1417
1418 * sim-main.h (FGRIDX): Remove, replace all uses with...
1419 (FGR_BASE): New macro.
1420 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1421 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1422 (NR_FGR, FGR): Likewise.
1423 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1424 * mips.igen: Likewise.
1425
d3eb724f
CD		 14262002-06-04 Chris Demetriou <cgd@broadcom.com>
1427
1428 * cp1.c: Add an FSF Copyright notice to this file.
1429
ba46ddd0 14302002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1431 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1432
1433 * cp1.c (Infinity): Remove.
1434 * sim-main.h (Infinity): Likewise.
1435
1436 * cp1.c (fp_unary, fp_binary): New functions.
1437 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1438 (fp_sqrt): New functions, implemented in terms of the above.
1439 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1440 (Recip, SquareRoot): Remove (replaced by functions above).
1441 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1442 (fp_recip, fp_sqrt): New prototypes.
1443 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1444 (Recip, SquareRoot): Replace prototypes with #defines which
1445 invoke the functions above.
72f4393d 1446
18d8a52d
CD		 14472002-06-03 Chris Demetriou <cgd@broadcom.com>
1448
1449 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1450 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1451 file, remove PARAMS from prototypes.
1452 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1453 simulator state arguments.
1454 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1455 pass simulator state arguments.
1456 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1457 (store_fpr, convert): Remove 'sd' argument.
1458 (value_fpr): Likewise. Convert to use 'SD' instead.
1459
0f154cbd
CD		 14602002-06-03 Chris Demetriou <cgd@broadcom.com>
1461
1462 * cp1.c (Min, Max): Remove #if 0'd functions.
1463 * sim-main.h (Min, Max): Remove.
1464
e80fc152
CD		 14652002-06-03 Chris Demetriou <cgd@broadcom.com>
1466
1467 * cp1.c: fix formatting of switch case and default labels.
1468 * interp.c: Likewise.
1469 * sim-main.c: Likewise.
1470
bad673a9
CD		 14712002-06-03 Chris Demetriou <cgd@broadcom.com>
1472
1473 * cp1.c: Clean up comments which describe FP formats.
1474 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1475
7cbea089 14762002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1477 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1478
1479 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1480 Broadcom SiByte SB-1 processor configurations.
1481 * configure: Regenerate.
1482 * sb1.igen: New file.
1483 * mips.igen: Include sb1.igen.
1484 (sb1): New model.
1485 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1486 * mdmx.igen: Add "sb1" model to all appropriate functions and
1487 instructions.
1488 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1489 (ob_func, ob_acc): Reference the above.
1490 (qh_acc): Adjust to keep the same size as ob_acc.
1491 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1492 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1493
909daa82
CD		 14942002-06-03 Chris Demetriou <cgd@broadcom.com>
1495
1496 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1497
f4f1b9f1 14982002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1499 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1500
1501 * mips.igen (mdmx): New (pseudo-)model.
1502 * mdmx.c, mdmx.igen: New files.
1503 * Makefile.in (SIM_OBJS): Add mdmx.o.
1504 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1505 New typedefs.
1506 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1507 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1508 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1509 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1510 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1511 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1512 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1513 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1514 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1515 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1516 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1517 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1518 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1519 (qh_fmtsel): New macros.
1520 (_sim_cpu): New member "acc".
1521 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1522 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1523
5accf1ff
CD		 15242002-05-01 Chris Demetriou <cgd@broadcom.com>
1525
1526 * interp.c: Use 'deprecated' rather than 'depreciated.'
1527 * sim-main.h: Likewise.
1528
402586aa
CD		 15292002-05-01 Chris Demetriou <cgd@broadcom.com>
1530
1531 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1532 which wouldn't compile anyway.
1533 * sim-main.h (unpredictable_action): New function prototype.
1534 (Unpredictable): Define to call igen function unpredictable().
1535 (NotWordValue): New macro to call igen function not_word_value().
1536 (UndefinedResult): Remove.
1537 * interp.c (undefined_result): Remove.
1538 (unpredictable_action): New function.
1539 * mips.igen (not_word_value, unpredictable): New functions.
1540 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1541 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1542 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1543 NotWordValue() to check for unpredictable inputs, then
1544 Unpredictable() to handle them.
1545
c9b9995a
CD		 15462002-02-24 Chris Demetriou <cgd@broadcom.com>
1547
1548 * mips.igen: Fix formatting of calls to Unpredictable().
1549
e1015982
AC		 15502002-04-20 Andrew Cagney <ac131313@redhat.com>
1551
1552 * interp.c (sim_open): Revert previous change.
1553
b882a66b
AO		 15542002-04-18 Alexandre Oliva <aoliva@redhat.com>
1555
1556 * interp.c (sim_open): Disable chunk of code that wrote code in
1557 vector table entries.
1558
c429b7dd
CD		 15592002-03-19 Chris Demetriou <cgd@broadcom.com>
1560
1561 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1562 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1563 unused definitions.
1564
37d146fa
CD		 15652002-03-19 Chris Demetriou <cgd@broadcom.com>
1566
1567 * cp1.c: Fix many formatting issues.
1568
07892c0b
CD		 15692002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1570
1571 * cp1.c (fpu_format_name): New function to replace...
1572 (DOFMT): This. Delete, and update all callers.
1573 (fpu_rounding_mode_name): New function to replace...
1574 (RMMODE): This. Delete, and update all callers.
1575
487f79b7
CD		 15762002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1577
1578 * interp.c: Move FPU support routines from here to...
1579 * cp1.c: Here. New file.
1580 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1581 (cp1.o): New target.
1582
1e799e28
CD		 15832002-03-12 Chris Demetriou <cgd@broadcom.com>
1584
1585 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1586 * mips.igen (mips32, mips64): New models, add to all instructions
1587 and functions as appropriate.
1588 (loadstore_ea, check_u64): New variant for model mips64.
1589 (check_fmt_p): New variant for models mipsV and mips64, remove
1590 mipsV model marking fro other variant.
1591 (SLL) Rename to...
1592 (SLLa) this.
1593 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1594 for mips32 and mips64.
1595 (DCLO, DCLZ): New instructions for mips64.
1596
82f728db
CD		 15972002-03-07 Chris Demetriou <cgd@broadcom.com>
1598
1599 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1600 immediate or code as a hex value with the "%#lx" format.
1601 (ANDI): Likewise, and fix printed instruction name.
1602
b96e7ef1
CD		 16032002-03-05 Chris Demetriou <cgd@broadcom.com>
1604
1605 * sim-main.h (UndefinedResult, Unpredictable): New macros
1606 which currently do nothing.
1607
d35d4f70
CD		 16082002-03-05 Chris Demetriou <cgd@broadcom.com>
1609
1610 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1611 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1612 (status_CU3): New definitions.
1613
1614 * sim-main.h (ExceptionCause): Add new values for MIPS32
1615 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1616 for DebugBreakPoint and NMIReset to note their status in
1617 MIPS32 and MIPS64.
1618 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1619 (SignalExceptionCacheErr): New exception macros.
1620
3ad6f714
CD		 16212002-03-05 Chris Demetriou <cgd@broadcom.com>
1622
1623 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1624 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1625 is always enabled.
1626 (SignalExceptionCoProcessorUnusable): Take as argument the
1627 unusable coprocessor number.
1628
86b77b47
CD		 16292002-03-05 Chris Demetriou <cgd@broadcom.com>
1630
1631 * mips.igen: Fix formatting of all SignalException calls.
1632
97a88e93 16332002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1634
1635 * sim-main.h (SIGNEXTEND): Remove.
1636
97a88e93 16372002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1638
1639 * mips.igen: Remove gencode comment from top of file, fix
1640 spelling in another comment.
1641
97a88e93 16422002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1643
1644 * mips.igen (check_fmt, check_fmt_p): New functions to check
1645 whether specific floating point formats are usable.
1646 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1647 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1648 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1649 Use the new functions.
1650 (do_c_cond_fmt): Remove format checks...
1651 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1652
97a88e93 16532002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1654
1655 * mips.igen: Fix formatting of check_fpu calls.
1656
41774c9d
CD		 16572002-03-03 Chris Demetriou <cgd@broadcom.com>
1658
1659 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1660
4a0bd876
CD		 16612002-03-03 Chris Demetriou <cgd@broadcom.com>
1662
1663 * mips.igen: Remove whitespace at end of lines.
1664
09297648
CD		 16652002-03-02 Chris Demetriou <cgd@broadcom.com>
1666
1667 * mips.igen (loadstore_ea): New function to do effective
1668 address calculations.
1669 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1670 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1671 CACHE): Use loadstore_ea to do effective address computations.
1672
043b7057
CD		 16732002-03-02 Chris Demetriou <cgd@broadcom.com>
1674
1675 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1676 * mips.igen (LL, CxC1, MxC1): Likewise.
1677
c1e8ada4
CD		 16782002-03-02 Chris Demetriou <cgd@broadcom.com>
1679
1680 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1681 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1682 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1683 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1684 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1685 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1686 Don't split opcode fields by hand, use the opcode field values
1687 provided by igen.
1688
3e1dca16
CD		 16892002-03-01 Chris Demetriou <cgd@broadcom.com>
1690
1691 * mips.igen (do_divu): Fix spacing.
1692
1693 * mips.igen (do_dsllv): Move to be right before DSLLV,
1694 to match the rest of the do_<shift> functions.
1695
fff8d27d
CD		 16962002-03-01 Chris Demetriou <cgd@broadcom.com>
1697
1698 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1699 DSRL32, do_dsrlv): Trace inputs and results.
1700
0d3e762b
CD		 17012002-03-01 Chris Demetriou <cgd@broadcom.com>
1702
1703 * mips.igen (CACHE): Provide instruction-printing string.
1704
1705 * interp.c (signal_exception): Comment tokens after #endif.
1706
eb5fcf93
CD		 17072002-02-28 Chris Demetriou <cgd@broadcom.com>
1708
1709 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1710 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1711 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1712 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1713 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1714 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1715 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1716 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1717
bb22bd7d
CD		 17182002-02-28 Chris Demetriou <cgd@broadcom.com>
1719
1720 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1721 instruction-printing string.
1722 (LWU): Use '64' as the filter flag.
1723
91a177cf
CD		 17242002-02-28 Chris Demetriou <cgd@broadcom.com>
1725
1726 * mips.igen (SDXC1): Fix instruction-printing string.
1727
387f484a
CD		 17282002-02-28 Chris Demetriou <cgd@broadcom.com>
1729
1730 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1731 filter flags "32,f".
1732
3d81f391
CD		 17332002-02-27 Chris Demetriou <cgd@broadcom.com>
1734
1735 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1736 as the filter flag.
1737
af5107af
CD		 17382002-02-27 Chris Demetriou <cgd@broadcom.com>
1739
1740 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1741 add a comma) so that it more closely match the MIPS ISA
1742 documentation opcode partitioning.
1743 (PREF): Put useful names on opcode fields, and include
1744 instruction-printing string.
1745
ca971540
CD		 17462002-02-27 Chris Demetriou <cgd@broadcom.com>
1747
1748 * mips.igen (check_u64): New function which in the future will
1749 check whether 64-bit instructions are usable and signal an
1750 exception if not. Currently a no-op.
1751 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1752 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1753 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1754 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1755
1756 * mips.igen (check_fpu): New function which in the future will
1757 check whether FPU instructions are usable and signal an exception
1758 if not. Currently a no-op.
1759 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1760 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1761 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1762 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1763 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1764 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1765 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1766 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1767
1c47a468
CD		 17682002-02-27 Chris Demetriou <cgd@broadcom.com>
1769
1770 * mips.igen (do_load_left, do_load_right): Move to be immediately
1771 following do_load.
1772 (do_store_left, do_store_right): Move to be immediately following
1773 do_store.
1774
603a98e7
CD		 17752002-02-27 Chris Demetriou <cgd@broadcom.com>
1776
1777 * mips.igen (mipsV): New model name. Also, add it to
1778 all instructions and functions where it is appropriate.
1779
c5d00cc7
CD		 17802002-02-18 Chris Demetriou <cgd@broadcom.com>
1781
1782 * mips.igen: For all functions and instructions, list model
1783 names that support that instruction one per line.
1784
074e9cb8
CD		 17852002-02-11 Chris Demetriou <cgd@broadcom.com>
1786
1787 * mips.igen: Add some additional comments about supported
1788 models, and about which instructions go where.
1789 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1790 order as is used in the rest of the file.
1791
9805e229
CD		 17922002-02-11 Chris Demetriou <cgd@broadcom.com>
1793
1794 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1795 indicating that ALU32_END or ALU64_END are there to check
1796 for overflow.
1797 (DADD): Likewise, but also remove previous comment about
1798 overflow checking.
1799
f701dad2
CD		 18002002-02-10 Chris Demetriou <cgd@broadcom.com>
1801
1802 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1803 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1804 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1805 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1806 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1807 fields (i.e., add and move commas) so that they more closely
1808 match the MIPS ISA documentation opcode partitioning.
1809
18102002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1811
72f4393d
L		 1812 * mips.igen (ADDI): Print immediate value.
1813 (BREAK): Print code.
1814 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1815 (SLL): Print "nop" specially, and don't run the code
1816 that does the shift for the "nop" case.
20ae0098 1817
9e52972e
FF		 18182001-11-17 Fred Fish <fnf@redhat.com>
1819
1820 * sim-main.h (float_operation): Move enum declaration outside
1821 of _sim_cpu struct declaration.
1822
c0efbca4
JB		 18232001-04-12 Jim Blandy <jimb@redhat.com>
1824
1825 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1826 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1827 set of the FCSR.
1828 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1829 PENDING_FILL, and you can get the intended effect gracefully by
1830 calling PENDING_SCHED directly.
1831
fb891446
BE		 18322001-02-23 Ben Elliston <bje@redhat.com>
1833
1834 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1835 already defined elsewhere.
1836
8030f857
BE		 18372001-02-19 Ben Elliston <bje@redhat.com>
1838
1839 * sim-main.h (sim_monitor): Return an int.
1840 * interp.c (sim_monitor): Add return values.
1841 (signal_exception): Handle error conditions from sim_monitor.
1842
56b48a7a
CD		 18432001-02-08 Ben Elliston <bje@redhat.com>
1844
1845 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1846 (store_memory): Likewise, pass cia to sim_core_write*.
1847
d3ee60d9
FCE		 18482000-10-19 Frank Ch. Eigler <fche@redhat.com>
1849
1850 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1851 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1852
071da002
AC		 1853Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1856 * Makefile.in: Don't delete *.igen when cleaning directory.
1857
a28c02cd
AC		 1858Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1859
1860 * m16.igen (break): Call SignalException not sim_engine_halt.
1861
80ee11fa
AC		 1862Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1863
1864 From Jason Eckhardt:
1865 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1866
673388c0
AC		 1867Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1868
1869 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1870
4c0deff4
NC		 18712000-05-24 Michael Hayes <mhayes@cygnus.com>
1872
1873 * mips.igen (do_dmultx): Fix typo.
1874
eb2d80b4
AC		 1875Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1876
1877 * configure: Regenerated to track ../common/aclocal.m4 changes.
1878
dd37a34b
AC		 1879Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1880
1881 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1882
4c0deff4
NC		 18832000-04-12 Frank Ch. Eigler <fche@redhat.com>
1884
1885 * sim-main.h (GPR_CLEAR): Define macro.
1886
e30db738
AC		 1887Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1888
1889 * interp.c (decode_coproc): Output long using %lx and not %s.
1890
cb7450ea
FCE		 18912000-03-21 Frank Ch. Eigler <fche@redhat.com>
1892
1893 * interp.c (sim_open): Sort & extend dummy memory regions for
1894 --board=jmr3904 for eCos.
1895
a3027dd7
FCE		 18962000-03-02 Frank Ch. Eigler <fche@redhat.com>
1897
1898 * configure: Regenerated.
1899
1900Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1901
1902 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1903 calls, conditional on the simulator being in verbose mode.
1904
dfcd3bfb
JM		 1905Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1906
1907 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1908 cache don't get ReservedInstruction traps.
1909
c2d11a7d
JM		 19101999-11-29 Mark Salter <msalter@cygnus.com>
1911
1912 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1913 to clear status bits in sdisr register. This is how the hardware works.
1914
1915 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1916 being used by cygmon.
1917
4ce44c66
JM		 19181999-11-11 Andrew Haley <aph@cygnus.com>
1919
1920 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1921 instructions.
1922
cff3e48b
JM		 1923Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1924
1925 * mips.igen (MULT): Correct previous mis-applied patch.
1926
d4f3574e
SS		 1927Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1928
1929 * mips.igen (delayslot32): Handle sequence like
1930 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1931 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1932 (MULT): Actually pass the third register...
1933
19341999-09-03 Mark Salter <msalter@cygnus.com>
1935
1936 * interp.c (sim_open): Added more memory aliases for additional
1937 hardware being touched by cygmon on jmr3904 board.
1938
1939Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1940
1941 * configure: Regenerated to track ../common/aclocal.m4 changes.
1942
a0b3c4fd
JM		 1943Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1944
1945 * interp.c (sim_store_register): Handle case where client - GDB -
1946 specifies that a 4 byte register is 8 bytes in size.
1947 (sim_fetch_register): Ditto.
72f4393d 1948
adf40b2e
JM		 19491999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1950
1951 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1952 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1953 (idt_monitor_base): Base address for IDT monitor traps.
1954 (pmon_monitor_base): Ditto for PMON.
1955 (lsipmon_monitor_base): Ditto for LSI PMON.
1956 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1957 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1958 (sim_firmware_command): New function.
1959 (mips_option_handler): Call it for OPTION_FIRMWARE.
1960 (sim_open): Allocate memory for idt_monitor region. If "--board"
1961 option was given, add no monitor by default. Add BREAK hooks only if
1962 monitors are also there.
72f4393d 1963
43e526b9
JM		 1964Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1965
1966 * interp.c (sim_monitor): Flush output before reading input.
1967
1968Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1969
1970 * tconfig.in (SIM_HANDLES_LMA): Always define.
1971
1972Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1973
1974 From Mark Salter <msalter@cygnus.com>:
1975 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1976 (sim_open): Add setup for BSP board.
1977
9846de1b
JM		 1978Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1979
1980 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1981 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1982 them as unimplemented.
1983
cd0fc7c3
SS		 19841999-05-08 Felix Lee <flee@cygnus.com>
1985
1986 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1987
7a292a7a
SS		 19881999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1989
1990 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1991
1992Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1993
1994 * configure.in: Any mips64vr5*-*-* target should have
1995 -DTARGET_ENABLE_FR=1.
1996 (default_endian): Any mips64vr*el-*-* target should default to
1997 LITTLE_ENDIAN.
1998 * configure: Re-generate.
1999
20001999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
2001
2002 * mips.igen (ldl): Extend from _16_, not 32.
2003
2004Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
2005
2006 * interp.c (sim_store_register): Force registers written to by GDB
2007 into an un-interpreted state.
2008
c906108c
SS		 20091999-02-05 Frank Ch. Eigler <fche@cygnus.com>
2010
2011 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
2012 CPU, start periodic background I/O polls.
72f4393d 2013 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 2014
20151998-12-30 Frank Ch. Eigler <fche@cygnus.com>
2016
2017 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 2018
c906108c
SS		 2019Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
2020
2021 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
2022 case statement.
2023
20241998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 2025
2026 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 2027 (load_word): Call SIM_CORE_SIGNAL hook on error.
2028 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
2029 starting. For exception dispatching, pass PC instead of NULL_CIA.
2030 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 2031 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 2032 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
2033 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 2034 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 2035 * mips.igen (*): Replace memory-related SignalException* calls
2036 with references to SIM_CORE_SIGNAL hook.
72f4393d 2037
c906108c
SS		 2038 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
2039 fix.
2040 * sim-main.c (*): Minor warning cleanups.
72f4393d 2041
c906108c
SS		 20421998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2043
2044 * m16.igen (DADDIU5): Correct type-o.
2045
2046Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2047
2048 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2049 variables.
2050
2051Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2052
2053 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2054 to include path.
2055 (interp.o): Add dependency on itable.h
2056 (oengine.c, gencode): Delete remaining references.
2057 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2058
c906108c 20591998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2060
c906108c
SS		 2061 * vr4run.c: New.
2062 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2063 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2064 tmp-run-hack) : New.
2065 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2066 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2067 Drop the "64" qualifier to get the HACK generator working.
2068 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2069 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2070 qualifier to get the hack generator working.
2071 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2072 (DSLL): Use do_dsll.
2073 (DSLLV): Use do_dsllv.
2074 (DSRA): Use do_dsra.
2075 (DSRL): Use do_dsrl.
2076 (DSRLV): Use do_dsrlv.
2077 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2078 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2079 get the HACK generator working.
2080 (MACC) Rename to get the HACK generator working.
2081 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2082
c906108c
SS		 20831998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2084
2085 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2086 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2087
c906108c
SS		 20881998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2089
2090 * mips/interp.c (DEBUG): Cleanups.
2091
20921998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2093
2094 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2095 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2096
c906108c
SS		 20971998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2098
2099 * interp.c (sim_close): Uninstall modules.
2100
2101Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2102
2103 * sim-main.h, interp.c (sim_monitor): Change to global
2104 function.
2105
2106Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2107
2108 * configure.in (vr4100): Only include vr4100 instructions in
2109 simulator.
2110 * configure: Re-generate.
2111 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2112
2113Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2114
2115 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2116 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2117 true alternative.
2118
2119 * configure.in (sim_default_gen, sim_use_gen): Replace with
2120 sim_gen.
2121 (--enable-sim-igen): Delete config option. Always using IGEN.
2122 * configure: Re-generate.
72f4393d 2123
c906108c
SS		 2124 * Makefile.in (gencode): Kill, kill, kill.
2125 * gencode.c: Ditto.
72f4393d 2126
c906108c
SS		 2127Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2128
2129 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2130 bit mips16 igen simulator.
2131 * configure: Re-generate.
2132
2133 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2134 as part of vr4100 ISA.
2135 * vr.igen: Mark all instructions as 64 bit only.
2136
2137Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2138
2139 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2140 Pacify GCC.
2141
2142Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2143
2144 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2145 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2146 * configure: Re-generate.
2147
2148 * m16.igen (BREAK): Define breakpoint instruction.
2149 (JALX32): Mark instruction as mips16 and not r3900.
2150 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2151
2152 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2153
2154Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2155
2156 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2157 insn as a debug breakpoint.
2158
2159 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2160 pending.slot_size.
2161 (PENDING_SCHED): Clean up trace statement.
2162 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2163 (PENDING_FILL): Delay write by only one cycle.
2164 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2165
2166 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2167 of pending writes.
2168 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2169 32 & 64.
2170 (pending_tick): Move incrementing of index to FOR statement.
2171 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2172
c906108c
SS		 2173 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2174 build simulator.
2175 * configure: Re-generate.
72f4393d 2176
c906108c
SS		 2177 * interp.c (sim_engine_run OLD): Delete explicit call to
2178 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2179
c906108c
SS		 2180Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2181
2182 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2183 interrupt level number to match changed SignalExceptionInterrupt
2184 macro.
2185
2186Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2187
2188 * interp.c: #include "itable.h" if WITH_IGEN.
2189 (get_insn_name): New function.
2190 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2191 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2192
2193Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2194
2195 * configure: Rebuilt to inhale new common/aclocal.m4.
2196
2197Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2198
2199 * dv-tx3904sio.c: Include sim-assert.h.
2200
2201Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2202
2203 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2204 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2205 Reorganize target-specific sim-hardware checks.
2206 * configure: rebuilt.
2207 * interp.c (sim_open): For tx39 target boards, set
2208 OPERATING_ENVIRONMENT, add tx3904sio devices.
2209 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2210 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2211
c906108c
SS		 2212 * dv-tx3904irc.c: Compiler warning clean-up.
2213 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2214 frequent hw-trace messages.
2215
2216Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2217
2218 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2219
2220Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2221
2222 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2223
2224 * vr.igen: New file.
2225 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2226 * mips.igen: Define vr4100 model. Include vr.igen.
2227Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2228
2229 * mips.igen (check_mf_hilo): Correct check.
2230
2231Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2232
2233 * sim-main.h (interrupt_event): Add prototype.
2234
2235 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2236 register_ptr, register_value.
2237 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2238
2239 * sim-main.h (tracefh): Make extern.
2240
2241Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2242
2243 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2244 Reduce unnecessarily high timer event frequency.
c906108c 2245 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2246
c906108c
SS		 2247Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2248
2249 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2250 to allay warnings.
2251 (interrupt_event): Made non-static.
72f4393d 2252
c906108c
SS		 2253 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2254 interchange of configuration values for external vs. internal
2255 clock dividers.
72f4393d 2256
c906108c
SS		 2257Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2258
72f4393d 2259 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2260 simulator-reserved break instructions.
2261 * gencode.c (build_instruction): Ditto.
2262 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2263 reserved instructions now use exception vector, rather
c906108c
SS		 2264 than halting sim.
2265 * sim-main.h: Moved magic constants to here.
2266
2267Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2268
2269 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2270 register upon non-zero interrupt event level, clear upon zero
2271 event value.
2272 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2273 by passing zero event value.
2274 (*_io_{read,write}_buffer): Endianness fixes.
2275 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2276 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2277
2278 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2279 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2280
c906108c
SS		 2281Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2282
72f4393d 2283 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2284 and BigEndianCPU.
2285
2286Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2287
2288 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2289 parts.
2290 * configure: Update.
2291
2292Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2293
2294 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2295 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2296 * configure.in: Include tx3904tmr in hw_device list.
2297 * configure: Rebuilt.
2298 * interp.c (sim_open): Instantiate three timer instances.
2299 Fix address typo of tx3904irc instance.
2300
2301Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2302
2303 * interp.c (signal_exception): SystemCall exception now uses
2304 the exception vector.
2305
2306Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2307
2308 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2309 to allay warnings.
2310
2311Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2312
2313 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2314
2315Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2316
2317 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2318
2319 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2320 sim-main.h. Declare a struct hw_descriptor instead of struct
2321 hw_device_descriptor.
2322
2323Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2324
2325 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2326 right bits and then re-align left hand bytes to correct byte
2327 lanes. Fix incorrect computation in do_store_left when loading
2328 bytes from second word.
2329
2330Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2331
2332 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2333 * interp.c (sim_open): Only create a device tree when HW is
2334 enabled.
2335
2336 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2337 * interp.c (signal_exception): Ditto.
2338
2339Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2340
2341 * gencode.c: Mark BEGEZALL as LIKELY.
2342
2343Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2344
2345 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2346 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2347
c906108c
SS		 2348Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2349
2350 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2351 modules. Recognize TX39 target with "mips*tx39" pattern.
2352 * configure: Rebuilt.
2353 * sim-main.h (*): Added many macros defining bits in
2354 TX39 control registers.
2355 (SignalInterrupt): Send actual PC instead of NULL.
2356 (SignalNMIReset): New exception type.
2357 * interp.c (board): New variable for future use to identify
2358 a particular board being simulated.
2359 (mips_option_handler,mips_options): Added "--board" option.
2360 (interrupt_event): Send actual PC.
2361 (sim_open): Make memory layout conditional on board setting.
2362 (signal_exception): Initial implementation of hardware interrupt
2363 handling. Accept another break instruction variant for simulator
2364 exit.
2365 (decode_coproc): Implement RFE instruction for TX39.
2366 (mips.igen): Decode RFE instruction as such.
2367 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2368 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2369 bbegin to implement memory map.
2370 * dv-tx3904cpu.c: New file.
2371 * dv-tx3904irc.c: New file.
2372
2373Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2374
2375 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2376
2377Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2378
2379 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2380 with calls to check_div_hilo.
2381
2382Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2383
2384 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2385 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2386 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2387 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2388 with calls to check_mult_hilo.
2389 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2390 with calls to check_div_hilo.
2391
2392Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2393
2394 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2395 Document a replacement.
2396
2397Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2398
2399 * interp.c (sim_monitor): Make mon_printf work.
2400
2401Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2402
2403 * sim-main.h (INSN_NAME): New arg `cpu'.
2404
2405Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2406
72f4393d 2407 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2408
2409Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2410
2411 * configure: Regenerated to track ../common/aclocal.m4 changes.
2412 * config.in: Ditto.
2413
2414Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2415
2416 * acconfig.h: New file.
2417 * configure.in: Reverted change of Apr 24; use sinclude again.
2418
2419Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2420
2421 * configure: Regenerated to track ../common/aclocal.m4 changes.
2422 * config.in: Ditto.
2423
2424Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2425
2426 * configure.in: Don't call sinclude.
2427
2428Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2429
2430 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2431
2432Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2433
2434 * mips.igen (ERET): Implement.
2435
2436 * interp.c (decode_coproc): Return sign-extended EPC.
2437
2438 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2439
2440 * interp.c (signal_exception): Do not ignore Trap.
2441 (signal_exception): On TRAP, restart at exception address.
2442 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2443 (signal_exception): Update.
2444 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2445 so that TRAP instructions are caught.
2446
2447Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2448
2449 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2450 contains HI/LO access history.
2451 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2452 (HIACCESS, LOACCESS): Delete, replace with
2453 (HIHISTORY, LOHISTORY): New macros.
2454 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2455
c906108c
SS		 2456 * gencode.c (build_instruction): Do not generate checks for
2457 correct HI/LO register usage.
2458
2459 * interp.c (old_engine_run): Delete checks for correct HI/LO
2460 register usage.
2461
2462 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2463 check_mf_cycles): New functions.
2464 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2465 do_divu, domultx, do_mult, do_multu): Use.
2466
2467 * tx.igen ("madd", "maddu"): Use.
72f4393d 2468
c906108c
SS		 2469Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2470
2471 * mips.igen (DSRAV): Use function do_dsrav.
2472 (SRAV): Use new function do_srav.
2473
2474 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2475 (B): Sign extend 11 bit immediate.
2476 (EXT-B*): Shift 16 bit immediate left by 1.
2477 (ADDIU*): Don't sign extend immediate value.
2478
2479Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2480
2481 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2482
2483 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2484 functions.
2485
2486 * mips.igen (delayslot32, nullify_next_insn): New functions.
2487 (m16.igen): Always include.
2488 (do_*): Add more tracing.
2489
2490 * m16.igen (delayslot16): Add NIA argument, could be called by a
2491 32 bit MIPS16 instruction.
72f4393d 2492
c906108c
SS		 2493 * interp.c (ifetch16): Move function from here.
2494 * sim-main.c (ifetch16): To here.
72f4393d 2495
c906108c
SS		 2496 * sim-main.c (ifetch16, ifetch32): Update to match current
2497 implementations of LH, LW.
2498 (signal_exception): Don't print out incorrect hex value of illegal
2499 instruction.
2500
2501Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2502
2503 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2504 instruction.
2505
2506 * m16.igen: Implement MIPS16 instructions.
72f4393d 2507
c906108c
SS		 2508 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2509 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2510 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2511 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2512 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2513 bodies of corresponding code from 32 bit insn to these. Also used
2514 by MIPS16 versions of functions.
72f4393d 2515
c906108c
SS		 2516 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2517 (IMEM16): Drop NR argument from macro.
2518
2519Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2520
2521 * Makefile.in (SIM_OBJS): Add sim-main.o.
2522
2523 * sim-main.h (address_translation, load_memory, store_memory,
2524 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2525 as INLINE_SIM_MAIN.
2526 (pr_addr, pr_uword64): Declare.
2527 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2528
c906108c
SS		 2529 * interp.c (address_translation, load_memory, store_memory,
2530 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2531 from here.
2532 * sim-main.c: To here. Fix compilation problems.
72f4393d 2533
c906108c
SS		 2534 * configure.in: Enable inlining.
2535 * configure: Re-config.
2536
2537Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2538
2539 * configure: Regenerated to track ../common/aclocal.m4 changes.
2540
2541Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2542
2543 * mips.igen: Include tx.igen.
2544 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2545 * tx.igen: New file, contains MADD and MADDU.
2546
2547 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2548 the hardwired constant `7'.
2549 (store_memory): Ditto.
2550 (LOADDRMASK): Move definition to sim-main.h.
2551
2552 mips.igen (MTC0): Enable for r3900.
2553 (ADDU): Add trace.
2554
2555 mips.igen (do_load_byte): Delete.
2556 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2557 do_store_right): New functions.
2558 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2559
2560 configure.in: Let the tx39 use igen again.
2561 configure: Update.
72f4393d 2562
c906108c
SS		 2563Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2564
2565 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2566 not an address sized quantity. Return zero for cache sizes.
2567
2568Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2569
2570 * mips.igen (r3900): r3900 does not support 64 bit integer
2571 operations.
2572
2573Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2574
2575 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2576 than igen one.
2577 * configure : Rebuild.
72f4393d 2578
c906108c
SS		 2579Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2580
2581 * configure: Regenerated to track ../common/aclocal.m4 changes.
2582
2583Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2584
2585 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2586
2587Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2588
2589 * configure: Regenerated to track ../common/aclocal.m4 changes.
2590 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2591
2592Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2593
2594 * configure: Regenerated to track ../common/aclocal.m4 changes.
2595
2596Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2597
2598 * interp.c (Max, Min): Comment out functions. Not yet used.
2599
2600Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2601
2602 * configure: Regenerated to track ../common/aclocal.m4 changes.
2603
2604Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2605
2606 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2607 configurable settings for stand-alone simulator.
72f4393d 2608
c906108c 2609 * configure.in: Added X11 search, just in case.
72f4393d 2610
c906108c
SS		 2611 * configure: Regenerated.
2612
2613Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2614
2615 * interp.c (sim_write, sim_read, load_memory, store_memory):
2616 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2617
2618Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2619
2620 * sim-main.h (GETFCC): Return an unsigned value.
2621
2622Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2623
2624 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2625 (DADD): Result destination is RD not RT.
2626
2627Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2628
2629 * sim-main.h (HIACCESS, LOACCESS): Always define.
2630
2631 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2632
2633 * interp.c (sim_info): Delete.
2634
2635Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2636
2637 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2638 (mips_option_handler): New argument `cpu'.
2639 (sim_open): Update call to sim_add_option_table.
2640
2641Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2642
2643 * mips.igen (CxC1): Add tracing.
2644
2645Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2646
2647 * sim-main.h (Max, Min): Declare.
2648
2649 * interp.c (Max, Min): New functions.
2650
2651 * mips.igen (BC1): Add tracing.
72f4393d 2652
c906108c 2653Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2654
c906108c 2655 * interp.c Added memory map for stack in vr4100
72f4393d 2656
c906108c
SS		 2657Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2658
2659 * interp.c (load_memory): Add missing "break"'s.
2660
2661Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2662
2663 * interp.c (sim_store_register, sim_fetch_register): Pass in
2664 length parameter. Return -1.
2665
2666Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2667
2668 * interp.c: Added hardware init hook, fixed warnings.
2669
2670Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2671
2672 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2673
2674Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2675
2676 * interp.c (ifetch16): New function.
2677
2678 * sim-main.h (IMEM32): Rename IMEM.
2679 (IMEM16_IMMED): Define.
2680 (IMEM16): Define.
2681 (DELAY_SLOT): Update.
72f4393d 2682
c906108c 2683 * m16run.c (sim_engine_run): New file.
72f4393d 2684
c906108c
SS		 2685 * m16.igen: All instructions except LB.
2686 (LB): Call do_load_byte.
2687 * mips.igen (do_load_byte): New function.
2688 (LB): Call do_load_byte.
2689
2690 * mips.igen: Move spec for insn bit size and high bit from here.
2691 * Makefile.in (tmp-igen, tmp-m16): To here.
2692
2693 * m16.dc: New file, decode mips16 instructions.
2694
2695 * Makefile.in (SIM_NO_ALL): Define.
2696 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2697
2698Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2699
2700 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2701 point unit to 32 bit registers.
2702 * configure: Re-generate.
2703
2704Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2705
2706 * configure.in (sim_use_gen): Make IGEN the default simulator
2707 generator for generic 32 and 64 bit mips targets.
2708 * configure: Re-generate.
2709
2710Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2711
2712 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2713 bitsize.
2714
2715 * interp.c (sim_fetch_register, sim_store_register): Read/write
2716 FGR from correct location.
2717 (sim_open): Set size of FGR's according to
2718 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2719
c906108c
SS		 2720 * sim-main.h (FGR): Store floating point registers in a separate
2721 array.
2722
2723Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2724
2725 * configure: Regenerated to track ../common/aclocal.m4 changes.
2726
2727Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2728
2729 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2730
2731 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2732
2733 * interp.c (pending_tick): New function. Deliver pending writes.
2734
2735 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2736 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2737 it can handle mixed sized quantites and single bits.
72f4393d 2738
c906108c
SS		 2739Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2740
2741 * interp.c (oengine.h): Do not include when building with IGEN.
2742 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2743 (sim_info): Ditto for PROCESSOR_64BIT.
2744 (sim_monitor): Replace ut_reg with unsigned_word.
2745 (*): Ditto for t_reg.
2746 (LOADDRMASK): Define.
2747 (sim_open): Remove defunct check that host FP is IEEE compliant,
2748 using software to emulate floating point.
2749 (value_fpr, ...): Always compile, was conditional on HASFPU.
2750
2751Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2752
2753 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2754 size.
2755
2756 * interp.c (SD, CPU): Define.
2757 (mips_option_handler): Set flags in each CPU.
2758 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2759 (sim_close): Do not clear STATE, deleted anyway.
2760 (sim_write, sim_read): Assume CPU zero's vm should be used for
2761 data transfers.
2762 (sim_create_inferior): Set the PC for all processors.
2763 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2764 argument.
2765 (mips16_entry): Pass correct nr of args to store_word, load_word.
2766 (ColdReset): Cold reset all cpu's.
2767 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2768 (sim_monitor, load_memory, store_memory, signal_exception): Use
2769 `CPU' instead of STATE_CPU.
2770
2771
2772 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2773 SD or CPU_.
72f4393d 2774
c906108c
SS		 2775 * sim-main.h (signal_exception): Add sim_cpu arg.
2776 (SignalException*): Pass both SD and CPU to signal_exception.
2777 * interp.c (signal_exception): Update.
72f4393d 2778
c906108c
SS		 2779 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2780 Ditto
2781 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2782 address_translation): Ditto
2783 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2784
c906108c
SS		 2785Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2786
2787 * configure: Regenerated to track ../common/aclocal.m4 changes.
2788
2789Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2790
2791 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2792
72f4393d 2793 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2794
2795 * sim-main.h (CPU_CIA): Delete.
2796 (SET_CIA, GET_CIA): Define
2797
2798Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2799
2800 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2801 regiser.
2802
2803 * configure.in (default_endian): Configure a big-endian simulator
2804 by default.
2805 * configure: Re-generate.
72f4393d 2806
c906108c
SS		 2807Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2808
2809 * configure: Regenerated to track ../common/aclocal.m4 changes.
2810
2811Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2812
2813 * interp.c (sim_monitor): Handle Densan monitor outbyte
2814 and inbyte functions.
2815
28161997-12-29 Felix Lee <flee@cygnus.com>
2817
2818 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2819
2820Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2821
2822 * Makefile.in (tmp-igen): Arrange for $zero to always be
2823 reset to zero after every instruction.
2824
2825Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2826
2827 * configure: Regenerated to track ../common/aclocal.m4 changes.
2828 * config.in: Ditto.
2829
2830Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2831
2832 * mips.igen (MSUB): Fix to work like MADD.
2833 * gencode.c (MSUB): Similarly.
2834
2835Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2836
2837 * configure: Regenerated to track ../common/aclocal.m4 changes.
2838
2839Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2840
2841 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2842
2843Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2844
2845 * sim-main.h (sim-fpu.h): Include.
2846
2847 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2848 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2849 using host independant sim_fpu module.
2850
2851Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2852
2853 * interp.c (signal_exception): Report internal errors with SIGABRT
2854 not SIGQUIT.
2855
2856 * sim-main.h (C0_CONFIG): New register.
2857 (signal.h): No longer include.
2858
2859 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2860
2861Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2862
2863 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2864
2865Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2866
2867 * mips.igen: Tag vr5000 instructions.
2868 (ANDI): Was missing mipsIV model, fix assembler syntax.
2869 (do_c_cond_fmt): New function.
2870 (C.cond.fmt): Handle mips I-III which do not support CC field
2871 separatly.
2872 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2873 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2874 in IV3.2 spec.
2875 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2876 vr5000 which saves LO in a GPR separatly.
72f4393d 2877
c906108c
SS		 2878 * configure.in (enable-sim-igen): For vr5000, select vr5000
2879 specific instructions.
2880 * configure: Re-generate.
72f4393d 2881
c906108c
SS		 2882Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2883
2884 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2885
2886 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2887 fmt_uninterpreted_64 bit cases to switch. Convert to
2888 fmt_formatted,
2889
2890 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2891
2892 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2893 as specified in IV3.2 spec.
2894 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2895
2896Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2897
2898 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2899 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2900 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2901 PENDING_FILL versions of instructions. Simplify.
2902 (X): New function.
2903 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2904 instructions.
2905 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2906 a signed value.
2907 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2908
c906108c
SS		 2909 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2910 global.
2911 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2912
2913Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2914
2915 * gencode.c (build_mips16_operands): Replace IPC with cia.
2916
2917 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2918 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2919 IPC to `cia'.
2920 (UndefinedResult): Replace function with macro/function
2921 combination.
2922 (sim_engine_run): Don't save PC in IPC.
2923
2924 * sim-main.h (IPC): Delete.
2925
2926
2927 * interp.c (signal_exception, store_word, load_word,
2928 address_translation, load_memory, store_memory, cache_op,
2929 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2930 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2931 current instruction address - cia - argument.
2932 (sim_read, sim_write): Call address_translation directly.
2933 (sim_engine_run): Rename variable vaddr to cia.
2934 (signal_exception): Pass cia to sim_monitor
72f4393d 2935
c906108c
SS		 2936 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2937 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2938 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2939
2940 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2941 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2942 SIM_ASSERT.
72f4393d 2943
c906108c
SS		 2944 * interp.c (signal_exception): Pass restart address to
2945 sim_engine_restart.
2946
2947 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2948 idecode.o): Add dependency.
2949
2950 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2951 Delete definitions
2952 (DELAY_SLOT): Update NIA not PC with branch address.
2953 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2954
2955 * mips.igen: Use CIA not PC in branch calculations.
2956 (illegal): Call SignalException.
2957 (BEQ, ADDIU): Fix assembler.
2958
2959Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2960
2961 * m16.igen (JALX): Was missing.
2962
2963 * configure.in (enable-sim-igen): New configuration option.
2964 * configure: Re-generate.
72f4393d 2965
c906108c
SS		 2966 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2967
2968 * interp.c (load_memory, store_memory): Delete parameter RAW.
2969 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2970 bypassing {load,store}_memory.
2971
2972 * sim-main.h (ByteSwapMem): Delete definition.
2973
2974 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2975
2976 * interp.c (sim_do_command, sim_commands): Delete mips specific
2977 commands. Handled by module sim-options.
72f4393d 2978
c906108c
SS		 2979 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2980 (WITH_MODULO_MEMORY): Define.
2981
2982 * interp.c (sim_info): Delete code printing memory size.
2983
2984 * interp.c (mips_size): Nee sim_size, delete function.
2985 (power2): Delete.
2986 (monitor, monitor_base, monitor_size): Delete global variables.
2987 (sim_open, sim_close): Delete code creating monitor and other
2988 memory regions. Use sim-memopts module, via sim_do_commandf, to
2989 manage memory regions.
2990 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2991
c906108c
SS		 2992 * interp.c (address_translation): Delete all memory map code
2993 except line forcing 32 bit addresses.
2994
2995Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2996
2997 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2998 trace options.
2999
3000 * interp.c (logfh, logfile): Delete globals.
3001 (sim_open, sim_close): Delete code opening & closing log file.
3002 (mips_option_handler): Delete -l and -n options.
3003 (OPTION mips_options): Ditto.
3004
3005 * interp.c (OPTION mips_options): Rename option trace to dinero.
3006 (mips_option_handler): Update.
3007
3008Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3009
3010 * interp.c (fetch_str): New function.
3011 (sim_monitor): Rewrite using sim_read & sim_write.
3012 (sim_open): Check magic number.
3013 (sim_open): Write monitor vectors into memory using sim_write.
3014 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
3015 (sim_read, sim_write): Simplify - transfer data one byte at a
3016 time.
3017 (load_memory, store_memory): Clarify meaning of parameter RAW.
3018
3019 * sim-main.h (isHOST): Defete definition.
3020 (isTARGET): Mark as depreciated.
3021 (address_translation): Delete parameter HOST.
3022
3023 * interp.c (address_translation): Delete parameter HOST.
3024
3025Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3026
72f4393d 3027 * mips.igen:
c906108c
SS		 3028
3029 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
3030 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
3031
3032Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
3033
3034 * mips.igen: Add model filter field to records.
3035
3036Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3037
3038 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 3039
c906108c
SS		 3040 interp.c (sim_engine_run): Do not compile function sim_engine_run
3041 when WITH_IGEN == 1.
3042
3043 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3044 target architecture.
3045
3046 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3047 igen. Replace with configuration variables sim_igen_flags /
3048 sim_m16_flags.
3049
3050 * m16.igen: New file. Copy mips16 insns here.
3051 * mips.igen: From here.
3052
3053Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3054
3055 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3056 to top.
3057 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3058
3059Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3060
3061 * gencode.c (build_instruction): Follow sim_write's lead in using
3062 BigEndianMem instead of !ByteSwapMem.
3063
3064Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3065
3066 * configure.in (sim_gen): Dependent on target, select type of
3067 generator. Always select old style generator.
3068
3069 configure: Re-generate.
3070
3071 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3072 targets.
3073 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3074 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3075 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3076 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3077 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3078
c906108c
SS		 3079Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3080
3081 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3082
3083 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3084 CURRENT_FLOATING_POINT instead.
3085
3086 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3087 (address_translation): Raise exception InstructionFetch when
3088 translation fails and isINSTRUCTION.
72f4393d 3089
c906108c
SS		 3090 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3091 sim_engine_run): Change type of of vaddr and paddr to
3092 address_word.
3093 (address_translation, prefetch, load_memory, store_memory,
3094 cache_op): Change type of vAddr and pAddr to address_word.
3095
3096 * gencode.c (build_instruction): Change type of vaddr and paddr to
3097 address_word.
3098
3099Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3100
3101 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3102 macro to obtain result of ALU op.
3103
3104Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3105
3106 * interp.c (sim_info): Call profile_print.
3107
3108Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3109
3110 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3111
3112 * sim-main.h (WITH_PROFILE): Do not define, defined in
3113 common/sim-config.h. Use sim-profile module.
3114 (simPROFILE): Delete defintion.
3115
3116 * interp.c (PROFILE): Delete definition.
3117 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3118 (sim_close): Delete code writing profile histogram.
3119 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3120 Delete.
3121 (sim_engine_run): Delete code profiling the PC.
3122
3123Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3124
3125 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3126
3127 * interp.c (sim_monitor): Make register pointers of type
3128 unsigned_word*.
3129
3130 * sim-main.h: Make registers of type unsigned_word not
3131 signed_word.
3132
3133Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3134
3135 * interp.c (sync_operation): Rename from SyncOperation, make
3136 global, add SD argument.
3137 (prefetch): Rename from Prefetch, make global, add SD argument.
3138 (decode_coproc): Make global.
3139
3140 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3141
3142 * gencode.c (build_instruction): Generate DecodeCoproc not
3143 decode_coproc calls.
3144
3145 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3146 (SizeFGR): Move to sim-main.h
3147 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3148 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3149 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3150 sim-main.h.
3151 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3152 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3153 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3154 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3155 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3156 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3157
c906108c
SS		 3158 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3159 exception.
3160 (sim-alu.h): Include.
3161 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3162 (sim_cia): Typedef to instruction_address.
72f4393d 3163
c906108c
SS		 3164Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3165
3166 * Makefile.in (interp.o): Rename generated file engine.c to
3167 oengine.c.
72f4393d 3168
c906108c 3169 * interp.c: Update.
72f4393d 3170
c906108c
SS		 3171Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3172
3173 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3174
c906108c
SS		 3175Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3176
3177 * gencode.c (build_instruction): For "FPSQRT", output correct
3178 number of arguments to Recip.
72f4393d 3179
c906108c
SS		 3180Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3181
3182 * Makefile.in (interp.o): Depends on sim-main.h
3183
3184 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3185
3186 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3187 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3188 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3189 STATE, DSSTATE): Define
3190 (GPR, FGRIDX, ..): Define.
3191
3192 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3193 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3194 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3195
c906108c 3196 * interp.c: Update names to match defines from sim-main.h
72f4393d 3197
c906108c
SS		 3198Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3199
3200 * interp.c (sim_monitor): Add SD argument.
3201 (sim_warning): Delete. Replace calls with calls to
3202 sim_io_eprintf.
3203 (sim_error): Delete. Replace calls with sim_io_error.
3204 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3205 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3206 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3207 argument.
3208 (mips_size): Rename from sim_size. Add SD argument.
3209
3210 * interp.c (simulator): Delete global variable.
3211 (callback): Delete global variable.
3212 (mips_option_handler, sim_open, sim_write, sim_read,
3213 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3214 sim_size,sim_monitor): Use sim_io_* not callback->*.
3215 (sim_open): ZALLOC simulator struct.
3216 (PROFILE): Do not define.
3217
3218Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3219
3220 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3221 support.h with corresponding code.
3222
3223 * sim-main.h (word64, uword64), support.h: Move definition to
3224 sim-main.h.
3225 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3226
3227 * support.h: Delete
3228 * Makefile.in: Update dependencies
3229 * interp.c: Do not include.
72f4393d 3230
c906108c
SS		 3231Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3232
3233 * interp.c (address_translation, load_memory, store_memory,
3234 cache_op): Rename to from AddressTranslation et.al., make global,
3235 add SD argument
72f4393d 3236
c906108c
SS		 3237 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3238 CacheOp): Define.
72f4393d 3239
c906108c
SS		 3240 * interp.c (SignalException): Rename to signal_exception, make
3241 global.
3242
3243 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3244
c906108c
SS		 3245 * sim-main.h (SignalException, SignalExceptionInterrupt,
3246 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3247 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3248 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3249 Define.
72f4393d 3250
c906108c 3251 * interp.c, support.h: Use.
72f4393d 3252
c906108c
SS		 3253Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3254
3255 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3256 to value_fpr / store_fpr. Add SD argument.
3257 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3258 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3259
3260 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3261
c906108c
SS		 3262Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3263
3264 * interp.c (sim_engine_run): Check consistency between configure
3265 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3266 and HASFPU.
3267
3268 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3269 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3270 (mips_endian): Configure WITH_TARGET_ENDIAN.
3271 * configure: Update.
3272
3273Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3274
3275 * configure: Regenerated to track ../common/aclocal.m4 changes.
3276
3277Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3278
3279 * configure: Regenerated.
3280
3281Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3282
3283 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3284
3285Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3286
3287 * gencode.c (print_igen_insn_models): Assume certain architectures
3288 include all mips* instructions.
3289 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3290 instruction.
3291
3292 * Makefile.in (tmp.igen): Add target. Generate igen input from
3293 gencode file.
3294
3295 * gencode.c (FEATURE_IGEN): Define.
3296 (main): Add --igen option. Generate output in igen format.
3297 (process_instructions): Format output according to igen option.
3298 (print_igen_insn_format): New function.
3299 (print_igen_insn_models): New function.
3300 (process_instructions): Only issue warnings and ignore
3301 instructions when no FEATURE_IGEN.
3302
3303Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3304
3305 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3306 MIPS targets.
3307
3308Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3309
3310 * configure: Regenerated to track ../common/aclocal.m4 changes.
3311
3312Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3313
3314 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3315 SIM_RESERVED_BITS): Delete, moved to common.
3316 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3317
c906108c
SS		 3318Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3319
3320 * configure.in: Configure non-strict memory alignment.
3321 * configure: Regenerated to track ../common/aclocal.m4 changes.
3322
3323Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3324
3325 * configure: Regenerated to track ../common/aclocal.m4 changes.
3326
3327Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3328
3329 * gencode.c (SDBBP,DERET): Added (3900) insns.
3330 (RFE): Turn on for 3900.
3331 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3332 (dsstate): Made global.
3333 (SUBTARGET_R3900): Added.
3334 (CANCELDELAYSLOT): New.
3335 (SignalException): Ignore SystemCall rather than ignore and
3336 terminate. Add DebugBreakPoint handling.
3337 (decode_coproc): New insns RFE, DERET; and new registers Debug
3338 and DEPC protected by SUBTARGET_R3900.
3339 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3340 bits explicitly.
3341 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3342 * configure: Update.
c906108c
SS		 3343
3344Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3345
3346 * gencode.c: Add r3900 (tx39).
72f4393d 3347
c906108c
SS		 3348
3349Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3350
3351 * gencode.c (build_instruction): Don't need to subtract 4 for
3352 JALR, just 2.
3353
3354Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3355
3356 * interp.c: Correct some HASFPU problems.
3357
3358Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3359
3360 * configure: Regenerated to track ../common/aclocal.m4 changes.
3361
3362Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3363
3364 * interp.c (mips_options): Fix samples option short form, should
3365 be `x'.
3366
3367Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3368
3369 * interp.c (sim_info): Enable info code. Was just returning.
3370
3371Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3372
3373 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3374 MFC0.
3375
3376Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3377
3378 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3379 constants.
3380 (build_instruction): Ditto for LL.
3381
3382Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3383
3384 * configure: Regenerated to track ../common/aclocal.m4 changes.
3385
3386Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3387
3388 * configure: Regenerated to track ../common/aclocal.m4 changes.
3389 * config.in: Ditto.
3390
3391Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3392
3393 * interp.c (sim_open): Add call to sim_analyze_program, update
3394 call to sim_config.
3395
3396Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3397
3398 * interp.c (sim_kill): Delete.
3399 (sim_create_inferior): Add ABFD argument. Set PC from same.
3400 (sim_load): Move code initializing trap handlers from here.
3401 (sim_open): To here.
3402 (sim_load): Delete, use sim-hload.c.
3403
3404 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3405
3406Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3407
3408 * configure: Regenerated to track ../common/aclocal.m4 changes.
3409 * config.in: Ditto.
3410
3411Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3412
3413 * interp.c (sim_open): Add ABFD argument.
3414 (sim_load): Move call to sim_config from here.
3415 (sim_open): To here. Check return status.
3416
3417Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3418
c906108c
SS		 3419 * gencode.c (build_instruction): Two arg MADD should
3420 not assign result to $0.
72f4393d 3421
c906108c
SS		 3422Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3423
3424 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3425 * sim/mips/configure.in: Regenerate.
3426
3427Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3428
3429 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3430 signed8, unsigned8 et.al. types.
3431
3432 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3433 hosts when selecting subreg.
3434
3435Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3436
3437 * interp.c (sim_engine_run): Reset the ZERO register to zero
3438 regardless of FEATURE_WARN_ZERO.
3439 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3440
3441Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3442
3443 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3444 (SignalException): For BreakPoints ignore any mode bits and just
3445 save the PC.
3446 (SignalException): Always set the CAUSE register.
3447
3448Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3449
3450 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3451 exception has been taken.
3452
3453 * interp.c: Implement the ERET and mt/f sr instructions.
3454
3455Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3456
3457 * interp.c (SignalException): Don't bother restarting an
3458 interrupt.
3459
3460Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3461
3462 * interp.c (SignalException): Really take an interrupt.
3463 (interrupt_event): Only deliver interrupts when enabled.
3464
3465Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3466
3467 * interp.c (sim_info): Only print info when verbose.
3468 (sim_info) Use sim_io_printf for output.
72f4393d 3469
c906108c
SS		 3470Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3471
3472 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3473 mips architectures.
3474
3475Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3476
3477 * interp.c (sim_do_command): Check for common commands if a
3478 simulator specific command fails.
3479
3480Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3481
3482 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3483 and simBE when DEBUG is defined.
3484
3485Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3486
3487 * interp.c (interrupt_event): New function. Pass exception event
3488 onto exception handler.
3489
3490 * configure.in: Check for stdlib.h.
3491 * configure: Regenerate.
3492
3493 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3494 variable declaration.
3495 (build_instruction): Initialize memval1.
3496 (build_instruction): Add UNUSED attribute to byte, bigend,
3497 reverse.
3498 (build_operands): Ditto.
3499
3500 * interp.c: Fix GCC warnings.
3501 (sim_get_quit_code): Delete.
3502
3503 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3504 * Makefile.in: Ditto.
3505 * configure: Re-generate.
72f4393d 3506
c906108c
SS		 3507 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3508
3509Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3510
3511 * interp.c (mips_option_handler): New function parse argumes using
3512 sim-options.
3513 (myname): Replace with STATE_MY_NAME.
3514 (sim_open): Delete check for host endianness - performed by
3515 sim_config.
3516 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3517 (sim_open): Move much of the initialization from here.
3518 (sim_load): To here. After the image has been loaded and
3519 endianness set.
3520 (sim_open): Move ColdReset from here.
3521 (sim_create_inferior): To here.
3522 (sim_open): Make FP check less dependant on host endianness.
3523
3524 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3525 run.
3526 * interp.c (sim_set_callbacks): Delete.
3527
3528 * interp.c (membank, membank_base, membank_size): Replace with
3529 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3530 (sim_open): Remove call to callback->init. gdb/run do this.
3531
3532 * interp.c: Update
3533
3534 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3535
3536 * interp.c (big_endian_p): Delete, replaced by
3537 current_target_byte_order.
3538
3539Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3540
3541 * interp.c (host_read_long, host_read_word, host_swap_word,
3542 host_swap_long): Delete. Using common sim-endian.
3543 (sim_fetch_register, sim_store_register): Use H2T.
3544 (pipeline_ticks): Delete. Handled by sim-events.
3545 (sim_info): Update.
3546 (sim_engine_run): Update.
3547
3548Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3549
3550 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3551 reason from here.
3552 (SignalException): To here. Signal using sim_engine_halt.
3553 (sim_stop_reason): Delete, moved to common.
72f4393d 3554
c906108c
SS		 3555Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3556
3557 * interp.c (sim_open): Add callback argument.
3558 (sim_set_callbacks): Delete SIM_DESC argument.
3559 (sim_size): Ditto.
3560
3561Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3562
3563 * Makefile.in (SIM_OBJS): Add common modules.
3564
3565 * interp.c (sim_set_callbacks): Also set SD callback.
3566 (set_endianness, xfer_*, swap_*): Delete.
3567 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3568 Change to functions using sim-endian macros.
3569 (control_c, sim_stop): Delete, use common version.
3570 (simulate): Convert into.
3571 (sim_engine_run): This function.
3572 (sim_resume): Delete.
72f4393d 3573
c906108c
SS		 3574 * interp.c (simulation): New variable - the simulator object.
3575 (sim_kind): Delete global - merged into simulation.
3576 (sim_load): Cleanup. Move PC assignment from here.
3577 (sim_create_inferior): To here.
3578
3579 * sim-main.h: New file.
3580 * interp.c (sim-main.h): Include.
72f4393d 3581
c906108c
SS		 3582Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3583
3584 * configure: Regenerated to track ../common/aclocal.m4 changes.
3585
3586Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3587
3588 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3589
3590Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3591
72f4393d
L		 3592 * gencode.c (build_instruction): DIV instructions: check
3593 for division by zero and integer overflow before using
c906108c
SS		 3594 host's division operation.
3595
3596Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3597
3598 * Makefile.in (SIM_OBJS): Add sim-load.o.
3599 * interp.c: #include bfd.h.
3600 (target_byte_order): Delete.
3601 (sim_kind, myname, big_endian_p): New static locals.
3602 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3603 after argument parsing. Recognize -E arg, set endianness accordingly.
3604 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3605 load file into simulator. Set PC from bfd.
3606 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3607 (set_endianness): Use big_endian_p instead of target_byte_order.
3608
3609Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3610
3611 * interp.c (sim_size): Delete prototype - conflicts with
3612 definition in remote-sim.h. Correct definition.
3613
3614Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3615
3616 * configure: Regenerated to track ../common/aclocal.m4 changes.
3617 * config.in: Ditto.
3618
3619Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3620
3621 * interp.c (sim_open): New arg `kind'.
3622
3623 * configure: Regenerated to track ../common/aclocal.m4 changes.
3624
3625Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3626
3627 * configure: Regenerated to track ../common/aclocal.m4 changes.
3628
3629Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3630
3631 * interp.c (sim_open): Set optind to 0 before calling getopt.
3632
3633Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3634
3635 * configure: Regenerated to track ../common/aclocal.m4 changes.
3636
3637Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3638
3639 * interp.c : Replace uses of pr_addr with pr_uword64
3640 where the bit length is always 64 independent of SIM_ADDR.
3641 (pr_uword64) : added.
3642
3643Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3644
3645 * configure: Re-generate.
3646
3647Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3648
3649 * configure: Regenerate to track ../common/aclocal.m4 changes.
3650
3651Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3652
3653 * interp.c (sim_open): New SIM_DESC result. Argument is now
3654 in argv form.
3655 (other sim_*): New SIM_DESC argument.
3656
3657Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3658
3659 * interp.c: Fix printing of addresses for non-64-bit targets.
3660 (pr_addr): Add function to print address based on size.
3661
3662Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3663
3664 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3665
3666Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3667
3668 * gencode.c (build_mips16_operands): Correct computation of base
3669 address for extended PC relative instruction.
3670
3671Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3672
3673 * interp.c (mips16_entry): Add support for floating point cases.
3674 (SignalException): Pass floating point cases to mips16_entry.
3675 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3676 registers.
3677 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3678 or fmt_word.
3679 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3680 and then set the state to fmt_uninterpreted.
3681 (COP_SW): Temporarily set the state to fmt_word while calling
3682 ValueFPR.
3683
3684Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3685
3686 * gencode.c (build_instruction): The high order may be set in the
3687 comparison flags at any ISA level, not just ISA 4.
3688
3689Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3690
3691 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3692 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3693 * configure.in: sinclude ../common/aclocal.m4.
3694 * configure: Regenerated.
3695
3696Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3697
3698 * configure: Rebuild after change to aclocal.m4.
3699
3700Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3701
3702 * configure configure.in Makefile.in: Update to new configure
3703 scheme which is more compatible with WinGDB builds.
3704 * configure.in: Improve comment on how to run autoconf.
3705 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3706 * Makefile.in: Use autoconf substitution to install common
3707 makefile fragment.
3708
3709Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3710
3711 * gencode.c (build_instruction): Use BigEndianCPU instead of
3712 ByteSwapMem.
3713
3714Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3715
3716 * interp.c (sim_monitor): Make output to stdout visible in
3717 wingdb's I/O log window.
3718
3719Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3720
3721 * support.h: Undo previous change to SIGTRAP
3722 and SIGQUIT values.
3723
3724Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3725
3726 * interp.c (store_word, load_word): New static functions.
3727 (mips16_entry): New static function.
3728 (SignalException): Look for mips16 entry and exit instructions.
3729 (simulate): Use the correct index when setting fpr_state after
3730 doing a pending move.
3731
3732Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3733
3734 * interp.c: Fix byte-swapping code throughout to work on
3735 both little- and big-endian hosts.
3736
3737Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3738
3739 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3740 with gdb/config/i386/xm-windows.h.
3741
3742Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3743
3744 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3745 that messes up arithmetic shifts.
3746
3747Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3748
3749 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3750 SIGTRAP and SIGQUIT for _WIN32.
3751
3752Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3753
3754 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3755 force a 64 bit multiplication.
3756 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3757 destination register is 0, since that is the default mips16 nop
3758 instruction.
3759
3760Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3761
3762 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3763 (build_endian_shift): Don't check proc64.
3764 (build_instruction): Always set memval to uword64. Cast op2 to
3765 uword64 when shifting it left in memory instructions. Always use
3766 the same code for stores--don't special case proc64.
3767
3768 * gencode.c (build_mips16_operands): Fix base PC value for PC
3769 relative operands.
3770 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3771 jal instruction.
3772 * interp.c (simJALDELAYSLOT): Define.
3773 (JALDELAYSLOT): Define.
3774 (INDELAYSLOT, INJALDELAYSLOT): Define.
3775 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3776
3777Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3778
3779 * interp.c (sim_open): add flush_cache as a PMON routine
3780 (sim_monitor): handle flush_cache by ignoring it
3781
3782Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3783
3784 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3785 BigEndianMem.
3786 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3787 (BigEndianMem): Rename to ByteSwapMem and change sense.
3788 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3789 BigEndianMem references to !ByteSwapMem.
3790 (set_endianness): New function, with prototype.
3791 (sim_open): Call set_endianness.
3792 (sim_info): Use simBE instead of BigEndianMem.
3793 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3794 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3795 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3796 ifdefs, keeping the prototype declaration.
3797 (swap_word): Rewrite correctly.
3798 (ColdReset): Delete references to CONFIG. Delete endianness related
3799 code; moved to set_endianness.
72f4393d 3800
c906108c
SS		 3801Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3802
3803 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3804 * interp.c (CHECKHILO): Define away.
3805 (simSIGINT): New macro.
3806 (membank_size): Increase from 1MB to 2MB.
3807 (control_c): New function.
3808 (sim_resume): Rename parameter signal to signal_number. Add local
3809 variable prev. Call signal before and after simulate.
3810 (sim_stop_reason): Add simSIGINT support.
3811 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3812 functions always.
3813 (sim_warning): Delete call to SignalException. Do call printf_filtered
3814 if logfh is NULL.
3815 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3816 a call to sim_warning.
3817
3818Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3819
3820 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3821 16 bit instructions.
3822
3823Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3824
3825 Add support for mips16 (16 bit MIPS implementation):
3826 * gencode.c (inst_type): Add mips16 instruction encoding types.
3827 (GETDATASIZEINSN): Define.
3828 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3829 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3830 mtlo.
3831 (MIPS16_DECODE): New table, for mips16 instructions.
3832 (bitmap_val): New static function.
3833 (struct mips16_op): Define.
3834 (mips16_op_table): New table, for mips16 operands.
3835 (build_mips16_operands): New static function.
3836 (process_instructions): If PC is odd, decode a mips16
3837 instruction. Break out instruction handling into new
3838 build_instruction function.
3839 (build_instruction): New static function, broken out of
3840 process_instructions. Check modifiers rather than flags for SHIFT
3841 bit count and m[ft]{hi,lo} direction.
3842 (usage): Pass program name to fprintf.
3843 (main): Remove unused variable this_option_optind. Change
3844 ``*loptarg++'' to ``loptarg++''.
3845 (my_strtoul): Parenthesize && within ||.
3846 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3847 (simulate): If PC is odd, fetch a 16 bit instruction, and
3848 increment PC by 2 rather than 4.
3849 * configure.in: Add case for mips16*-*-*.
3850 * configure: Rebuild.
3851
3852Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3853
3854 * interp.c: Allow -t to enable tracing in standalone simulator.
3855 Fix garbage output in trace file and error messages.
3856
3857Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3858
3859 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3860 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3861 * configure.in: Simplify using macros in ../common/aclocal.m4.
3862 * configure: Regenerated.
3863 * tconfig.in: New file.
3864
3865Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3866
3867 * interp.c: Fix bugs in 64-bit port.
3868 Use ansi function declarations for msvc compiler.
3869 Initialize and test file pointer in trace code.
3870 Prevent duplicate definition of LAST_EMED_REGNUM.
3871
3872Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3873
3874 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3875
3876Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3877
3878 * interp.c (SignalException): Check for explicit terminating
3879 breakpoint value.
3880 * gencode.c: Pass instruction value through SignalException()
3881 calls for Trap, Breakpoint and Syscall.
3882
3883Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3884
3885 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3886 only used on those hosts that provide it.
3887 * configure.in: Add sqrt() to list of functions to be checked for.
3888 * config.in: Re-generated.
3889 * configure: Re-generated.
3890
3891Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3892
3893 * gencode.c (process_instructions): Call build_endian_shift when
3894 expanding STORE RIGHT, to fix swr.
3895 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3896 clear the high bits.
3897 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3898 Fix float to int conversions to produce signed values.
3899
3900Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3901
3902 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3903 (process_instructions): Correct handling of nor instruction.
3904 Correct shift count for 32 bit shift instructions. Correct sign
3905 extension for arithmetic shifts to not shift the number of bits in
3906 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3907 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3908 Fix madd.
3909 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3910 It's OK to have a mult follow a mult. What's not OK is to have a
3911 mult follow an mfhi.
3912 (Convert): Comment out incorrect rounding code.
3913
3914Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3915
3916 * interp.c (sim_monitor): Improved monitor printf
3917 simulation. Tidied up simulator warnings, and added "--log" option
3918 for directing warning message output.
3919 * gencode.c: Use sim_warning() rather than WARNING macro.
3920
3921Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3922
3923 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3924 getopt1.o, rather than on gencode.c. Link objects together.
3925 Don't link against -liberty.
3926 (gencode.o, getopt.o, getopt1.o): New targets.
3927 * gencode.c: Include <ctype.h> and "ansidecl.h".
3928 (AND): Undefine after including "ansidecl.h".
3929 (ULONG_MAX): Define if not defined.
3930 (OP_*): Don't define macros; now defined in opcode/mips.h.
3931 (main): Call my_strtoul rather than strtoul.
3932 (my_strtoul): New static function.
3933
3934Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3935
3936 * gencode.c (process_instructions): Generate word64 and uword64
3937 instead of `long long' and `unsigned long long' data types.
3938 * interp.c: #include sysdep.h to get signals, and define default
3939 for SIGBUS.
3940 * (Convert): Work around for Visual-C++ compiler bug with type
3941 conversion.
3942 * support.h: Make things compile under Visual-C++ by using
3943 __int64 instead of `long long'. Change many refs to long long
3944 into word64/uword64 typedefs.
3945
3946Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3947
72f4393d
L		 3948 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3949 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3950 (docdir): Removed.
3951 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3952 (AC_PROG_INSTALL): Added.
c906108c 3953 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3954 * configure: Rebuilt.
3955
c906108c
SS		 3956Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3957
3958 * configure.in: Define @SIMCONF@ depending on mips target.
3959 * configure: Rebuild.
3960 * Makefile.in (run): Add @SIMCONF@ to control simulator
3961 construction.
3962 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3963 * interp.c: Remove some debugging, provide more detailed error
3964 messages, update memory accesses to use LOADDRMASK.
72f4393d 3965
c906108c
SS		 3966Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3967
3968 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3969 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3970 stamp-h.
3971 * configure: Rebuild.
3972 * config.in: New file, generated by autoheader.
3973 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3974 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3975 HAVE_ANINT and HAVE_AINT, as appropriate.
3976 * Makefile.in (run): Use @LIBS@ rather than -lm.
3977 (interp.o): Depend upon config.h.
3978 (Makefile): Just rebuild Makefile.
3979 (clean): Remove stamp-h.
3980 (mostlyclean): Make the same as clean, not as distclean.
3981 (config.h, stamp-h): New targets.
3982
3983Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3984
3985 * interp.c (ColdReset): Fix boolean test. Make all simulator
3986 globals static.
3987
3988Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3989
3990 * interp.c (xfer_direct_word, xfer_direct_long,
3991 swap_direct_word, swap_direct_long, xfer_big_word,
3992 xfer_big_long, xfer_little_word, xfer_little_long,
3993 swap_word,swap_long): Added.
3994 * interp.c (ColdReset): Provide function indirection to
3995 host<->simulated_target transfer routines.
3996 * interp.c (sim_store_register, sim_fetch_register): Updated to
3997 make use of indirected transfer routines.
3998
3999Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
4000
4001 * gencode.c (process_instructions): Ensure FP ABS instruction
4002 recognised.
4003 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
4004 system call support.
4005
4006Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
4007
4008 * interp.c (sim_do_command): Complain if callback structure not
4009 initialised.
4010
4011Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
4012
4013 * interp.c (Convert): Provide round-to-nearest and round-to-zero
4014 support for Sun hosts.
4015 * Makefile.in (gencode): Ensure the host compiler and libraries
4016 used for cross-hosted build.
4017
4018Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
4019
4020 * interp.c, gencode.c: Some more (TODO) tidying.
4021
4022Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
4023
4024 * gencode.c, interp.c: Replaced explicit long long references with
4025 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
4026 * support.h (SET64LO, SET64HI): Macros added.
4027
4028Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
4029
4030 * configure: Regenerate with autoconf 2.7.
4031
4032Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
4033
4034 * interp.c (LoadMemory): Enclose text following #endif in /* */.
4035 * support.h: Remove superfluous "1" from #if.
4036 * support.h (CHECKSIM): Remove stray 'a' at end of line.
4037
4038Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
4039
4040 * interp.c (StoreFPR): Control UndefinedResult() call on
4041 WARN_RESULT manifest.
4042
4043Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4044
4045 * gencode.c: Tidied instruction decoding, and added FP instruction
4046 support.
4047
4048 * interp.c: Added dineroIII, and BSD profiling support. Also
4049 run-time FP handling.
4050
4051Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4052
4053 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4054 gencode.c, interp.c, support.h: created.
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