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* aout64.h (N_SHARED_LIB): Define as 0 if TEXT_START_ADDR is
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
9846de1b
JM		 1Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
2
3 * mips.igen (MULT, MULTU): Add syntax for two operand version.
4 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
5 them as unimplemented.
6
cd0fc7c3
SS		 71999-05-08 Felix Lee <flee@cygnus.com>
8
9 * configure: Regenerated to track ../common/aclocal.m4 changes.
10
7a292a7a
SS		 111999-04-21 Frank Ch. Eigler <fche@cygnus.com>
12
13 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
14
15Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
16
17 * configure.in: Any mips64vr5*-*-* target should have
18 -DTARGET_ENABLE_FR=1.
19 (default_endian): Any mips64vr*el-*-* target should default to
20 LITTLE_ENDIAN.
21 * configure: Re-generate.
22
231999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
24
25 * mips.igen (ldl): Extend from _16_, not 32.
26
27Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
28
29 * interp.c (sim_store_register): Force registers written to by GDB
30 into an un-interpreted state.
31
c906108c
SS		 321999-02-05 Frank Ch. Eigler <fche@cygnus.com>
33
34 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
35 CPU, start periodic background I/O polls.
36 (tx3904sio_poll): New function: periodic I/O poller.
37
381998-12-30 Frank Ch. Eigler <fche@cygnus.com>
39
40 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
41
42Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
43
44 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
45 case statement.
46
471998-12-29 Frank Ch. Eigler <fche@cygnus.com>
48
49 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
50 (load_word): Call SIM_CORE_SIGNAL hook on error.
51 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
52 starting. For exception dispatching, pass PC instead of NULL_CIA.
53 (decode_coproc): Use COP0_BADVADDR to store faulting address.
54 * sim-main.h (COP0_BADVADDR): Define.
55 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
56 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
57 (_sim_cpu): Add exc_* fields to store register value snapshots.
58 * mips.igen (*): Replace memory-related SignalException* calls
59 with references to SIM_CORE_SIGNAL hook.
60
61 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
62 fix.
63 * sim-main.c (*): Minor warning cleanups.
64
651998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
66
67 * m16.igen (DADDIU5): Correct type-o.
68
69Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
70
71 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
72 variables.
73
74Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
75
76 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
77 to include path.
78 (interp.o): Add dependency on itable.h
79 (oengine.c, gencode): Delete remaining references.
80 (BUILT_SRC_FROM_GEN): Clean up.
81
821998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
83
84 * vr4run.c: New.
85 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
86 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
87 tmp-run-hack) : New.
88 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
89 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
90 Drop the "64" qualifier to get the HACK generator working.
91 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
92 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
93 qualifier to get the hack generator working.
94 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
95 (DSLL): Use do_dsll.
96 (DSLLV): Use do_dsllv.
97 (DSRA): Use do_dsra.
98 (DSRL): Use do_dsrl.
99 (DSRLV): Use do_dsrlv.
100 (BC1): Move *vr4100 to get the HACK generator working.
101 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
102 get the HACK generator working.
103 (MACC) Rename to get the HACK generator working.
104 (DMACC,MACCS,DMACCS): Add the 64.
105
1061998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
107
108 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
109 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
110
1111998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
112
113 * mips/interp.c (DEBUG): Cleanups.
114
1151998-12-10 Frank Ch. Eigler <fche@cygnus.com>
116
117 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
118 (tx3904sio_tickle): fflush after a stdout character output.
119
1201998-12-03 Frank Ch. Eigler <fche@cygnus.com>
121
122 * interp.c (sim_close): Uninstall modules.
123
124Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
125
126 * sim-main.h, interp.c (sim_monitor): Change to global
127 function.
128
129Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
130
131 * configure.in (vr4100): Only include vr4100 instructions in
132 simulator.
133 * configure: Re-generate.
134 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
135
136Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
137
138 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
139 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
140 true alternative.
141
142 * configure.in (sim_default_gen, sim_use_gen): Replace with
143 sim_gen.
144 (--enable-sim-igen): Delete config option. Always using IGEN.
145 * configure: Re-generate.
146
147 * Makefile.in (gencode): Kill, kill, kill.
148 * gencode.c: Ditto.
149
150Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
151
152 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
153 bit mips16 igen simulator.
154 * configure: Re-generate.
155
156 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
157 as part of vr4100 ISA.
158 * vr.igen: Mark all instructions as 64 bit only.
159
160Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
161
162 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
163 Pacify GCC.
164
165Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
166
167 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
168 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
169 * configure: Re-generate.
170
171 * m16.igen (BREAK): Define breakpoint instruction.
172 (JALX32): Mark instruction as mips16 and not r3900.
173 * mips.igen (C.cond.fmt): Fix typo in instruction format.
174
175 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
176
177Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
178
179 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
180 insn as a debug breakpoint.
181
182 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
183 pending.slot_size.
184 (PENDING_SCHED): Clean up trace statement.
185 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
186 (PENDING_FILL): Delay write by only one cycle.
187 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
188
189 * sim-main.c (pending_tick): Clean up trace statements. Add trace
190 of pending writes.
191 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
192 32 & 64.
193 (pending_tick): Move incrementing of index to FOR statement.
194 (pending_tick): Only update PENDING_OUT after a write has occured.
195
196 * configure.in: Add explicit mips-lsi-* target. Use gencode to
197 build simulator.
198 * configure: Re-generate.
199
200 * interp.c (sim_engine_run OLD): Delete explicit call to
201 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
202
203Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
204
205 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
206 interrupt level number to match changed SignalExceptionInterrupt
207 macro.
208
209Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
210
211 * interp.c: #include "itable.h" if WITH_IGEN.
212 (get_insn_name): New function.
213 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
214 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
215
216Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
217
218 * configure: Rebuilt to inhale new common/aclocal.m4.
219
220Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
221
222 * dv-tx3904sio.c: Include sim-assert.h.
223
224Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
225
226 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
227 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
228 Reorganize target-specific sim-hardware checks.
229 * configure: rebuilt.
230 * interp.c (sim_open): For tx39 target boards, set
231 OPERATING_ENVIRONMENT, add tx3904sio devices.
232 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
233 ROM executables. Install dv-sockser into sim-modules list.
234
235 * dv-tx3904irc.c: Compiler warning clean-up.
236 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
237 frequent hw-trace messages.
238
239Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
240
241 * vr.igen (MulAcc): Identify as a vr4100 specific function.
242
243Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
244
245 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
246
247 * vr.igen: New file.
248 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
249 * mips.igen: Define vr4100 model. Include vr.igen.
250Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
251
252 * mips.igen (check_mf_hilo): Correct check.
253
254Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
255
256 * sim-main.h (interrupt_event): Add prototype.
257
258 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
259 register_ptr, register_value.
260 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
261
262 * sim-main.h (tracefh): Make extern.
263
264Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
265
266 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
267 Reduce unnecessarily high timer event frequency.
268 * dv-tx3904cpu.c: Ditto for interrupt event.
269
270Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
271
272 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
273 to allay warnings.
274 (interrupt_event): Made non-static.
275
276 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
277 interchange of configuration values for external vs. internal
278 clock dividers.
279
280Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
281
282 * mips.igen (BREAK): Moved code to here for
283 simulator-reserved break instructions.
284 * gencode.c (build_instruction): Ditto.
285 * interp.c (signal_exception): Code moved from here. Non-
286 reserved instructions now use exception vector, rather
287 than halting sim.
288 * sim-main.h: Moved magic constants to here.
289
290Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
291
292 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
293 register upon non-zero interrupt event level, clear upon zero
294 event value.
295 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
296 by passing zero event value.
297 (*_io_{read,write}_buffer): Endianness fixes.
298 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
299 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
300
301 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
302 serial I/O and timer module at base address 0xFFFF0000.
303
304Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
305
306 * mips.igen (SWC1) : Correct the handling of ReverseEndian
307 and BigEndianCPU.
308
309Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
310
311 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
312 parts.
313 * configure: Update.
314
315Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
316
317 * dv-tx3904tmr.c: New file - implements tx3904 timer.
318 * dv-tx3904{irc,cpu}.c: Mild reformatting.
319 * configure.in: Include tx3904tmr in hw_device list.
320 * configure: Rebuilt.
321 * interp.c (sim_open): Instantiate three timer instances.
322 Fix address typo of tx3904irc instance.
323
324Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
325
326 * interp.c (signal_exception): SystemCall exception now uses
327 the exception vector.
328
329Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
330
331 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
332 to allay warnings.
333
334Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
335
336 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
337
338Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
339
340 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
341
342 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
343 sim-main.h. Declare a struct hw_descriptor instead of struct
344 hw_device_descriptor.
345
346Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
347
348 * mips.igen (do_store_left, do_load_left): Compute nr of left and
349 right bits and then re-align left hand bytes to correct byte
350 lanes. Fix incorrect computation in do_store_left when loading
351 bytes from second word.
352
353Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
354
355 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
356 * interp.c (sim_open): Only create a device tree when HW is
357 enabled.
358
359 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
360 * interp.c (signal_exception): Ditto.
361
362Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
363
364 * gencode.c: Mark BEGEZALL as LIKELY.
365
366Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
367
368 * sim-main.h (ALU32_END): Sign extend 32 bit results.
369 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
370
371Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
372
373 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
374 modules. Recognize TX39 target with "mips*tx39" pattern.
375 * configure: Rebuilt.
376 * sim-main.h (*): Added many macros defining bits in
377 TX39 control registers.
378 (SignalInterrupt): Send actual PC instead of NULL.
379 (SignalNMIReset): New exception type.
380 * interp.c (board): New variable for future use to identify
381 a particular board being simulated.
382 (mips_option_handler,mips_options): Added "--board" option.
383 (interrupt_event): Send actual PC.
384 (sim_open): Make memory layout conditional on board setting.
385 (signal_exception): Initial implementation of hardware interrupt
386 handling. Accept another break instruction variant for simulator
387 exit.
388 (decode_coproc): Implement RFE instruction for TX39.
389 (mips.igen): Decode RFE instruction as such.
390 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
391 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
392 bbegin to implement memory map.
393 * dv-tx3904cpu.c: New file.
394 * dv-tx3904irc.c: New file.
395
396Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
397
398 * mips.igen (check_mt_hilo): Create a separate r3900 version.
399
400Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
401
402 * tx.igen (madd,maddu): Replace calls to check_op_hilo
403 with calls to check_div_hilo.
404
405Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
406
407 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
408 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
409 Add special r3900 version of do_mult_hilo.
410 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
411 with calls to check_mult_hilo.
412 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
413 with calls to check_div_hilo.
414
415Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
416
417 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
418 Document a replacement.
419
420Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
421
422 * interp.c (sim_monitor): Make mon_printf work.
423
424Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
425
426 * sim-main.h (INSN_NAME): New arg `cpu'.
427
428Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
429
430 * configure: Regenerated to track ../common/aclocal.m4 changes.
431
432Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
433
434 * configure: Regenerated to track ../common/aclocal.m4 changes.
435 * config.in: Ditto.
436
437Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
438
439 * acconfig.h: New file.
440 * configure.in: Reverted change of Apr 24; use sinclude again.
441
442Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
443
444 * configure: Regenerated to track ../common/aclocal.m4 changes.
445 * config.in: Ditto.
446
447Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
448
449 * configure.in: Don't call sinclude.
450
451Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
452
453 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
454
455Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
456
457 * mips.igen (ERET): Implement.
458
459 * interp.c (decode_coproc): Return sign-extended EPC.
460
461 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
462
463 * interp.c (signal_exception): Do not ignore Trap.
464 (signal_exception): On TRAP, restart at exception address.
465 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
466 (signal_exception): Update.
467 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
468 so that TRAP instructions are caught.
469
470Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
471
472 * sim-main.h (struct hilo_access, struct hilo_history): Define,
473 contains HI/LO access history.
474 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
475 (HIACCESS, LOACCESS): Delete, replace with
476 (HIHISTORY, LOHISTORY): New macros.
477 (CHECKHILO): Delete all, moved to mips.igen
478
479 * gencode.c (build_instruction): Do not generate checks for
480 correct HI/LO register usage.
481
482 * interp.c (old_engine_run): Delete checks for correct HI/LO
483 register usage.
484
485 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
486 check_mf_cycles): New functions.
487 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
488 do_divu, domultx, do_mult, do_multu): Use.
489
490 * tx.igen ("madd", "maddu"): Use.
491
492Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
493
494 * mips.igen (DSRAV): Use function do_dsrav.
495 (SRAV): Use new function do_srav.
496
497 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
498 (B): Sign extend 11 bit immediate.
499 (EXT-B*): Shift 16 bit immediate left by 1.
500 (ADDIU*): Don't sign extend immediate value.
501
502Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
503
504 * m16run.c (sim_engine_run): Restore CIA after handling an event.
505
506 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
507 functions.
508
509 * mips.igen (delayslot32, nullify_next_insn): New functions.
510 (m16.igen): Always include.
511 (do_*): Add more tracing.
512
513 * m16.igen (delayslot16): Add NIA argument, could be called by a
514 32 bit MIPS16 instruction.
515
516 * interp.c (ifetch16): Move function from here.
517 * sim-main.c (ifetch16): To here.
518
519 * sim-main.c (ifetch16, ifetch32): Update to match current
520 implementations of LH, LW.
521 (signal_exception): Don't print out incorrect hex value of illegal
522 instruction.
523
524Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
525
526 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
527 instruction.
528
529 * m16.igen: Implement MIPS16 instructions.
530
531 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
532 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
533 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
534 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
535 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
536 bodies of corresponding code from 32 bit insn to these. Also used
537 by MIPS16 versions of functions.
538
539 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
540 (IMEM16): Drop NR argument from macro.
541
542Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
543
544 * Makefile.in (SIM_OBJS): Add sim-main.o.
545
546 * sim-main.h (address_translation, load_memory, store_memory,
547 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
548 as INLINE_SIM_MAIN.
549 (pr_addr, pr_uword64): Declare.
550 (sim-main.c): Include when H_REVEALS_MODULE_P.
551
552 * interp.c (address_translation, load_memory, store_memory,
553 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
554 from here.
555 * sim-main.c: To here. Fix compilation problems.
556
557 * configure.in: Enable inlining.
558 * configure: Re-config.
559
560Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
561
562 * configure: Regenerated to track ../common/aclocal.m4 changes.
563
564Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
565
566 * mips.igen: Include tx.igen.
567 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
568 * tx.igen: New file, contains MADD and MADDU.
569
570 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
571 the hardwired constant `7'.
572 (store_memory): Ditto.
573 (LOADDRMASK): Move definition to sim-main.h.
574
575 mips.igen (MTC0): Enable for r3900.
576 (ADDU): Add trace.
577
578 mips.igen (do_load_byte): Delete.
579 (do_load, do_store, do_load_left, do_load_write, do_store_left,
580 do_store_right): New functions.
581 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
582
583 configure.in: Let the tx39 use igen again.
584 configure: Update.
585
586Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
587
588 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
589 not an address sized quantity. Return zero for cache sizes.
590
591Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
592
593 * mips.igen (r3900): r3900 does not support 64 bit integer
594 operations.
595
596Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
597
598 * configure.in (mipstx39*-*-*): Use gencode simulator rather
599 than igen one.
600 * configure : Rebuild.
601
602Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
603
604 * configure: Regenerated to track ../common/aclocal.m4 changes.
605
606Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
607
608 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
609
610Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
611
612 * configure: Regenerated to track ../common/aclocal.m4 changes.
613 * config.in: Regenerated to track ../common/aclocal.m4 changes.
614
615Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
616
617 * configure: Regenerated to track ../common/aclocal.m4 changes.
618
619Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
620
621 * interp.c (Max, Min): Comment out functions. Not yet used.
622
623Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
624
625 * configure: Regenerated to track ../common/aclocal.m4 changes.
626
627Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
628
629 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
630 configurable settings for stand-alone simulator.
631
632 * configure.in: Added X11 search, just in case.
633
634 * configure: Regenerated.
635
636Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
637
638 * interp.c (sim_write, sim_read, load_memory, store_memory):
639 Replace sim_core_*_map with read_map, write_map, exec_map resp.
640
641Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
642
643 * sim-main.h (GETFCC): Return an unsigned value.
644
645Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
646
647 * mips.igen (DIV): Fix check for -1 / MIN_INT.
648 (DADD): Result destination is RD not RT.
649
650Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
651
652 * sim-main.h (HIACCESS, LOACCESS): Always define.
653
654 * mdmx.igen (Maxi, Mini): Rename Max, Min.
655
656 * interp.c (sim_info): Delete.
657
658Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
659
660 * interp.c (DECLARE_OPTION_HANDLER): Use it.
661 (mips_option_handler): New argument `cpu'.
662 (sim_open): Update call to sim_add_option_table.
663
664Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
665
666 * mips.igen (CxC1): Add tracing.
667
668Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
669
670 * sim-main.h (Max, Min): Declare.
671
672 * interp.c (Max, Min): New functions.
673
674 * mips.igen (BC1): Add tracing.
675
676Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
677
678 * interp.c Added memory map for stack in vr4100
679
680Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
681
682 * interp.c (load_memory): Add missing "break"'s.
683
684Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
685
686 * interp.c (sim_store_register, sim_fetch_register): Pass in
687 length parameter. Return -1.
688
689Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
690
691 * interp.c: Added hardware init hook, fixed warnings.
692
693Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
694
695 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
696
697Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
698
699 * interp.c (ifetch16): New function.
700
701 * sim-main.h (IMEM32): Rename IMEM.
702 (IMEM16_IMMED): Define.
703 (IMEM16): Define.
704 (DELAY_SLOT): Update.
705
706 * m16run.c (sim_engine_run): New file.
707
708 * m16.igen: All instructions except LB.
709 (LB): Call do_load_byte.
710 * mips.igen (do_load_byte): New function.
711 (LB): Call do_load_byte.
712
713 * mips.igen: Move spec for insn bit size and high bit from here.
714 * Makefile.in (tmp-igen, tmp-m16): To here.
715
716 * m16.dc: New file, decode mips16 instructions.
717
718 * Makefile.in (SIM_NO_ALL): Define.
719 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
720
721Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
722
723 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
724 point unit to 32 bit registers.
725 * configure: Re-generate.
726
727Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
728
729 * configure.in (sim_use_gen): Make IGEN the default simulator
730 generator for generic 32 and 64 bit mips targets.
731 * configure: Re-generate.
732
733Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
734
735 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
736 bitsize.
737
738 * interp.c (sim_fetch_register, sim_store_register): Read/write
739 FGR from correct location.
740 (sim_open): Set size of FGR's according to
741 WITH_TARGET_FLOATING_POINT_BITSIZE.
742
743 * sim-main.h (FGR): Store floating point registers in a separate
744 array.
745
746Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
747
748 * configure: Regenerated to track ../common/aclocal.m4 changes.
749
750Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
751
752 * interp.c (ColdReset): Call PENDING_INVALIDATE.
753
754 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
755
756 * interp.c (pending_tick): New function. Deliver pending writes.
757
758 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
759 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
760 it can handle mixed sized quantites and single bits.
761
762Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
763
764 * interp.c (oengine.h): Do not include when building with IGEN.
765 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
766 (sim_info): Ditto for PROCESSOR_64BIT.
767 (sim_monitor): Replace ut_reg with unsigned_word.
768 (*): Ditto for t_reg.
769 (LOADDRMASK): Define.
770 (sim_open): Remove defunct check that host FP is IEEE compliant,
771 using software to emulate floating point.
772 (value_fpr, ...): Always compile, was conditional on HASFPU.
773
774Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
775
776 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
777 size.
778
779 * interp.c (SD, CPU): Define.
780 (mips_option_handler): Set flags in each CPU.
781 (interrupt_event): Assume CPU 0 is the one being iterrupted.
782 (sim_close): Do not clear STATE, deleted anyway.
783 (sim_write, sim_read): Assume CPU zero's vm should be used for
784 data transfers.
785 (sim_create_inferior): Set the PC for all processors.
786 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
787 argument.
788 (mips16_entry): Pass correct nr of args to store_word, load_word.
789 (ColdReset): Cold reset all cpu's.
790 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
791 (sim_monitor, load_memory, store_memory, signal_exception): Use
792 `CPU' instead of STATE_CPU.
793
794
795 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
796 SD or CPU_.
797
798 * sim-main.h (signal_exception): Add sim_cpu arg.
799 (SignalException*): Pass both SD and CPU to signal_exception.
800 * interp.c (signal_exception): Update.
801
802 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
803 Ditto
804 (sync_operation, prefetch, cache_op, store_memory, load_memory,
805 address_translation): Ditto
806 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
807
808Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
809
810 * configure: Regenerated to track ../common/aclocal.m4 changes.
811
812Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
813
814 * interp.c (sim_engine_run): Add `nr_cpus' argument.
815
816 * mips.igen (model): Map processor names onto BFD name.
817
818 * sim-main.h (CPU_CIA): Delete.
819 (SET_CIA, GET_CIA): Define
820
821Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
822
823 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
824 regiser.
825
826 * configure.in (default_endian): Configure a big-endian simulator
827 by default.
828 * configure: Re-generate.
829
830Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
831
832 * configure: Regenerated to track ../common/aclocal.m4 changes.
833
834Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
835
836 * interp.c (sim_monitor): Handle Densan monitor outbyte
837 and inbyte functions.
838
8391997-12-29 Felix Lee <flee@cygnus.com>
840
841 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
842
843Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
844
845 * Makefile.in (tmp-igen): Arrange for $zero to always be
846 reset to zero after every instruction.
847
848Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
849
850 * configure: Regenerated to track ../common/aclocal.m4 changes.
851 * config.in: Ditto.
852
853Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
854
855 * mips.igen (MSUB): Fix to work like MADD.
856 * gencode.c (MSUB): Similarly.
857
858Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
859
860 * configure: Regenerated to track ../common/aclocal.m4 changes.
861
862Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
863
864 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
865
866Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
867
868 * sim-main.h (sim-fpu.h): Include.
869
870 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
871 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
872 using host independant sim_fpu module.
873
874Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
875
876 * interp.c (signal_exception): Report internal errors with SIGABRT
877 not SIGQUIT.
878
879 * sim-main.h (C0_CONFIG): New register.
880 (signal.h): No longer include.
881
882 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
883
884Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
885
886 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
887
888Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
889
890 * mips.igen: Tag vr5000 instructions.
891 (ANDI): Was missing mipsIV model, fix assembler syntax.
892 (do_c_cond_fmt): New function.
893 (C.cond.fmt): Handle mips I-III which do not support CC field
894 separatly.
895 (bc1): Handle mips IV which do not have a delaed FCC separatly.
896 (SDR): Mask paddr when BigEndianMem, not the converse as specified
897 in IV3.2 spec.
898 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
899 vr5000 which saves LO in a GPR separatly.
900
901 * configure.in (enable-sim-igen): For vr5000, select vr5000
902 specific instructions.
903 * configure: Re-generate.
904
905Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
906
907 * Makefile.in (SIM_OBJS): Add sim-fpu module.
908
909 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
910 fmt_uninterpreted_64 bit cases to switch. Convert to
911 fmt_formatted,
912
913 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
914
915 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
916 as specified in IV3.2 spec.
917 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
918
919Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
920
921 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
922 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
923 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
924 PENDING_FILL versions of instructions. Simplify.
925 (X): New function.
926 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
927 instructions.
928 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
929 a signed value.
930 (MTHI, MFHI): Disable code checking HI-LO.
931
932 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
933 global.
934 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
935
936Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
937
938 * gencode.c (build_mips16_operands): Replace IPC with cia.
939
940 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
941 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
942 IPC to `cia'.
943 (UndefinedResult): Replace function with macro/function
944 combination.
945 (sim_engine_run): Don't save PC in IPC.
946
947 * sim-main.h (IPC): Delete.
948
949
950 * interp.c (signal_exception, store_word, load_word,
951 address_translation, load_memory, store_memory, cache_op,
952 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
953 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
954 current instruction address - cia - argument.
955 (sim_read, sim_write): Call address_translation directly.
956 (sim_engine_run): Rename variable vaddr to cia.
957 (signal_exception): Pass cia to sim_monitor
958
959 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
960 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
961 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
962
963 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
964 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
965 SIM_ASSERT.
966
967 * interp.c (signal_exception): Pass restart address to
968 sim_engine_restart.
969
970 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
971 idecode.o): Add dependency.
972
973 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
974 Delete definitions
975 (DELAY_SLOT): Update NIA not PC with branch address.
976 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
977
978 * mips.igen: Use CIA not PC in branch calculations.
979 (illegal): Call SignalException.
980 (BEQ, ADDIU): Fix assembler.
981
982Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
983
984 * m16.igen (JALX): Was missing.
985
986 * configure.in (enable-sim-igen): New configuration option.
987 * configure: Re-generate.
988
989 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
990
991 * interp.c (load_memory, store_memory): Delete parameter RAW.
992 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
993 bypassing {load,store}_memory.
994
995 * sim-main.h (ByteSwapMem): Delete definition.
996
997 * Makefile.in (SIM_OBJS): Add sim-memopt module.
998
999 * interp.c (sim_do_command, sim_commands): Delete mips specific
1000 commands. Handled by module sim-options.
1001
1002 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1003 (WITH_MODULO_MEMORY): Define.
1004
1005 * interp.c (sim_info): Delete code printing memory size.
1006
1007 * interp.c (mips_size): Nee sim_size, delete function.
1008 (power2): Delete.
1009 (monitor, monitor_base, monitor_size): Delete global variables.
1010 (sim_open, sim_close): Delete code creating monitor and other
1011 memory regions. Use sim-memopts module, via sim_do_commandf, to
1012 manage memory regions.
1013 (load_memory, store_memory): Use sim-core for memory model.
1014
1015 * interp.c (address_translation): Delete all memory map code
1016 except line forcing 32 bit addresses.
1017
1018Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1019
1020 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1021 trace options.
1022
1023 * interp.c (logfh, logfile): Delete globals.
1024 (sim_open, sim_close): Delete code opening & closing log file.
1025 (mips_option_handler): Delete -l and -n options.
1026 (OPTION mips_options): Ditto.
1027
1028 * interp.c (OPTION mips_options): Rename option trace to dinero.
1029 (mips_option_handler): Update.
1030
1031Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1032
1033 * interp.c (fetch_str): New function.
1034 (sim_monitor): Rewrite using sim_read & sim_write.
1035 (sim_open): Check magic number.
1036 (sim_open): Write monitor vectors into memory using sim_write.
1037 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1038 (sim_read, sim_write): Simplify - transfer data one byte at a
1039 time.
1040 (load_memory, store_memory): Clarify meaning of parameter RAW.
1041
1042 * sim-main.h (isHOST): Defete definition.
1043 (isTARGET): Mark as depreciated.
1044 (address_translation): Delete parameter HOST.
1045
1046 * interp.c (address_translation): Delete parameter HOST.
1047
1048Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1049
1050 * mips.igen:
1051
1052 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1053 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1054
1055Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1056
1057 * mips.igen: Add model filter field to records.
1058
1059Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1060
1061 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1062
1063 interp.c (sim_engine_run): Do not compile function sim_engine_run
1064 when WITH_IGEN == 1.
1065
1066 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1067 target architecture.
1068
1069 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1070 igen. Replace with configuration variables sim_igen_flags /
1071 sim_m16_flags.
1072
1073 * m16.igen: New file. Copy mips16 insns here.
1074 * mips.igen: From here.
1075
1076Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1077
1078 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1079 to top.
1080 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1081
1082Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1083
1084 * gencode.c (build_instruction): Follow sim_write's lead in using
1085 BigEndianMem instead of !ByteSwapMem.
1086
1087Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1088
1089 * configure.in (sim_gen): Dependent on target, select type of
1090 generator. Always select old style generator.
1091
1092 configure: Re-generate.
1093
1094 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1095 targets.
1096 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1097 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1098 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1099 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1100 SIM_@sim_gen@_*, set by autoconf.
1101
1102Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1103
1104 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1105
1106 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1107 CURRENT_FLOATING_POINT instead.
1108
1109 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1110 (address_translation): Raise exception InstructionFetch when
1111 translation fails and isINSTRUCTION.
1112
1113 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1114 sim_engine_run): Change type of of vaddr and paddr to
1115 address_word.
1116 (address_translation, prefetch, load_memory, store_memory,
1117 cache_op): Change type of vAddr and pAddr to address_word.
1118
1119 * gencode.c (build_instruction): Change type of vaddr and paddr to
1120 address_word.
1121
1122Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1123
1124 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1125 macro to obtain result of ALU op.
1126
1127Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1128
1129 * interp.c (sim_info): Call profile_print.
1130
1131Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1132
1133 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1134
1135 * sim-main.h (WITH_PROFILE): Do not define, defined in
1136 common/sim-config.h. Use sim-profile module.
1137 (simPROFILE): Delete defintion.
1138
1139 * interp.c (PROFILE): Delete definition.
1140 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1141 (sim_close): Delete code writing profile histogram.
1142 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1143 Delete.
1144 (sim_engine_run): Delete code profiling the PC.
1145
1146Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1147
1148 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1149
1150 * interp.c (sim_monitor): Make register pointers of type
1151 unsigned_word*.
1152
1153 * sim-main.h: Make registers of type unsigned_word not
1154 signed_word.
1155
1156Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1157
1158 * interp.c (sync_operation): Rename from SyncOperation, make
1159 global, add SD argument.
1160 (prefetch): Rename from Prefetch, make global, add SD argument.
1161 (decode_coproc): Make global.
1162
1163 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1164
1165 * gencode.c (build_instruction): Generate DecodeCoproc not
1166 decode_coproc calls.
1167
1168 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1169 (SizeFGR): Move to sim-main.h
1170 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1171 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1172 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1173 sim-main.h.
1174 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1175 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1176 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1177 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1178 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1179 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1180
1181 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1182 exception.
1183 (sim-alu.h): Include.
1184 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1185 (sim_cia): Typedef to instruction_address.
1186
1187Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1188
1189 * Makefile.in (interp.o): Rename generated file engine.c to
1190 oengine.c.
1191
1192 * interp.c: Update.
1193
1194Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1195
1196 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1197
1198Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1199
1200 * gencode.c (build_instruction): For "FPSQRT", output correct
1201 number of arguments to Recip.
1202
1203Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1204
1205 * Makefile.in (interp.o): Depends on sim-main.h
1206
1207 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1208
1209 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1210 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1211 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1212 STATE, DSSTATE): Define
1213 (GPR, FGRIDX, ..): Define.
1214
1215 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1216 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1217 (GPR, FGRIDX, ...): Delete macros.
1218
1219 * interp.c: Update names to match defines from sim-main.h
1220
1221Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1222
1223 * interp.c (sim_monitor): Add SD argument.
1224 (sim_warning): Delete. Replace calls with calls to
1225 sim_io_eprintf.
1226 (sim_error): Delete. Replace calls with sim_io_error.
1227 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1228 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1229 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1230 argument.
1231 (mips_size): Rename from sim_size. Add SD argument.
1232
1233 * interp.c (simulator): Delete global variable.
1234 (callback): Delete global variable.
1235 (mips_option_handler, sim_open, sim_write, sim_read,
1236 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1237 sim_size,sim_monitor): Use sim_io_* not callback->*.
1238 (sim_open): ZALLOC simulator struct.
1239 (PROFILE): Do not define.
1240
1241Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1242
1243 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1244 support.h with corresponding code.
1245
1246 * sim-main.h (word64, uword64), support.h: Move definition to
1247 sim-main.h.
1248 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1249
1250 * support.h: Delete
1251 * Makefile.in: Update dependencies
1252 * interp.c: Do not include.
1253
1254Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1255
1256 * interp.c (address_translation, load_memory, store_memory,
1257 cache_op): Rename to from AddressTranslation et.al., make global,
1258 add SD argument
1259
1260 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1261 CacheOp): Define.
1262
1263 * interp.c (SignalException): Rename to signal_exception, make
1264 global.
1265
1266 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1267
1268 * sim-main.h (SignalException, SignalExceptionInterrupt,
1269 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1270 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1271 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1272 Define.
1273
1274 * interp.c, support.h: Use.
1275
1276Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1277
1278 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1279 to value_fpr / store_fpr. Add SD argument.
1280 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1281 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1282
1283 * sim-main.h (ValueFPR, StoreFPR): Define.
1284
1285Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1286
1287 * interp.c (sim_engine_run): Check consistency between configure
1288 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1289 and HASFPU.
1290
1291 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1292 (mips_fpu): Configure WITH_FLOATING_POINT.
1293 (mips_endian): Configure WITH_TARGET_ENDIAN.
1294 * configure: Update.
1295
1296Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1297
1298 * configure: Regenerated to track ../common/aclocal.m4 changes.
1299
1300Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1301
1302 * configure: Regenerated.
1303
1304Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1305
1306 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1307
1308Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1309
1310 * gencode.c (print_igen_insn_models): Assume certain architectures
1311 include all mips* instructions.
1312 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1313 instruction.
1314
1315 * Makefile.in (tmp.igen): Add target. Generate igen input from
1316 gencode file.
1317
1318 * gencode.c (FEATURE_IGEN): Define.
1319 (main): Add --igen option. Generate output in igen format.
1320 (process_instructions): Format output according to igen option.
1321 (print_igen_insn_format): New function.
1322 (print_igen_insn_models): New function.
1323 (process_instructions): Only issue warnings and ignore
1324 instructions when no FEATURE_IGEN.
1325
1326Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1327
1328 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1329 MIPS targets.
1330
1331Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1332
1333 * configure: Regenerated to track ../common/aclocal.m4 changes.
1334
1335Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1336
1337 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1338 SIM_RESERVED_BITS): Delete, moved to common.
1339 (SIM_EXTRA_CFLAGS): Update.
1340
1341Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1342
1343 * configure.in: Configure non-strict memory alignment.
1344 * configure: Regenerated to track ../common/aclocal.m4 changes.
1345
1346Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1347
1348 * configure: Regenerated to track ../common/aclocal.m4 changes.
1349
1350Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1351
1352 * gencode.c (SDBBP,DERET): Added (3900) insns.
1353 (RFE): Turn on for 3900.
1354 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1355 (dsstate): Made global.
1356 (SUBTARGET_R3900): Added.
1357 (CANCELDELAYSLOT): New.
1358 (SignalException): Ignore SystemCall rather than ignore and
1359 terminate. Add DebugBreakPoint handling.
1360 (decode_coproc): New insns RFE, DERET; and new registers Debug
1361 and DEPC protected by SUBTARGET_R3900.
1362 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1363 bits explicitly.
1364 * Makefile.in,configure.in: Add mips subtarget option.
1365 * configure: Update.
1366
1367Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1368
1369 * gencode.c: Add r3900 (tx39).
1370
1371
1372Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1373
1374 * gencode.c (build_instruction): Don't need to subtract 4 for
1375 JALR, just 2.
1376
1377Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1378
1379 * interp.c: Correct some HASFPU problems.
1380
1381Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1382
1383 * configure: Regenerated to track ../common/aclocal.m4 changes.
1384
1385Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1386
1387 * interp.c (mips_options): Fix samples option short form, should
1388 be `x'.
1389
1390Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1391
1392 * interp.c (sim_info): Enable info code. Was just returning.
1393
1394Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1395
1396 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1397 MFC0.
1398
1399Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1400
1401 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1402 constants.
1403 (build_instruction): Ditto for LL.
1404
1405Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1406
1407 * configure: Regenerated to track ../common/aclocal.m4 changes.
1408
1409Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1410
1411 * configure: Regenerated to track ../common/aclocal.m4 changes.
1412 * config.in: Ditto.
1413
1414Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * interp.c (sim_open): Add call to sim_analyze_program, update
1417 call to sim_config.
1418
1419Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1420
1421 * interp.c (sim_kill): Delete.
1422 (sim_create_inferior): Add ABFD argument. Set PC from same.
1423 (sim_load): Move code initializing trap handlers from here.
1424 (sim_open): To here.
1425 (sim_load): Delete, use sim-hload.c.
1426
1427 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1428
1429Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1430
1431 * configure: Regenerated to track ../common/aclocal.m4 changes.
1432 * config.in: Ditto.
1433
1434Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1435
1436 * interp.c (sim_open): Add ABFD argument.
1437 (sim_load): Move call to sim_config from here.
1438 (sim_open): To here. Check return status.
1439
1440Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1441
1442 * gencode.c (build_instruction): Two arg MADD should
1443 not assign result to $0.
1444
1445Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1446
1447 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1448 * sim/mips/configure.in: Regenerate.
1449
1450Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1451
1452 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1453 signed8, unsigned8 et.al. types.
1454
1455 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1456 hosts when selecting subreg.
1457
1458Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1459
1460 * interp.c (sim_engine_run): Reset the ZERO register to zero
1461 regardless of FEATURE_WARN_ZERO.
1462 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1463
1464Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1465
1466 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1467 (SignalException): For BreakPoints ignore any mode bits and just
1468 save the PC.
1469 (SignalException): Always set the CAUSE register.
1470
1471Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1472
1473 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1474 exception has been taken.
1475
1476 * interp.c: Implement the ERET and mt/f sr instructions.
1477
1478Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1479
1480 * interp.c (SignalException): Don't bother restarting an
1481 interrupt.
1482
1483Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1484
1485 * interp.c (SignalException): Really take an interrupt.
1486 (interrupt_event): Only deliver interrupts when enabled.
1487
1488Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1489
1490 * interp.c (sim_info): Only print info when verbose.
1491 (sim_info) Use sim_io_printf for output.
1492
1493Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1494
1495 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1496 mips architectures.
1497
1498Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1499
1500 * interp.c (sim_do_command): Check for common commands if a
1501 simulator specific command fails.
1502
1503Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1504
1505 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1506 and simBE when DEBUG is defined.
1507
1508Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1509
1510 * interp.c (interrupt_event): New function. Pass exception event
1511 onto exception handler.
1512
1513 * configure.in: Check for stdlib.h.
1514 * configure: Regenerate.
1515
1516 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1517 variable declaration.
1518 (build_instruction): Initialize memval1.
1519 (build_instruction): Add UNUSED attribute to byte, bigend,
1520 reverse.
1521 (build_operands): Ditto.
1522
1523 * interp.c: Fix GCC warnings.
1524 (sim_get_quit_code): Delete.
1525
1526 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1527 * Makefile.in: Ditto.
1528 * configure: Re-generate.
1529
1530 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1531
1532Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1533
1534 * interp.c (mips_option_handler): New function parse argumes using
1535 sim-options.
1536 (myname): Replace with STATE_MY_NAME.
1537 (sim_open): Delete check for host endianness - performed by
1538 sim_config.
1539 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1540 (sim_open): Move much of the initialization from here.
1541 (sim_load): To here. After the image has been loaded and
1542 endianness set.
1543 (sim_open): Move ColdReset from here.
1544 (sim_create_inferior): To here.
1545 (sim_open): Make FP check less dependant on host endianness.
1546
1547 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1548 run.
1549 * interp.c (sim_set_callbacks): Delete.
1550
1551 * interp.c (membank, membank_base, membank_size): Replace with
1552 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1553 (sim_open): Remove call to callback->init. gdb/run do this.
1554
1555 * interp.c: Update
1556
1557 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1558
1559 * interp.c (big_endian_p): Delete, replaced by
1560 current_target_byte_order.
1561
1562Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1563
1564 * interp.c (host_read_long, host_read_word, host_swap_word,
1565 host_swap_long): Delete. Using common sim-endian.
1566 (sim_fetch_register, sim_store_register): Use H2T.
1567 (pipeline_ticks): Delete. Handled by sim-events.
1568 (sim_info): Update.
1569 (sim_engine_run): Update.
1570
1571Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1572
1573 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1574 reason from here.
1575 (SignalException): To here. Signal using sim_engine_halt.
1576 (sim_stop_reason): Delete, moved to common.
1577
1578Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1579
1580 * interp.c (sim_open): Add callback argument.
1581 (sim_set_callbacks): Delete SIM_DESC argument.
1582 (sim_size): Ditto.
1583
1584Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1585
1586 * Makefile.in (SIM_OBJS): Add common modules.
1587
1588 * interp.c (sim_set_callbacks): Also set SD callback.
1589 (set_endianness, xfer_*, swap_*): Delete.
1590 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1591 Change to functions using sim-endian macros.
1592 (control_c, sim_stop): Delete, use common version.
1593 (simulate): Convert into.
1594 (sim_engine_run): This function.
1595 (sim_resume): Delete.
1596
1597 * interp.c (simulation): New variable - the simulator object.
1598 (sim_kind): Delete global - merged into simulation.
1599 (sim_load): Cleanup. Move PC assignment from here.
1600 (sim_create_inferior): To here.
1601
1602 * sim-main.h: New file.
1603 * interp.c (sim-main.h): Include.
1604
1605Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1606
1607 * configure: Regenerated to track ../common/aclocal.m4 changes.
1608
1609Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1610
1611 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1612
1613Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1614
1615 * gencode.c (build_instruction): DIV instructions: check
1616 for division by zero and integer overflow before using
1617 host's division operation.
1618
1619Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1620
1621 * Makefile.in (SIM_OBJS): Add sim-load.o.
1622 * interp.c: #include bfd.h.
1623 (target_byte_order): Delete.
1624 (sim_kind, myname, big_endian_p): New static locals.
1625 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1626 after argument parsing. Recognize -E arg, set endianness accordingly.
1627 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1628 load file into simulator. Set PC from bfd.
1629 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1630 (set_endianness): Use big_endian_p instead of target_byte_order.
1631
1632Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1633
1634 * interp.c (sim_size): Delete prototype - conflicts with
1635 definition in remote-sim.h. Correct definition.
1636
1637Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1638
1639 * configure: Regenerated to track ../common/aclocal.m4 changes.
1640 * config.in: Ditto.
1641
1642Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1643
1644 * interp.c (sim_open): New arg `kind'.
1645
1646 * configure: Regenerated to track ../common/aclocal.m4 changes.
1647
1648Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1649
1650 * configure: Regenerated to track ../common/aclocal.m4 changes.
1651
1652Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1653
1654 * interp.c (sim_open): Set optind to 0 before calling getopt.
1655
1656Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1657
1658 * configure: Regenerated to track ../common/aclocal.m4 changes.
1659
1660Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1661
1662 * interp.c : Replace uses of pr_addr with pr_uword64
1663 where the bit length is always 64 independent of SIM_ADDR.
1664 (pr_uword64) : added.
1665
1666Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1667
1668 * configure: Re-generate.
1669
1670Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1671
1672 * configure: Regenerate to track ../common/aclocal.m4 changes.
1673
1674Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1675
1676 * interp.c (sim_open): New SIM_DESC result. Argument is now
1677 in argv form.
1678 (other sim_*): New SIM_DESC argument.
1679
1680Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1681
1682 * interp.c: Fix printing of addresses for non-64-bit targets.
1683 (pr_addr): Add function to print address based on size.
1684
1685Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1686
1687 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1688
1689Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1690
1691 * gencode.c (build_mips16_operands): Correct computation of base
1692 address for extended PC relative instruction.
1693
1694Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1695
1696 * interp.c (mips16_entry): Add support for floating point cases.
1697 (SignalException): Pass floating point cases to mips16_entry.
1698 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1699 registers.
1700 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1701 or fmt_word.
1702 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1703 and then set the state to fmt_uninterpreted.
1704 (COP_SW): Temporarily set the state to fmt_word while calling
1705 ValueFPR.
1706
1707Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1708
1709 * gencode.c (build_instruction): The high order may be set in the
1710 comparison flags at any ISA level, not just ISA 4.
1711
1712Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1713
1714 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1715 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1716 * configure.in: sinclude ../common/aclocal.m4.
1717 * configure: Regenerated.
1718
1719Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1720
1721 * configure: Rebuild after change to aclocal.m4.
1722
1723Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1724
1725 * configure configure.in Makefile.in: Update to new configure
1726 scheme which is more compatible with WinGDB builds.
1727 * configure.in: Improve comment on how to run autoconf.
1728 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1729 * Makefile.in: Use autoconf substitution to install common
1730 makefile fragment.
1731
1732Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1733
1734 * gencode.c (build_instruction): Use BigEndianCPU instead of
1735 ByteSwapMem.
1736
1737Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1738
1739 * interp.c (sim_monitor): Make output to stdout visible in
1740 wingdb's I/O log window.
1741
1742Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1743
1744 * support.h: Undo previous change to SIGTRAP
1745 and SIGQUIT values.
1746
1747Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1748
1749 * interp.c (store_word, load_word): New static functions.
1750 (mips16_entry): New static function.
1751 (SignalException): Look for mips16 entry and exit instructions.
1752 (simulate): Use the correct index when setting fpr_state after
1753 doing a pending move.
1754
1755Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1756
1757 * interp.c: Fix byte-swapping code throughout to work on
1758 both little- and big-endian hosts.
1759
1760Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1761
1762 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1763 with gdb/config/i386/xm-windows.h.
1764
1765Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1766
1767 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1768 that messes up arithmetic shifts.
1769
1770Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1771
1772 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1773 SIGTRAP and SIGQUIT for _WIN32.
1774
1775Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1776
1777 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1778 force a 64 bit multiplication.
1779 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1780 destination register is 0, since that is the default mips16 nop
1781 instruction.
1782
1783Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1784
1785 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1786 (build_endian_shift): Don't check proc64.
1787 (build_instruction): Always set memval to uword64. Cast op2 to
1788 uword64 when shifting it left in memory instructions. Always use
1789 the same code for stores--don't special case proc64.
1790
1791 * gencode.c (build_mips16_operands): Fix base PC value for PC
1792 relative operands.
1793 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1794 jal instruction.
1795 * interp.c (simJALDELAYSLOT): Define.
1796 (JALDELAYSLOT): Define.
1797 (INDELAYSLOT, INJALDELAYSLOT): Define.
1798 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1799
1800Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1801
1802 * interp.c (sim_open): add flush_cache as a PMON routine
1803 (sim_monitor): handle flush_cache by ignoring it
1804
1805Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1806
1807 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1808 BigEndianMem.
1809 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1810 (BigEndianMem): Rename to ByteSwapMem and change sense.
1811 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1812 BigEndianMem references to !ByteSwapMem.
1813 (set_endianness): New function, with prototype.
1814 (sim_open): Call set_endianness.
1815 (sim_info): Use simBE instead of BigEndianMem.
1816 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1817 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1818 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1819 ifdefs, keeping the prototype declaration.
1820 (swap_word): Rewrite correctly.
1821 (ColdReset): Delete references to CONFIG. Delete endianness related
1822 code; moved to set_endianness.
1823
1824Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1825
1826 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1827 * interp.c (CHECKHILO): Define away.
1828 (simSIGINT): New macro.
1829 (membank_size): Increase from 1MB to 2MB.
1830 (control_c): New function.
1831 (sim_resume): Rename parameter signal to signal_number. Add local
1832 variable prev. Call signal before and after simulate.
1833 (sim_stop_reason): Add simSIGINT support.
1834 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1835 functions always.
1836 (sim_warning): Delete call to SignalException. Do call printf_filtered
1837 if logfh is NULL.
1838 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1839 a call to sim_warning.
1840
1841Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1842
1843 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1844 16 bit instructions.
1845
1846Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1847
1848 Add support for mips16 (16 bit MIPS implementation):
1849 * gencode.c (inst_type): Add mips16 instruction encoding types.
1850 (GETDATASIZEINSN): Define.
1851 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1852 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1853 mtlo.
1854 (MIPS16_DECODE): New table, for mips16 instructions.
1855 (bitmap_val): New static function.
1856 (struct mips16_op): Define.
1857 (mips16_op_table): New table, for mips16 operands.
1858 (build_mips16_operands): New static function.
1859 (process_instructions): If PC is odd, decode a mips16
1860 instruction. Break out instruction handling into new
1861 build_instruction function.
1862 (build_instruction): New static function, broken out of
1863 process_instructions. Check modifiers rather than flags for SHIFT
1864 bit count and m[ft]{hi,lo} direction.
1865 (usage): Pass program name to fprintf.
1866 (main): Remove unused variable this_option_optind. Change
1867 ``*loptarg++'' to ``loptarg++''.
1868 (my_strtoul): Parenthesize && within ||.
1869 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1870 (simulate): If PC is odd, fetch a 16 bit instruction, and
1871 increment PC by 2 rather than 4.
1872 * configure.in: Add case for mips16*-*-*.
1873 * configure: Rebuild.
1874
1875Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1876
1877 * interp.c: Allow -t to enable tracing in standalone simulator.
1878 Fix garbage output in trace file and error messages.
1879
1880Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1881
1882 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1883 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1884 * configure.in: Simplify using macros in ../common/aclocal.m4.
1885 * configure: Regenerated.
1886 * tconfig.in: New file.
1887
1888Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1889
1890 * interp.c: Fix bugs in 64-bit port.
1891 Use ansi function declarations for msvc compiler.
1892 Initialize and test file pointer in trace code.
1893 Prevent duplicate definition of LAST_EMED_REGNUM.
1894
1895Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1896
1897 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1898
1899Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1900
1901 * interp.c (SignalException): Check for explicit terminating
1902 breakpoint value.
1903 * gencode.c: Pass instruction value through SignalException()
1904 calls for Trap, Breakpoint and Syscall.
1905
1906Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1907
1908 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1909 only used on those hosts that provide it.
1910 * configure.in: Add sqrt() to list of functions to be checked for.
1911 * config.in: Re-generated.
1912 * configure: Re-generated.
1913
1914Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1915
1916 * gencode.c (process_instructions): Call build_endian_shift when
1917 expanding STORE RIGHT, to fix swr.
1918 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1919 clear the high bits.
1920 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1921 Fix float to int conversions to produce signed values.
1922
1923Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1924
1925 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1926 (process_instructions): Correct handling of nor instruction.
1927 Correct shift count for 32 bit shift instructions. Correct sign
1928 extension for arithmetic shifts to not shift the number of bits in
1929 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1930 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1931 Fix madd.
1932 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1933 It's OK to have a mult follow a mult. What's not OK is to have a
1934 mult follow an mfhi.
1935 (Convert): Comment out incorrect rounding code.
1936
1937Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1938
1939 * interp.c (sim_monitor): Improved monitor printf
1940 simulation. Tidied up simulator warnings, and added "--log" option
1941 for directing warning message output.
1942 * gencode.c: Use sim_warning() rather than WARNING macro.
1943
1944Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1945
1946 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1947 getopt1.o, rather than on gencode.c. Link objects together.
1948 Don't link against -liberty.
1949 (gencode.o, getopt.o, getopt1.o): New targets.
1950 * gencode.c: Include <ctype.h> and "ansidecl.h".
1951 (AND): Undefine after including "ansidecl.h".
1952 (ULONG_MAX): Define if not defined.
1953 (OP_*): Don't define macros; now defined in opcode/mips.h.
1954 (main): Call my_strtoul rather than strtoul.
1955 (my_strtoul): New static function.
1956
1957Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
1958
1959 * gencode.c (process_instructions): Generate word64 and uword64
1960 instead of `long long' and `unsigned long long' data types.
1961 * interp.c: #include sysdep.h to get signals, and define default
1962 for SIGBUS.
1963 * (Convert): Work around for Visual-C++ compiler bug with type
1964 conversion.
1965 * support.h: Make things compile under Visual-C++ by using
1966 __int64 instead of `long long'. Change many refs to long long
1967 into word64/uword64 typedefs.
1968
1969Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
1970
1971 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
1972 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
1973 (docdir): Removed.
1974 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
1975 (AC_PROG_INSTALL): Added.
1976 (AC_PROG_CC): Moved to before configure.host call.
1977 * configure: Rebuilt.
1978
1979Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
1980
1981 * configure.in: Define @SIMCONF@ depending on mips target.
1982 * configure: Rebuild.
1983 * Makefile.in (run): Add @SIMCONF@ to control simulator
1984 construction.
1985 * gencode.c: Change LOADDRMASK to 64bit memory model only.
1986 * interp.c: Remove some debugging, provide more detailed error
1987 messages, update memory accesses to use LOADDRMASK.
1988
1989Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
1990
1991 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
1992 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
1993 stamp-h.
1994 * configure: Rebuild.
1995 * config.in: New file, generated by autoheader.
1996 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
1997 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
1998 HAVE_ANINT and HAVE_AINT, as appropriate.
1999 * Makefile.in (run): Use @LIBS@ rather than -lm.
2000 (interp.o): Depend upon config.h.
2001 (Makefile): Just rebuild Makefile.
2002 (clean): Remove stamp-h.
2003 (mostlyclean): Make the same as clean, not as distclean.
2004 (config.h, stamp-h): New targets.
2005
2006Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2007
2008 * interp.c (ColdReset): Fix boolean test. Make all simulator
2009 globals static.
2010
2011Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2012
2013 * interp.c (xfer_direct_word, xfer_direct_long,
2014 swap_direct_word, swap_direct_long, xfer_big_word,
2015 xfer_big_long, xfer_little_word, xfer_little_long,
2016 swap_word,swap_long): Added.
2017 * interp.c (ColdReset): Provide function indirection to
2018 host<->simulated_target transfer routines.
2019 * interp.c (sim_store_register, sim_fetch_register): Updated to
2020 make use of indirected transfer routines.
2021
2022Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2023
2024 * gencode.c (process_instructions): Ensure FP ABS instruction
2025 recognised.
2026 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2027 system call support.
2028
2029Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2030
2031 * interp.c (sim_do_command): Complain if callback structure not
2032 initialised.
2033
2034Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2035
2036 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2037 support for Sun hosts.
2038 * Makefile.in (gencode): Ensure the host compiler and libraries
2039 used for cross-hosted build.
2040
2041Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2042
2043 * interp.c, gencode.c: Some more (TODO) tidying.
2044
2045Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2046
2047 * gencode.c, interp.c: Replaced explicit long long references with
2048 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2049 * support.h (SET64LO, SET64HI): Macros added.
2050
2051Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2052
2053 * configure: Regenerate with autoconf 2.7.
2054
2055Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2056
2057 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2058 * support.h: Remove superfluous "1" from #if.
2059 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2060
2061Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2062
2063 * interp.c (StoreFPR): Control UndefinedResult() call on
2064 WARN_RESULT manifest.
2065
2066Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2067
2068 * gencode.c: Tidied instruction decoding, and added FP instruction
2069 support.
2070
2071 * interp.c: Added dineroIII, and BSD profiling support. Also
2072 run-time FP handling.
2073
2074Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2075
2076 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2077 gencode.c, interp.c, support.h: created.
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