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* config/sh/tm-sh.h (BELIEVE_PCC_PROMOTION): Define, so that
[thirdparty/binutils-gdb.git] / sim / mn10300 / am33.igen
CommitLineData
9c55817e
JL		 1// Helper:
2//
3// Given an extended register number, translate it into an index into the
4// register array. This is necessary as the upper 8 extended registers are
5// actually synonyms for the d0-d3/a0-a3 registers.
6//
7//
8
9:function:::int:translate_rreg:int rreg
10{
11
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
18 else
19 return REG_E0 + rreg;
20}
21
6d254a2d
JL		 22:function:::int:translate_xreg:int xreg
23{
24 switch (xreg)
25 {
26 case 0:
27 return REG_SP;
28 case 1:
29 return REG_MDRQ;
30 case 2:
31 return REG_MCRH;
32 case 3:
33 return REG_MCRL;
34 case 4:
35 return REG_MCVF;
36 default:
37 abort ();
38 }
39}
40
0f7d7385
JL		 41// 1111 0000 0010 00An; mov USP,An
428.0xf0+4.0x2,00,2.AN0:D0m:::mov
43"mov"
44*am33
45{
46 PC = cia;
47 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
48}
49
50
51// 1111 0000 0010 01An; mov SSP,An
528.0xf0+4.0x2,01,2.AN0:D0n:::mov
53"mov"
54*am33
55{
56 PC = cia;
57 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
58}
59
60
61// 1111 0000 0010 10An; mov MSP,An
628.0xf0+4.0x2,10,2.AN0:D0o:::mov
63"mov"
64*am33
65{
66 PC = cia;
67 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
68}
69
70
71// 1111 0000 0010 11An; mov PC,An
728.0xf0+4.0x2,11,2.AN0:D0p:::mov
73"mov"
74*am33
75{
76 PC = cia;
77 State.regs[REG_A0 + AN0] = PC;
78}
79
80
81// 1111 0000 0011 Am00; mov Am,USP
828.0xf0+4.0x3,2.AM1,00:D0q:::mov
83"mov"
3e75ff7e 84*am33
0f7d7385
JL		 85{
86 PC = cia;
87 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
88}
89
90// 1111 0000 0011 Am01; mov Am,SSP
918.0xf0+4.0x3,2.AM1,01:D0r:::mov
92"mov"
3e75ff7e 93*am33
0f7d7385
JL		 94{
95 PC = cia;
96 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
97}
98
99// 1111 0000 0011 Am10; mov Am,MSP
1008.0xf0+4.0x3,2.AM1,10:D0s:::mov
101"mov"
3e75ff7e 102*am33
0f7d7385
JL		 103{
104 PC = cia;
105 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
106}
107
108
109// 1111 0000 1110 imm4; syscall
1108.0xf0+4.0xe,IMM4:D0t:::syscall
111"syscall"
112*am33
113{
114 unsigned int sp, next_pc;
115
116 PC = cia;
117 sp = State.regs[REG_SP];
118 next_pc = State.regs[REG_PC] + 2;
119 store_word (sp - 4, next_pc);
120 store_word (sp - 8, PSW);
121 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
122 nia = PC;
123}
124
125
126// 1111 0010 1110 11Dn; mov EPSW,Dn
1278.0xf2+4.0xe,11,2.DN0:D0u:::mov
128"mov"
129*am33
130{
131 PC = cia;
132 State.regs[REG_D0 + DN0] = PSW;
133}
134
135
136// 1111 0010 1111 Dm01; mov Dm,EPSW
1378.0xf2+4.0xf,2.DM1,01:D0v:::mov
138"mov"
139*am33
140{
141 PC = cia;
142 PSW = State.regs[REG_D0 + DM1];
143}
144
145// 1111 0101 00Am Rn; mov Am,Rn
1468.0xf5+00,2.AM1,4.RN0:D0w:::mov
147"mov"
148*am33
149{
9c55817e
JL		 150 int destreg = translate_rreg (SD_, RN0);
151
0f7d7385 152 PC = cia;
9c55817e 153 State.regs[destreg] = State.regs[REG_A0 + AM1];
0f7d7385
JL		 154}
155
156// 1111 0101 01Dm Rn; mov Dm,Rn
1578.0xf5+01,2.DM1,4.RN0:D0x:::mov
158"mov"
159*am33
160{
9c55817e
JL		 161 int destreg = translate_rreg (SD_, RN0);
162
0f7d7385 163 PC = cia;
9c55817e 164 State.regs[destreg] = State.regs[REG_D0 + DM1];
0f7d7385
JL		 165}
166
167// 1111 0101 10Rm An; mov Rm,An
1688.0xf5+10,4.RM1,2.AN0:D0y:::mov
169"mov"
170*am33
171{
9c55817e
JL		 172 int destreg = translate_rreg (SD_, RM1);
173
0f7d7385 174 PC = cia;
9c55817e 175 State.regs[REG_A0 + AN0] = State.regs[destreg];
0f7d7385
JL		 176}
177
178// 1111 0101 11Rm Dn; mov Rm,Dn
1798.0xf5+11,4.RM1,2.DN0:D0z:::mov
180"mov"
181*am33
182{
9c55817e
JL		 183 int destreg = translate_rreg (SD_, RM1);
184
0f7d7385 185 PC = cia;
9c55817e 186 State.regs[REG_D0 + DN0] = State.regs[destreg];
0f7d7385
JL		 187}
188
189
190// 1111 1000 1100 1110 regs....; movm (USP),regs
1918.0xf8+8.0xce+8.REGS:D1a:::movm
192"movm"
3e75ff7e 193*am33
0f7d7385
JL		 194{
195 unsigned long usp = State.regs[REG_USP];
196 unsigned long mask;
197
198 PC = cia;
199 mask = REGS;
200
201 if (mask & 0x8)
202 {
203 usp += 4;
204 State.regs[REG_LAR] = load_word (usp);
205 usp += 4;
206 State.regs[REG_LIR] = load_word (usp);
207 usp += 4;
208 State.regs[REG_MDR] = load_word (usp);
209 usp += 4;
210 State.regs[REG_A0 + 1] = load_word (usp);
211 usp += 4;
212 State.regs[REG_A0] = load_word (usp);
213 usp += 4;
214 State.regs[REG_D0 + 1] = load_word (usp);
215 usp += 4;
216 State.regs[REG_D0] = load_word (usp);
217 usp += 4;
218 }
219
220 if (mask & 0x10)
221 {
222 State.regs[REG_A0 + 3] = load_word (usp);
223 usp += 4;
224 }
225
226 if (mask & 0x20)
227 {
228 State.regs[REG_A0 + 2] = load_word (usp);
229 usp += 4;
230 }
231
232 if (mask & 0x40)
233 {
234 State.regs[REG_D0 + 3] = load_word (usp);
235 usp += 4;
236 }
237
238 if (mask & 0x80)
239 {
240 State.regs[REG_D0 + 2] = load_word (usp);
241 usp += 4;
242 }
243
244 /* start-sanitize-am33 */
245 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
246 {
247 if (mask & 0x1)
248 {
249 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
250 usp += 16;
251 State.regs[REG_E0 + 1] = load_word (usp);
252 usp += 4;
253 State.regs[REG_E0 + 0] = load_word (usp);
254 usp += 4;
255 }
256
257 if (mask & 0x2)
258 {
259 State.regs[REG_E0 + 7] = load_word (usp);
260 usp += 4;
261 State.regs[REG_E0 + 6] = load_word (usp);
262 usp += 4;
263 State.regs[REG_E0 + 5] = load_word (usp);
264 usp += 4;
265 State.regs[REG_E0 + 4] = load_word (usp);
266 usp += 4;
267 }
268
269 if (mask & 0x4)
270 {
271 State.regs[REG_E0 + 3] = load_word (usp);
272 usp += 4;
273 State.regs[REG_E0 + 2] = load_word (usp);
274 usp += 4;
275 }
276 }
277 /* end-sanitize-am33 */
278
279 /* And make sure to update the stack pointer. */
280 State.regs[REG_USP] = usp;
281}
282
283// 1111 1000 1100 1111 regs....; movm (USP),regs
2848.0xf8+8.0xcf+8.REGS:D1b:::movm
285"movm"
3e75ff7e 286*am33
0f7d7385
JL		 287{
288 unsigned long usp = State.regs[REG_USP];
289 unsigned long mask;
290
291 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
292 {
293 if (mask & 0x4)
294 {
295 usp -= 4;
296 store_word (usp, State.regs[REG_E0 + 2]);
297 usp -= 4;
298 store_word (usp, State.regs[REG_E0 + 3]);
299 }
300
301 if (mask & 0x2)
302 {
303 usp -= 4;
304 store_word (usp, State.regs[REG_E0 + 4]);
305 usp -= 4;
306 store_word (usp, State.regs[REG_E0 + 5]);
307 usp -= 4;
308 store_word (usp, State.regs[REG_E0 + 6]);
309 usp -= 4;
310 store_word (usp, State.regs[REG_E0 + 7]);
311 }
312
313 if (mask & 0x1)
314 {
315 usp -= 4;
316 store_word (usp, State.regs[REG_E0 + 0]);
317 usp -= 4;
318 store_word (usp, State.regs[REG_E0 + 1]);
319 usp -= 16;
320 /* Need to save MDQR, MCRH, MCRL, and MCVF */
321 }
322 }
323 /* end-sanitize-am33 */
324
325 if (mask & 0x80)
326 {
327 usp -= 4;
328 store_word (usp, State.regs[REG_D0 + 2]);
329 }
330
331 if (mask & 0x40)
332 {
333 usp -= 4;
334 store_word (usp, State.regs[REG_D0 + 3]);
335 }
336
337 if (mask & 0x20)
338 {
339 usp -= 4;
340 store_word (usp, State.regs[REG_A0 + 2]);
341 }
342
343 if (mask & 0x10)
344 {
345 usp -= 4;
346 store_word (usp, State.regs[REG_A0 + 3]);
347 }
348
349 if (mask & 0x8)
350 {
351 usp -= 4;
352 store_word (usp, State.regs[REG_D0]);
353 usp -= 4;
354 store_word (usp, State.regs[REG_D0 + 1]);
355 usp -= 4;
356 store_word (usp, State.regs[REG_A0]);
357 usp -= 4;
358 store_word (usp, State.regs[REG_A0 + 1]);
359 usp -= 4;
360 store_word (usp, State.regs[REG_MDR]);
361 usp -= 4;
362 store_word (usp, State.regs[REG_LIR]);
363 usp -= 4;
364 store_word (usp, State.regs[REG_LAR]);
365 usp -= 4;
366 }
367
368 /* And make sure to update the stack pointer. */
369 State.regs[REG_USP] = usp;
370}
371
372// 1111 1100 1111 1100 imm32...; and imm32,EPSW
3738.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
374"and"
375*am33
376{
377 PC = cia;
378 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
379}
380
381// 1111 1100 1111 1101 imm32...; or imm32,EPSW
3828.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
383"or"
384*am33
385{
386 PC = cia;
387 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
388}
389
390// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
3918.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
392"mov"
393*am33
394{
395 int srcreg, dstreg;
396
397 PC = cia;
398
9c55817e
JL		 399 srcreg = translate_rreg (SD_, RM2);
400 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 401 State.regs[dstreg] = State.regs[srcreg];
402}
403
404// 1111 1001 0001 1000 Rn Rn; ext Rn
4058.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
406"mov"
407*am33
408{
9c55817e 409 int srcreg;
0f7d7385
JL		 410
411 PC = cia;
9c55817e 412 srcreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 413 if (State.regs[srcreg] & 0x80000000)
414 State.regs[REG_MDR] = -1;
415 else
416 State.regs[REG_MDR] = 0;
417}
418
419// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
4208.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
421"extb"
422*am33
423{
424 int srcreg, dstreg;
425
426 PC = cia;
9c55817e
JL		 427 srcreg = translate_rreg (SD_, RM2);
428 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 429 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
430}
431
432// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
4338.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
434"extbu"
435*am33
436{
437 int srcreg, dstreg;
438
439 PC = cia;
9c55817e
JL		 440 srcreg = translate_rreg (SD_, RM2);
441 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 442 State.regs[dstreg] = State.regs[srcreg] & 0xff;
443}
444
445// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
4468.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
447"exth"
448*am33
449{
450 int srcreg, dstreg;
451
452 PC = cia;
9c55817e
JL		 453 srcreg = translate_rreg (SD_, RM2);
454 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 455 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
456}
457
458// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
4598.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
460"exthu"
461*am33
462{
463 int srcreg, dstreg;
464
465 PC = cia;
9c55817e
JL		 466 srcreg = translate_rreg (SD_, RM2);
467 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 468 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
469}
470
471// 1111 1001 0110 1000 Rn Rn; clr Rn
4728.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
473"clr"
474*am33
475{
9c55817e 476 int dstreg;
0f7d7385
JL		 477
478 PC = cia;
9c55817e 479 dstreg = translate_rreg (SD_, RN0);
0f7d7385 480 State.regs[dstreg] = 0;
0f7d7385
JL		 481 PSW |= PSW_Z;
482 PSW &= ~(PSW_V | PSW_C | PSW_N);
483}
484
485// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
4868.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
487"add"
488*am33
489{
490 int srcreg, dstreg;
491
492 PC = cia;
9c55817e
JL		 493 srcreg = translate_rreg (SD_, RM2);
494 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 495 genericAdd (State.regs[srcreg], dstreg);
496}
497
498// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
4998.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
500"addc"
501*am33
502{
503 int srcreg, dstreg;
504 int z, c, n, v;
505 unsigned long reg1, reg2, sum;
506
507 PC = cia;
9c55817e
JL		 508 srcreg = translate_rreg (SD_, RM2);
509 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 510
511 reg1 = State.regs[srcreg];
512 reg2 = State.regs[dstreg];
513 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
514 State.regs[dstreg] = sum;
515
4e86afb8 516 z = ((PSW & PSW_Z) != 0) && (sum == 0);
0f7d7385
JL		 517 n = (sum & 0x80000000);
518 c = (sum < reg1) || (sum < reg2);
519 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
520 && (reg2 & 0x80000000) != (sum & 0x80000000));
521
522 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
523 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
524 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
525}
526
527// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
5288.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
529"sub"
530*am33
531{
532 int srcreg, dstreg;
533
534 PC = cia;
9c55817e
JL		 535 srcreg = translate_rreg (SD_, RM2);
536 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 537 genericSub (State.regs[srcreg], dstreg);
538}
539
540// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
5418.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
542"subc"
543*am33
544{
545 int srcreg, dstreg;
546 int z, c, n, v;
547 unsigned long reg1, reg2, difference;
548
549 PC = cia;
9c55817e
JL		 550 srcreg = translate_rreg (SD_, RM2);
551 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 552
553 reg1 = State.regs[srcreg];
554 reg2 = State.regs[dstreg];
555 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
556 State.regs[dstreg] = difference;
557
4e86afb8 558 z = ((PSW & PSW_Z) != 0) && (difference == 0);
0f7d7385
JL		 559 n = (difference & 0x80000000);
560 c = (reg1 > reg2);
561 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
562 && (reg2 & 0x80000000) != (difference & 0x80000000));
563
564 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
565 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
566 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
567}
568
569// 1111 1001 1011 1000 Rn Rn; inc Rn
5708.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
571"inc"
572*am33
573{
574 int dstreg;
575
576 PC = cia;
9c55817e 577 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 578 genericAdd (1, dstreg);
579}
580
581// 1111 1001 1101 1000 Rn Rn; inc Rn
5828.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
583"inc4"
584*am33
585{
586 int dstreg;
587
588 PC = cia;
9c55817e 589 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 590 State.regs[dstreg] += 4;
591}
592
593// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
5948.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
595"cmp"
596*am33
597{
598 int srcreg1, srcreg2;
599
600 PC = cia;
9c55817e
JL		 601 srcreg1 = translate_rreg (SD_, RN0);
602 srcreg2 = translate_rreg (SD_, RM2);
0f7d7385
JL		 603 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
604}
605
606// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
6078.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
608"mov"
609*am33
610{
6d254a2d 611 int dstreg, srcreg;
0f7d7385
JL		 612
613 PC = cia;
9c55817e 614 dstreg = translate_rreg (SD_, RN0);
6d254a2d 615 srcreg = translate_xreg (SD_, XRM2);
0f7d7385 616
6d254a2d 617 State.regs[dstreg] = State.regs[srcreg];
0f7d7385
JL		 618}
619
620// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
6218.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
622"mov"
623*am33
624{
6d254a2d 625 int srcreg, dstreg;
0f7d7385
JL		 626
627 PC = cia;
9c55817e 628 srcreg = translate_rreg (SD_, RM2);
6d254a2d 629 dstreg = translate_xreg (SD_, XRN0);
0f7d7385 630
6d254a2d 631 State.regs[dstreg] = State.regs[srcreg];
0f7d7385
JL		 632}
633
634// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
6358.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
636"and"
637*am33
638{
639 int srcreg, dstreg;
640 int z, n;
641
642 PC = cia;
643
9c55817e
JL		 644 srcreg = translate_rreg (SD_, RM2);
645 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 646
647 State.regs[dstreg] &= State.regs[srcreg];
648 z = (State.regs[dstreg] == 0);
649 n = (State.regs[dstreg] & 0x80000000) != 0;
650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
651 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
652}
653
654// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
6558.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
656"or"
657*am33
658{
659 int srcreg, dstreg;
660 int z, n;
661
662 PC = cia;
9c55817e
JL		 663 srcreg = translate_rreg (SD_, RM2);
664 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 665
666 State.regs[dstreg] |= State.regs[srcreg];
667 z = (State.regs[dstreg] == 0);
668 n = (State.regs[dstreg] & 0x80000000) != 0;
669 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
670 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
671}
672
673// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
6748.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
675"xor"
676*am33
677{
678 int srcreg, dstreg;
679 int z, n;
680
681 PC = cia;
9c55817e
JL		 682 srcreg = translate_rreg (SD_, RM2);
683 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 684
685 State.regs[dstreg] ^= State.regs[srcreg];
686 z = (State.regs[dstreg] == 0);
687 n = (State.regs[dstreg] & 0x80000000) != 0;
688 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
689 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
690}
691
692// 1111 1001 0011 1001 Rn Rn; not Rn
6938.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
694"not"
695*am33
696{
697 int dstreg;
698 int z, n;
699
700 PC = cia;
9c55817e 701 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 702
703 State.regs[dstreg] = ~State.regs[dstreg];
704 z = (State.regs[dstreg] == 0);
705 n = (State.regs[dstreg] & 0x80000000) != 0;
706 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
707 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
708}
709
710// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
7118.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
712"asr"
713*am33
714{
715 int srcreg, dstreg;
716 long temp;
717 int c, z, n;
718
719 PC = cia;
9c55817e
JL		 720 srcreg = translate_rreg (SD_, RM2);
721 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 722
723 temp = State.regs[dstreg];
724 c = temp & 1;
725 temp >>= State.regs[srcreg];
726 State.regs[dstreg] = temp;
727 z = (State.regs[dstreg] == 0);
728 n = (State.regs[dstreg] & 0x80000000) != 0;
729 PSW &= ~(PSW_Z | PSW_N | PSW_C);
730 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
731}
732
733// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
7348.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
735"lsr"
736*am33
737{
738 int srcreg, dstreg;
739 int z, n, c;
740
741 PC = cia;
742
9c55817e
JL		 743 srcreg = translate_rreg (SD_, RM2);
744 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 745
746 c = State.regs[dstreg] & 1;
747 State.regs[dstreg] >>= State.regs[srcreg];
748 z = (State.regs[dstreg] == 0);
749 n = (State.regs[dstreg] & 0x80000000) != 0;
750 PSW &= ~(PSW_Z | PSW_N | PSW_C);
751 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
752}
753
754// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
7558.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
756"asl"
757*am33
758{
759 int srcreg, dstreg;
760 int z, n;
761
762 PC = cia;
9c55817e
JL		 763 srcreg = translate_rreg (SD_, RM2);
764 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 765
766 State.regs[dstreg] <<= State.regs[srcreg];
767 z = (State.regs[dstreg] == 0);
768 n = (State.regs[dstreg] & 0x80000000) != 0;
769 PSW &= ~(PSW_Z | PSW_N);
770 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
771}
772
773// 1111 1001 0111 1001 Rn Rn; asl2 Rn
7748.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
775"asl2"
776*am33
777{
778 int dstreg;
779 int n, z;
780
781 PC = cia;
9c55817e 782 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 783
784 State.regs[dstreg] <<= 2;
785 z = (State.regs[dstreg] == 0);
786 n = (State.regs[dstreg] & 0x80000000) != 0;
787 PSW &= ~(PSW_Z | PSW_N);
788 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
789}
790
791// 1111 1001 1000 1001 Rn Rn; ror Rn
7928.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
793"ror"
794*am33
795{
796 int dstreg;
797 int c, n, z;
798 unsigned long value;
799
800 PC = cia;
9c55817e 801 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 802
803 value = State.regs[dstreg];
804 c = (value & 0x1);
805
806 value >>= 1;
807 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
808 State.regs[dstreg] = value;
809 z = (value == 0);
810 n = (value & 0x80000000) != 0;
811 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
812 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
813}
814
815// 1111 1001 1001 1001 Rn Rn; rol Rn
8168.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
817"rol"
818*am33
819{
820 int dstreg;
821 int c, n, z;
822 unsigned long value;
823
824 PC = cia;
9c55817e 825 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 826
827 value = State.regs[dstreg];
828 c = (value & 0x80000000) ? 1 : 0;
829
830 value <<= 1;
831 value |= ((PSW & PSW_C) != 0);
832 State.regs[dstreg] = value;
833 z = (value == 0);
834 n = (value & 0x80000000) != 0;
835 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
836 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
837}
838
839// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
8408.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
841"mul"
842*am33
843{
844 int srcreg, dstreg;
845 unsigned long long temp;
846 int n, z;
847
848 PC = cia;
9c55817e
JL		 849 srcreg = translate_rreg (SD_, RM2);
850 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 851
852 temp = ((signed64)(signed32)State.regs[dstreg]
853 * (signed64)(signed32)State.regs[srcreg]);
854 State.regs[dstreg] = temp & 0xffffffff;
855 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
856 z = (State.regs[dstreg] == 0);
857 n = (State.regs[dstreg] & 0x80000000) != 0;
858 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
859 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
860}
861
862// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
8638.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
864"mulu"
865*am33
866{
867 int srcreg, dstreg;
868 unsigned long long temp;
869 int n, z;
870
871 PC = cia;
9c55817e
JL		 872 srcreg = translate_rreg (SD_, RM2);
873 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 874
875 temp = ((unsigned64)State.regs[dstreg]
876 * (unsigned64)State.regs[srcreg]);
877 State.regs[dstreg] = temp & 0xffffffff;
878 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
879 z = (State.regs[dstreg] == 0);
880 n = (State.regs[dstreg] & 0x80000000) != 0;
881 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
882 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
883}
884
885// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
8868.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
887"div"
888*am33
889{
890 int srcreg, dstreg;
377e53bb 891 long long temp;
0f7d7385
JL		 892 int n, z;
893
894 PC = cia;
9c55817e
JL		 895 srcreg = translate_rreg (SD_, RM2);
896 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 897
898 temp = State.regs[REG_MDR];
899 temp <<= 32;
900 temp |= State.regs[dstreg];
377e53bb 901 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
4e86afb8 902 temp /= (signed32)State.regs[srcreg];
0f7d7385
JL		 903 State.regs[dstreg] = temp & 0xffffffff;
904 z = (State.regs[dstreg] == 0);
905 n = (State.regs[dstreg] & 0x80000000) != 0;
906 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
907 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
908}
909
910// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
9118.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
912"divu"
913*am33
914{
915 int srcreg, dstreg;
916 unsigned long long temp;
917 int n, z;
918
919 PC = cia;
9c55817e
JL		 920 srcreg = translate_rreg (SD_, RM2);
921 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 922
923 temp = State.regs[REG_MDR];
924 temp <<= 32;
925 temp |= State.regs[dstreg];
926 State.regs[REG_MDR] = temp % State.regs[srcreg];
927 temp /= State.regs[srcreg];
928 State.regs[dstreg] = temp & 0xffffffff;
929 z = (State.regs[dstreg] == 0);
930 n = (State.regs[dstreg] & 0x80000000) != 0;
931 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
932 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
933}
934
935
936// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
3e75ff7e 9378.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
0f7d7385
JL		 938"mov"
939*am33
940{
941 int srcreg, dstreg;
942
943 PC = cia;
9c55817e
JL		 944 srcreg = translate_rreg (SD_, RM0);
945 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 946 State.regs[dstreg] = load_word (State.regs[srcreg]);
947}
948
949// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
9508.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
951"mov"
952*am33
953{
954 int srcreg, dstreg;
955
956 PC = cia;
9c55817e
JL		 957 srcreg = translate_rreg (SD_, RM2);
958 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 959 store_word (State.regs[dstreg], State.regs[srcreg]);
960}
961
962// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
3e75ff7e 9638.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
0f7d7385
JL		 964"movbu"
965*am33
966{
967 int srcreg, dstreg;
968
969 PC = cia;
9c55817e
JL		 970 srcreg = translate_rreg (SD_, RM0);
971 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 972 State.regs[dstreg] = load_byte (State.regs[srcreg]);
973}
974
975// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
9768.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
977"movbu"
978*am33
979{
980 int srcreg, dstreg;
981
982 PC = cia;
9c55817e
JL		 983 srcreg = translate_rreg (SD_, RM2);
984 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 985 store_byte (State.regs[dstreg], State.regs[srcreg]);
986}
987
988// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
3e75ff7e 9898.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
0f7d7385
JL		 990"movhu"
991*am33
992{
993 int srcreg, dstreg;
994
995 PC = cia;
9c55817e
JL		 996 srcreg = translate_rreg (SD_, RM0);
997 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 998 State.regs[dstreg] = load_half (State.regs[srcreg]);
999}
1000
1001// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
10028.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1003"movhu"
1004*am33
1005{
1006 int srcreg, dstreg;
1007
1008 PC = cia;
9c55817e
JL		 1009 srcreg = translate_rreg (SD_, RM2);
1010 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 1011 store_half (State.regs[dstreg], State.regs[srcreg]);
1012}
1013
377e53bb 1014// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
3e202231 10158.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
377e53bb
JL		 1016"mov"
1017*am33
1018{
1019 int srcreg, dstreg;
1020
1021 PC = cia;
9c55817e
JL		 1022 srcreg = translate_rreg (SD_, RM0);
1023 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1024 State.regs[dstreg] = load_word (State.regs[srcreg]);
1025 State.regs[srcreg] += 4;
1026}
1027
1028// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
3e202231 10298.0xf9+8.0x7a+4.RM2,4.RN0!RM2:D1z:::mov
377e53bb
JL		 1030"mov"
1031*am33
1032{
1033 int srcreg, dstreg;
1034
1035 PC = cia;
9c55817e
JL		 1036 srcreg = translate_rreg (SD_, RM2);
1037 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1038 store_word (State.regs[dstreg], State.regs[srcreg]);
1039 State.regs[dstreg] += 4;
1040}
0f7d7385
JL		 1041
1042// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
10438.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1044"mov"
1045*am33
1046{
9c55817e 1047 int dstreg;
0f7d7385
JL		 1048
1049 PC = cia;
9c55817e 1050 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1051 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1052}
1053
1054// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
10558.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1056"mov"
1057*am33
1058{
9c55817e 1059 int srcreg;
0f7d7385
JL		 1060
1061 PC = cia;
9c55817e
JL		 1062 srcreg = translate_rreg (SD_, RM2);
1063 store_word (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1064}
1065
1066// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
10678.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1068"movbu"
1069*am33
1070{
9c55817e 1071 int dstreg;
0f7d7385
JL		 1072
1073 PC = cia;
9c55817e 1074 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1075 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1076}
1077
1078// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
10798.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1080"movbu"
1081*am33
1082{
9c55817e 1083 int srcreg;
0f7d7385
JL		 1084
1085 PC = cia;
9c55817e
JL		 1086 srcreg = translate_rreg (SD_, RM2);
1087 store_byte (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1088}
1089
1090// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
10918.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1092"movhu"
1093*am33
1094{
9c55817e 1095 int dstreg;
0f7d7385
JL		 1096
1097 PC = cia;
9c55817e 1098 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1099 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1100}
1101
1102// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
11038.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1104"movhu"
1105*am33
1106{
9c55817e 1107 int srcreg;
0f7d7385
JL		 1108
1109 PC = cia;
9c55817e
JL		 1110 srcreg = translate_rreg (SD_, RM2);
1111 store_half (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1112}
1113
377e53bb 1114// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
3e202231 11158.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
377e53bb 1116"movhu"
0f7d7385
JL		 1117*am33
1118{
377e53bb 1119 int srcreg, dstreg;
0f7d7385
JL		 1120
1121 PC = cia;
9c55817e
JL		 1122 srcreg = translate_rreg (SD_, RM0);
1123 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1124 State.regs[dstreg] = load_half (State.regs[srcreg]);
1125 State.regs[srcreg] += 2;
0f7d7385
JL		 1126}
1127
377e53bb 1128// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
3e202231 11298.0xf9+8.0xfa+4.RM2,4.RN0!RM2:D1z:::movhu
377e53bb 1130"movhu"
0f7d7385
JL		 1131*am33
1132{
377e53bb 1133 int srcreg, dstreg;
0f7d7385
JL		 1134
1135 PC = cia;
9c55817e
JL		 1136 srcreg = translate_rreg (SD_, RM2);
1137 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1138 store_half (State.regs[dstreg], State.regs[srcreg]);
1139 State.regs[dstreg] += 2;
0f7d7385
JL		 1140}
1141
377e53bb
JL		 1142
1143// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
11448.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1145"mac"
0f7d7385
JL		 1146*am33
1147{
377e53bb
JL		 1148 int srcreg1, srcreg2;
1149 long long temp, sum;
1150 int c, v;
0f7d7385
JL		 1151
1152 PC = cia;
9c55817e
JL		 1153 srcreg1 = translate_rreg (SD_, RM2);
1154 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1155
4e86afb8
JL		 1156 temp = ((signed64)(signed32)State.regs[srcreg2]
1157 * (signed64)(signed32)State.regs[srcreg1]);
377e53bb
JL		 1158 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1159 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1160 State.regs[REG_MCRL] = sum;
1161 temp >>= 32;
1162 temp &= 0xffffffff;
1163 sum = State.regs[REG_MCRH] + temp + c;
1164 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1165 && (temp & 0x80000000) != (sum & 0x80000000));
1166 State.regs[REG_MCRH] = sum;
1167 if (v)
1168 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1169}
1170
377e53bb
JL		 1171// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
11728.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1173"macu"
0f7d7385
JL		 1174*am33
1175{
377e53bb
JL		 1176 int srcreg1, srcreg2;
1177 unsigned long long temp, sum;
1178 int c, v;
0f7d7385
JL		 1179
1180 PC = cia;
9c55817e
JL		 1181 srcreg1 = translate_rreg (SD_, RM2);
1182 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1183
377e53bb
JL		 1184 temp = ((unsigned64)State.regs[srcreg2]
1185 * (unsigned64)State.regs[srcreg1]);
1186 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1187 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1188 State.regs[REG_MCRL] = sum;
1189 temp >>= 32;
1190 temp &= 0xffffffff;
1191 sum = State.regs[REG_MCRH] + temp + c;
1192 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1193 && (temp & 0x80000000) != (sum & 0x80000000));
1194 State.regs[REG_MCRH] = sum;
1195 if (v)
1196 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1197}
1198
377e53bb
JL		 1199// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
12008.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1201"macb"
0f7d7385
JL		 1202*am33
1203{
377e53bb
JL		 1204 int srcreg1, srcreg2;
1205 long temp, sum;
1206 int v;
0f7d7385
JL		 1207
1208 PC = cia;
9c55817e
JL		 1209 srcreg1 = translate_rreg (SD_, RM2);
1210 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1211
4e86afb8
JL		 1212 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1213 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
377e53bb
JL		 1214 sum = State.regs[REG_MCRL] + temp;
1215 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1216 && (temp & 0x80000000) != (sum & 0x80000000));
1217 State.regs[REG_MCRL] = sum;
1218 if (v)
1219 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1220}
1221
377e53bb
JL		 1222// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
12238.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1224"macbu"
0f7d7385
JL		 1225*am33
1226{
377e53bb
JL		 1227 int srcreg1, srcreg2;
1228 long long temp, sum;
1229 int v;
0f7d7385
JL		 1230
1231 PC = cia;
9c55817e
JL		 1232 srcreg1 = translate_rreg (SD_, RM2);
1233 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1234
377e53bb
JL		 1235 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1236 * (unsigned32)(State.regs[srcreg1] & 0xff));
1237 sum = State.regs[REG_MCRL] + temp;
1238 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1239 && (temp & 0x80000000) != (sum & 0x80000000));
1240 State.regs[REG_MCRL] = sum;
1241 if (v)
1242 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1243}
1244
377e53bb
JL		 1245// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
12468.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1247"mach"
0f7d7385
JL		 1248*am33
1249{
377e53bb
JL		 1250 int srcreg1, srcreg2;
1251 long long temp, sum;
1252 int c, v;
0f7d7385
JL		 1253
1254 PC = cia;
9c55817e
JL		 1255 srcreg1 = translate_rreg (SD_, RM2);
1256 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1257
4e86afb8
JL		 1258 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1259 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
377e53bb
JL		 1260 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1261 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1262 State.regs[REG_MCRL] = sum;
1263 temp >>= 32;
1264 temp &= 0xffffffff;
1265 sum = State.regs[REG_MCRH] + temp + c;
1266 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1267 && (temp & 0x80000000) != (sum & 0x80000000));
1268 State.regs[REG_MCRH] = sum;
1269 if (v)
1270 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1271}
1272
377e53bb
JL		 1273// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
12748.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1275"machu"
0f7d7385
JL		 1276*am33
1277{
377e53bb
JL		 1278 int srcreg1, srcreg2;
1279 long long temp, sum;
1280 int c, v;
0f7d7385
JL		 1281
1282 PC = cia;
9c55817e
JL		 1283 srcreg1 = translate_rreg (SD_, RM2);
1284 srcreg2 = translate_rreg (SD_, RN0);
377e53bb
JL		 1285
1286 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1287 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1288 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1289 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1290 State.regs[REG_MCRL] = sum;
1291 temp >>= 32;
1292 temp &= 0xffffffff;
1293 sum = State.regs[REG_MCRH] + temp + c;
1294 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1295 && (temp & 0x80000000) != (sum & 0x80000000));
1296 State.regs[REG_MCRH] = sum;
1297 if (v)
1298 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1299}
1300
377e53bb
JL		 1301// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
13028.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1303"dmach"
0f7d7385
JL		 1304*am33
1305{
377e53bb
JL		 1306 int srcreg1, srcreg2;
1307 long temp, temp2, sum;
1308 int v;
0f7d7385
JL		 1309
1310 PC = cia;
9c55817e
JL		 1311 srcreg1 = translate_rreg (SD_, RM2);
1312 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1313
4e86afb8
JL		 1314 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1315 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1316 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1317 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
377e53bb
JL		 1318 sum = temp + temp2 + State.regs[REG_MCRL];
1319 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1320 && (temp & 0x80000000) != (sum & 0x80000000));
1321 State.regs[REG_MCRL] = sum;
1322 if (v)
1323 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1324}
1325
377e53bb
JL		 1326// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
13278.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1328"dmachu"
0f7d7385
JL		 1329*am33
1330{
377e53bb
JL		 1331 int srcreg1, srcreg2;
1332 unsigned long temp, temp2, sum;
1333 int v;
0f7d7385
JL		 1334
1335 PC = cia;
9c55817e
JL		 1336 srcreg1 = translate_rreg (SD_, RM2);
1337 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1338
377e53bb
JL		 1339 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1340 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1341 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1342 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1343 sum = temp + temp2 + State.regs[REG_MCRL];
1344 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1345 && (temp & 0x80000000) != (sum & 0x80000000));
1346 State.regs[REG_MCRL] = sum;
1347 if (v)
1348 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1349}
1350
377e53bb
JL		 1351// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
13528.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1353"dmulh"
0f7d7385
JL		 1354*am33
1355{
377e53bb
JL		 1356 int srcreg, dstreg;
1357 long temp;
0f7d7385
JL		 1358
1359 PC = cia;
9c55817e
JL		 1360 srcreg = translate_rreg (SD_, RM2);
1361 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1362
4e86afb8
JL		 1363 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1364 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
377e53bb 1365 State.regs[REG_MDRQ] = temp;
4e86afb8
JL		 1366 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1367 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
377e53bb 1368 State.regs[dstreg] = temp;
0f7d7385
JL		 1369}
1370
377e53bb
JL		 1371// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
13728.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1373"dmachu"
0f7d7385
JL		 1374*am33
1375{
377e53bb
JL		 1376 int srcreg, dstreg;
1377 unsigned long temp;
0f7d7385
JL		 1378
1379 PC = cia;
9c55817e
JL		 1380 srcreg = translate_rreg (SD_, RM2);
1381 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1382
377e53bb
JL		 1383 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1384 * (unsigned32)(State.regs[srcreg] & 0xffff));
1385 State.regs[REG_MDRQ] = temp;
1386 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1387 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
0f7d7385 1388 State.regs[dstreg] = temp;
0f7d7385
JL		 1389}
1390
377e53bb
JL		 1391// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
13928.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1393"sat16"
0f7d7385
JL		 1394*am33
1395{
377e53bb 1396 int srcreg, dstreg;
4e86afb8 1397 int value, z, n;
0f7d7385
JL		 1398
1399 PC = cia;
9c55817e
JL		 1400 srcreg = translate_rreg (SD_, RM2);
1401 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1402
377e53bb
JL		 1403 value = State.regs[srcreg];
1404
1405 if (value >= 0x7fff)
1406 State.regs[dstreg] = 0x7fff;
1407 else if (value <= 0xffff8000)
1408 State.regs[dstreg] = 0xffff8000;
1409 else
1410 State.regs[dstreg] = value;
4e86afb8
JL		 1411
1412 n = (State.regs[dstreg] & 0x8000) != 0;
1413 z = (State.regs[dstreg] == 0);
1414 PSW &= ~(PSW_Z | PSW_N);
1415 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1416}
1417
1f0ba346
JL		 1418// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
14198.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1420"mcste"
1421*am33
1422{
1423 int srcreg, dstreg;
1424
1425 PC = cia;
1426 srcreg = translate_rreg (SD_, RM2);
1427 dstreg = translate_rreg (SD_, RN0);
1428
1429 PSW &= ~(PSW_V | PSW_C);
1430 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1431
1432 /* 32bit saturation. */
1433 if (State.regs[srcreg] == 0x20)
1434 {
1435 long long tmp;
1436
1437 tmp = State.regs[REG_MCRH];
1438 tmp <<= 32;
1439 tmp += State.regs[REG_MCRL];
1440
1441 if (tmp > 0x7fffffff)
1442 State.regs[dstreg] = 0x7fffffff;
1443 else if (tmp < 0xffffffff80000000LL)
1444 State.regs[dstreg] = 0x80000000;
1445 else
1446 State.regs[dstreg] = tmp;
1447 }
1448 /* 16bit saturation */
1449 else if (State.regs[srcreg] == 0x10)
1450 {
1451 long long tmp;
1452
1453 tmp = State.regs[REG_MCRH];
1454 tmp <<= 32;
1455 tmp += State.regs[REG_MCRL];
1456
1457 if (tmp > 0x7fff)
1458 State.regs[dstreg] = 0x7fff;
1459 else if (tmp < 0xffffffffffff8000LL)
1460 State.regs[dstreg] = 0x8000;
1461 else
1462 State.regs[dstreg] = tmp;
1463 }
1464 /* 8 bit saturation */
1465 else if (State.regs[srcreg] == 0x8)
1466 {
1467 long long tmp;
1468
1469 tmp = State.regs[REG_MCRH];
1470 tmp <<= 32;
1471 tmp += State.regs[REG_MCRL];
1472
1473 if (tmp > 0x7f)
1474 State.regs[dstreg] = 0x7f;
1475 else if (tmp < 0xffffffffffffff80LL)
1476 State.regs[dstreg] = 0x80;
1477 else
1478 State.regs[dstreg] = tmp;
1479 }
1480 /* 9 bit saturation */
1481 else if (State.regs[srcreg] == 0x9)
1482 {
1483 long long tmp;
1484
1485 tmp = State.regs[REG_MCRH];
1486 tmp <<= 32;
1487 tmp += State.regs[REG_MCRL];
1488
1489 if (tmp > 0x80)
1490 State.regs[dstreg] = 0x80;
1491 else if (tmp < 0xffffffffffffff81LL)
1492 State.regs[dstreg] = 0x81;
1493 else
1494 State.regs[dstreg] = tmp;
1495 }
1496 /* 9 bit saturation */
1497 else if (State.regs[srcreg] == 0x30)
1498 {
1499 long long tmp;
1500
1501 tmp = State.regs[REG_MCRH];
1502 tmp <<= 32;
1503 tmp += State.regs[REG_MCRL];
1504
1505 if (tmp > 0x7fffffffffffLL)
1506 tmp = 0x7fffffffffffLL;
1507 else if (tmp < 0xffff800000000000LL)
1508 tmp = 0xffff800000000000LL;
1509
1510 tmp >>= 16;
1511 State.regs[dstreg] = tmp;
1512 }
1513}
377e53bb
JL		 1514
1515// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
15168.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1517"swap"
0f7d7385
JL		 1518*am33
1519{
1520 int srcreg, dstreg;
0f7d7385 1521
9c55817e
JL		 1522 PC = cia;
1523 srcreg = translate_rreg (SD_, RM2);
1524 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1525
377e53bb
JL		 1526 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1527 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1528 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1529 | ((State.regs[srcreg] >> 24) & 0xff));
0f7d7385
JL		 1530}
1531
377e53bb
JL		 1532// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
15338.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1534"swaph"
0f7d7385
JL		 1535*am33
1536{
377e53bb 1537 int srcreg, dstreg;
0f7d7385 1538
9c55817e
JL		 1539 PC = cia;
1540 srcreg = translate_rreg (SD_, RM2);
1541 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1542
377e53bb
JL		 1543 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1544 | ((State.regs[srcreg] >> 8) & 0xff)
1545 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1546 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
0f7d7385
JL		 1547}
1548
377e53bb
JL		 1549// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
15508.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1551"swhw"
0f7d7385
JL		 1552*am33
1553{
377e53bb 1554 int srcreg, dstreg;
0f7d7385 1555
9c55817e
JL		 1556 PC = cia;
1557 srcreg = translate_rreg (SD_, RM2);
1558 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1559
377e53bb
JL		 1560 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1561 | ((State.regs[srcreg] >> 16) & 0xffff));
0f7d7385
JL		 1562}
1563
377e53bb
JL		 1564// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
15658.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1566"bsch"
3e75ff7e
JL		 1567*am33
1568{
377e53bb
JL		 1569 int temp, c, i;
1570 int srcreg, dstreg;
1571 int start;
3e75ff7e
JL		 1572
1573 PC = cia;
9c55817e
JL		 1574 srcreg = translate_rreg (SD_, RM2);
1575 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1576
1577 temp = State.regs[srcreg];
1578 start = (State.regs[dstreg] & 0x1f) - 1;
1579 if (start == -1)
1580 start = 31;
1581
1582 for (i = start; i >= 0; i--)
1583 {
1584 if (temp & (1 << i))
1585 {
1586 c = 1;
1587 State.regs[dstreg] = i;
1588 break;
1589 }
1590 }
3e75ff7e 1591
377e53bb
JL		 1592 if (i < 0)
1593 {
1594 c = 0;
1595 State.regs[dstreg] = 0;
1596 }
1597 PSW &= ~(PSW_C);
1598 PSW |= (c ? PSW_C : 0);
3e75ff7e
JL		 1599}
1600
0f7d7385 1601
377e53bb
JL		 1602// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
16038.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
0f7d7385 1604"mov"
3e75ff7e 1605*am33
0f7d7385 1606{
377e53bb 1607 int dstreg;
0f7d7385
JL		 1608
1609 PC = cia;
9c55817e 1610 dstreg = translate_rreg (SD_, RN0);
377e53bb 1611 State.regs[dstreg] = EXTEND8 (IMM8);
0f7d7385
JL		 1612}
1613
377e53bb
JL		 1614// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
16158.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1616"movu"
1617*am33
0f7d7385 1618{
377e53bb 1619 int dstreg;
0f7d7385
JL		 1620
1621 PC = cia;
9c55817e 1622 dstreg = translate_rreg (SD_, RN0);
377e53bb 1623 State.regs[dstreg] = IMM8 & 0xff;
0f7d7385
JL		 1624}
1625
377e53bb
JL		 1626// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
16278.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1628"add"
1629*am33
0f7d7385 1630{
377e53bb 1631 int dstreg;
0f7d7385
JL		 1632
1633 PC = cia;
9c55817e 1634 dstreg = translate_rreg (SD_, RN0);
377e53bb 1635 genericAdd (EXTEND8 (IMM8), dstreg);
0f7d7385
JL		 1636}
1637
377e53bb
JL		 1638// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
16398.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1640"addc"
1641*am33
0f7d7385 1642{
377e53bb
JL		 1643 int dstreg, imm;
1644 int z, c, n, v;
1645 unsigned long reg1, reg2, sum;
0f7d7385
JL		 1646
1647 PC = cia;
9c55817e 1648 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1649
377e53bb
JL		 1650 imm = EXTEND8 (IMM8);
1651 reg2 = State.regs[dstreg];
1652 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1653 State.regs[dstreg] = sum;
1654
080ee2ba 1655 z = ((PSW & PSW_Z) != 0) && (sum == 0);
377e53bb
JL		 1656 n = (sum & 0x80000000);
1657 c = (sum < imm) || (sum < reg2);
1658 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1659 && (reg2 & 0x80000000) != (sum & 0x80000000));
1660
1661 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1662 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1663 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
0f7d7385
JL		 1664}
1665
377e53bb
JL		 1666// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
16678.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1668"sub"
1669*am33
0f7d7385 1670{
377e53bb 1671 int dstreg;
0f7d7385
JL		 1672
1673 PC = cia;
9c55817e 1674 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1675
377e53bb 1676 genericSub (EXTEND8 (IMM8), dstreg);
0f7d7385
JL		 1677}
1678
377e53bb
JL		 1679// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
16808.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1681"subc"
1682*am33
0f7d7385 1683{
377e53bb
JL		 1684 int imm, dstreg;
1685 int z, c, n, v;
1686 unsigned long reg1, reg2, difference;
0f7d7385
JL		 1687
1688 PC = cia;
9c55817e 1689 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1690
377e53bb
JL		 1691 imm = EXTEND8 (IMM8);
1692 reg2 = State.regs[dstreg];
1693 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1694 State.regs[dstreg] = difference;
0f7d7385 1695
080ee2ba 1696 z = ((PSW & PSW_Z) != 0) && (difference == 0);
377e53bb
JL		 1697 n = (difference & 0x80000000);
1698 c = (imm > reg2);
1699 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1700 && (reg2 & 0x80000000) != (difference & 0x80000000));
0f7d7385 1701
377e53bb
JL		 1702 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1703 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1704 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1705}
1706
1707// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
17088.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1709"cmp"
1710*am33
0f7d7385 1711{
377e53bb 1712 int srcreg;
0f7d7385
JL		 1713
1714 PC = cia;
9c55817e 1715 srcreg = translate_rreg (SD_, RN0);
377e53bb 1716 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
0f7d7385
JL		 1717}
1718
377e53bb
JL		 1719// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
17208.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
0f7d7385 1721"mov"
377e53bb 1722*am33
0f7d7385 1723{
377e53bb 1724 int dstreg;
0f7d7385
JL		 1725
1726 PC = cia;
6d254a2d 1727 dstreg = translate_xreg (SD_, XRN0);
0f7d7385 1728
6d254a2d 1729 State.regs[dstreg] = IMM8;
0f7d7385
JL		 1730}
1731
377e53bb
JL		 1732// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
17338.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1734"and"
1735*am33
0f7d7385
JL		 1736{
1737 int dstreg;
377e53bb 1738 int z, n;
0f7d7385
JL		 1739
1740 PC = cia;
9c55817e 1741 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1742
377e53bb
JL		 1743 State.regs[dstreg] &= (IMM8 & 0xff);
1744 z = (State.regs[dstreg] == 0);
1745 n = (State.regs[dstreg] & 0x80000000) != 0;
1746 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1747 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1748}
1749
377e53bb
JL		 1750// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
17518.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1752"or"
1753*am33
0f7d7385 1754{
377e53bb
JL		 1755 int dstreg;
1756 int z, n;
0f7d7385
JL		 1757
1758 PC = cia;
9c55817e 1759 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1760
377e53bb
JL		 1761 State.regs[dstreg] |= (IMM8 & 0xff);
1762 z = (State.regs[dstreg] == 0);
1763 n = (State.regs[dstreg] & 0x80000000) != 0;
1764 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1765 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1766}
1767
377e53bb
JL		 1768// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
17698.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1770"xor"
1771*am33
0f7d7385
JL		 1772{
1773 int dstreg;
377e53bb 1774 int z, n;
0f7d7385
JL		 1775
1776 PC = cia;
9c55817e 1777 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1778
377e53bb
JL		 1779 State.regs[dstreg] ^= (IMM8 & 0xff);
1780 z = (State.regs[dstreg] == 0);
1781 n = (State.regs[dstreg] & 0x80000000) != 0;
1782 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1783 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1784}
1785
377e53bb
JL		 1786// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
17878.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1788"asr"
1789*am33
0f7d7385 1790{
377e53bb
JL		 1791 int dstreg;
1792 long temp;
1793 int c, z, n;
0f7d7385
JL		 1794
1795 PC = cia;
9c55817e 1796 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1797
377e53bb
JL		 1798 temp = State.regs[dstreg];
1799 c = temp & 1;
1800 temp >>= (IMM8 & 0xff);
1801 State.regs[dstreg] = temp;
1802 z = (State.regs[dstreg] == 0);
1803 n = (State.regs[dstreg] & 0x80000000) != 0;
1804 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1805 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
0f7d7385
JL		 1806}
1807
377e53bb
JL		 1808// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
18098.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1810"lsr"
1811*am33
1812{
1813 int dstreg;
1814 int z, n, c;
1815
1816 PC = cia;
9c55817e 1817 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1818
1819 c = State.regs[dstreg] & 1;
1820 State.regs[dstreg] >>= (IMM8 & 0xff);
1821 z = (State.regs[dstreg] == 0);
1822 n = (State.regs[dstreg] & 0x80000000) != 0;
1823 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1824 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1825}
1826
1827// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
18288.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1829"asl"
1830*am33
1831{
1832 int srcreg, dstreg;
1833 int z, n;
1834
1835 PC = cia;
9c55817e 1836 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1837
1838 State.regs[dstreg] <<= (IMM8 & 0xff);
1839 z = (State.regs[dstreg] == 0);
1840 n = (State.regs[dstreg] & 0x80000000) != 0;
1841 PSW &= ~(PSW_Z | PSW_N);
1842 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1843}
1844
1845// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
18468.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1847"mul"
1848*am33
1849{
1850 int dstreg;
1851 unsigned long long temp;
1852 int z, n;
1853
1854 PC = cia;
9c55817e 1855 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1856
1857 temp = ((signed64)(signed32)State.regs[dstreg]
1858 * (signed64)(signed32)EXTEND8 (IMM8));
1859 State.regs[dstreg] = temp & 0xffffffff;
1860 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1861 z = (State.regs[dstreg] == 0);
1862 n = (State.regs[dstreg] & 0x80000000) != 0;
1863 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1864 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1865}
1866
1867// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
18688.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1869"mulu"
1870*am33
1871{
1872 int dstreg;
1873 unsigned long long temp;
1874 int z, n;
1875
1876 PC = cia;
9c55817e 1877 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1878
1879 temp = ((unsigned64)State.regs[dstreg]
1880 * (unsigned64)(IMM8 & 0xff));
1881 State.regs[dstreg] = temp & 0xffffffff;
1882 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1883 z = (State.regs[dstreg] == 0);
1884 n = (State.regs[dstreg] & 0x80000000) != 0;
1885 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1886 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1887}
1888
1889// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
18908.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1891"btst"
1892*am33
1893{
1894 int srcreg;
1895
1896 PC = cia;
9c55817e 1897 srcreg = translate_rreg (SD_, RM0);
377e53bb 1898 genericBtst(IMM8, State.regs[srcreg]);
377e53bb
JL		 1899}
1900
377e53bb
JL		 1901// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
19028.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1903"mov"
1904*am33
1905{
1906 int srcreg, dstreg;
1907
1908 PC = cia;
9c55817e
JL		 1909 srcreg = translate_rreg (SD_, RM0);
1910 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1911 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1912}
1913
1914// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
19158.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1916"mov"
1917{
1918 int srcreg, dstreg;
1919
1920 PC = cia;
9c55817e
JL		 1921 srcreg = translate_rreg (SD_, RM2);
1922 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1923 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1924}
1925
1926// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
19278.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1928"movbu"
1929{
1930 int srcreg, dstreg;
1931
1932 PC = cia;
9c55817e
JL		 1933 srcreg = translate_rreg (SD_, RM0);
1934 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1935 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1936}
1937
1938// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
19398.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1940"movbu"
1941{
1942 int srcreg, dstreg;
1943
1944 PC = cia;
9c55817e
JL		 1945 srcreg = translate_rreg (SD_, RM2);
1946 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1947 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1948}
1949
1950// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
19518.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1952"movhu"
1953{
1954 int srcreg, dstreg;
1955
1956 PC = cia;
9c55817e
JL		 1957 srcreg = translate_rreg (SD_, RM0);
1958 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1959 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1960}
1961
1962// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
19638.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1964"movhu"
1965{
1966 int srcreg, dstreg;
1967
1968 PC = cia;
9c55817e
JL		 1969 srcreg = translate_rreg (SD_, RM2);
1970 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1971 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1972}
1973
1974// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
3e202231 19758.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
377e53bb
JL		 1976"mov"
1977*am33
1978{
1979 int srcreg, dstreg;
1980
1981 PC = cia;
9c55817e
JL		 1982 srcreg = translate_rreg (SD_, RM0);
1983 dstreg = translate_rreg (SD_, RN2);
6ae1456e
JL		 1984 State.regs[dstreg] = load_word (State.regs[srcreg]);
1985 State.regs[srcreg] += EXTEND8 (IMM8);
377e53bb
JL		 1986}
1987
1988// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
3e202231 19898.0xfb+8.0x7a+4.RM2,4.RN0!RM2+8.IMM8:D2z:::mov
377e53bb
JL		 1990"mov"
1991{
1992 int srcreg, dstreg;
1993
1994 PC = cia;
9c55817e
JL		 1995 srcreg = translate_rreg (SD_, RM2);
1996 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 1997 store_word (State.regs[dstreg], State.regs[srcreg]);
1998 State.regs[dstreg] += EXTEND8 (IMM8);
377e53bb
JL		 1999}
2000
2001
2002// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
20038.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2004"mov"
2005{
2006 int dstreg;
2007
2008 PC = cia;
9c55817e 2009 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2010 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2011}
2012
2013// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
20148.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2015"mov"
2016{
2017 int srcreg;
2018
2019 PC = cia;
9c55817e 2020 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2021 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2022}
2023
2024// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
20258.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2026"movbu"
2027{
2028 int dstreg;
2029
2030 PC = cia;
9c55817e 2031 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2032 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2033}
2034
2035// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
20368.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2037"movbu"
2038{
2039 int srcreg;
2040
2041 PC = cia;
9c55817e 2042 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2043 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2044}
2045
2046// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
20478.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2048"movhu"
2049{
2050 int dstreg;
2051
2052 PC = cia;
9c55817e 2053 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2054 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2055}
2056
2057// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
20588.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2059"movhu"
2060{
2061 int srcreg;
2062
2063 PC = cia;
9c55817e 2064 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2065 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2066}
2067
2068// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
3e202231 20698.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
377e53bb
JL		 2070"movhu"
2071*am33
2072{
2073 int srcreg, dstreg;
2074
2075 PC = cia;
9c55817e
JL		 2076 srcreg = translate_rreg (SD_, RM0);
2077 dstreg = translate_rreg (SD_, RN2);
6ae1456e
JL		 2078 State.regs[dstreg] = load_half (State.regs[srcreg]);
2079 State.regs[srcreg] += EXTEND8 (IMM8);
377e53bb
JL		 2080}
2081
2082// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
3e202231 20838.0xfb+8.0xfa+4.RM2,4.RN0!RM2+8.IMM8:D2z:::movhu
377e53bb
JL		 2084"movhu"
2085{
2086 int srcreg, dstreg;
2087
2088 PC = cia;
9c55817e
JL		 2089 srcreg = translate_rreg (SD_, RM2);
2090 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 2091 store_half (State.regs[dstreg], State.regs[srcreg]);
2092 State.regs[dstreg] += EXTEND8 (IMM8);
377e53bb
JL		 2093}
2094
2095
2096// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
20978.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2098"mac"
2099{
9c55817e 2100 int srcreg;
377e53bb
JL		 2101 long long temp, sum;
2102 int c, v;
2103
2104 PC = cia;
9c55817e 2105 srcreg = translate_rreg (SD_, RN2);
377e53bb 2106
080ee2ba
JL		 2107 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2108 * (signed64)(signed32)State.regs[srcreg]);
377e53bb
JL		 2109 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2110 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2111 State.regs[REG_MCRL] = sum;
2112 temp >>= 32;
2113 temp &= 0xffffffff;
2114 sum = State.regs[REG_MCRH] + temp + c;
2115 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2116 && (temp & 0x80000000) != (sum & 0x80000000));
2117 State.regs[REG_MCRH] = sum;
2118 if (v)
2119 State.regs[REG_MCVF] = 1;
2120}
2121
2122// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
21238.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2124"macu"
2125{
9c55817e 2126 int srcreg;
377e53bb
JL		 2127 long long temp, sum;
2128 int c, v;
2129
2130 PC = cia;
9c55817e 2131 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2132
2133 temp = ((unsigned64) (IMM8)
9c55817e 2134 * (unsigned64)State.regs[srcreg]);
377e53bb
JL		 2135 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2136 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2137 State.regs[REG_MCRL] = sum;
2138 temp >>= 32;
2139 temp &= 0xffffffff;
2140 sum = State.regs[REG_MCRH] + temp + c;
2141 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2142 && (temp & 0x80000000) != (sum & 0x80000000));
2143 State.regs[REG_MCRH] = sum;
2144 if (v)
2145 State.regs[REG_MCVF] = 1;
2146}
2147
2148// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
21498.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2150"macb"
2151{
9c55817e 2152 int srcreg;
377e53bb
JL		 2153 long long temp, sum;
2154 int c, v;
2155
2156 PC = cia;
9c55817e 2157 srcreg = translate_rreg (SD_, RN2);
377e53bb 2158
080ee2ba
JL		 2159 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2160 * (signed64)(signed8)State.regs[srcreg] & 0xff);
377e53bb
JL		 2161 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2162 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2163 State.regs[REG_MCRL] = sum;
2164 temp >>= 32;
2165 temp &= 0xffffffff;
2166 sum = State.regs[REG_MCRH] + temp + c;
2167 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2168 && (temp & 0x80000000) != (sum & 0x80000000));
2169 State.regs[REG_MCRH] = sum;
2170 if (v)
2171 State.regs[REG_MCVF] = 1;
2172}
2173
2174// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
21758.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2176"macbu"
2177{
9c55817e 2178 int srcreg;
377e53bb
JL		 2179 long long temp, sum;
2180 int c, v;
2181
2182 PC = cia;
9c55817e 2183 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2184
2185 temp = ((unsigned64) (IMM8)
9c55817e 2186 * (unsigned64)State.regs[srcreg] & 0xff);
377e53bb
JL		 2187 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2188 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2189 State.regs[REG_MCRL] = sum;
2190 temp >>= 32;
2191 temp &= 0xffffffff;
2192 sum = State.regs[REG_MCRH] + temp + c;
2193 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2194 && (temp & 0x80000000) != (sum & 0x80000000));
2195 State.regs[REG_MCRH] = sum;
2196 if (v)
2197 State.regs[REG_MCVF] = 1;
2198}
2199
2200// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
22018.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2202"mach"
2203{
9c55817e 2204 int srcreg;
377e53bb
JL		 2205 long long temp, sum;
2206 int c, v;
2207
2208 PC = cia;
9c55817e 2209 srcreg = translate_rreg (SD_, RN2);
377e53bb 2210
080ee2ba
JL		 2211 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2212 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
377e53bb
JL		 2213 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2214 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2215 State.regs[REG_MCRL] = sum;
2216 temp >>= 32;
2217 temp &= 0xffffffff;
2218 sum = State.regs[REG_MCRH] + temp + c;
2219 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2220 && (temp & 0x80000000) != (sum & 0x80000000));
2221 State.regs[REG_MCRH] = sum;
2222 if (v)
2223 State.regs[REG_MCVF] = 1;
2224}
2225
2226// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
22278.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2228"machu"
2229{
9c55817e 2230 int srcreg;
377e53bb
JL		 2231 long long temp, sum;
2232 int c, v;
2233
2234 PC = cia;
9c55817e 2235 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2236
2237 temp = ((unsigned64) (IMM8)
9c55817e 2238 * (unsigned64)State.regs[srcreg] & 0xffff);
377e53bb
JL		 2239 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2240 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2241 State.regs[REG_MCRL] = sum;
2242 temp >>= 32;
2243 temp &= 0xffffffff;
2244 sum = State.regs[REG_MCRH] + temp + c;
2245 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2246 && (temp & 0x80000000) != (sum & 0x80000000));
2247 State.regs[REG_MCRH] = sum;
2248 if (v)
2249 State.regs[REG_MCVF] = 1;
2250}
2251
1f0ba346
JL		 2252// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
22538.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2254"mcste"
2255{
2256 int dstreg;
2257
2258 PC = cia;
2259 dstreg = translate_rreg (SD_, RN0);
2260
2261 PSW &= ~(PSW_V | PSW_C);
2262 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2263
2264 /* 32bit saturation. */
2265 if (IMM8 == 0x20)
2266 {
2267 long long tmp;
2268
2269 tmp = State.regs[REG_MCRH];
2270 tmp <<= 32;
2271 tmp += State.regs[REG_MCRL];
2272
2273 if (tmp > 0x7fffffff)
2274 State.regs[dstreg] = 0x7fffffff;
2275 else if (tmp < 0xffffffff80000000LL)
2276 State.regs[dstreg] = 0x80000000;
2277 else
2278 State.regs[dstreg] = tmp;
2279 }
2280 /* 16bit saturation */
2281 else if (IMM8 == 0x10)
2282 {
2283 long long tmp;
2284
2285 tmp = State.regs[REG_MCRH];
2286 tmp <<= 32;
2287 tmp += State.regs[REG_MCRL];
2288
2289 if (tmp > 0x7fff)
2290 State.regs[dstreg] = 0x7fff;
2291 else if (tmp < 0xffffffffffff8000LL)
2292 State.regs[dstreg] = 0x8000;
2293 else
2294 State.regs[dstreg] = tmp;
2295 }
2296 /* 8 bit saturation */
2297 else if (IMM8 == 0x8)
2298 {
2299 long long tmp;
2300
2301 tmp = State.regs[REG_MCRH];
2302 tmp <<= 32;
2303 tmp += State.regs[REG_MCRL];
2304
2305 if (tmp > 0x7f)
2306 State.regs[dstreg] = 0x7f;
2307 else if (tmp < 0xffffffffffffff80LL)
2308 State.regs[dstreg] = 0x80;
2309 else
2310 State.regs[dstreg] = tmp;
2311 }
2312 /* 9 bit saturation */
2313 else if (IMM8 == 0x9)
2314 {
2315 long long tmp;
2316
2317 tmp = State.regs[REG_MCRH];
2318 tmp <<= 32;
2319 tmp += State.regs[REG_MCRL];
2320
2321 if (tmp > 0x80)
2322 State.regs[dstreg] = 0x80;
2323 else if (tmp < 0xffffffffffffff81LL)
2324 State.regs[dstreg] = 0x81;
2325 else
2326 State.regs[dstreg] = tmp;
2327 }
2328 /* 9 bit saturation */
2329 else if (IMM8 == 0x30)
2330 {
2331 long long tmp;
2332
2333 tmp = State.regs[REG_MCRH];
2334 tmp <<= 32;
2335 tmp += State.regs[REG_MCRL];
2336
2337 if (tmp > 0x7fffffffffffLL)
2338 tmp = 0x7fffffffffffLL;
2339 else if (tmp < 0xffff800000000000LL)
2340 tmp = 0xffff800000000000LL;
2341
2342 tmp >>= 16;
2343 State.regs[dstreg] = tmp;
2344 }
2345}
377e53bb 2346
0f7d7385
JL		 2347// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
23488.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2349"add"
2350*am33
2351{
ee61616c 2352 int z, c, n, v;
377e53bb
JL		 2353 unsigned long sum, source1, source2;
2354 int srcreg1, srcreg2, dstreg;
2355
2356 PC = cia;
9c55817e
JL		 2357 srcreg1 = translate_rreg (SD_, RM2);
2358 srcreg2 = translate_rreg (SD_, RN0);
2359 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2360
2361 source1 = State.regs[srcreg1];
2362 source2 = State.regs[srcreg2];
2363 sum = source1 + source2;
2364 State.regs[dstreg] = sum;
2365
2366 z = (sum == 0);
2367 n = (sum & 0x80000000);
2368 c = (sum < source1) || (sum < source2);
2369 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2370 && (source1 & 0x80000000) != (sum & 0x80000000));
2371
2372 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2373 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2374 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2375}
2376
2377// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
23788.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2379"addc"
2380*am33
2381{
2382 int z, c, n, v;
2383 unsigned long sum, source1, source2;
2384 int srcreg1, srcreg2, dstreg;
2385
2386 PC = cia;
9c55817e
JL		 2387 srcreg1 = translate_rreg (SD_, RM2);
2388 srcreg2 = translate_rreg (SD_, RN0);
2389 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2390
2391 source1 = State.regs[srcreg1];
2392 source2 = State.regs[srcreg2];
2393 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2394 State.regs[dstreg] = sum;
2395
080ee2ba 2396 z = ((PSW & PSW_Z) != 0) && (sum == 0);
377e53bb
JL		 2397 n = (sum & 0x80000000);
2398 c = (sum < source1) || (sum < source2);
2399 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2400 && (source1 & 0x80000000) != (sum & 0x80000000));
2401
2402 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2403 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2404 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2405}
2406
2407// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
24088.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2409"sub"
2410*am33
2411{
2412 int z, c, n, v;
2413 unsigned long difference, source1, source2;
2414 int srcreg1, srcreg2, dstreg;
2415
2416 PC = cia;
9c55817e
JL		 2417 srcreg1 = translate_rreg (SD_, RM2);
2418 srcreg2 = translate_rreg (SD_, RN0);
2419 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2420
2421 source1 = State.regs[srcreg1];
2422 source2 = State.regs[srcreg2];
2423 difference = source2 - source1;
2424 State.regs[dstreg] = difference;
2425
2426 z = (difference == 0);
2427 n = (difference & 0x80000000);
2428 c = (source1 > source1);
2429 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2430 && (source1 & 0x80000000) != (difference & 0x80000000));
2431
2432 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2433 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2434 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2435}
2436
2437// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
24388.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2439"subc"
2440*am33
2441{
2442 int z, c, n, v;
2443 unsigned long difference, source1, source2;
2444 int srcreg1, srcreg2, dstreg;
2445
2446 PC = cia;
9c55817e
JL		 2447 srcreg1 = translate_rreg (SD_, RM2);
2448 srcreg2 = translate_rreg (SD_, RN0);
2449 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2450
2451 source1 = State.regs[srcreg1];
2452 source2 = State.regs[srcreg2];
2453 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2454 State.regs[dstreg] = difference;
2455
080ee2ba 2456 z = ((PSW & PSW_Z) != 0) && (difference == 0);
377e53bb
JL		 2457 n = (difference & 0x80000000);
2458 c = (source1 > source2);
2459 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2460 && (source1 & 0x80000000) != (difference & 0x80000000));
2461
2462 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2463 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2464 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2465}
2466
2467// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
24688.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2469"and"
2470*am33
2471{
080ee2ba 2472 int z, n;
377e53bb
JL		 2473 int srcreg1, srcreg2, dstreg;
2474
2475 PC = cia;
9c55817e
JL		 2476 srcreg1 = translate_rreg (SD_, RM2);
2477 srcreg2 = translate_rreg (SD_, RN0);
2478 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2479
2480 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2481
2482 z = (State.regs[dstreg] == 0);
2483 n = (State.regs[dstreg] & 0x80000000);
2484
2485 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2486 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2487}
2488
2489// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
24908.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2491"or"
2492*am33
2493{
080ee2ba 2494 int z, n;
0f7d7385
JL		 2495 int srcreg1, srcreg2, dstreg;
2496
2497 PC = cia;
9c55817e
JL		 2498 srcreg1 = translate_rreg (SD_, RM2);
2499 srcreg2 = translate_rreg (SD_, RN0);
2500 dstreg = translate_rreg (SD_, RD0);
0f7d7385 2501
377e53bb 2502 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
ee61616c 2503
377e53bb
JL		 2504 z = (State.regs[dstreg] == 0);
2505 n = (State.regs[dstreg] & 0x80000000);
ee61616c
JL		 2506
2507 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
377e53bb 2508 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2509}
2510
377e53bb
JL		 2511// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
25128.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2513"xor"
0f7d7385
JL		 2514*am33
2515{
080ee2ba 2516 int z, n;
3e75ff7e 2517 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2518
2519 PC = cia;
9c55817e
JL		 2520 srcreg1 = translate_rreg (SD_, RM2);
2521 srcreg2 = translate_rreg (SD_, RN0);
2522 dstreg = translate_rreg (SD_, RD0);
3e75ff7e 2523
377e53bb 2524 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
3e75ff7e 2525
377e53bb
JL		 2526 z = (State.regs[dstreg] == 0);
2527 n = (State.regs[dstreg] & 0x80000000);
0f7d7385 2528
3e75ff7e 2529 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
377e53bb 2530 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2531}
2532
377e53bb
JL		 2533// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
25348.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2535"asr"
0f7d7385
JL		 2536*am33
2537{
080ee2ba 2538 int z, c, n;
377e53bb 2539 long temp;
3e75ff7e 2540 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2541
2542 PC = cia;
9c55817e
JL		 2543 srcreg1 = translate_rreg (SD_, RM2);
2544 srcreg2 = translate_rreg (SD_, RN0);
2545 dstreg = translate_rreg (SD_, RD0);
3e75ff7e 2546
377e53bb
JL		 2547 temp = State.regs[srcreg2];
2548 c = temp & 1;
2549 temp >>= State.regs[srcreg1];
2550 State.regs[dstreg] = temp;
3e75ff7e 2551
377e53bb
JL		 2552 z = (State.regs[dstreg] == 0);
2553 n = (State.regs[dstreg] & 0x80000000);
3e75ff7e 2554
377e53bb
JL		 2555 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2556 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2557}
2558
377e53bb
JL		 2559// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
25608.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2561"lsr"
2562*am33
2563{
080ee2ba 2564 int z, c, n;
377e53bb
JL		 2565 int srcreg1, srcreg2, dstreg;
2566
2567 PC = cia;
9c55817e
JL		 2568 srcreg1 = translate_rreg (SD_, RM2);
2569 srcreg2 = translate_rreg (SD_, RN0);
2570 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2571
2572 c = State.regs[srcreg2] & 1;
2573 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2574
2575 z = (State.regs[dstreg] == 0);
2576 n = (State.regs[dstreg] & 0x80000000);
2577
2578 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2579 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2580}
2581
2582// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
25838.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2584"asl"
2585*am33
2586{
080ee2ba 2587 int z, n;
377e53bb
JL		 2588 int srcreg1, srcreg2, dstreg;
2589
2590 PC = cia;
9c55817e
JL		 2591 srcreg1 = translate_rreg (SD_, RM2);
2592 srcreg2 = translate_rreg (SD_, RN0);
2593 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2594
2595 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2596
2597 z = (State.regs[dstreg] == 0);
2598 n = (State.regs[dstreg] & 0x80000000);
2599
2600 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2601 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2602}
2603
2604// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
3e202231 26058.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
377e53bb
JL		 2606"mul"
2607*am33
2608{
2609 int srcreg1, srcreg2, dstreg1, dstreg2;
2610 signed long long temp;
0a785507 2611 int n, z;
377e53bb
JL		 2612
2613 PC = cia;
9c55817e
JL		 2614 srcreg1 = translate_rreg (SD_, RM2);
2615 srcreg2 = translate_rreg (SD_, RN0);
2616 dstreg1 = translate_rreg (SD_, RD0);
2617 dstreg2 = translate_rreg (SD_, RD2);
377e53bb
JL		 2618
2619 temp = ((signed64)(signed32)State.regs[srcreg1]
2620 * (signed64)(signed32)State.regs[srcreg2]);
2621 State.regs[dstreg1] = temp & 0xffffffff;
2622 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
0a785507
JL		 2623
2624 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2625 n = (State.regs[dstreg2] & 0x80000000);
2626
2627 PSW &= ~(PSW_Z | PSW_N);
2628 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
377e53bb
JL		 2629}
2630
2631// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
3e202231 26328.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
377e53bb
JL		 2633"mulu"
2634*am33
2635{
2636 int srcreg1, srcreg2, dstreg1, dstreg2;
2637 signed long long temp;
0a785507 2638 int n, z;
377e53bb
JL		 2639
2640 PC = cia;
9c55817e
JL		 2641 srcreg1 = translate_rreg (SD_, RM2);
2642 srcreg2 = translate_rreg (SD_, RN0);
2643 dstreg1 = translate_rreg (SD_, RD0);
2644 dstreg2 = translate_rreg (SD_, RD2);
377e53bb 2645
080ee2ba
JL		 2646 temp = ((unsigned64)State.regs[srcreg1]
2647 * (unsigned64)State.regs[srcreg2]);
377e53bb
JL		 2648 State.regs[dstreg1] = temp & 0xffffffff;
2649 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
0a785507
JL		 2650
2651 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2652 n = (State.regs[dstreg2] & 0x80000000);
2653
2654 PSW &= ~(PSW_Z | PSW_N);
2655 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
377e53bb
JL		 2656}
2657
2658// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
26598.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2660"mov"
2661*am33
2662{
2663 int dstreg;
2664
2665 PC = cia;
9c55817e 2666 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2667 State.regs[dstreg] = load_word (IMM8);
2668}
2669
2670// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
26718.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2672"mov"
2673*am33
2674{
2675 int srcreg;
2676
9c55817e
JL		 2677 PC = cia;
2678 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2679 store_word (IMM8, State.regs[srcreg]);
2680}
2681
2682// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
26838.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2684"movbu"
2685*am33
2686{
2687 int dstreg;
2688
2689 PC = cia;
9c55817e 2690 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2691 State.regs[dstreg] = load_byte (IMM8);
2692}
2693
2694// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
26958.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2696"movbu"
0f7d7385
JL		 2697*am33
2698{
377e53bb 2699 int srcreg;
0f7d7385
JL		 2700
2701 PC = cia;
9c55817e 2702 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2703 store_byte (IMM8, State.regs[srcreg]);
2704}
0f7d7385 2705
377e53bb
JL		 2706// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
27078.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2708"movhu"
2709*am33
2710{
2711 int dstreg;
2712
2713 PC = cia;
9c55817e 2714 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2715 State.regs[dstreg] = load_half (IMM8);
2716}
3e75ff7e 2717
377e53bb
JL		 2718// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
27198.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2720"movhu"
2721*am33
2722{
2723 int srcreg;
3e75ff7e 2724
377e53bb 2725 PC = cia;
9c55817e 2726 srcreg = translate_rreg (SD_, RM2);
377e53bb 2727 store_half (IMM8, State.regs[srcreg]);
0f7d7385
JL		 2728}
2729
377e53bb
JL		 2730// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
27318.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2732"mov"
0f7d7385
JL		 2733*am33
2734{
3e75ff7e 2735 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2736
2737 PC = cia;
9c55817e
JL		 2738 srcreg1 = translate_rreg (SD_, RM0);
2739 srcreg1 = translate_rreg (SD_, RI0);
2740 dstreg = translate_rreg (SD_, RN0);
377e53bb 2741 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
3e75ff7e
JL		 2742}
2743
377e53bb
JL		 2744// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
27458.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2746"mov"
3e75ff7e
JL		 2747*am33
2748{
377e53bb 2749 int srcreg, dstreg1, dstreg2;
3e75ff7e
JL		 2750
2751 PC = cia;
9c55817e
JL		 2752 srcreg = translate_rreg (SD_, RM0);
2753 dstreg1 = translate_rreg (SD_, RI0);
2754 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2755 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2756}
2757
377e53bb
JL		 2758// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
27598.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2760"movbu"
3e75ff7e
JL		 2761*am33
2762{
3e75ff7e
JL		 2763 int srcreg1, srcreg2, dstreg;
2764
2765 PC = cia;
9c55817e
JL		 2766 srcreg1 = translate_rreg (SD_, RM0);
2767 srcreg1 = translate_rreg (SD_, RI0);
2768 dstreg = translate_rreg (SD_, RN0);
377e53bb 2769 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
3e75ff7e
JL		 2770}
2771
377e53bb
JL		 2772// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
27738.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2774"movbu"
3e75ff7e
JL		 2775*am33
2776{
377e53bb 2777 int srcreg, dstreg1, dstreg2;
3e75ff7e
JL		 2778
2779 PC = cia;
9c55817e
JL		 2780 srcreg = translate_rreg (SD_, RM0);
2781 dstreg1 = translate_rreg (SD_, RI0);
2782 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2783 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2784}
2785
377e53bb
JL		 2786// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
27878.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2788"movhu"
3e75ff7e
JL		 2789*am33
2790{
3e75ff7e
JL		 2791 int srcreg1, srcreg2, dstreg;
2792
9c55817e
JL		 2793 PC = cia;
2794 srcreg1 = translate_rreg (SD_, RM0);
2795 srcreg1 = translate_rreg (SD_, RI0);
2796 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 2797 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2798}
2799
2800// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
28018.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2802"movhu"
2803*am33
2804{
2805 int srcreg, dstreg1, dstreg2;
2806
2807 PC = cia;
9c55817e
JL		 2808 srcreg = translate_rreg (SD_, RM0);
2809 dstreg1 = translate_rreg (SD_, RI0);
2810 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2811 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2812}
2813
1f0ba346 2814// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
3e202231 28158.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
1f0ba346
JL		 2816"mac"
2817*am33
2818{
2819 int srcreg1, srcreg2, dstreg1, dstreg2;
2820 signed long long temp;
2821 unsigned long sum;
2822 int c, v;
2823
2824 PC = cia;
2825 srcreg1 = translate_rreg (SD_, RM2);
2826 srcreg2 = translate_rreg (SD_, RN0);
2827 dstreg1 = translate_rreg (SD_, RD0);
2828 dstreg2 = translate_rreg (SD_, RD2);
2829
2830 temp = ((signed64)(signed32)State.regs[srcreg1]
2831 * (signed64)(signed32)State.regs[srcreg2]);
2832
2833 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2834 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2835 State.regs[dstreg2] = sum;
2836 temp >>= 32;
2837 temp &= 0xffffffff;
2838 sum = State.regs[dstreg1] + temp + c;
2839 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2840 && (temp & 0x80000000) != (sum & 0x80000000));
2841 State.regs[dstreg1] = sum;
2842 if (v)
0a785507
JL		 2843 {
2844 State.regs[REG_MCVF] = 1;
2845 PSW &= ~(PSW_V);
2846 PSW |= (( v ? PSW_V : 0));
2847 }
1f0ba346
JL		 2848}
2849
2850// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
3e202231 28518.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
1f0ba346
JL		 2852"macu"
2853*am33
2854{
2855 int srcreg1, srcreg2, dstreg1, dstreg2;
2856 signed long long temp;
2857 unsigned long sum;
2858 int c, v;
2859
2860 PC = cia;
2861 srcreg1 = translate_rreg (SD_, RM2);
2862 srcreg2 = translate_rreg (SD_, RN0);
2863 dstreg1 = translate_rreg (SD_, RD0);
2864 dstreg2 = translate_rreg (SD_, RD2);
2865
2866 temp = ((unsigned64)State.regs[srcreg1]
2867 * (unsigned64)State.regs[srcreg2]);
2868
2869 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2870 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2871 State.regs[dstreg2] = sum;
2872 temp >>= 32;
2873 temp &= 0xffffffff;
2874 sum = State.regs[dstreg1] + temp + c;
2875 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2876 && (temp & 0x80000000) != (sum & 0x80000000));
2877 State.regs[dstreg1] = sum;
2878 if (v)
0a785507
JL		 2879 {
2880 State.regs[REG_MCVF] = 1;
2881 PSW &= ~(PSW_V);
2882 PSW |= (( v ? PSW_V : 0));
2883 }
1f0ba346
JL		 2884}
2885
2886// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
28878.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2888"macb"
2889*am33
2890{
2891 int srcreg1, srcreg2, dstreg;
2892 long temp, sum;
2893 int v;
2894
2895 PC = cia;
2896 srcreg1 = translate_rreg (SD_, RM2);
2897 srcreg2 = translate_rreg (SD_, RN0);
2898 dstreg = translate_rreg (SD_, RD0);
2899
2900 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2901 * (signed32)(State.regs[srcreg1] & 0xff));
2902 sum = State.regs[dstreg] + temp;
2903 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2904 && (temp & 0x80000000) != (sum & 0x80000000));
2905 State.regs[dstreg] = sum;
2906 if (v)
0a785507
JL		 2907 {
2908 State.regs[REG_MCVF] = 1;
2909 PSW &= ~(PSW_V);
2910 PSW |= ((v ? PSW_V : 0));
2911 }
1f0ba346
JL		 2912}
2913
2914// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
29158.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2916"macbu"
2917*am33
2918{
2919 int srcreg1, srcreg2, dstreg;
2920 long temp, sum;
2921 int v;
2922
2923 PC = cia;
2924 srcreg1 = translate_rreg (SD_, RM2);
2925 srcreg2 = translate_rreg (SD_, RN0);
2926 dstreg = translate_rreg (SD_, RD0);
2927
2928 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2929 * (unsigned32)(State.regs[srcreg1] & 0xff));
2930 sum = State.regs[dstreg] + temp;
2931 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2932 && (temp & 0x80000000) != (sum & 0x80000000));
2933 State.regs[dstreg] = sum;
2934 if (v)
0a785507
JL		 2935 {
2936 State.regs[REG_MCVF] = 1;
2937 PSW &= ~(PSW_V);
2938 PSW |= ((v ? PSW_V : 0));
2939 }
1f0ba346
JL		 2940}
2941
3e202231
JL		 2942// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
29438.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
1f0ba346
JL		 2944"mach"
2945*am33
2946{
3e202231
JL		 2947 int srcreg1, srcreg2, dstreg1, dstreg2;
2948 long long temp, sum;
1f0ba346
JL		 2949 int v;
2950
2951 PC = cia;
2952 srcreg1 = translate_rreg (SD_, RM2);
2953 srcreg2 = translate_rreg (SD_, RN0);
3e202231
JL		 2954 dstreg1 = translate_rreg (SD_, RD0);
2955 dstreg2 = translate_rreg (SD_, RD0);
1f0ba346
JL		 2956
2957 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2958 * (signed32)(State.regs[srcreg1] & 0xffff));
3e202231
JL		 2959 State.regs[dstreg2] += (temp & 0xffffffff);
2960 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2961 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
1f0ba346 2962 && (temp & 0x80000000) != (sum & 0x80000000));
3e202231 2963 State.regs[dstreg1] = sum;
1f0ba346 2964 if (v)
0a785507
JL		 2965 {
2966 State.regs[REG_MCVF] = 1;
2967 PSW &= ~(PSW_V);
2968 PSW |= ((v ? PSW_V : 0));
2969 }
1f0ba346
JL		 2970}
2971
3e202231
JL		 2972// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
29738.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
1f0ba346
JL		 2974"machu"
2975*am33
2976{
3e202231
JL		 2977 int srcreg1, srcreg2, dstreg1, dstreg2;
2978 long long temp, sum;
1f0ba346
JL		 2979 int v;
2980
2981 PC = cia;
2982 srcreg1 = translate_rreg (SD_, RM2);
2983 srcreg2 = translate_rreg (SD_, RN0);
3e202231
JL		 2984 dstreg1 = translate_rreg (SD_, RD0);
2985 dstreg2 = translate_rreg (SD_, RD0);
1f0ba346
JL		 2986
2987 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2988 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3e202231
JL		 2989 State.regs[dstreg2] += (temp & 0xffffffff);
2990 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2991 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
1f0ba346 2992 && (temp & 0x80000000) != (sum & 0x80000000));
3e202231 2993 State.regs[dstreg1] = sum;
1f0ba346 2994 if (v)
0a785507
JL		 2995 {
2996 State.regs[REG_MCVF] = 1;
2997 PSW &= ~(PSW_V);
2998 PSW |= ((v ? PSW_V : 0));
2999 }
1f0ba346
JL		 3000}
3001
3002// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
30038.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
3004"dmach"
3005*am33
3006{
3007 int srcreg1, srcreg2, dstreg;
3008 long temp, temp2, sum;
3009 int v;
3010
3011 PC = cia;
3012 srcreg1 = translate_rreg (SD_, RM2);
3013 srcreg2 = translate_rreg (SD_, RN0);
3014 dstreg = translate_rreg (SD_, RD0);
3015
3016 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3017 * (signed32)(State.regs[srcreg1] & 0xffff));
3018 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3019 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3020 sum = temp + temp2 + State.regs[dstreg];
3021 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3022 && (temp & 0x80000000) != (sum & 0x80000000));
3023 State.regs[dstreg] = sum;
3024 if (v)
0a785507
JL		 3025 {
3026 State.regs[REG_MCVF] = 1;
3027 PSW &= ~(PSW_V);
3028 PSW |= ((v ? PSW_V : 0));
3029 }
1f0ba346
JL		 3030}
3031
3032// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
30338.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3034"dmachu"
3035*am33
3036{
3037 int srcreg1, srcreg2, dstreg;
3038 long temp, temp2, sum;
3039 int v;
3040
3041 PC = cia;
3042 srcreg1 = translate_rreg (SD_, RM2);
3043 srcreg2 = translate_rreg (SD_, RN0);
3044 dstreg = translate_rreg (SD_, RD0);
3045
3046 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3047 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3048 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3049 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3050 sum = temp + temp2 + State.regs[dstreg];
3051 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3052 && (temp & 0x80000000) != (sum & 0x80000000));
3053 State.regs[dstreg] = sum;
3054 if (v)
0a785507
JL		 3055 {
3056 State.regs[REG_MCVF] = 1;
3057 PSW &= ~(PSW_V);
3058 PSW |= ((v ? PSW_V : 0));
3059 }
1f0ba346
JL		 3060}
3061
3062// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3e202231 30638.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
1f0ba346
JL		 3064"dmulh"
3065*am33
3066{
3067 int srcreg1, srcreg2, dstreg1, dstreg2;
3068 signed long long temp;
3069
3070 PC = cia;
3071 srcreg1 = translate_rreg (SD_, RM2);
3072 srcreg2 = translate_rreg (SD_, RN0);
3073 dstreg1 = translate_rreg (SD_, RD0);
3074 dstreg2 = translate_rreg (SD_, RD2);
3075
3076 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3077 * (signed32)(State.regs[srcreg1] & 0xffff));
3078 State.regs[dstreg2] = temp;
3079 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3080 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3081 State.regs[dstreg1] = temp;
3082}
3083
3084// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3e202231 30858.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
1f0ba346
JL		 3086"dmulhu"
3087*am33
3088{
3089 int srcreg1, srcreg2, dstreg1, dstreg2;
3090 signed long long temp;
3091
3092 PC = cia;
3093 srcreg1 = translate_rreg (SD_, RM2);
3094 srcreg2 = translate_rreg (SD_, RN0);
3095 dstreg1 = translate_rreg (SD_, RD0);
3096 dstreg2 = translate_rreg (SD_, RD2);
3097
3098 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3099 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3100 State.regs[dstreg2] = temp;
3101 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3102 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3103 State.regs[dstreg1] = temp;
3104}
377e53bb
JL		 3105
3106// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
31078.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3108"sat24"
3e75ff7e
JL		 3109*am33
3110{
377e53bb 3111 int srcreg, dstreg;
0a785507 3112 int value, n, z;
3e75ff7e
JL		 3113
3114 PC = cia;
9c55817e
JL		 3115 srcreg = translate_rreg (SD_, RM2);
3116 dstreg = translate_rreg (SD_, RN0);
3e75ff7e 3117
377e53bb 3118 value = State.regs[srcreg];
3e75ff7e 3119
377e53bb
JL		 3120 if (value >= 0x7fffff)
3121 State.regs[dstreg] = 0x7fffff;
3122 else if (value <= 0xff800000)
3123 State.regs[dstreg] = 0xff800000;
3124 else
3125 State.regs[dstreg] = value;
0a785507
JL		 3126
3127 n = (State.regs[dstreg] & 0x800000) != 0;
3128 z = (State.regs[dstreg] == 0);
3129 PSW &= ~(PSW_Z | PSW_N);
3130 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3e75ff7e
JL		 3131}
3132
1f0ba346
JL		 3133// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
31348.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3135"bsch"
3136*am33
3137{
3138 int temp, c, i;
3139 int srcreg1, srcreg2, dstreg;
3140 int start;
3141
3142 PC = cia;
3143 srcreg1 = translate_rreg (SD_, RM2);
3144 srcreg2 = translate_rreg (SD_, RN0);
3145 dstreg = translate_rreg (SD_, RD0);
3146
3147 temp = State.regs[srcreg1];
3148 start = (State.regs[srcreg2] & 0x1f) - 1;
3149 if (start == -1)
3150 start = 31;
3151
3152 for (i = start; i >= 0; i--)
3153 {
3154 if (temp & (1 << i))
3155 {
3156 c = 1;
3157 State.regs[dstreg] = i;
3158 break;
3159 }
3160 }
3161
3162 if (i < 0)
3163 {
3164 c = 0;
3165 State.regs[dstreg] = 0;
3166 }
3167 PSW &= ~(PSW_C);
3168 PSW |= (c ? PSW_C : 0);
3169}
3e75ff7e
JL		 3170
3171// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
31728.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3173"mov"
3174*am33
3175{
3176 int dstreg;
3177
3178 PC = cia;
9c55817e 3179 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3180 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3181}
3182
3183// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
31848.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3185"movu"
3186*am33
3187{
3188 int dstreg;
3189
3190 PC = cia;
9c55817e 3191 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3192 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3193}
3194
3195// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
31968.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3197"add"
3198*am33
3199{
3200 int dstreg;
3201
3202 PC = cia;
9c55817e 3203 dstreg = translate_rreg (SD_, RN0);
4e86afb8 3204 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3e75ff7e
JL		 3205}
3206
3207// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
32088.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3209"addc"
3210*am33
3211{
3212 int dstreg, z, n, c, v;
3213 unsigned long sum, imm, reg2;
3214
3215 PC = cia;
9c55817e 3216 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3217
3218 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3219 reg2 = State.regs[dstreg];
3220 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3221 State.regs[dstreg] = sum;
3222
080ee2ba 3223 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3e75ff7e
JL		 3224 n = (sum & 0x80000000);
3225 c = (sum < imm) || (sum < reg2);
3226 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3227 && (reg2 & 0x80000000) != (sum & 0x80000000));
3228
3229 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3230 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3231 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3232}
3233
3234// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
32358.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3236"sub"
3237*am33
3238{
3239 int dstreg;
3240
3241 PC = cia;
9c55817e 3242 dstreg = translate_rreg (SD_, RN0);
4e86afb8 3243 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3e75ff7e
JL		 3244}
3245
3246// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
32478.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3248"subc"
3249*am33
3250{
3251 int dstreg, z, n, c, v;
3252 unsigned long difference, imm, reg2;
3253
3254 PC = cia;
9c55817e 3255 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3256
3257 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3258 reg2 = State.regs[dstreg];
3259 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3260 State.regs[dstreg] = difference;
3261
080ee2ba 3262 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3e75ff7e
JL		 3263 n = (difference & 0x80000000);
3264 c = (imm > reg2);
3265 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3266 && (reg2 & 0x80000000) != (difference & 0x80000000));
3267
3268 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3269 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3270 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3271}
3272
3273// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
32748.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3275"cmp"
3276*am33
3277{
3278 int srcreg;
3279
3280 PC = cia;
9c55817e 3281 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3282 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3283}
3284
3285// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
32868.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3287"mov"
3288*am33
3289{
6d254a2d
JL		 3290 int dstreg;
3291
3e75ff7e 3292 PC = cia;
6d254a2d 3293 dstreg = translate_xreg (SD_, XRN0);
3e75ff7e 3294
6d254a2d 3295 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3e75ff7e
JL		 3296}
3297
3298// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
32998.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3300"and"
3301*am33
3302{
3303 int dstreg;
3304 int z,n;
3305
3306 PC = cia;
9c55817e 3307 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3308
3309 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3310 z = (State.regs[dstreg] == 0);
3311 n = (State.regs[dstreg] & 0x80000000) != 0;
3312 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3313 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3314}
3315
3316// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
33178.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3318"or"
3319*am33
3320{
3321 int dstreg;
3322 int z,n;
3323
3324 PC = cia;
9c55817e 3325 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3326
3327 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3328 z = (State.regs[dstreg] == 0);
3329 n = (State.regs[dstreg] & 0x80000000) != 0;
3330 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3331 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3332}
3333
3334// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
33358.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3336"xor"
3337*am33
3338{
3339 int dstreg;
3340 int z,n;
3341
3342 PC = cia;
9c55817e 3343 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3344
3345 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3346 z = (State.regs[dstreg] == 0);
3347 n = (State.regs[dstreg] & 0x80000000) != 0;
3348 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3349 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3350}
3351
3352// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
33538.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3354"asr"
3355*am33
3356{
3357 int dstreg;
3358 long temp;
3359 int c, z, n;
3360
3361 PC = cia;
9c55817e 3362 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3363
3364 temp = State.regs[dstreg];
3365 c = temp & 1;
3366 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3367 State.regs[dstreg] = temp;
3368 z = (State.regs[dstreg] == 0);
3369 n = (State.regs[dstreg] & 0x80000000) != 0;
3370 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3371 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3372}
3373
3374
3375// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
33768.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3377"lsr"
3378*am33
3379{
3380 int dstreg;
3381 int z, n, c;
3382
3383 PC = cia;
9c55817e 3384 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3385
3386 c = State.regs[dstreg] & 1;
3387 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3388 z = (State.regs[dstreg] == 0);
3389 n = (State.regs[dstreg] & 0x80000000) != 0;
3390 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3391 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3392}
3393
3394// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
33958.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3396"asl"
3397*am33
3398{
3399 int srcreg, dstreg;
3400 int z, n;
3401
3402 PC = cia;
9c55817e 3403 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3404
3405 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3406 z = (State.regs[dstreg] == 0);
3407 n = (State.regs[dstreg] & 0x80000000) != 0;
3408 PSW &= ~(PSW_Z | PSW_N);
3409 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3410}
3411
1f0ba346
JL		 3412// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
34138.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3414"mul"
3415*am33
3416{
3417 int dstreg;
3418 unsigned long long temp;
3419 int z, n;
3420
3421 PC = cia;
3422 dstreg = translate_rreg (SD_, RN0);
3423
3424 temp = ((signed64)(signed32)State.regs[dstreg]
0a785507 3425 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
1f0ba346
JL		 3426 State.regs[dstreg] = temp & 0xffffffff;
3427 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3428 z = (State.regs[dstreg] == 0);
3429 n = (State.regs[dstreg] & 0x80000000) != 0;
3430 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3431 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3432}
3433
3434// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
34358.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3436"mulu"
3437*am33
3438{
3439 int dstreg;
3440 unsigned long long temp;
3441 int z, n;
3442
3443 PC = cia;
3444 dstreg = translate_rreg (SD_, RN0);
3445
3446 temp = ((unsigned64)State.regs[dstreg]
0a785507 3447 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
1f0ba346
JL		 3448 State.regs[dstreg] = temp & 0xffffffff;
3449 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3450 z = (State.regs[dstreg] == 0);
3451 n = (State.regs[dstreg] & 0x80000000) != 0;
3452 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3453 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3454}
3e75ff7e
JL		 3455
3456// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
34578.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3458"btst"
3459*am33
3460{
3461 int srcreg;
3462
3463 PC = cia;
9c55817e 3464 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3465 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3466}
3467
3468// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
34698.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3470"mov"
3471*am33
3472{
3473 int srcreg, dstreg;
3474
3475 PC = cia;
9c55817e
JL		 3476 srcreg = translate_rreg (SD_, RM0);
3477 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3478 State.regs[dstreg] = load_word (State.regs[srcreg]
080ee2ba
JL		 3479 + EXTEND24 (FETCH24 (IMM24A,
3480 IMM24B, IMM24C)));
3e75ff7e
JL		 3481}
3482
3483// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
34848.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3485"mov"
3486*am33
3487{
3488 int srcreg, dstreg;
3489
3490 PC = cia;
9c55817e
JL		 3491 srcreg = translate_rreg (SD_, RM2);
3492 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3493 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3494 State.regs[srcreg]);
3495}
3496
3497// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
34988.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3499"movbu"
3500*am33
3501{
3502 int srcreg, dstreg;
3503
3504 PC = cia;
9c55817e
JL		 3505 srcreg = translate_rreg (SD_, RM0);
3506 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3507 State.regs[dstreg] = load_byte (State.regs[srcreg]
080ee2ba
JL		 3508 + EXTEND24 (FETCH24 (IMM24A,
3509 IMM24B, IMM24C)));
3e75ff7e
JL		 3510}
3511
3512// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
35138.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3514"movbu"
3515*am33
3516{
3517 int srcreg, dstreg;
3518
3519 PC = cia;
9c55817e
JL		 3520 srcreg = translate_rreg (SD_, RM2);
3521 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3522 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3523 State.regs[srcreg]);
3524}
3525
3526// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
35278.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3528"movhu"
3529*am33
3530{
3531 int srcreg, dstreg;
3532
3533 PC = cia;
9c55817e
JL		 3534 srcreg = translate_rreg (SD_, RM0);
3535 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3536 State.regs[dstreg] = load_half (State.regs[srcreg]
080ee2ba
JL		 3537 + EXTEND24 (FETCH24 (IMM24A,
3538 IMM24B, IMM24C)));
3e75ff7e
JL		 3539}
3540
3541// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
35428.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3543"movhu"
3544*am33
3545{
3546 int srcreg, dstreg;
3547
3548 PC = cia;
9c55817e
JL		 3549 srcreg = translate_rreg (SD_, RM2);
3550 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3551 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3552 State.regs[srcreg]);
3553}
3554
377e53bb 3555// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3e202231 35568.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
377e53bb
JL		 3557"mov"
3558*am33
3559{
3560 int srcreg, dstreg;
3561
3562 PC = cia;
9c55817e
JL		 3563 srcreg = translate_rreg (SD_, RM0);
3564 dstreg = translate_rreg (SD_, RN2);
6ae1456e
JL		 3565 State.regs[dstreg] = load_word (State.regs[srcreg]);
3566 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
377e53bb
JL		 3567}
3568
3569// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3e202231 35708.0xfd+8.0x7a+4.RM2,4.RN0!RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
377e53bb
JL		 3571"mov"
3572*am33
3573{
3574 int srcreg, dstreg;
3575
3576 PC = cia;
9c55817e
JL		 3577 srcreg = translate_rreg (SD_, RM2);
3578 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 3579 store_word (State.regs[dstreg], State.regs[srcreg]);
3580 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
377e53bb
JL		 3581}
3582
3e75ff7e
JL		 3583
3584// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
35858.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3586"mov"
3587*am33
3588{
3589 int dstreg;
3590
3591 PC = cia;
9c55817e 3592 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3593 State.regs[dstreg] = load_word (State.regs[REG_SP]
080ee2ba
JL		 3594 + EXTEND24 (FETCH24 (IMM24A,
3595 IMM24B, IMM24C)));
3e75ff7e
JL		 3596}
3597
3598// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
35998.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3600"mov"
3601*am33
3602{
3603 int srcreg;
3604
3605 PC = cia;
9c55817e 3606 srcreg = translate_rreg (SD_, RM2);
080ee2ba 3607 store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3608 State.regs[srcreg]);
3609}
3610
3611// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
36128.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3613"movbu"
3614*am33
3615{
3616 int dstreg;
3617
3618 PC = cia;
9c55817e 3619 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3620 State.regs[dstreg] = load_byte (State.regs[REG_SP]
080ee2ba
JL		 3621 + EXTEND24 (FETCH24 (IMM24A,
3622 IMM24B, IMM24C)));
3e75ff7e
JL		 3623}
3624
3625// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
36268.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3627"movbu"
3628*am33
3629{
3630 int srcreg;
3631
3632 PC = cia;
9c55817e 3633 srcreg = translate_rreg (SD_, RM2);
080ee2ba 3634 store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3635 State.regs[srcreg]);
3636}
3637
3638// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
36398.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3640"movhu"
3641*am33
3642{
3643 int dstreg;
3644
3645 PC = cia;
9c55817e 3646 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3647 State.regs[dstreg] = load_half (State.regs[REG_SP]
080ee2ba
JL		 3648 + EXTEND24 (FETCH24 (IMM24A,
3649 IMM24B, IMM24C)));
3e75ff7e
JL		 3650}
3651
3652// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
36538.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3654"movhu"
3655*am33
3656{
3657 int srcreg;
3658
3659 PC = cia;
9c55817e 3660 srcreg = translate_rreg (SD_, RM2);
080ee2ba 3661 store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3662 State.regs[srcreg]);
3663}
3664
377e53bb 3665// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3e202231 36668.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
377e53bb
JL		 3667"movhu"
3668*am33
3669{
3670 int srcreg, dstreg;
3671
3672 PC = cia;
9c55817e
JL		 3673 srcreg = translate_rreg (SD_, RM0);
3674 dstreg = translate_rreg (SD_, RN2);
6ae1456e
JL		 3675 State.regs[dstreg] = load_half (State.regs[srcreg]);
3676 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
377e53bb
JL		 3677}
3678
3679// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3e202231 36808.0xfd+8.0xfa+4.RM2,4.RN0!RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
377e53bb
JL		 3681"movhu"
3682*am33
3683{
3684 int srcreg, dstreg;
3685
3686 PC = cia;
9c55817e
JL		 3687 srcreg = translate_rreg (SD_, RM2);
3688 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 3689 store_half (State.regs[dstreg], State.regs[srcreg]);
3690 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
377e53bb
JL		 3691}
3692
1f0ba346
JL		 3693// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
36948.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3695"mac"
3696*am33
3697{
3698 int srcreg;
3699 long long temp, sum;
3700 int c, v;
3701
3702 PC = cia;
3703 srcreg = translate_rreg (SD_, RN2);
3704
0a785507 3705 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
1f0ba346
JL		 3706 * (signed64)State.regs[srcreg]);
3707 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3708 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3709 State.regs[REG_MCRL] = sum;
3710 temp >>= 32;
3711 temp &= 0xffffffff;
3712 sum = State.regs[REG_MCRH] + temp + c;
3713 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3714 && (temp & 0x80000000) != (sum & 0x80000000));
3715 State.regs[REG_MCRH] = sum;
3716 if (v)
3717 State.regs[REG_MCVF] = 1;
3718}
3719
3720// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
37218.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3722"macu"
3723*am33
3724{
3725 int srcreg;
3726 long long temp, sum;
3727 int c, v;
3728
3729 PC = cia;
3730 srcreg = translate_rreg (SD_, RN2);
3731
3732 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3733 * (unsigned64)State.regs[srcreg]);
3734 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3735 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3736 State.regs[REG_MCRL] = sum;
3737 temp >>= 32;
3738 temp &= 0xffffffff;
3739 sum = State.regs[REG_MCRH] + temp + c;
3740 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3741 && (temp & 0x80000000) != (sum & 0x80000000));
3742 State.regs[REG_MCRH] = sum;
3743 if (v)
3744 State.regs[REG_MCVF] = 1;
3745}
3746
3747// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
37488.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3749"macb"
3750*am33
3751{
3752 int srcreg;
3753 long long temp, sum;
3754 int c, v;
3755
3756 PC = cia;
3757 srcreg = translate_rreg (SD_, RN2);
3758
3759 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3760 * (signed64)State.regs[srcreg] & 0xff);
3761 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3762 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3763 State.regs[REG_MCRL] = sum;
3764 temp >>= 32;
3765 temp &= 0xffffffff;
3766 sum = State.regs[REG_MCRH] + temp + c;
3767 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3768 && (temp & 0x80000000) != (sum & 0x80000000));
3769 State.regs[REG_MCRH] = sum;
3770 if (v)
3771 State.regs[REG_MCVF] = 1;
3772}
3773
3774// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
37758.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3776"macbu"
3777*am33
3778{
3779 int srcreg;
3780 long long temp, sum;
3781 int c, v;
3782
3783 PC = cia;
3784 srcreg = translate_rreg (SD_, RN2);
3785
3786 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3787 * (unsigned64)State.regs[srcreg] & 0xff);
3788 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3789 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3790 State.regs[REG_MCRL] = sum;
3791 temp >>= 32;
3792 temp &= 0xffffffff;
3793 sum = State.regs[REG_MCRH] + temp + c;
3794 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3795 && (temp & 0x80000000) != (sum & 0x80000000));
3796 State.regs[REG_MCRH] = sum;
3797 if (v)
3798 State.regs[REG_MCVF] = 1;
3799}
3800
3801// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
38028.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3803"mach"
3804*am33
3805{
3806 int srcreg;
3807 long long temp, sum;
3808 int c, v;
3809
3810 PC = cia;
3811 srcreg = translate_rreg (SD_, RN2);
3812
3813 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3814 * (signed64)State.regs[srcreg] & 0xffff);
3815 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3816 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3817 State.regs[REG_MCRL] = sum;
3818 temp >>= 32;
3819 temp &= 0xffffffff;
3820 sum = State.regs[REG_MCRH] + temp + c;
3821 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3822 && (temp & 0x80000000) != (sum & 0x80000000));
3823 State.regs[REG_MCRH] = sum;
3824 if (v)
3825 State.regs[REG_MCVF] = 1;
3826}
3827
3828// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
38298.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3830"machu"
3831*am33
3832{
3833 int srcreg;
3834 long long temp, sum;
3835 int c, v;
3836
3837 PC = cia;
3838 srcreg = translate_rreg (SD_, RN2);
3839
3840 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3841 * (unsigned64)State.regs[srcreg] & 0xffff);
3842 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3843 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3844 State.regs[REG_MCRL] = sum;
3845 temp >>= 32;
3846 temp &= 0xffffffff;
3847 sum = State.regs[REG_MCRH] + temp + c;
3848 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3849 && (temp & 0x80000000) != (sum & 0x80000000));
3850 State.regs[REG_MCRH] = sum;
3851 if (v)
3852 State.regs[REG_MCVF] = 1;
3853}
3e75ff7e
JL		 3854
3855// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
38568.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3857"mov"
3858*am33
3859{
3860 int dstreg;
3861
3862 PC = cia;
9c55817e 3863 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3864 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3865}
3866
3867// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
38688.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3869"mov"
3870*am33
3871{
3872 int srcreg;
3873
3874 PC = cia;
9c55817e 3875 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3876 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3877}
3878
3879
3880// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
38818.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3882"movbu"
3883*am33
3884{
3885 int dstreg;
3886
3887 PC = cia;
9c55817e 3888 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3889 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3890}
3891
3892// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
38938.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3894"movbu"
3895*am33
3896{
3897 int srcreg;
3898
3899 PC = cia;
9c55817e 3900 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3901 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3902}
3903
3904
3905// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
39068.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3907"movhu"
3908*am33
3909{
3910 int dstreg;
3911
3912 PC = cia;
9c55817e 3913 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3914 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3915}
3916
3917// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
39188.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3919"movhu"
3920*am33
3921{
3922 int srcreg;
3923
3924 PC = cia;
9c55817e 3925 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3926 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3927}
3928
3929
3930// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
39318.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3932"mov"
3933*am33
3934{
3935 int dstreg;
3936
3937 PC = cia;
9c55817e 3938 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3939 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3940}
3941
3942// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
39438.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3944"movu"
3945*am33
3946{
3947 int dstreg;
3948
3949 PC = cia;
9c55817e 3950 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3951 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3952}
3953
3954// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
39558.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3956"add"
3957*am33
3958{
3959 int dstreg;
3960
3961 PC = cia;
9c55817e 3962 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3963 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3964}
3965
3966// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
39678.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3968"addc"
3969*am33
3970{
3971 int dstreg;
3972 unsigned int imm, reg2, sum;
3973 int z, n, c, v;
3974
3975 PC = cia;
9c55817e 3976 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3977
3978 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3979 reg2 = State.regs[dstreg];
3980 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3981 State.regs[dstreg] = sum;
3982
080ee2ba 3983 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3e75ff7e
JL		 3984 n = (sum & 0x80000000);
3985 c = (sum < imm) || (sum < reg2);
3986 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3987 && (reg2 & 0x80000000) != (sum & 0x80000000));
3988
3989 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3990 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3991 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3992}
3993
3994// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
39958.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3996"sub"
3997*am33
3998{
3999 int dstreg;
4000
4001 PC = cia;
9c55817e 4002 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4003 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4004}
4005
4006// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
40078.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4008"subc"
4009*am33
4010{
4011 int dstreg;
4012 unsigned int imm, reg2, difference;
4013 int z, n, c, v;
4014
4015 PC = cia;
9c55817e 4016 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4017
4018 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4019 reg2 = State.regs[dstreg];
4020 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4021 State.regs[dstreg] = difference;
4022
080ee2ba 4023 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3e75ff7e
JL		 4024 n = (difference & 0x80000000);
4025 c = (imm > reg2);
4026 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4027 && (reg2 & 0x80000000) != (difference & 0x80000000));
4028
4029 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4030 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4031 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4032}
4033
4034// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
40358.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4036"cmp"
4037*am33
4038{
4039 int srcreg;
4040
4041 PC = cia;
9c55817e 4042 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4043 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4044}
4045
4046// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
40478.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4048"mov"
4049*am33
4050{
6d254a2d
JL		 4051 int dstreg;
4052
3e75ff7e 4053 PC = cia;
6d254a2d 4054 dstreg = translate_xreg (SD_, XRN0);
3e75ff7e 4055
6d254a2d 4056 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3e75ff7e
JL		 4057}
4058
4059// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
40608.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4061"and"
4062*am33
4063{
4064 int dstreg;
4065 int z,n;
4066
4067 PC = cia;
9c55817e 4068 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4069
4070 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4071 z = (State.regs[dstreg] == 0);
4072 n = (State.regs[dstreg] & 0x80000000) != 0;
4073 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4074 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4075}
4076
4077// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
40788.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4079"or"
4080*am33
4081{
4082 int dstreg;
4083 int z,n;
4084
4085 PC = cia;
9c55817e 4086 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4087
4088 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4089 z = (State.regs[dstreg] == 0);
4090 n = (State.regs[dstreg] & 0x80000000) != 0;
4091 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4092 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4093}
4094
4095// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
40968.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4097"xor"
4098*am33
4099{
4100 int dstreg;
4101 int z,n;
4102
4103 PC = cia;
9c55817e 4104 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4105
4106 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4107 z = (State.regs[dstreg] == 0);
4108 n = (State.regs[dstreg] & 0x80000000) != 0;
4109 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4110 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4111}
4112
4113// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
41148.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4115"asr"
4116*am33
4117{
4118 int dstreg;
4119 long temp;
4120 int c, z, n;
4121
4122 PC = cia;
9c55817e 4123 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4124
4125 temp = State.regs[dstreg];
4126 c = temp & 1;
4127 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4128 State.regs[dstreg] = temp;
4129 z = (State.regs[dstreg] == 0);
4130 n = (State.regs[dstreg] & 0x80000000) != 0;
4131 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4132 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4133}
4134
4135// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
41368.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4137"lsr"
4138*am33
4139{
4140 int dstreg;
4141 int z, n, c;
4142
4143 PC = cia;
9c55817e 4144 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4145
4146 c = State.regs[dstreg] & 1;
4147 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4148 z = (State.regs[dstreg] == 0);
4149 n = (State.regs[dstreg] & 0x80000000) != 0;
4150 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4151 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4152}
4153
4154// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
41558.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4156"asl"
4157*am33
4158{
4159 int srcreg, dstreg;
4160 int z, n;
4161
4162 PC = cia;
9c55817e 4163 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4164
4165 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4166 z = (State.regs[dstreg] == 0);
4167 n = (State.regs[dstreg] & 0x80000000) != 0;
4168 PSW &= ~(PSW_Z | PSW_N);
4169 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4170}
4171
0a785507
JL		 4172// 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
41738.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4174"mul"
4175*am33
4176{
4177 int dstreg;
4178 unsigned long long temp;
4179 int z, n;
4180
4181 PC = cia;
4182 dstreg = translate_rreg (SD_, RN0);
4183
4184 temp = ((signed64)(signed32)State.regs[dstreg]
4185 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4186 State.regs[dstreg] = temp & 0xffffffff;
4187 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4188 z = (State.regs[dstreg] == 0);
4189 n = (State.regs[dstreg] & 0x80000000) != 0;
4190 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4191 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4192}
4193
4194// 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
41958.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4196"mulu"
4197*am33
4198{
4199 int dstreg;
4200 unsigned long long temp;
4201 int z, n;
4202
4203 PC = cia;
4204 dstreg = translate_rreg (SD_, RN0);
4205
4206 temp = ((unsigned64)State.regs[dstreg]
4207 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4208 State.regs[dstreg] = temp & 0xffffffff;
4209 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4210 z = (State.regs[dstreg] == 0);
4211 n = (State.regs[dstreg] & 0x80000000) != 0;
4212 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4213 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4214}
3e75ff7e
JL		 4215
4216// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
42178.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4218"btst"
4219*am33
4220{
4221 int srcreg;
4222
4223 PC = cia;
9c55817e 4224 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4225 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4226}
4227
4228// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
42298.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4230"mov"
4231*am33
4232{
4233 int srcreg, dstreg;
4234
4235 PC = cia;
9c55817e
JL		 4236 srcreg = translate_rreg (SD_, RM0);
4237 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4238 State.regs[dstreg] = load_word (State.regs[srcreg]
4239 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4240}
4241
4242// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
42438.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4244"mov"
4245*am33
4246{
4247 int srcreg, dstreg;
4248
4249 PC = cia;
9c55817e
JL		 4250 srcreg = translate_rreg (SD_, RM2);
4251 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4252 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4253 State.regs[srcreg]);
4254}
4255
4256// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
42578.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4258"movbu"
4259*am33
4260{
4261 int srcreg, dstreg;
4262
4263 PC = cia;
9c55817e
JL		 4264 srcreg = translate_rreg (SD_, RM0);
4265 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4266 State.regs[dstreg] = load_byte (State.regs[srcreg]
4267 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4268}
4269
4270// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
42718.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4272"movbu"
4273*am33
4274{
4275 int srcreg, dstreg;
4276
4277 PC = cia;
9c55817e
JL		 4278 srcreg = translate_rreg (SD_, RM2);
4279 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4280 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4281 State.regs[srcreg]);
0f7d7385
JL		 4282}
4283
3e75ff7e
JL		 4284// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
42858.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4286"movhu"
0f7d7385
JL		 4287*am33
4288{
3e75ff7e
JL		 4289 int srcreg, dstreg;
4290
4291 PC = cia;
9c55817e
JL		 4292 srcreg = translate_rreg (SD_, RM0);
4293 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4294 State.regs[dstreg] = load_half (State.regs[srcreg]
4295 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4296}
4297
4298// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
42998.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4300"movhu"
4301*am33
4302{
4303 int srcreg, dstreg;
0f7d7385
JL		 4304
4305 PC = cia;
9c55817e
JL		 4306 srcreg = translate_rreg (SD_, RM2);
4307 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4308 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4309 State.regs[srcreg]);
4310}
4311
377e53bb 4312// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
3e202231 43138.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
377e53bb
JL		 4314"mov"
4315*am33
4316{
4317 int srcreg, dstreg;
4318
4319 PC = cia;
9c55817e
JL		 4320 srcreg = translate_rreg (SD_, RM0);
4321 dstreg = translate_rreg (SD_, RN2);
6ae1456e 4322 State.regs[dstreg] = load_word (State.regs[srcreg]);
4b6651c9 4323 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
377e53bb
JL		 4324}
4325
4326// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
3e202231 43278.0xfe+8.0x7a+4.RM2,4.RN0!RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
377e53bb
JL		 4328"mov"
4329*am33
4330{
4331 int srcreg, dstreg;
4332
4333 PC = cia;
9c55817e
JL		 4334 srcreg = translate_rreg (SD_, RM2);
4335 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 4336 store_word (State.regs[dstreg], State.regs[srcreg]);
4337 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
377e53bb
JL		 4338}
4339
3e75ff7e
JL		 4340
4341// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
43428.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4343"mov"
4344*am33
4345{
4346 int dstreg;
4347
4348 PC = cia;
9c55817e 4349 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4350 State.regs[dstreg] = load_word (State.regs[REG_SP]
4351 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4352}
4353
4354// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
43558.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4356"mov"
4357*am33
4358{
4359 int srcreg;
4360
4361 PC = cia;
9c55817e 4362 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4363 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4364 State.regs[srcreg]);
4365}
4366
4367// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
43688.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4369"movbu"
4370*am33
4371{
4372 int dstreg;
4373
4374 PC = cia;
9c55817e 4375 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4376 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4377 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4378}
4379
4380// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
43818.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4382"movbu"
4383*am33
4384{
4385 int srcreg;
4386
4387 PC = cia;
9c55817e 4388 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4389 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4390 State.regs[srcreg]);
4391}
4392
4393// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
43948.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4395"movhu"
4396*am33
4397{
4398 int dstreg;
4399
4400 PC = cia;
9c55817e 4401 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4402 State.regs[dstreg] = load_half (State.regs[REG_SP]
4403 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4404}
4405
4406// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
44078.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4408"movhu"
4409*am33
4410{
4411 int srcreg;
4412
4413 PC = cia;
9c55817e 4414 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4415 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4416 State.regs[srcreg]);
4417}
4418
4419
377e53bb 4420// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
3e202231 44218.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
377e53bb
JL		 4422"movhu"
4423*am33
4424{
4425 int srcreg, dstreg;
4426
4427 PC = cia;
9c55817e
JL		 4428 srcreg = translate_rreg (SD_, RM0);
4429 dstreg = translate_rreg (SD_, RN2);
6ae1456e
JL		 4430 State.regs[dstreg] = load_half (State.regs[srcreg]);
4431 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
377e53bb
JL		 4432}
4433
4434// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
3e202231 44358.0xfe+8.0xfa+4.RM2,4.RN0!RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
377e53bb
JL		 4436"movhu"
4437*am33
4438{
4439 int srcreg, dstreg;
4440
4441 PC = cia;
9c55817e
JL		 4442 srcreg = translate_rreg (SD_, RM2);
4443 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 4444 store_half (State.regs[dstreg], State.regs[srcreg]);
4445 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
377e53bb
JL		 4446}
4447
3e75ff7e 4448
4b6651c9
JL		 4449// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
44508.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
4451"mac"
4452*am33
4453{
4454 int srcreg, imm;
4455 long long temp, sum;
4456 int c, v;
4457
4458 PC = cia;
4459 srcreg = translate_rreg (SD_, RN0);
4460 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4461
4462 temp = ((signed64)(signed32)State.regs[srcreg]
4463 * (signed64)(signed32)imm);
4464 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4465 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4466 State.regs[REG_MCRL] = sum;
4467 temp >>= 32;
4468 temp &= 0xffffffff;
4469 sum = State.regs[REG_MCRH] + temp + c;
4470 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4471 && (temp & 0x80000000) != (sum & 0x80000000));
4472 State.regs[REG_MCRH] = sum;
4473 if (v)
4474 State.regs[REG_MCVF] = 1;
4475}
4476
4477// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
44788.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
4479"macu"
4480*am33
4481{
4482 int srcreg, imm;
4483 long long temp, sum;
4484 int c, v;
4485
4486 PC = cia;
4487 srcreg = translate_rreg (SD_, RN0);
4488 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4489
4490 temp = ((unsigned64)State.regs[srcreg]
4491 * (unsigned64)imm);
4492 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4493 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4494 State.regs[REG_MCRL] = sum;
4495 temp >>= 32;
4496 temp &= 0xffffffff;
4497 sum = State.regs[REG_MCRH] + temp + c;
4498 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4499 && (temp & 0x80000000) != (sum & 0x80000000));
4500 State.regs[REG_MCRH] = sum;
4501 if (v)
4502 State.regs[REG_MCVF] = 1;
4503}
4504
4505// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
45068.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
4507"macb"
4508*am33
4509{
4510 int srcreg, imm;
4511 long temp, sum;
4512 int v;
4513
4514 PC = cia;
4515 srcreg = translate_rreg (SD_, RN0);
4516 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4517
4518 temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
4519 * (signed32)(signed8)(imm & 0xff));
4520 sum = State.regs[REG_MCRL] + temp;
4521 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4522 && (temp & 0x80000000) != (sum & 0x80000000));
4523 State.regs[REG_MCRL] = sum;
4524 if (v)
4525 State.regs[REG_MCVF] = 1;
4526}
4527
4528// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
45298.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
4530"macbu"
4531*am33
4532{
4533 int srcreg, imm;
4534 long temp, sum;
4535 int v;
4536
4537 PC = cia;
4538 srcreg = translate_rreg (SD_, RN0);
4539 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4540
4541 temp = ((unsigned32)(State.regs[srcreg] & 0xff)
4542 * (unsigned32)(imm & 0xff));
4543 sum = State.regs[REG_MCRL] + temp;
4544 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4545 && (temp & 0x80000000) != (sum & 0x80000000));
4546 State.regs[REG_MCRL] = sum;
4547 if (v)
4548 State.regs[REG_MCVF] = 1;
4549}
4550
4551// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
45528.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
4553"mach"
4554*am33
4555{
4556 int srcreg, imm;
4557 long temp, sum;
4558 int v;
4559
4560 PC = cia;
4561 srcreg = translate_rreg (SD_, RN0);
4562 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4563
4564 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4565 * (signed32)(signed16)(imm & 0xffff));
4566 sum = State.regs[REG_MCRL] + temp;
4567 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4568 && (temp & 0x80000000) != (sum & 0x80000000));
4569 State.regs[REG_MCRL] = sum;
4570 if (v)
4571 State.regs[REG_MCVF] = 1;
4572}
4573
4574// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
45758.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
4576"machu"
4577*am33
4578{
4579 int srcreg, imm;
4580 long temp, sum;
4581 int v;
4582
4583 PC = cia;
4584 srcreg = translate_rreg (SD_, RN0);
4585 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4586
4587 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4588 * (unsigned32)(imm & 0xffff));
4589 sum = State.regs[REG_MCRL] + temp;
4590 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4591 && (temp & 0x80000000) != (sum & 0x80000000));
4592 State.regs[REG_MCRL] = sum;
4593 if (v)
4594 State.regs[REG_MCVF] = 1;
4595}
4596
4597// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
45988.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
4599"dmach"
4600*am33
4601{
4602 int srcreg, imm;
4603 long temp, temp2, sum;
4604 int v;
4605
4606 PC = cia;
4607 srcreg = translate_rreg (SD_, RN0);
4608 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4609
4610 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4611 * (signed32)(signed16)(imm & 0xffff));
4612 temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
4613 * (signed32)(signed16)((imm >> 16) & 0xffff));
4614 sum = temp + temp2 + State.regs[REG_MCRL];
4615 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4616 && (temp & 0x80000000) != (sum & 0x80000000));
4617 State.regs[REG_MCRL] = sum;
4618 if (v)
4619 State.regs[REG_MCVF] = 1;
4620}
4621
4622// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
46238.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
4624"dmachu"
4625*am33
4626{
4627 int srcreg, imm;
4628 long temp, temp2, sum;
4629 int v;
4630
4631 PC = cia;
4632 srcreg = translate_rreg (SD_, RN0);
4633 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4634
4635 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4636 * (unsigned32)(imm & 0xffff));
4637 temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
4638 * (unsigned32)((imm >> 16) & 0xffff));
4639 sum = temp + temp2 + State.regs[REG_MCRL];
4640 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4641 && (temp & 0x80000000) != (sum & 0x80000000));
4642 State.regs[REG_MCRL] = sum;
4643 if (v)
4644 State.regs[REG_MCVF] = 1;
4645}
4646
4647// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
46488.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
4649"dmulh"
4650*am33
4651{
4652 int imm, dstreg;
4653 long temp;
4654
4655 PC = cia;
4656 dstreg = translate_rreg (SD_, RN0);
4657 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4658
4659 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
4660 * (signed32)(signed16)(imm & 0xffff));
4661 State.regs[REG_MDRQ] = temp;
4662 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
4663 * (signed32)(signed16)((imm>>16) & 0xffff));
4664 State.regs[dstreg] = temp;
4665}
4666
4667// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
46688.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
4669"dmulhu"
4670*am33
4671{
4672 int imm, dstreg;
4673 long temp;
4674
4675 PC = cia;
4676 dstreg = translate_rreg (SD_, RN0);
4677 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4678
4679 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
4680 * (unsigned32)(imm & 0xffff));
4681 State.regs[REG_MDRQ] = temp;
4682 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
4683 * (unsigned32)((imm >>16) & 0xffff));
4684 State.regs[dstreg] = temp;
4685}
3e75ff7e
JL		 4686
4687// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
46888.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4689"mov"
4690*am33
4691{
4692 int dstreg;
4693
4694 PC = cia;
9c55817e 4695 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4696 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4697}
4698
4699// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
47008.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4701"mov"
4702*am33
4703{
4704 int srcreg;
4705
4706 PC = cia;
9c55817e 4707 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4708 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4709}
4710
4711// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
47128.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4713"movbu"
4714*am33
4715{
4716 int dstreg;
4717
4718 PC = cia;
9c55817e 4719 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4720 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4721}
4722
4723// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
47248.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4725"movbu"
4726*am33
4727{
4728 int srcreg;
4729
4730 PC = cia;
9c55817e 4731 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4732 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4733}
4734
4735// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
47368.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4737"movhu"
4738*am33
4739{
4740 int dstreg;
4741
4742 PC = cia;
9c55817e 4743 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4744 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4745}
4746
4747// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
47488.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4749"movhu"
4750*am33
4751{
4752 int srcreg;
4753
4754 PC = cia;
9c55817e 4755 srcreg = translate_rreg (SD_, RM2);
3e75ff7e 4756 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
0f7d7385
JL		 4757}
4758
0a785507
JL		 4759// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
47608.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_add
4761"add_add"
4762*am33
4763{
4764 int srcreg1, srcreg2, dstreg1, dstreg2;
4765
4766 PC = cia;
4767 srcreg1 = translate_rreg (SD_, RM1);
4768 srcreg2 = translate_rreg (SD_, RM2);
4769 dstreg1 = translate_rreg (SD_, RN1);
4770 dstreg2 = translate_rreg (SD_, RN2);
4771
4772 State.regs[dstreg1] += State.regs[srcreg1];
4773 State.regs[dstreg2] += State.regs[srcreg2];
4774}
4775
4776// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
47778.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_add
4778"add_add"
4779*am33
4780{
4781 int srcreg1, dstreg1, dstreg2;
4782
4783 PC = cia;
4784 srcreg1 = translate_rreg (SD_, RM1);
4785 dstreg1 = translate_rreg (SD_, RN1);
4786 dstreg2 = translate_rreg (SD_, RN2);
4787
4788 State.regs[dstreg1] += State.regs[srcreg1];
4789 State.regs[dstreg2] += EXTEND4 (IMM4);
4790}
4791
4792// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
47938.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_sub
4794"add_sub"
4795*am33
4796{
4797 int srcreg1, srcreg2, dstreg1, dstreg2;
4798
4799 PC = cia;
4800 srcreg1 = translate_rreg (SD_, RM1);
4801 srcreg2 = translate_rreg (SD_, RM2);
4802 dstreg1 = translate_rreg (SD_, RN1);
4803 dstreg2 = translate_rreg (SD_, RN2);
4804
4805 State.regs[dstreg1] += State.regs[srcreg1];
4806 State.regs[dstreg2] -= State.regs[srcreg2];
4807}
4808
4809// 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
48108.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_sub
4811"add_sub"
4812*am33
4813{
4814 int srcreg1, dstreg1, dstreg2;
4815
4816 PC = cia;
4817 srcreg1 = translate_rreg (SD_, RM1);
4818 dstreg1 = translate_rreg (SD_, RN1);
4819 dstreg2 = translate_rreg (SD_, RN2);
4820
4821 State.regs[dstreg1] += State.regs[srcreg1];
4822 State.regs[dstreg2] -= EXTEND4 (IMM4);
4823}
4824
4825// 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
48268.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_cmp
4827"add_cmp"
4828*am33
4829{
4830 int srcreg1, srcreg2, dstreg1, dstreg2;
4831
4832 PC = cia;
4833 srcreg1 = translate_rreg (SD_, RM1);
4834 srcreg2 = translate_rreg (SD_, RM2);
4835 dstreg1 = translate_rreg (SD_, RN1);
4836 dstreg2 = translate_rreg (SD_, RN2);
4837
4838 State.regs[dstreg1] += State.regs[srcreg1];
4839 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4840}
4841
4842// 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
48438.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_cmp
4844"add_cmp"
4845*am33
4846{
4847 int srcreg1, dstreg1, dstreg2;
4848
4849 PC = cia;
4850 srcreg1 = translate_rreg (SD_, RM1);
4851 dstreg1 = translate_rreg (SD_, RN1);
4852 dstreg2 = translate_rreg (SD_, RN2);
4853
4854 State.regs[dstreg1] += State.regs[srcreg1];
4855 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4856}
4857
4858// 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
48598.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_mov
4860"add_mov"
4861*am33
4862{
4863 int srcreg1, srcreg2, dstreg1, dstreg2;
4864
4865 PC = cia;
4866 srcreg1 = translate_rreg (SD_, RM1);
4867 srcreg2 = translate_rreg (SD_, RM2);
4868 dstreg1 = translate_rreg (SD_, RN1);
4869 dstreg2 = translate_rreg (SD_, RN2);
4870
4871 State.regs[dstreg1] += State.regs[srcreg1];
4872 State.regs[dstreg2] = State.regs[srcreg2];
4873}
4874
4875// 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
48768.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_mov
4877"add_mov"
4878*am33
4879{
4880 int srcreg1, dstreg1, dstreg2;
4881
4882 PC = cia;
4883 srcreg1 = translate_rreg (SD_, RM1);
4884 dstreg1 = translate_rreg (SD_, RN1);
4885 dstreg2 = translate_rreg (SD_, RN2);
4886
4887 State.regs[dstreg1] += State.regs[srcreg1];
4888 State.regs[dstreg2] = EXTEND4 (IMM4);
4889}
4890
4891// 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
48928.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asr
4893"add_asr"
4894*am33
4895{
4896 int srcreg1, srcreg2, dstreg1, dstreg2;
4897 signed int temp;
4898
4899 PC = cia;
4900 srcreg1 = translate_rreg (SD_, RM1);
4901 srcreg2 = translate_rreg (SD_, RM2);
4902 dstreg1 = translate_rreg (SD_, RN1);
4903 dstreg2 = translate_rreg (SD_, RN2);
4904
4905 State.regs[dstreg1] += State.regs[srcreg1];
4906 temp = State.regs[dstreg2];
4907 temp >>= State.regs[srcreg2];
4908 State.regs[dstreg2] = temp;
4909}
4910
4911// 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
49128.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asr
4913"add_asr"
4914*am33
4915{
4916 int srcreg1, dstreg1, dstreg2;
4917 signed int temp;
4918
4919 PC = cia;
4920 srcreg1 = translate_rreg (SD_, RM1);
4921 dstreg1 = translate_rreg (SD_, RN1);
4922 dstreg2 = translate_rreg (SD_, RN2);
4923
4924 State.regs[dstreg1] += State.regs[srcreg1];
4925 temp = State.regs[dstreg2];
4926 temp >>= IMM4;
4927 State.regs[dstreg2] = temp;
4928}
4929
4930// 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
49318.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_lsr
4932"add_lsr"
4933*am33
4934{
4935 int srcreg1, srcreg2, dstreg1, dstreg2;
4936
4937 PC = cia;
4938 srcreg1 = translate_rreg (SD_, RM1);
4939 srcreg2 = translate_rreg (SD_, RM2);
4940 dstreg1 = translate_rreg (SD_, RN1);
4941 dstreg2 = translate_rreg (SD_, RN2);
4942
4943 State.regs[dstreg1] += State.regs[srcreg1];
4944 State.regs[dstreg2] >>= State.regs[srcreg2];
4945}
4946
4947// 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
49488.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_lsr
4949"add_lsr"
4950*am33
4951{
4952 int srcreg1, dstreg1, dstreg2;
4953 signed int temp;
4954
4955 PC = cia;
4956 srcreg1 = translate_rreg (SD_, RM1);
4957 dstreg1 = translate_rreg (SD_, RN1);
4958 dstreg2 = translate_rreg (SD_, RN2);
4959
4960 State.regs[dstreg1] += State.regs[srcreg1];
4961 State.regs[dstreg2] >>= IMM4;
4962}
4963
4964
4965// 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
49668.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asl
4967"add_asl"
4968*am33
4969{
4970 int srcreg1, srcreg2, dstreg1, dstreg2;
4971
4972 PC = cia;
4973 srcreg1 = translate_rreg (SD_, RM1);
4974 srcreg2 = translate_rreg (SD_, RM2);
4975 dstreg1 = translate_rreg (SD_, RN1);
4976 dstreg2 = translate_rreg (SD_, RN2);
4977
4978 State.regs[dstreg1] += State.regs[srcreg1];
4979 State.regs[dstreg2] <<= State.regs[srcreg2];
4980}
4981
4982// 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
49838.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asl
4984"add_asl"
4985*am33
4986{
4987 int srcreg1, dstreg1, dstreg2;
4988 signed int temp;
4989
4990 PC = cia;
4991 srcreg1 = translate_rreg (SD_, RM1);
4992 dstreg1 = translate_rreg (SD_, RN1);
4993 dstreg2 = translate_rreg (SD_, RN2);
4994
4995 State.regs[dstreg1] += State.regs[srcreg1];
4996 State.regs[dstreg2] <<= IMM4;
4997}
4998
4999// 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
50008.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_add
5001"cmp_add"
5002*am33
5003{
5004 int srcreg1, srcreg2, dstreg1, dstreg2;
5005
5006 PC = cia;
5007 srcreg1 = translate_rreg (SD_, RM1);
5008 srcreg2 = translate_rreg (SD_, RM2);
5009 dstreg1 = translate_rreg (SD_, RN1);
5010 dstreg2 = translate_rreg (SD_, RN2);
5011
5012 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5013 State.regs[dstreg2] += State.regs[srcreg2];
5014}
5015
5016// 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
50178.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_add
5018"cmp_add"
5019*am33
5020{
5021 int srcreg1, dstreg1, dstreg2;
5022
5023 PC = cia;
5024 srcreg1 = translate_rreg (SD_, RM1);
5025 dstreg1 = translate_rreg (SD_, RN1);
5026 dstreg2 = translate_rreg (SD_, RN2);
5027
5028 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5029 State.regs[dstreg2] += EXTEND4 (IMM4);
5030}
5031
5032// 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
50338.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_sub
5034"cmp_sub"
5035*am33
5036{
5037 int srcreg1, srcreg2, dstreg1, dstreg2;
5038
5039 PC = cia;
5040 srcreg1 = translate_rreg (SD_, RM1);
5041 srcreg2 = translate_rreg (SD_, RM2);
5042 dstreg1 = translate_rreg (SD_, RN1);
5043 dstreg2 = translate_rreg (SD_, RN2);
5044
5045 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5046 State.regs[dstreg2] -= State.regs[srcreg2];
5047}
5048
5049// 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
50508.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_sub
5051"cmp_sub"
5052*am33
5053{
5054 int srcreg1, dstreg1, dstreg2;
5055
5056 PC = cia;
5057 srcreg1 = translate_rreg (SD_, RM1);
5058 dstreg1 = translate_rreg (SD_, RN1);
5059 dstreg2 = translate_rreg (SD_, RN2);
5060
5061 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5062 State.regs[dstreg2] -= EXTEND4 (IMM4);
5063}
5064
5065// 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
50668.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_mov
5067"cmp_mov"
5068*am33
5069{
5070 int srcreg1, srcreg2, dstreg1, dstreg2;
5071
5072 PC = cia;
5073 srcreg1 = translate_rreg (SD_, RM1);
5074 srcreg2 = translate_rreg (SD_, RM2);
5075 dstreg1 = translate_rreg (SD_, RN1);
5076 dstreg2 = translate_rreg (SD_, RN2);
5077
5078 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5079 State.regs[dstreg2] = State.regs[srcreg2];
5080}
5081
5082// 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
50838.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_mov
5084"cmp_mov"
5085*am33
5086{
5087 int srcreg1, dstreg1, dstreg2;
5088
5089 PC = cia;
5090 srcreg1 = translate_rreg (SD_, RM1);
5091 dstreg1 = translate_rreg (SD_, RN1);
5092 dstreg2 = translate_rreg (SD_, RN2);
5093
5094 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5095 State.regs[dstreg2] = EXTEND4 (IMM4);
5096}
5097
5098// 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
50998.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asr
5100"cmp_asr"
5101*am33
5102{
5103 int srcreg1, srcreg2, dstreg1, dstreg2;
5104 signed int temp;
5105
5106 PC = cia;
5107 srcreg1 = translate_rreg (SD_, RM1);
5108 srcreg2 = translate_rreg (SD_, RM2);
5109 dstreg1 = translate_rreg (SD_, RN1);
5110 dstreg2 = translate_rreg (SD_, RN2);
5111
5112 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5113 temp = State.regs[dstreg2];
5114 temp >>= State.regs[srcreg2];
5115 State.regs[dstreg2] = temp;
5116}
5117
5118// 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
51198.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asr
5120"cmp_asr"
5121*am33
5122{
5123 int srcreg1, dstreg1, dstreg2;
5124 signed int temp;
5125
5126 PC = cia;
5127 srcreg1 = translate_rreg (SD_, RM1);
5128 dstreg1 = translate_rreg (SD_, RN1);
5129 dstreg2 = translate_rreg (SD_, RN2);
5130
5131 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5132 temp = State.regs[dstreg2];
5133 temp >>= IMM4;
5134 State.regs[dstreg2] = temp;
5135}
5136
5137// 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
51388.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_lsr
5139"cmp_lsr"
5140*am33
5141{
5142 int srcreg1, srcreg2, dstreg1, dstreg2;
5143
5144 PC = cia;
5145 srcreg1 = translate_rreg (SD_, RM1);
5146 srcreg2 = translate_rreg (SD_, RM2);
5147 dstreg1 = translate_rreg (SD_, RN1);
5148 dstreg2 = translate_rreg (SD_, RN2);
5149
5150 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5151 State.regs[dstreg2] >>= State.regs[srcreg2];
5152}
5153
5154// 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
51558.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_lsr
5156"cmp_lsr"
5157*am33
5158{
5159 int srcreg1, dstreg1, dstreg2;
5160 signed int temp;
5161
5162 PC = cia;
5163 srcreg1 = translate_rreg (SD_, RM1);
5164 dstreg1 = translate_rreg (SD_, RN1);
5165 dstreg2 = translate_rreg (SD_, RN2);
5166
5167 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5168 State.regs[dstreg2] >>= IMM4;
5169}
5170
5171
5172// 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
51738.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asl
5174"cmp_asl"
5175*am33
5176{
5177 int srcreg1, srcreg2, dstreg1, dstreg2;
5178
5179 PC = cia;
5180 srcreg1 = translate_rreg (SD_, RM1);
5181 srcreg2 = translate_rreg (SD_, RM2);
5182 dstreg1 = translate_rreg (SD_, RN1);
5183 dstreg2 = translate_rreg (SD_, RN2);
5184
5185 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5186 State.regs[dstreg2] <<= State.regs[srcreg2];
5187}
5188
5189// 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
51908.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asl
5191"cmp_asl"
5192*am33
5193{
5194 int srcreg1, dstreg1, dstreg2;
5195 signed int temp;
5196
5197 PC = cia;
5198 srcreg1 = translate_rreg (SD_, RM1);
5199 dstreg1 = translate_rreg (SD_, RN1);
5200 dstreg2 = translate_rreg (SD_, RN2);
5201
5202 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5203 State.regs[dstreg2] <<= IMM4;
5204}
5205
5206// 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
52078.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_add
5208"sub_add"
5209*am33
5210{
5211 int srcreg1, srcreg2, dstreg1, dstreg2;
5212
5213 PC = cia;
5214 srcreg1 = translate_rreg (SD_, RM1);
5215 srcreg2 = translate_rreg (SD_, RM2);
5216 dstreg1 = translate_rreg (SD_, RN1);
5217 dstreg2 = translate_rreg (SD_, RN2);
5218
5219 State.regs[dstreg1] -= State.regs[srcreg1];
5220 State.regs[dstreg2] += State.regs[srcreg2];
5221}
5222
5223// 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
52248.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_add
5225"sub_add"
5226*am33
5227{
5228 int srcreg1, dstreg1, dstreg2;
5229
5230 PC = cia;
5231 srcreg1 = translate_rreg (SD_, RM1);
5232 dstreg1 = translate_rreg (SD_, RN1);
5233 dstreg2 = translate_rreg (SD_, RN2);
5234
5235 State.regs[dstreg1] -= State.regs[srcreg1];
5236 State.regs[dstreg2] += EXTEND4 (IMM4);
5237}
5238
5239// 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
52408.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_sub
5241"sub_sub"
5242*am33
5243{
5244 int srcreg1, srcreg2, dstreg1, dstreg2;
5245
5246 PC = cia;
5247 srcreg1 = translate_rreg (SD_, RM1);
5248 srcreg2 = translate_rreg (SD_, RM2);
5249 dstreg1 = translate_rreg (SD_, RN1);
5250 dstreg2 = translate_rreg (SD_, RN2);
5251
5252 State.regs[dstreg1] -= State.regs[srcreg1];
5253 State.regs[dstreg2] -= State.regs[srcreg2];
5254}
5255
5256// 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
52578.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_sub
5258"sub_sub"
5259*am33
5260{
5261 int srcreg1, dstreg1, dstreg2;
5262
5263 PC = cia;
5264 srcreg1 = translate_rreg (SD_, RM1);
5265 dstreg1 = translate_rreg (SD_, RN1);
5266 dstreg2 = translate_rreg (SD_, RN2);
5267
5268 State.regs[dstreg1] -= State.regs[srcreg1];
5269 State.regs[dstreg2] -= EXTEND4 (IMM4);
5270}
5271
5272// 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
52738.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_cmp
5274"sub_cmp"
5275*am33
5276{
5277 int srcreg1, srcreg2, dstreg1, dstreg2;
5278
5279 PC = cia;
5280 srcreg1 = translate_rreg (SD_, RM1);
5281 srcreg2 = translate_rreg (SD_, RM2);
5282 dstreg1 = translate_rreg (SD_, RN1);
5283 dstreg2 = translate_rreg (SD_, RN2);
5284
5285 State.regs[dstreg1] -= State.regs[srcreg1];
5286 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5287}
5288
5289// 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
52908.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_cmp
5291"sub_cmp"
5292*am33
5293{
5294 int srcreg1, dstreg1, dstreg2;
5295
5296 PC = cia;
5297 srcreg1 = translate_rreg (SD_, RM1);
5298 dstreg1 = translate_rreg (SD_, RN1);
5299 dstreg2 = translate_rreg (SD_, RN2);
5300
5301 State.regs[dstreg1] -= State.regs[srcreg1];
5302 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5303}
5304
5305// 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
53068.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_mov
5307"sub_mov"
5308*am33
5309{
5310 int srcreg1, srcreg2, dstreg1, dstreg2;
5311
5312 PC = cia;
5313 srcreg1 = translate_rreg (SD_, RM1);
5314 srcreg2 = translate_rreg (SD_, RM2);
5315 dstreg1 = translate_rreg (SD_, RN1);
5316 dstreg2 = translate_rreg (SD_, RN2);
5317
5318 State.regs[dstreg1] -= State.regs[srcreg1];
5319 State.regs[dstreg2] = State.regs[srcreg2];
5320}
5321
5322// 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
53238.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_mov
5324"sub_mov"
5325*am33
5326{
5327 int srcreg1, dstreg1, dstreg2;
5328
5329 PC = cia;
5330 srcreg1 = translate_rreg (SD_, RM1);
5331 dstreg1 = translate_rreg (SD_, RN1);
5332 dstreg2 = translate_rreg (SD_, RN2);
5333
5334 State.regs[dstreg1] -= State.regs[srcreg1];
5335 State.regs[dstreg2] = EXTEND4 (IMM4);
5336}
5337
5338// 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
53398.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asr
5340"sub_asr"
5341*am33
5342{
5343 int srcreg1, srcreg2, dstreg1, dstreg2;
5344 signed int temp;
5345
5346 PC = cia;
5347 srcreg1 = translate_rreg (SD_, RM1);
5348 srcreg2 = translate_rreg (SD_, RM2);
5349 dstreg1 = translate_rreg (SD_, RN1);
5350 dstreg2 = translate_rreg (SD_, RN2);
5351
5352 State.regs[dstreg1] -= State.regs[srcreg1];
5353 temp = State.regs[dstreg2];
5354 temp >>= State.regs[srcreg2];
5355 State.regs[dstreg2] = temp;
5356}
5357
5358// 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
53598.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asr
5360"sub_asr"
5361*am33
5362{
5363 int srcreg1, dstreg1, dstreg2;
5364 signed int temp;
5365
5366 PC = cia;
5367 srcreg1 = translate_rreg (SD_, RM1);
5368 dstreg1 = translate_rreg (SD_, RN1);
5369 dstreg2 = translate_rreg (SD_, RN2);
5370
5371 State.regs[dstreg1] -= State.regs[srcreg1];
5372 temp = State.regs[dstreg2];
5373 temp >>= IMM4;
5374 State.regs[dstreg2] = temp;
5375}
5376
5377// 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
53788.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_lsr
5379"sub_lsr"
5380*am33
5381{
5382 int srcreg1, srcreg2, dstreg1, dstreg2;
5383
5384 PC = cia;
5385 srcreg1 = translate_rreg (SD_, RM1);
5386 srcreg2 = translate_rreg (SD_, RM2);
5387 dstreg1 = translate_rreg (SD_, RN1);
5388 dstreg2 = translate_rreg (SD_, RN2);
5389
5390 State.regs[dstreg1] -= State.regs[srcreg1];
5391 State.regs[dstreg2] >>= State.regs[srcreg2];
5392}
5393
5394// 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
53958.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_lsr
5396"sub_lsr"
5397*am33
5398{
5399 int srcreg1, dstreg1, dstreg2;
5400 signed int temp;
5401
5402 PC = cia;
5403 srcreg1 = translate_rreg (SD_, RM1);
5404 dstreg1 = translate_rreg (SD_, RN1);
5405 dstreg2 = translate_rreg (SD_, RN2);
5406
5407 State.regs[dstreg1] -= State.regs[srcreg1];
5408 State.regs[dstreg2] >>= IMM4;
5409}
5410
5411
5412// 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
54138.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asl
5414"sub_asl"
5415*am33
5416{
5417 int srcreg1, srcreg2, dstreg1, dstreg2;
5418
5419 PC = cia;
5420 srcreg1 = translate_rreg (SD_, RM1);
5421 srcreg2 = translate_rreg (SD_, RM2);
5422 dstreg1 = translate_rreg (SD_, RN1);
5423 dstreg2 = translate_rreg (SD_, RN2);
5424
5425 State.regs[dstreg1] -= State.regs[srcreg1];
5426 State.regs[dstreg2] <<= State.regs[srcreg2];
5427}
5428
5429// 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
54308.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asl
5431"sub_asl"
5432*am33
5433{
5434 int srcreg1, dstreg1, dstreg2;
5435 signed int temp;
5436
5437 PC = cia;
5438 srcreg1 = translate_rreg (SD_, RM1);
5439 dstreg1 = translate_rreg (SD_, RN1);
5440 dstreg2 = translate_rreg (SD_, RN2);
5441
5442 State.regs[dstreg1] -= State.regs[srcreg1];
5443 State.regs[dstreg2] <<= IMM4;
5444}
5445
5446// 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
54478.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_add
5448"mov_add"
5449*am33
5450{
5451 int srcreg1, srcreg2, dstreg1, dstreg2;
5452
5453 PC = cia;
5454 srcreg1 = translate_rreg (SD_, RM1);
5455 srcreg2 = translate_rreg (SD_, RM2);
5456 dstreg1 = translate_rreg (SD_, RN1);
5457 dstreg2 = translate_rreg (SD_, RN2);
5458
5459 State.regs[dstreg1] = State.regs[srcreg1];
5460 State.regs[dstreg2] += State.regs[srcreg2];
5461}
5462
5463// 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
54648.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_add
5465"mov_add"
5466*am33
5467{
5468 int srcreg1, dstreg1, dstreg2;
5469
5470 PC = cia;
5471 srcreg1 = translate_rreg (SD_, RM1);
5472 dstreg1 = translate_rreg (SD_, RN1);
5473 dstreg2 = translate_rreg (SD_, RN2);
5474
5475 State.regs[dstreg1] = State.regs[srcreg1];
5476 State.regs[dstreg2] += EXTEND4 (IMM4);
5477}
5478
5479// 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
54808.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_sub
5481"mov_sub"
5482*am33
5483{
5484 int srcreg1, srcreg2, dstreg1, dstreg2;
5485
5486 PC = cia;
5487 srcreg1 = translate_rreg (SD_, RM1);
5488 srcreg2 = translate_rreg (SD_, RM2);
5489 dstreg1 = translate_rreg (SD_, RN1);
5490 dstreg2 = translate_rreg (SD_, RN2);
5491
5492 State.regs[dstreg1] = State.regs[srcreg1];
5493 State.regs[dstreg2] -= State.regs[srcreg2];
5494}
5495
5496// 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
54978.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_sub
5498"mov_sub"
5499*am33
5500{
5501 int srcreg1, dstreg1, dstreg2;
5502
5503 PC = cia;
5504 srcreg1 = translate_rreg (SD_, RM1);
5505 dstreg1 = translate_rreg (SD_, RN1);
5506 dstreg2 = translate_rreg (SD_, RN2);
5507
5508 State.regs[dstreg1] = State.regs[srcreg1];
5509 State.regs[dstreg2] -= EXTEND4 (IMM4);
5510}
5511
5512// 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
55138.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_cmp
5514"mov_cmp"
5515*am33
5516{
5517 int srcreg1, srcreg2, dstreg1, dstreg2;
5518
5519 PC = cia;
5520 srcreg1 = translate_rreg (SD_, RM1);
5521 srcreg2 = translate_rreg (SD_, RM2);
5522 dstreg1 = translate_rreg (SD_, RN1);
5523 dstreg2 = translate_rreg (SD_, RN2);
5524
5525 State.regs[dstreg1] = State.regs[srcreg1];
5526 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5527}
5528
5529// 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
55308.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_cmp
5531"mov_cmp"
5532*am33
5533{
5534 int srcreg1, dstreg1, dstreg2;
5535
5536 PC = cia;
5537 srcreg1 = translate_rreg (SD_, RM1);
5538 dstreg1 = translate_rreg (SD_, RN1);
5539 dstreg2 = translate_rreg (SD_, RN2);
5540
5541 State.regs[dstreg1] = State.regs[srcreg1];
5542 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5543}
5544
5545// 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
55468.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_mov
5547"mov_mov"
5548*am33
5549{
5550 int srcreg1, srcreg2, dstreg1, dstreg2;
5551
5552 PC = cia;
5553 srcreg1 = translate_rreg (SD_, RM1);
5554 srcreg2 = translate_rreg (SD_, RM2);
5555 dstreg1 = translate_rreg (SD_, RN1);
5556 dstreg2 = translate_rreg (SD_, RN2);
5557
5558 State.regs[dstreg1] = State.regs[srcreg1];
5559 State.regs[dstreg2] = State.regs[srcreg2];
5560}
5561
5562// 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
55638.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_mov
5564"mov_mov"
5565*am33
5566{
5567 int srcreg1, dstreg1, dstreg2;
5568
5569 PC = cia;
5570 srcreg1 = translate_rreg (SD_, RM1);
5571 dstreg1 = translate_rreg (SD_, RN1);
5572 dstreg2 = translate_rreg (SD_, RN2);
5573
5574 State.regs[dstreg1] = State.regs[srcreg1];
5575 State.regs[dstreg2] = EXTEND4 (IMM4);
5576}
5577
5578// 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
55798.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asr
5580"mov_asr"
5581*am33
5582{
5583 int srcreg1, srcreg2, dstreg1, dstreg2;
5584 signed int temp;
5585
5586 PC = cia;
5587 srcreg1 = translate_rreg (SD_, RM1);
5588 srcreg2 = translate_rreg (SD_, RM2);
5589 dstreg1 = translate_rreg (SD_, RN1);
5590 dstreg2 = translate_rreg (SD_, RN2);
5591
5592 State.regs[dstreg1] = State.regs[srcreg1];
5593 temp = State.regs[dstreg2];
5594 temp >>= State.regs[srcreg2];
5595 State.regs[dstreg2] = temp;
5596}
5597
5598// 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
55998.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asr
5600"mov_asr"
5601*am33
5602{
5603 int srcreg1, dstreg1, dstreg2;
5604 signed int temp;
5605
5606 PC = cia;
5607 srcreg1 = translate_rreg (SD_, RM1);
5608 dstreg1 = translate_rreg (SD_, RN1);
5609 dstreg2 = translate_rreg (SD_, RN2);
5610
5611 State.regs[dstreg1] = State.regs[srcreg1];
5612 temp = State.regs[dstreg2];
5613 temp >>= IMM4;
5614 State.regs[dstreg2] = temp;
5615}
5616
5617// 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
56188.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_lsr
5619"mov_lsr"
5620*am33
5621{
5622 int srcreg1, srcreg2, dstreg1, dstreg2;
5623
5624 PC = cia;
5625 srcreg1 = translate_rreg (SD_, RM1);
5626 srcreg2 = translate_rreg (SD_, RM2);
5627 dstreg1 = translate_rreg (SD_, RN1);
5628 dstreg2 = translate_rreg (SD_, RN2);
5629
5630 State.regs[dstreg1] = State.regs[srcreg1];
5631 State.regs[dstreg2] >>= State.regs[srcreg2];
5632}
5633
5634// 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
56358.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_lsr
5636"mov_lsr"
5637*am33
5638{
5639 int srcreg1, dstreg1, dstreg2;
5640 signed int temp;
5641
5642 PC = cia;
5643 srcreg1 = translate_rreg (SD_, RM1);
5644 dstreg1 = translate_rreg (SD_, RN1);
5645 dstreg2 = translate_rreg (SD_, RN2);
5646
5647 State.regs[dstreg1] = State.regs[srcreg1];
5648 State.regs[dstreg2] >>= IMM4;
5649}
5650
5651
5652// 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
56538.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asl
5654"mov_asl"
5655*am33
5656{
5657 int srcreg1, srcreg2, dstreg1, dstreg2;
5658
5659 PC = cia;
5660 srcreg1 = translate_rreg (SD_, RM1);
5661 srcreg2 = translate_rreg (SD_, RM2);
5662 dstreg1 = translate_rreg (SD_, RN1);
5663 dstreg2 = translate_rreg (SD_, RN2);
5664
5665 State.regs[dstreg1] = State.regs[srcreg1];
5666 State.regs[dstreg2] <<= State.regs[srcreg2];
5667}
5668
5669// 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
56708.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asl
5671"mov_asl"
5672*am33
5673{
5674 int srcreg1, dstreg1, dstreg2;
5675 signed int temp;
5676
5677 PC = cia;
5678 srcreg1 = translate_rreg (SD_, RM1);
5679 dstreg1 = translate_rreg (SD_, RN1);
5680 dstreg2 = translate_rreg (SD_, RN2);
5681
5682 State.regs[dstreg1] = State.regs[srcreg1];
5683 State.regs[dstreg2] <<= IMM4;
5684}
5685
5686// 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
56878.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_add
5688"add_add"
5689*am33
5690{
5691 int srcreg2, dstreg1, dstreg2;
5692
5693 PC = cia;
5694 srcreg2 = translate_rreg (SD_, RM2);
5695 dstreg1 = translate_rreg (SD_, RN1);
5696 dstreg2 = translate_rreg (SD_, RN2);
5697
5698 State.regs[dstreg1] += EXTEND4 (IMM4A);
5699 State.regs[dstreg2] += State.regs[srcreg2];
5700}
5701
5702// 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
57038.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_add
5704"add_add"
5705*am33
5706{
5707 int dstreg1, dstreg2;
5708
5709 PC = cia;
5710 dstreg1 = translate_rreg (SD_, RN1);
5711 dstreg2 = translate_rreg (SD_, RN2);
5712
5713 State.regs[dstreg1] += EXTEND4 (IMM4A);
5714 State.regs[dstreg2] += EXTEND4 (IMM4);
5715}
5716
5717// 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
57188.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_sub
5719"add_sub"
5720*am33
5721{
5722 int srcreg2, dstreg1, dstreg2;
5723
5724 PC = cia;
5725 srcreg2 = translate_rreg (SD_, RM2);
5726 dstreg1 = translate_rreg (SD_, RN1);
5727 dstreg2 = translate_rreg (SD_, RN2);
5728
5729 State.regs[dstreg1] += EXTEND4 (IMM4A);
5730 State.regs[dstreg2] -= State.regs[srcreg2];
5731}
5732
5733// 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
57348.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_sub
5735"add_sub"
5736*am33
5737{
5738 int dstreg1, dstreg2;
5739
5740 PC = cia;
5741 dstreg1 = translate_rreg (SD_, RN1);
5742 dstreg2 = translate_rreg (SD_, RN2);
5743
5744 State.regs[dstreg1] += EXTEND4 (IMM4A);
5745 State.regs[dstreg2] -= EXTEND4 (IMM4);
5746}
5747
5748// 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
57498.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_cmp
5750"add_cmp"
5751*am33
5752{
5753 int srcreg2, dstreg1, dstreg2;
5754
5755 PC = cia;
5756 srcreg2 = translate_rreg (SD_, RM2);
5757 dstreg1 = translate_rreg (SD_, RN1);
5758 dstreg2 = translate_rreg (SD_, RN2);
5759
5760 State.regs[dstreg1] += EXTEND4 (IMM4A);
5761 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5762}
5763
5764// 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
57658.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_cmp
5766"add_cmp"
5767*am33
5768{
5769 int dstreg1, dstreg2;
5770
5771 PC = cia;
5772 dstreg1 = translate_rreg (SD_, RN1);
5773 dstreg2 = translate_rreg (SD_, RN2);
5774
5775 State.regs[dstreg1] += EXTEND4 (IMM4A);
5776 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5777}
5778
5779// 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
57808.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_mov
5781"add_mov"
5782*am33
5783{
5784 int srcreg2, dstreg1, dstreg2;
5785
5786 PC = cia;
5787 srcreg2 = translate_rreg (SD_, RM2);
5788 dstreg1 = translate_rreg (SD_, RN1);
5789 dstreg2 = translate_rreg (SD_, RN2);
5790
5791 State.regs[dstreg1] += EXTEND4 (IMM4A);
5792 State.regs[dstreg2] = State.regs[srcreg2];
5793}
5794
5795// 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
57968.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_mov
5797"add_mov"
5798*am33
5799{
5800 int dstreg1, dstreg2;
5801
5802 PC = cia;
5803 dstreg1 = translate_rreg (SD_, RN1);
5804 dstreg2 = translate_rreg (SD_, RN2);
5805
5806 State.regs[dstreg1] += EXTEND4 (IMM4A);
5807 State.regs[dstreg2] = EXTEND4 (IMM4);
5808}
5809
5810// 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
58118.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asr
5812"add_asr"
5813*am33
5814{
5815 int srcreg2, dstreg1, dstreg2;
5816 signed int temp;
5817
5818 PC = cia;
5819 srcreg2 = translate_rreg (SD_, RM2);
5820 dstreg1 = translate_rreg (SD_, RN1);
5821 dstreg2 = translate_rreg (SD_, RN2);
5822
5823 State.regs[dstreg1] += EXTEND4 (IMM4A);
5824 temp = State.regs[dstreg2];
5825 temp >>= State.regs[srcreg2];
5826 State.regs[dstreg2] = temp;
5827}
5828
5829// 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
58308.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asr
5831"add_asr"
5832*am33
5833{
5834 int dstreg1, dstreg2;
5835 signed int temp;
5836
5837 PC = cia;
5838 dstreg1 = translate_rreg (SD_, RN1);
5839 dstreg2 = translate_rreg (SD_, RN2);
5840
5841 State.regs[dstreg1] += EXTEND4 (IMM4A);
5842 temp = State.regs[dstreg2];
5843 temp >>= IMM4;
5844 State.regs[dstreg2] = temp;
5845}
5846
5847// 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
58488.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_lsr
5849"add_lsr"
5850*am33
5851{
5852 int srcreg2, dstreg1, dstreg2;
5853
5854 PC = cia;
5855 srcreg2 = translate_rreg (SD_, RM2);
5856 dstreg1 = translate_rreg (SD_, RN1);
5857 dstreg2 = translate_rreg (SD_, RN2);
5858
5859 State.regs[dstreg1] += EXTEND4 (IMM4A);
5860 State.regs[dstreg2] >>= State.regs[srcreg2];
5861}
5862
5863// 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
58648.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_lsr
5865"add_lsr"
5866*am33
5867{
5868 int dstreg1, dstreg2;
5869 signed int temp;
5870
5871 PC = cia;
5872 dstreg1 = translate_rreg (SD_, RN1);
5873 dstreg2 = translate_rreg (SD_, RN2);
5874
5875 State.regs[dstreg1] += EXTEND4 (IMM4A);
5876 State.regs[dstreg2] >>= IMM4;
5877}
5878
5879
5880// 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
58818.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asl
5882"add_asl"
5883*am33
5884{
5885 int srcreg2, dstreg1, dstreg2;
5886
5887 PC = cia;
5888 srcreg2 = translate_rreg (SD_, RM2);
5889 dstreg1 = translate_rreg (SD_, RN1);
5890 dstreg2 = translate_rreg (SD_, RN2);
5891
5892 State.regs[dstreg1] += EXTEND4 (IMM4A);
5893 State.regs[dstreg2] <<= State.regs[srcreg2];
5894}
5895
5896// 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
58978.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asl
5898"add_asl"
5899*am33
5900{
5901 int dstreg1, dstreg2;
5902 signed int temp;
5903
5904 PC = cia;
5905 dstreg1 = translate_rreg (SD_, RN1);
5906 dstreg2 = translate_rreg (SD_, RN2);
5907
5908 State.regs[dstreg1] += EXTEND4 (IMM4A);
5909 State.regs[dstreg2] <<= IMM4;
5910}
5911
5912// 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
59138.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_add
5914"cmp_add"
5915*am33
5916{
5917 int srcreg2, dstreg1, dstreg2;
5918
5919 PC = cia;
5920 srcreg2 = translate_rreg (SD_, RM2);
5921 dstreg1 = translate_rreg (SD_, RN1);
5922 dstreg2 = translate_rreg (SD_, RN2);
5923
5924 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5925 State.regs[dstreg2] += State.regs[srcreg2];
5926}
5927
5928// 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
59298.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_add
5930"cmp_add"
5931*am33
5932{
5933 int dstreg1, dstreg2;
5934
5935 PC = cia;
5936 dstreg1 = translate_rreg (SD_, RN1);
5937 dstreg2 = translate_rreg (SD_, RN2);
5938
5939 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5940 State.regs[dstreg2] += EXTEND4 (IMM4);
5941}
5942
5943// 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
59448.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_sub
5945"cmp_sub"
5946*am33
5947{
5948 int srcreg2, dstreg1, dstreg2;
5949
5950 PC = cia;
5951 srcreg2 = translate_rreg (SD_, RM2);
5952 dstreg1 = translate_rreg (SD_, RN1);
5953 dstreg2 = translate_rreg (SD_, RN2);
5954
5955 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5956 State.regs[dstreg2] -= State.regs[srcreg2];
5957}
5958
5959// 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
59608.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_sub
5961"cmp_sub"
5962*am33
5963{
5964 int dstreg1, dstreg2;
5965
5966 PC = cia;
5967 dstreg1 = translate_rreg (SD_, RN1);
5968 dstreg2 = translate_rreg (SD_, RN2);
5969
5970 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5971 State.regs[dstreg2] -= EXTEND4 (IMM4);
5972}
5973
5974// 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
59758.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_mov
5976"cmp_mov"
5977*am33
5978{
5979 int srcreg2, dstreg1, dstreg2;
5980
5981 PC = cia;
5982 srcreg2 = translate_rreg (SD_, RM2);
5983 dstreg1 = translate_rreg (SD_, RN1);
5984 dstreg2 = translate_rreg (SD_, RN2);
5985
5986 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5987 State.regs[dstreg2] = State.regs[srcreg2];
5988}
5989
5990// 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
59918.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_mov
5992"cmp_mov"
5993*am33
5994{
5995 int dstreg1, dstreg2;
5996
5997 PC = cia;
5998 dstreg1 = translate_rreg (SD_, RN1);
5999 dstreg2 = translate_rreg (SD_, RN2);
6000
6001 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6002 State.regs[dstreg2] = EXTEND4 (IMM4);
6003}
6004
6005// 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
60068.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asr
6007"cmp_asr"
6008*am33
6009{
6010 int srcreg2, dstreg1, dstreg2;
6011 signed int temp;
6012
6013 PC = cia;
6014 srcreg2 = translate_rreg (SD_, RM2);
6015 dstreg1 = translate_rreg (SD_, RN1);
6016 dstreg2 = translate_rreg (SD_, RN2);
6017
6018 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6019 temp = State.regs[dstreg2];
6020 temp >>= State.regs[srcreg2];
6021 State.regs[dstreg2] = temp;
6022}
6023
6024// 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
60258.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asr
6026"cmp_asr"
6027*am33
6028{
6029 int dstreg1, dstreg2;
6030 signed int temp;
6031
6032 PC = cia;
6033 dstreg1 = translate_rreg (SD_, RN1);
6034 dstreg2 = translate_rreg (SD_, RN2);
6035
6036 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6037 temp = State.regs[dstreg2];
6038 temp >>= IMM4;
6039 State.regs[dstreg2] = temp;
6040}
6041
6042// 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
60438.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_lsr
6044"cmp_lsr"
6045*am33
6046{
6047 int srcreg2, dstreg1, dstreg2;
6048
6049 PC = cia;
6050 srcreg2 = translate_rreg (SD_, RM2);
6051 dstreg1 = translate_rreg (SD_, RN1);
6052 dstreg2 = translate_rreg (SD_, RN2);
6053
6054 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6055 State.regs[dstreg2] >>= State.regs[srcreg2];
6056}
6057
6058// 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
60598.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_lsr
6060"cmp_lsr"
6061*am33
6062{
6063 int dstreg1, dstreg2;
6064 signed int temp;
6065
6066 PC = cia;
6067 dstreg1 = translate_rreg (SD_, RN1);
6068 dstreg2 = translate_rreg (SD_, RN2);
6069
6070 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6071 State.regs[dstreg2] >>= IMM4;
6072}
6073
6074
6075// 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
60768.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asl
6077"cmp_asl"
6078*am33
6079{
6080 int srcreg2, dstreg1, dstreg2;
6081
6082 PC = cia;
6083 srcreg2 = translate_rreg (SD_, RM2);
6084 dstreg1 = translate_rreg (SD_, RN1);
6085 dstreg2 = translate_rreg (SD_, RN2);
6086
6087 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6088 State.regs[dstreg2] <<= State.regs[srcreg2];
6089}
6090
6091// 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
60928.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asl
6093"cmp_asl"
6094*am33
6095{
6096 int dstreg1, dstreg2;
6097 signed int temp;
6098
6099 PC = cia;
6100 dstreg1 = translate_rreg (SD_, RN1);
6101 dstreg2 = translate_rreg (SD_, RN2);
6102
6103 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6104 State.regs[dstreg2] <<= IMM4;
6105}
6106
6107// 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
61088.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_add
6109"sub_add"
6110*am33
6111{
6112 int srcreg2, dstreg1, dstreg2;
6113
6114 PC = cia;
6115 srcreg2 = translate_rreg (SD_, RM2);
6116 dstreg1 = translate_rreg (SD_, RN1);
6117 dstreg2 = translate_rreg (SD_, RN2);
6118
6119 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6120 State.regs[dstreg2] += State.regs[srcreg2];
6121}
6122
6123// 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
61248.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_add
6125"sub_add"
6126*am33
6127{
6128 int dstreg1, dstreg2;
6129
6130 PC = cia;
6131 dstreg1 = translate_rreg (SD_, RN1);
6132 dstreg2 = translate_rreg (SD_, RN2);
6133
6134 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6135 State.regs[dstreg2] += EXTEND4 (IMM4);
6136}
6137
6138// 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
61398.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_sub
6140"sub_sub"
6141*am33
6142{
6143 int srcreg2, dstreg1, dstreg2;
6144
6145 PC = cia;
6146 srcreg2 = translate_rreg (SD_, RM2);
6147 dstreg1 = translate_rreg (SD_, RN1);
6148 dstreg2 = translate_rreg (SD_, RN2);
6149
6150 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6151 State.regs[dstreg2] -= State.regs[srcreg2];
6152}
6153
6154// 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
61558.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_sub
6156"sub_sub"
6157*am33
6158{
6159 int dstreg1, dstreg2;
6160
6161 PC = cia;
6162 dstreg1 = translate_rreg (SD_, RN1);
6163 dstreg2 = translate_rreg (SD_, RN2);
6164
6165 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6166 State.regs[dstreg2] -= EXTEND4 (IMM4);
6167}
6168
6169// 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
61708.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_cmp
6171"sub_cmp"
6172*am33
6173{
6174 int srcreg2, dstreg1, dstreg2;
6175
6176 PC = cia;
6177 srcreg2 = translate_rreg (SD_, RM2);
6178 dstreg1 = translate_rreg (SD_, RN1);
6179 dstreg2 = translate_rreg (SD_, RN2);
6180
6181 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6182 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6183}
6184
6185// 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
61868.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_cmp
6187"sub_cmp"
6188*am33
6189{
6190 int dstreg1, dstreg2;
6191
6192 PC = cia;
6193 dstreg1 = translate_rreg (SD_, RN1);
6194 dstreg2 = translate_rreg (SD_, RN2);
6195
6196 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6197 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6198}
6199
6200// 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
62018.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_mov
6202"sub_mov"
6203*am33
6204{
6205 int srcreg2, dstreg1, dstreg2;
6206
6207 PC = cia;
6208 srcreg2 = translate_rreg (SD_, RM2);
6209 dstreg1 = translate_rreg (SD_, RN1);
6210 dstreg2 = translate_rreg (SD_, RN2);
6211
6212 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6213 State.regs[dstreg2] = State.regs[srcreg2];
6214}
6215
6216// 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
62178.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_mov
6218"sub_mov"
6219*am33
6220{
6221 int dstreg1, dstreg2;
6222
6223 PC = cia;
6224 dstreg1 = translate_rreg (SD_, RN1);
6225 dstreg2 = translate_rreg (SD_, RN2);
6226
6227 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6228 State.regs[dstreg2] = EXTEND4 (IMM4);
6229}
6230
6231// 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
62328.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asr
6233"sub_asr"
6234*am33
6235{
6236 int srcreg2, dstreg1, dstreg2;
6237 signed int temp;
6238
6239 PC = cia;
6240 srcreg2 = translate_rreg (SD_, RM2);
6241 dstreg1 = translate_rreg (SD_, RN1);
6242 dstreg2 = translate_rreg (SD_, RN2);
6243
6244 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6245 temp = State.regs[dstreg2];
6246 temp >>= State.regs[srcreg2];
6247 State.regs[dstreg2] = temp;
6248}
6249
6250// 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
62518.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asr
6252"sub_asr"
6253*am33
6254{
6255 int dstreg1, dstreg2;
6256 signed int temp;
6257
6258 PC = cia;
6259 dstreg1 = translate_rreg (SD_, RN1);
6260 dstreg2 = translate_rreg (SD_, RN2);
6261
6262 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6263 temp = State.regs[dstreg2];
6264 temp >>= IMM4;
6265 State.regs[dstreg2] = temp;
6266}
6267
6268// 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
62698.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_lsr
6270"sub_lsr"
6271*am33
6272{
6273 int srcreg2, dstreg1, dstreg2;
6274
6275 PC = cia;
6276 srcreg2 = translate_rreg (SD_, RM2);
6277 dstreg1 = translate_rreg (SD_, RN1);
6278 dstreg2 = translate_rreg (SD_, RN2);
6279
6280 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6281 State.regs[dstreg2] >>= State.regs[srcreg2];
6282}
6283
6284// 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
62858.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_lsr
6286"sub_lsr"
6287*am33
6288{
6289 int dstreg1, dstreg2;
6290 signed int temp;
6291
6292 PC = cia;
6293 dstreg1 = translate_rreg (SD_, RN1);
6294 dstreg2 = translate_rreg (SD_, RN2);
6295
6296 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6297 State.regs[dstreg2] >>= IMM4;
6298}
6299
6300
6301// 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
63028.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asl
6303"sub_asl"
6304*am33
6305{
6306 int srcreg2, dstreg1, dstreg2;
6307
6308 PC = cia;
6309 srcreg2 = translate_rreg (SD_, RM2);
6310 dstreg1 = translate_rreg (SD_, RN1);
6311 dstreg2 = translate_rreg (SD_, RN2);
6312
6313 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6314 State.regs[dstreg2] <<= State.regs[srcreg2];
6315}
6316
6317// 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
63188.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asl
6319"sub_asl"
6320*am33
6321{
6322 int dstreg1, dstreg2;
6323 signed int temp;
6324
6325 PC = cia;
6326 dstreg1 = translate_rreg (SD_, RN1);
6327 dstreg2 = translate_rreg (SD_, RN2);
6328
6329 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6330 State.regs[dstreg2] <<= IMM4;
6331}
6332
6333// 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
63348.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_add
6335"mov_add"
6336*am33
6337{
6338 int srcreg2, dstreg1, dstreg2;
6339
6340 PC = cia;
6341 srcreg2 = translate_rreg (SD_, RM2);
6342 dstreg1 = translate_rreg (SD_, RN1);
6343 dstreg2 = translate_rreg (SD_, RN2);
6344
6345 State.regs[dstreg1] = EXTEND4 (IMM4A);
6346 State.regs[dstreg2] += State.regs[srcreg2];
6347}
6348
6349// 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
63508.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_add
6351"mov_add"
6352*am33
6353{
6354 int dstreg1, dstreg2;
6355
6356 PC = cia;
6357 dstreg1 = translate_rreg (SD_, RN1);
6358 dstreg2 = translate_rreg (SD_, RN2);
6359
6360 State.regs[dstreg1] = EXTEND4 (IMM4A);
6361 State.regs[dstreg2] += EXTEND4 (IMM4);
6362}
6363
6364// 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
63658.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_sub
6366"mov_sub"
6367*am33
6368{
6369 int srcreg2, dstreg1, dstreg2;
6370
6371 PC = cia;
6372 srcreg2 = translate_rreg (SD_, RM2);
6373 dstreg1 = translate_rreg (SD_, RN1);
6374 dstreg2 = translate_rreg (SD_, RN2);
6375
6376 State.regs[dstreg1] = EXTEND4 (IMM4A);
6377 State.regs[dstreg2] -= State.regs[srcreg2];
6378}
6379
6380// 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
63818.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_sub
6382"mov_sub"
6383*am33
6384{
6385 int dstreg1, dstreg2;
6386
6387 PC = cia;
6388 dstreg1 = translate_rreg (SD_, RN1);
6389 dstreg2 = translate_rreg (SD_, RN2);
6390
6391 State.regs[dstreg1] = EXTEND4 (IMM4A);
6392 State.regs[dstreg2] -= EXTEND4 (IMM4);
6393}
6394
6395// 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
63968.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_cmp
6397"mov_cmp"
6398*am33
6399{
6400 int srcreg2, dstreg1, dstreg2;
6401
6402 PC = cia;
6403 srcreg2 = translate_rreg (SD_, RM2);
6404 dstreg1 = translate_rreg (SD_, RN1);
6405 dstreg2 = translate_rreg (SD_, RN2);
6406
6407 State.regs[dstreg1] = EXTEND4 (IMM4A);
6408 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6409}
6410
6411// 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
64128.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_cmp
6413"mov_cmp"
6414*am33
6415{
6416 int dstreg1, dstreg2;
6417
6418 PC = cia;
6419 dstreg1 = translate_rreg (SD_, RN1);
6420 dstreg2 = translate_rreg (SD_, RN2);
6421
6422 State.regs[dstreg1] = EXTEND4 (IMM4A);
6423 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6424}
6425
6426// 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
64278.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_mov
6428"mov_mov"
6429*am33
6430{
6431 int srcreg2, dstreg1, dstreg2;
6432
6433 PC = cia;
6434 srcreg2 = translate_rreg (SD_, RM2);
6435 dstreg1 = translate_rreg (SD_, RN1);
6436 dstreg2 = translate_rreg (SD_, RN2);
6437
6438 State.regs[dstreg1] = EXTEND4 (IMM4A);
6439 State.regs[dstreg2] = State.regs[srcreg2];
6440}
6441
6442// 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
64438.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_mov
6444"mov_mov"
6445*am33
6446{
6447 int dstreg1, dstreg2;
6448
6449 PC = cia;
6450 dstreg1 = translate_rreg (SD_, RN1);
6451 dstreg2 = translate_rreg (SD_, RN2);
6452
6453 State.regs[dstreg1] = EXTEND4 (IMM4A);
6454 State.regs[dstreg2] = EXTEND4 (IMM4);
6455}
6456
6457// 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
64588.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asr
6459"mov_asr"
6460*am33
6461{
6462 int srcreg2, dstreg1, dstreg2;
6463 signed int temp;
6464
6465 PC = cia;
6466 srcreg2 = translate_rreg (SD_, RM2);
6467 dstreg1 = translate_rreg (SD_, RN1);
6468 dstreg2 = translate_rreg (SD_, RN2);
6469
6470 State.regs[dstreg1] = EXTEND4 (IMM4A);
6471 temp = State.regs[dstreg2];
6472 temp >>= State.regs[srcreg2];
6473 State.regs[dstreg2] = temp;
6474}
6475
6476// 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
64778.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asr
6478"mov_asr"
6479*am33
6480{
6481 int dstreg1, dstreg2;
6482 signed int temp;
6483
6484 PC = cia;
6485 dstreg1 = translate_rreg (SD_, RN1);
6486 dstreg2 = translate_rreg (SD_, RN2);
6487
6488 State.regs[dstreg1] = EXTEND4 (IMM4A);
6489 temp = State.regs[dstreg2];
6490 temp >>= IMM4;
6491 State.regs[dstreg2] = temp;
6492}
6493
6494// 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
64958.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_lsr
6496"mov_lsr"
6497*am33
6498{
6499 int srcreg2, dstreg1, dstreg2;
6500
6501 PC = cia;
6502 srcreg2 = translate_rreg (SD_, RM2);
6503 dstreg1 = translate_rreg (SD_, RN1);
6504 dstreg2 = translate_rreg (SD_, RN2);
6505
6506 State.regs[dstreg1] = EXTEND4 (IMM4A);
6507 State.regs[dstreg2] >>= State.regs[srcreg2];
6508}
6509
6510// 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
65118.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_lsr
6512"mov_lsr"
6513*am33
6514{
6515 int dstreg1, dstreg2;
6516 signed int temp;
6517
6518 PC = cia;
6519 dstreg1 = translate_rreg (SD_, RN1);
6520 dstreg2 = translate_rreg (SD_, RN2);
6521
6522 State.regs[dstreg1] = EXTEND4 (IMM4A);
6523 State.regs[dstreg2] >>= IMM4;
6524}
6525
6526
6527// 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
65288.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asl
6529"mov_asl"
6530*am33
6531{
6532 int srcreg2, dstreg1, dstreg2;
6533
6534 PC = cia;
6535 srcreg2 = translate_rreg (SD_, RM2);
6536 dstreg1 = translate_rreg (SD_, RN1);
6537 dstreg2 = translate_rreg (SD_, RN2);
6538
6539 State.regs[dstreg1] = EXTEND4 (IMM4A);
6540 State.regs[dstreg2] <<= State.regs[srcreg2];
6541}
6542
6543// 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
65448.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asl
6545"mov_asl"
6546*am33
6547{
6548 int dstreg1, dstreg2;
6549 signed int temp;
6550
6551 PC = cia;
6552 dstreg1 = translate_rreg (SD_, RN1);
6553 dstreg2 = translate_rreg (SD_, RN2);
6554
6555 State.regs[dstreg1] = EXTEND4 (IMM4A);
6556 State.regs[dstreg2] <<= IMM4;
6557}
6558
6559// 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
65608.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_add
6561"and_add"
6562*am33
6563{
6564 int srcreg1, srcreg2, dstreg1, dstreg2;
6565
6566 PC = cia;
6567 srcreg1 = translate_rreg (SD_, RM1);
6568 srcreg2 = translate_rreg (SD_, RM2);
6569 dstreg1 = translate_rreg (SD_, RN1);
6570 dstreg2 = translate_rreg (SD_, RN2);
6571
6572 State.regs[dstreg1] &= State.regs[srcreg1];
6573 State.regs[dstreg2] += State.regs[srcreg2];
6574}
6575
6576// 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
65778.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_add
6578"and_add"
6579*am33
6580{
6581 int srcreg1, dstreg1, dstreg2;
6582
6583 PC = cia;
6584 srcreg1 = translate_rreg (SD_, RM1);
6585 dstreg1 = translate_rreg (SD_, RN1);
6586 dstreg2 = translate_rreg (SD_, RN2);
6587
6588 State.regs[dstreg1] &= State.regs[srcreg1];
6589 State.regs[dstreg2] += EXTEND4 (IMM4);
6590}
6591
6592// 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
65938.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_sub
6594"and_sub"
6595*am33
6596{
6597 int srcreg1, srcreg2, dstreg1, dstreg2;
6598
6599 PC = cia;
6600 srcreg1 = translate_rreg (SD_, RM1);
6601 srcreg2 = translate_rreg (SD_, RM2);
6602 dstreg1 = translate_rreg (SD_, RN1);
6603 dstreg2 = translate_rreg (SD_, RN2);
6604
6605 State.regs[dstreg1] &= State.regs[srcreg1];
6606 State.regs[dstreg2] -= State.regs[srcreg2];
6607}
6608
6609// 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
66108.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_sub
6611"and_sub"
6612*am33
6613{
6614 int srcreg1, dstreg1, dstreg2;
6615
6616 PC = cia;
6617 srcreg1 = translate_rreg (SD_, RM1);
6618 dstreg1 = translate_rreg (SD_, RN1);
6619 dstreg2 = translate_rreg (SD_, RN2);
6620
6621 State.regs[dstreg1] &= State.regs[srcreg1];
6622 State.regs[dstreg2] -= EXTEND4 (IMM4);
6623}
6624
6625// 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
66268.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_cmp
6627"and_cmp"
6628*am33
6629{
6630 int srcreg1, srcreg2, dstreg1, dstreg2;
6631
6632 PC = cia;
6633 srcreg1 = translate_rreg (SD_, RM1);
6634 srcreg2 = translate_rreg (SD_, RM2);
6635 dstreg1 = translate_rreg (SD_, RN1);
6636 dstreg2 = translate_rreg (SD_, RN2);
6637
6638 State.regs[dstreg1] &= State.regs[srcreg1];
6639 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6640}
6641
6642// 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
66438.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_cmp
6644"and_cmp"
6645*am33
6646{
6647 int srcreg1, dstreg1, dstreg2;
6648
6649 PC = cia;
6650 srcreg1 = translate_rreg (SD_, RM1);
6651 dstreg1 = translate_rreg (SD_, RN1);
6652 dstreg2 = translate_rreg (SD_, RN2);
6653
6654 State.regs[dstreg1] &= State.regs[srcreg1];
6655 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6656}
6657
6658// 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
66598.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_mov
6660"and_mov"
6661*am33
6662{
6663 int srcreg1, srcreg2, dstreg1, dstreg2;
6664
6665 PC = cia;
6666 srcreg1 = translate_rreg (SD_, RM1);
6667 srcreg2 = translate_rreg (SD_, RM2);
6668 dstreg1 = translate_rreg (SD_, RN1);
6669 dstreg2 = translate_rreg (SD_, RN2);
6670
6671 State.regs[dstreg1] &= State.regs[srcreg1];
6672 State.regs[dstreg2] = State.regs[srcreg2];
6673}
6674
6675// 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
66768.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_mov
6677"and_mov"
6678*am33
6679{
6680 int srcreg1, dstreg1, dstreg2;
6681
6682 PC = cia;
6683 srcreg1 = translate_rreg (SD_, RM1);
6684 dstreg1 = translate_rreg (SD_, RN1);
6685 dstreg2 = translate_rreg (SD_, RN2);
6686
6687 State.regs[dstreg1] &= State.regs[srcreg1];
6688 State.regs[dstreg2] = EXTEND4 (IMM4);
6689}
6690
6691// 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
66928.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asr
6693"and_asr"
6694*am33
6695{
6696 int srcreg1, srcreg2, dstreg1, dstreg2;
6697 signed int temp;
6698
6699 PC = cia;
6700 srcreg1 = translate_rreg (SD_, RM1);
6701 srcreg2 = translate_rreg (SD_, RM2);
6702 dstreg1 = translate_rreg (SD_, RN1);
6703 dstreg2 = translate_rreg (SD_, RN2);
6704
6705 State.regs[dstreg1] &= State.regs[srcreg1];
6706 temp = State.regs[dstreg2];
6707 temp >>= State.regs[srcreg2];
6708 State.regs[dstreg2] = temp;
6709}
6710
6711// 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
67128.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asr
6713"and_asr"
6714*am33
6715{
6716 int srcreg1, dstreg1, dstreg2;
6717 signed int temp;
6718
6719 PC = cia;
6720 srcreg1 = translate_rreg (SD_, RM1);
6721 dstreg1 = translate_rreg (SD_, RN1);
6722 dstreg2 = translate_rreg (SD_, RN2);
6723
6724 State.regs[dstreg1] &= State.regs[srcreg1];
6725 temp = State.regs[dstreg2];
6726 temp >>= IMM4;
6727 State.regs[dstreg2] = temp;
6728}
6729
6730// 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
67318.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_lsr
6732"and_lsr"
6733*am33
6734{
6735 int srcreg1, srcreg2, dstreg1, dstreg2;
6736
6737 PC = cia;
6738 srcreg1 = translate_rreg (SD_, RM1);
6739 srcreg2 = translate_rreg (SD_, RM2);
6740 dstreg1 = translate_rreg (SD_, RN1);
6741 dstreg2 = translate_rreg (SD_, RN2);
6742
6743 State.regs[dstreg1] &= State.regs[srcreg1];
6744 State.regs[dstreg2] >>= State.regs[srcreg2];
6745}
6746
6747// 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
67488.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_lsr
6749"and_lsr"
6750*am33
6751{
6752 int srcreg1, dstreg1, dstreg2;
6753 signed int temp;
6754
6755 PC = cia;
6756 srcreg1 = translate_rreg (SD_, RM1);
6757 dstreg1 = translate_rreg (SD_, RN1);
6758 dstreg2 = translate_rreg (SD_, RN2);
6759
6760 State.regs[dstreg1] &= State.regs[srcreg1];
6761 State.regs[dstreg2] >>= IMM4;
6762}
6763
6764
6765// 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
67668.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asl
6767"and_asl"
6768*am33
6769{
6770 int srcreg1, srcreg2, dstreg1, dstreg2;
6771
6772 PC = cia;
6773 srcreg1 = translate_rreg (SD_, RM1);
6774 srcreg2 = translate_rreg (SD_, RM2);
6775 dstreg1 = translate_rreg (SD_, RN1);
6776 dstreg2 = translate_rreg (SD_, RN2);
6777
6778 State.regs[dstreg1] &= State.regs[srcreg1];
6779 State.regs[dstreg2] <<= State.regs[srcreg2];
6780}
6781
6782// 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
67838.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asl
6784"and_asl"
6785*am33
6786{
6787 int srcreg1, dstreg1, dstreg2;
6788 signed int temp;
6789
6790 PC = cia;
6791 srcreg1 = translate_rreg (SD_, RM1);
6792 dstreg1 = translate_rreg (SD_, RN1);
6793 dstreg2 = translate_rreg (SD_, RN2);
6794
6795 State.regs[dstreg1] &= State.regs[srcreg1];
6796 State.regs[dstreg2] <<= IMM4;
6797}
6798
6799// 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
68008.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_add
6801"dmach_add"
6802*am33
6803{
6804 int srcreg1, srcreg2, dstreg1, dstreg2;
6805 long temp, temp2, sum;
6806
6807 PC = cia;
6808 srcreg1 = translate_rreg (SD_, RM1);
6809 srcreg2 = translate_rreg (SD_, RM2);
6810 dstreg1 = translate_rreg (SD_, RN1);
6811 dstreg2 = translate_rreg (SD_, RN2);
6812
6813 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6814 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6815 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6816 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6817 sum = temp + temp2 + State.regs[REG_MCRL];
6818
6819 State.regs[dstreg1] = sum;
6820 State.regs[dstreg2] += State.regs[srcreg2];
6821}
6822
6823// 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
68248.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_add
6825"dmach_add"
6826*am33
6827{
6828 int srcreg1, dstreg1, dstreg2;
6829 long temp, temp2, sum;
6830
6831 PC = cia;
6832 srcreg1 = translate_rreg (SD_, RM1);
6833 dstreg1 = translate_rreg (SD_, RN1);
6834 dstreg2 = translate_rreg (SD_, RN2);
6835
6836 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6837 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6838 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6839 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6840 sum = temp + temp2 + State.regs[REG_MCRL];
6841
6842 State.regs[dstreg1] = sum;
6843 State.regs[dstreg2] += EXTEND4 (IMM4);
6844}
6845
6846// 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
68478.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_sub
6848"dmach_sub"
6849*am33
6850{
6851 int srcreg1, srcreg2, dstreg1, dstreg2;
6852 long temp, temp2, sum;
6853
6854 PC = cia;
6855 srcreg1 = translate_rreg (SD_, RM1);
6856 srcreg2 = translate_rreg (SD_, RM2);
6857 dstreg1 = translate_rreg (SD_, RN1);
6858 dstreg2 = translate_rreg (SD_, RN2);
6859
6860 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6861 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6862 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6863 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6864 sum = temp + temp2 + State.regs[REG_MCRL];
6865
6866 State.regs[dstreg1] = sum;
6867 State.regs[dstreg2] -= State.regs[srcreg2];
6868}
6869
6870// 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
68718.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_sub
6872"dmach_sub"
6873*am33
6874{
6875 int srcreg1, dstreg1, dstreg2;
6876 long temp, temp2, sum;
6877
6878 PC = cia;
6879 srcreg1 = translate_rreg (SD_, RM1);
6880 dstreg1 = translate_rreg (SD_, RN1);
6881 dstreg2 = translate_rreg (SD_, RN2);
6882
6883 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6884 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6885 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6886 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6887 sum = temp + temp2 + State.regs[REG_MCRL];
6888
6889 State.regs[dstreg1] = sum;
6890 State.regs[dstreg2] -= EXTEND4 (IMM4);
6891}
6892
6893// 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
68948.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_cmp
6895"dmach_cmp"
6896*am33
6897{
6898 int srcreg1, srcreg2, dstreg1, dstreg2;
6899 long temp, temp2, sum;
6900
6901 PC = cia;
6902 srcreg1 = translate_rreg (SD_, RM1);
6903 srcreg2 = translate_rreg (SD_, RM2);
6904 dstreg1 = translate_rreg (SD_, RN1);
6905 dstreg2 = translate_rreg (SD_, RN2);
6906
6907 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6908 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6909 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6910 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6911 sum = temp + temp2 + State.regs[REG_MCRL];
6912
6913 State.regs[dstreg1] = sum;
6914 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6915}
6916
6917// 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
69188.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_cmp
6919"dmach_cmp"
6920*am33
6921{
6922 int srcreg1, dstreg1, dstreg2;
6923 long temp, temp2, sum;
6924
6925 PC = cia;
6926 srcreg1 = translate_rreg (SD_, RM1);
6927 dstreg1 = translate_rreg (SD_, RN1);
6928 dstreg2 = translate_rreg (SD_, RN2);
6929
6930 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6931 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6932 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6933 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6934 sum = temp + temp2 + State.regs[REG_MCRL];
6935
6936 State.regs[dstreg1] = sum;
6937 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6938}
6939
6940// 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
69418.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_mov
6942"dmach_mov"
6943*am33
6944{
6945 int srcreg1, srcreg2, dstreg1, dstreg2;
6946 long temp, temp2, sum;
6947
6948 PC = cia;
6949 srcreg1 = translate_rreg (SD_, RM1);
6950 srcreg2 = translate_rreg (SD_, RM2);
6951 dstreg1 = translate_rreg (SD_, RN1);
6952 dstreg2 = translate_rreg (SD_, RN2);
6953
6954 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6955 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6956 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6957 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6958 sum = temp + temp2 + State.regs[REG_MCRL];
6959
6960 State.regs[dstreg1] = sum;
6961 State.regs[dstreg2] = State.regs[srcreg2];
6962}
6963
6964// 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
69658.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_mov
6966"dmach_mov"
6967*am33
6968{
6969 int srcreg1, dstreg1, dstreg2;
6970 long temp, temp2, sum;
6971
6972 PC = cia;
6973 srcreg1 = translate_rreg (SD_, RM1);
6974 dstreg1 = translate_rreg (SD_, RN1);
6975 dstreg2 = translate_rreg (SD_, RN2);
6976
6977 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6978 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6979 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6980 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6981 sum = temp + temp2 + State.regs[REG_MCRL];
6982
6983 State.regs[dstreg1] = sum;
6984 State.regs[dstreg2] = EXTEND4 (IMM4);
6985}
6986
6987// 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
69888.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asr
6989"dmach_asr"
6990*am33
6991{
6992 int srcreg1, srcreg2, dstreg1, dstreg2;
6993 long temp, temp2, sum;
6994
6995 PC = cia;
6996 srcreg1 = translate_rreg (SD_, RM1);
6997 srcreg2 = translate_rreg (SD_, RM2);
6998 dstreg1 = translate_rreg (SD_, RN1);
6999 dstreg2 = translate_rreg (SD_, RN2);
7000
7001 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7002 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7003 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7004 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7005 sum = temp + temp2 + State.regs[REG_MCRL];
7006
7007 State.regs[dstreg1] = sum;
7008 temp = State.regs[dstreg2];
7009 temp >>= State.regs[srcreg2];
7010 State.regs[dstreg2] = temp;
7011}
7012
7013// 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
70148.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asr
7015"dmach_asr"
7016*am33
7017{
7018 int srcreg1, dstreg1, dstreg2;
7019 long temp, temp2, sum;
7020
7021 PC = cia;
7022 srcreg1 = translate_rreg (SD_, RM1);
7023 dstreg1 = translate_rreg (SD_, RN1);
7024 dstreg2 = translate_rreg (SD_, RN2);
7025
7026 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7027 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7028 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7029 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7030 sum = temp + temp2 + State.regs[REG_MCRL];
7031
7032 State.regs[dstreg1] = sum;
7033 temp = State.regs[dstreg2];
7034 temp >>= IMM4;
7035 State.regs[dstreg2] = temp;
7036}
7037
7038// 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
70398.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_lsr
7040"dmach_lsr"
7041*am33
7042{
7043 int srcreg1, srcreg2, dstreg1, dstreg2;
7044 long temp, temp2, sum;
7045
7046 PC = cia;
7047 srcreg1 = translate_rreg (SD_, RM1);
7048 srcreg2 = translate_rreg (SD_, RM2);
7049 dstreg1 = translate_rreg (SD_, RN1);
7050 dstreg2 = translate_rreg (SD_, RN2);
7051
7052 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7053 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7054 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7055 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7056 sum = temp + temp2 + State.regs[REG_MCRL];
7057
7058 State.regs[dstreg1] = sum;
7059 State.regs[dstreg2] >>= State.regs[srcreg2];
7060}
7061
7062// 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
70638.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_lsr
7064"dmach_lsr"
7065*am33
7066{
7067 int srcreg1, dstreg1, dstreg2;
7068 long temp, temp2, sum;
7069
7070 PC = cia;
7071 srcreg1 = translate_rreg (SD_, RM1);
7072 dstreg1 = translate_rreg (SD_, RN1);
7073 dstreg2 = translate_rreg (SD_, RN2);
7074
7075 State.regs[dstreg2] >>= IMM4;
7076}
7077
7078
7079// 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
70808.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asl
7081"dmach_asl"
7082*am33
7083{
7084 int srcreg1, srcreg2, dstreg1, dstreg2;
7085 long temp, temp2, sum;
7086
7087 PC = cia;
7088 srcreg1 = translate_rreg (SD_, RM1);
7089 srcreg2 = translate_rreg (SD_, RM2);
7090 dstreg1 = translate_rreg (SD_, RN1);
7091 dstreg2 = translate_rreg (SD_, RN2);
7092
7093 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7094 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7095 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7096 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7097 sum = temp + temp2 + State.regs[REG_MCRL];
7098
7099 State.regs[dstreg1] = sum;
7100 State.regs[dstreg2] <<= State.regs[srcreg2];
7101}
7102
7103// 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
71048.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asl
7105"dmach_asl"
7106*am33
7107{
7108 int srcreg1, dstreg1, dstreg2;
7109 long temp, temp2, sum;
7110
7111 PC = cia;
7112 srcreg1 = translate_rreg (SD_, RM1);
7113 dstreg1 = translate_rreg (SD_, RN1);
7114 dstreg2 = translate_rreg (SD_, RN2);
7115
7116 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7117 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7118 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7119 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7120 sum = temp + temp2 + State.regs[REG_MCRL];
7121
7122 State.regs[dstreg1] = sum;
7123 State.regs[dstreg2] <<= IMM4;
7124}
7125
7126// 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
71278.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_add
7128"xor_add"
7129*am33
7130{
7131 int srcreg1, srcreg2, dstreg1, dstreg2;
7132
7133 PC = cia;
7134 srcreg1 = translate_rreg (SD_, RM1);
7135 srcreg2 = translate_rreg (SD_, RM2);
7136 dstreg1 = translate_rreg (SD_, RN1);
7137 dstreg2 = translate_rreg (SD_, RN2);
7138
7139 State.regs[dstreg1] ^= State.regs[srcreg1];
7140 State.regs[dstreg2] += State.regs[srcreg2];
7141}
7142
7143// 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
71448.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_add
7145"xor_add"
7146*am33
7147{
7148 int srcreg1, dstreg1, dstreg2;
7149
7150 PC = cia;
7151 srcreg1 = translate_rreg (SD_, RM1);
7152 dstreg1 = translate_rreg (SD_, RN1);
7153 dstreg2 = translate_rreg (SD_, RN2);
7154
7155 State.regs[dstreg1] ^= State.regs[srcreg1];
7156 State.regs[dstreg2] += EXTEND4 (IMM4);
7157}
7158
7159// 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
71608.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_sub
7161"xor_sub"
7162*am33
7163{
7164 int srcreg1, srcreg2, dstreg1, dstreg2;
7165
7166 PC = cia;
7167 srcreg1 = translate_rreg (SD_, RM1);
7168 srcreg2 = translate_rreg (SD_, RM2);
7169 dstreg1 = translate_rreg (SD_, RN1);
7170 dstreg2 = translate_rreg (SD_, RN2);
7171
7172 State.regs[dstreg1] ^= State.regs[srcreg1];
7173 State.regs[dstreg2] -= State.regs[srcreg2];
7174}
7175
7176// 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
71778.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_sub
7178"xor_sub"
7179*am33
7180{
7181 int srcreg1, dstreg1, dstreg2;
7182
7183 PC = cia;
7184 srcreg1 = translate_rreg (SD_, RM1);
7185 dstreg1 = translate_rreg (SD_, RN1);
7186 dstreg2 = translate_rreg (SD_, RN2);
7187
7188 State.regs[dstreg1] ^= State.regs[srcreg1];
7189 State.regs[dstreg2] -= EXTEND4 (IMM4);
7190}
7191
7192// 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
71938.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_cmp
7194"xor_cmp"
7195*am33
7196{
7197 int srcreg1, srcreg2, dstreg1, dstreg2;
7198
7199 PC = cia;
7200 srcreg1 = translate_rreg (SD_, RM1);
7201 srcreg2 = translate_rreg (SD_, RM2);
7202 dstreg1 = translate_rreg (SD_, RN1);
7203 dstreg2 = translate_rreg (SD_, RN2);
7204
7205 State.regs[dstreg1] ^= State.regs[srcreg1];
7206 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7207}
7208
7209// 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
72108.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_cmp
7211"xor_cmp"
7212*am33
7213{
7214 int srcreg1, dstreg1, dstreg2;
7215
7216 PC = cia;
7217 srcreg1 = translate_rreg (SD_, RM1);
7218 dstreg1 = translate_rreg (SD_, RN1);
7219 dstreg2 = translate_rreg (SD_, RN2);
7220
7221 State.regs[dstreg1] ^= State.regs[srcreg1];
7222 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7223}
7224
7225// 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
72268.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_mov
7227"xor_mov"
7228*am33
7229{
7230 int srcreg1, srcreg2, dstreg1, dstreg2;
7231
7232 PC = cia;
7233 srcreg1 = translate_rreg (SD_, RM1);
7234 srcreg2 = translate_rreg (SD_, RM2);
7235 dstreg1 = translate_rreg (SD_, RN1);
7236 dstreg2 = translate_rreg (SD_, RN2);
7237
7238 State.regs[dstreg1] ^= State.regs[srcreg1];
7239 State.regs[dstreg2] = State.regs[srcreg2];
7240}
7241
7242// 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
72438.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_mov
7244"xor_mov"
7245*am33
7246{
7247 int srcreg1, dstreg1, dstreg2;
7248
7249 PC = cia;
7250 srcreg1 = translate_rreg (SD_, RM1);
7251 dstreg1 = translate_rreg (SD_, RN1);
7252 dstreg2 = translate_rreg (SD_, RN2);
7253
7254 State.regs[dstreg1] ^= State.regs[srcreg1];
7255 State.regs[dstreg2] = EXTEND4 (IMM4);
7256}
7257
7258// 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
72598.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asr
7260"xor_asr"
7261*am33
7262{
7263 int srcreg1, srcreg2, dstreg1, dstreg2;
7264 signed int temp;
7265
7266 PC = cia;
7267 srcreg1 = translate_rreg (SD_, RM1);
7268 srcreg2 = translate_rreg (SD_, RM2);
7269 dstreg1 = translate_rreg (SD_, RN1);
7270 dstreg2 = translate_rreg (SD_, RN2);
7271
7272 State.regs[dstreg1] ^= State.regs[srcreg1];
7273 temp = State.regs[dstreg2];
7274 temp >>= State.regs[srcreg2];
7275 State.regs[dstreg2] = temp;
7276}
7277
7278// 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
72798.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asr
7280"xor_asr"
7281*am33
7282{
7283 int srcreg1, dstreg1, dstreg2;
7284 signed int temp;
7285
7286 PC = cia;
7287 srcreg1 = translate_rreg (SD_, RM1);
7288 dstreg1 = translate_rreg (SD_, RN1);
7289 dstreg2 = translate_rreg (SD_, RN2);
7290
7291 State.regs[dstreg1] ^= State.regs[srcreg1];
7292 temp = State.regs[dstreg2];
7293 temp >>= IMM4;
7294 State.regs[dstreg2] = temp;
7295}
7296
7297// 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
72988.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_lsr
7299"xor_lsr"
7300*am33
7301{
7302 int srcreg1, srcreg2, dstreg1, dstreg2;
7303
7304 PC = cia;
7305 srcreg1 = translate_rreg (SD_, RM1);
7306 srcreg2 = translate_rreg (SD_, RM2);
7307 dstreg1 = translate_rreg (SD_, RN1);
7308 dstreg2 = translate_rreg (SD_, RN2);
7309
7310 State.regs[dstreg1] ^= State.regs[srcreg1];
7311 State.regs[dstreg2] >>= State.regs[srcreg2];
7312}
7313
7314// 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
73158.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_lsr
7316"xor_lsr"
7317*am33
7318{
7319 int srcreg1, dstreg1, dstreg2;
7320 signed int temp;
7321
7322 PC = cia;
7323 srcreg1 = translate_rreg (SD_, RM1);
7324 dstreg1 = translate_rreg (SD_, RN1);
7325 dstreg2 = translate_rreg (SD_, RN2);
7326
7327 State.regs[dstreg1] ^= State.regs[srcreg1];
7328 State.regs[dstreg2] >>= IMM4;
7329}
7330
7331
7332// 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
73338.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asl
7334"xor_asl"
7335*am33
7336{
7337 int srcreg1, srcreg2, dstreg1, dstreg2;
7338
7339 PC = cia;
7340 srcreg1 = translate_rreg (SD_, RM1);
7341 srcreg2 = translate_rreg (SD_, RM2);
7342 dstreg1 = translate_rreg (SD_, RN1);
7343 dstreg2 = translate_rreg (SD_, RN2);
7344
7345 State.regs[dstreg1] ^= State.regs[srcreg1];
7346 State.regs[dstreg2] <<= State.regs[srcreg2];
7347}
7348
7349// 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
73508.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asl
7351"xor_asl"
7352*am33
7353{
7354 int srcreg1, dstreg1, dstreg2;
7355 signed int temp;
7356
7357 PC = cia;
7358 srcreg1 = translate_rreg (SD_, RM1);
7359 dstreg1 = translate_rreg (SD_, RN1);
7360 dstreg2 = translate_rreg (SD_, RN2);
7361
7362 State.regs[dstreg1] ^= State.regs[srcreg1];
7363 State.regs[dstreg2] <<= IMM4;
7364}
7365
7366// 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
73678.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_add
7368"swhw_add"
7369*am33
7370{
7371 int srcreg1, srcreg2, dstreg1, dstreg2;
7372
7373 PC = cia;
7374 srcreg1 = translate_rreg (SD_, RM1);
7375 srcreg2 = translate_rreg (SD_, RM2);
7376 dstreg1 = translate_rreg (SD_, RN1);
7377 dstreg2 = translate_rreg (SD_, RN2);
7378
7379 State.regs[dstreg1] ^= State.regs[srcreg1];
7380 State.regs[dstreg2] += State.regs[srcreg2];
7381}
7382
7383// 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
73848.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_add
7385"swhw_add"
7386*am33
7387{
7388 int srcreg1, dstreg1, dstreg2;
7389
7390 PC = cia;
7391 srcreg1 = translate_rreg (SD_, RM1);
7392 dstreg1 = translate_rreg (SD_, RN1);
7393 dstreg2 = translate_rreg (SD_, RN2);
7394
7395 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7396 | ((State.regs[srcreg1] >> 16) & 0xffff));
7397 State.regs[dstreg2] += EXTEND4 (IMM4);
7398}
7399
7400// 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
74018.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_sub
7402"swhw_sub"
7403*am33
7404{
7405 int srcreg1, srcreg2, dstreg1, dstreg2;
7406
7407 PC = cia;
7408 srcreg1 = translate_rreg (SD_, RM1);
7409 srcreg2 = translate_rreg (SD_, RM2);
7410 dstreg1 = translate_rreg (SD_, RN1);
7411 dstreg2 = translate_rreg (SD_, RN2);
7412
7413 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7414 | ((State.regs[srcreg1] >> 16) & 0xffff));
7415 State.regs[dstreg2] -= State.regs[srcreg2];
7416}
7417
7418// 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
74198.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_sub
7420"swhw_sub"
7421*am33
7422{
7423 int srcreg1, dstreg1, dstreg2;
7424
7425 PC = cia;
7426 srcreg1 = translate_rreg (SD_, RM1);
7427 dstreg1 = translate_rreg (SD_, RN1);
7428 dstreg2 = translate_rreg (SD_, RN2);
7429
7430 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7431 | ((State.regs[srcreg1] >> 16) & 0xffff));
7432 State.regs[dstreg2] -= EXTEND4 (IMM4);
7433}
7434
7435// 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
74368.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_cmp
7437"swhw_cmp"
7438*am33
7439{
7440 int srcreg1, srcreg2, dstreg1, dstreg2;
7441
7442 PC = cia;
7443 srcreg1 = translate_rreg (SD_, RM1);
7444 srcreg2 = translate_rreg (SD_, RM2);
7445 dstreg1 = translate_rreg (SD_, RN1);
7446 dstreg2 = translate_rreg (SD_, RN2);
7447
7448 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7449 | ((State.regs[srcreg1] >> 16) & 0xffff));
7450 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7451}
7452
7453// 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
74548.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_cmp
7455"swhw_cmp"
7456*am33
7457{
7458 int srcreg1, dstreg1, dstreg2;
7459
7460 PC = cia;
7461 srcreg1 = translate_rreg (SD_, RM1);
7462 dstreg1 = translate_rreg (SD_, RN1);
7463 dstreg2 = translate_rreg (SD_, RN2);
7464
7465 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7466 | ((State.regs[srcreg1] >> 16) & 0xffff));
7467 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7468}
7469
7470// 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
74718.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_mov
7472"swhw_mov"
7473*am33
7474{
7475 int srcreg1, srcreg2, dstreg1, dstreg2;
7476
7477 PC = cia;
7478 srcreg1 = translate_rreg (SD_, RM1);
7479 srcreg2 = translate_rreg (SD_, RM2);
7480 dstreg1 = translate_rreg (SD_, RN1);
7481 dstreg2 = translate_rreg (SD_, RN2);
7482
7483 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7484 | ((State.regs[srcreg1] >> 16) & 0xffff));
7485 State.regs[dstreg2] = State.regs[srcreg2];
7486}
7487
7488// 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
74898.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_mov
7490"swhw_mov"
7491*am33
7492{
7493 int srcreg1, dstreg1, dstreg2;
7494
7495 PC = cia;
7496 srcreg1 = translate_rreg (SD_, RM1);
7497 dstreg1 = translate_rreg (SD_, RN1);
7498 dstreg2 = translate_rreg (SD_, RN2);
7499
7500 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7501 | ((State.regs[srcreg1] >> 16) & 0xffff));
7502 State.regs[dstreg2] = EXTEND4 (IMM4);
7503}
7504
7505// 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
75068.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asr
7507"swhw_asr"
7508*am33
7509{
7510 int srcreg1, srcreg2, dstreg1, dstreg2;
7511 signed int temp;
7512
7513 PC = cia;
7514 srcreg1 = translate_rreg (SD_, RM1);
7515 srcreg2 = translate_rreg (SD_, RM2);
7516 dstreg1 = translate_rreg (SD_, RN1);
7517 dstreg2 = translate_rreg (SD_, RN2);
7518
7519 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7520 | ((State.regs[srcreg1] >> 16) & 0xffff));
7521 temp = State.regs[dstreg2];
7522 temp >>= State.regs[srcreg2];
7523 State.regs[dstreg2] = temp;
7524}
7525
7526// 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
75278.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asr
7528"swhw_asr"
7529*am33
7530{
7531 int srcreg1, dstreg1, dstreg2;
7532 signed int temp;
7533
7534 PC = cia;
7535 srcreg1 = translate_rreg (SD_, RM1);
7536 dstreg1 = translate_rreg (SD_, RN1);
7537 dstreg2 = translate_rreg (SD_, RN2);
7538
7539 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7540 | ((State.regs[srcreg1] >> 16) & 0xffff));
7541 temp = State.regs[dstreg2];
7542 temp >>= IMM4;
7543 State.regs[dstreg2] = temp;
7544}
7545
7546// 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
75478.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_lsr
7548"swhw_lsr"
7549*am33
7550{
7551 int srcreg1, srcreg2, dstreg1, dstreg2;
7552
7553 PC = cia;
7554 srcreg1 = translate_rreg (SD_, RM1);
7555 srcreg2 = translate_rreg (SD_, RM2);
7556 dstreg1 = translate_rreg (SD_, RN1);
7557 dstreg2 = translate_rreg (SD_, RN2);
7558
7559 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7560 | ((State.regs[srcreg1] >> 16) & 0xffff));
7561 State.regs[dstreg2] >>= State.regs[srcreg2];
7562}
7563
7564// 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
75658.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_lsr
7566"swhw_lsr"
7567*am33
7568{
7569 int srcreg1, dstreg1, dstreg2;
7570 signed int temp;
7571
7572 PC = cia;
7573 srcreg1 = translate_rreg (SD_, RM1);
7574 dstreg1 = translate_rreg (SD_, RN1);
7575 dstreg2 = translate_rreg (SD_, RN2);
7576
7577 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7578 | ((State.regs[srcreg1] >> 16) & 0xffff));
7579 State.regs[dstreg2] >>= IMM4;
7580}
7581
7582
7583// 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
75848.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asl
7585"swhw_asl"
7586*am33
7587{
7588 int srcreg1, srcreg2, dstreg1, dstreg2;
7589
7590 PC = cia;
7591 srcreg1 = translate_rreg (SD_, RM1);
7592 srcreg2 = translate_rreg (SD_, RM2);
7593 dstreg1 = translate_rreg (SD_, RN1);
7594 dstreg2 = translate_rreg (SD_, RN2);
7595
7596 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7597 | ((State.regs[srcreg1] >> 16) & 0xffff));
7598 State.regs[dstreg2] <<= State.regs[srcreg2];
7599}
7600
7601// 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
76028.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asl
7603"swhw_asl"
7604*am33
7605{
7606 int srcreg1, dstreg1, dstreg2;
7607 signed int temp;
7608
7609 PC = cia;
7610 srcreg1 = translate_rreg (SD_, RM1);
7611 dstreg1 = translate_rreg (SD_, RN1);
7612 dstreg2 = translate_rreg (SD_, RN2);
7613
7614 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7615 | ((State.regs[srcreg1] >> 16) & 0xffff));
7616 State.regs[dstreg2] <<= IMM4;
7617}
7618
7619// 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
76208.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_add
7621"or_add"
7622*am33
7623{
7624 int srcreg1, srcreg2, dstreg1, dstreg2;
7625
7626 PC = cia;
7627 srcreg1 = translate_rreg (SD_, RM1);
7628 srcreg2 = translate_rreg (SD_, RM2);
7629 dstreg1 = translate_rreg (SD_, RN1);
7630 dstreg2 = translate_rreg (SD_, RN2);
7631
7632 State.regs[dstreg1] |= State.regs[srcreg1];
7633 State.regs[dstreg2] += State.regs[srcreg2];
7634}
7635
7636// 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
76378.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_add
7638"or_add"
7639*am33
7640{
7641 int srcreg1, dstreg1, dstreg2;
7642
7643 PC = cia;
7644 srcreg1 = translate_rreg (SD_, RM1);
7645 dstreg1 = translate_rreg (SD_, RN1);
7646 dstreg2 = translate_rreg (SD_, RN2);
7647
7648 State.regs[dstreg1] |= State.regs[srcreg1];
7649 State.regs[dstreg2] += EXTEND4 (IMM4);
7650}
7651
7652// 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
76538.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_sub
7654"or_sub"
7655*am33
7656{
7657 int srcreg1, srcreg2, dstreg1, dstreg2;
7658
7659 PC = cia;
7660 srcreg1 = translate_rreg (SD_, RM1);
7661 srcreg2 = translate_rreg (SD_, RM2);
7662 dstreg1 = translate_rreg (SD_, RN1);
7663 dstreg2 = translate_rreg (SD_, RN2);
7664
7665 State.regs[dstreg1] |= State.regs[srcreg1];
7666 State.regs[dstreg2] -= State.regs[srcreg2];
7667}
7668
7669// 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
76708.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_sub
7671"or_sub"
7672*am33
7673{
7674 int srcreg1, dstreg1, dstreg2;
7675
7676 PC = cia;
7677 srcreg1 = translate_rreg (SD_, RM1);
7678 dstreg1 = translate_rreg (SD_, RN1);
7679 dstreg2 = translate_rreg (SD_, RN2);
7680
7681 State.regs[dstreg1] |= State.regs[srcreg1];
7682 State.regs[dstreg2] -= EXTEND4 (IMM4);
7683}
7684
7685// 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
76868.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_cmp
7687"or_cmp"
7688*am33
7689{
7690 int srcreg1, srcreg2, dstreg1, dstreg2;
7691
7692 PC = cia;
7693 srcreg1 = translate_rreg (SD_, RM1);
7694 srcreg2 = translate_rreg (SD_, RM2);
7695 dstreg1 = translate_rreg (SD_, RN1);
7696 dstreg2 = translate_rreg (SD_, RN2);
7697
7698 State.regs[dstreg1] |= State.regs[srcreg1];
7699 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7700}
7701
7702// 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
77038.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_cmp
7704"or_cmp"
7705*am33
7706{
7707 int srcreg1, dstreg1, dstreg2;
7708
7709 PC = cia;
7710 srcreg1 = translate_rreg (SD_, RM1);
7711 dstreg1 = translate_rreg (SD_, RN1);
7712 dstreg2 = translate_rreg (SD_, RN2);
7713
7714 State.regs[dstreg1] |= State.regs[srcreg1];
7715 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7716}
7717
7718// 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
77198.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_mov
7720"or_mov"
7721*am33
7722{
7723 int srcreg1, srcreg2, dstreg1, dstreg2;
7724
7725 PC = cia;
7726 srcreg1 = translate_rreg (SD_, RM1);
7727 srcreg2 = translate_rreg (SD_, RM2);
7728 dstreg1 = translate_rreg (SD_, RN1);
7729 dstreg2 = translate_rreg (SD_, RN2);
7730
7731 State.regs[dstreg1] |= State.regs[srcreg1];
7732 State.regs[dstreg2] = State.regs[srcreg2];
7733}
7734
7735// 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
77368.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_mov
7737"or_mov"
7738*am33
7739{
7740 int srcreg1, dstreg1, dstreg2;
7741
7742 PC = cia;
7743 srcreg1 = translate_rreg (SD_, RM1);
7744 dstreg1 = translate_rreg (SD_, RN1);
7745 dstreg2 = translate_rreg (SD_, RN2);
7746
7747 State.regs[dstreg1] |= State.regs[srcreg1];
7748 State.regs[dstreg2] = EXTEND4 (IMM4);
7749}
7750
7751// 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
77528.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asr
7753"or_asr"
7754*am33
7755{
7756 int srcreg1, srcreg2, dstreg1, dstreg2;
7757 signed int temp;
7758
7759 PC = cia;
7760 srcreg1 = translate_rreg (SD_, RM1);
7761 srcreg2 = translate_rreg (SD_, RM2);
7762 dstreg1 = translate_rreg (SD_, RN1);
7763 dstreg2 = translate_rreg (SD_, RN2);
7764
7765 State.regs[dstreg1] |= State.regs[srcreg1];
7766 temp = State.regs[dstreg2];
7767 temp >>= State.regs[srcreg2];
7768 State.regs[dstreg2] = temp;
7769}
7770
7771// 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
77728.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asr
7773"or_asr"
7774*am33
7775{
7776 int srcreg1, dstreg1, dstreg2;
7777 signed int temp;
7778
7779 PC = cia;
7780 srcreg1 = translate_rreg (SD_, RM1);
7781 dstreg1 = translate_rreg (SD_, RN1);
7782 dstreg2 = translate_rreg (SD_, RN2);
7783
7784 State.regs[dstreg1] |= State.regs[srcreg1];
7785 temp = State.regs[dstreg2];
7786 temp >>= IMM4;
7787 State.regs[dstreg2] = temp;
7788}
7789
7790// 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
77918.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_lsr
7792"or_lsr"
7793*am33
7794{
7795 int srcreg1, srcreg2, dstreg1, dstreg2;
7796
7797 PC = cia;
7798 srcreg1 = translate_rreg (SD_, RM1);
7799 srcreg2 = translate_rreg (SD_, RM2);
7800 dstreg1 = translate_rreg (SD_, RN1);
7801 dstreg2 = translate_rreg (SD_, RN2);
7802
7803 State.regs[dstreg1] |= State.regs[srcreg1];
7804 State.regs[dstreg2] >>= State.regs[srcreg2];
7805}
7806
7807// 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
78088.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_lsr
7809"or_lsr"
7810*am33
7811{
7812 int srcreg1, dstreg1, dstreg2;
7813 signed int temp;
7814
7815 PC = cia;
7816 srcreg1 = translate_rreg (SD_, RM1);
7817 dstreg1 = translate_rreg (SD_, RN1);
7818 dstreg2 = translate_rreg (SD_, RN2);
7819
7820 State.regs[dstreg1] |= State.regs[srcreg1];
7821 State.regs[dstreg2] >>= IMM4;
7822}
7823
7824
7825// 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
78268.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asl
7827"or_asl"
7828*am33
7829{
7830 int srcreg1, srcreg2, dstreg1, dstreg2;
7831
7832 PC = cia;
7833 srcreg1 = translate_rreg (SD_, RM1);
7834 srcreg2 = translate_rreg (SD_, RM2);
7835 dstreg1 = translate_rreg (SD_, RN1);
7836 dstreg2 = translate_rreg (SD_, RN2);
7837
7838 State.regs[dstreg1] |= State.regs[srcreg1];
7839 State.regs[dstreg2] <<= State.regs[srcreg2];
7840}
7841
7842// 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
78438.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asl
7844"or_asl"
7845*am33
7846{
7847 int srcreg1, dstreg1, dstreg2;
7848 signed int temp;
7849
7850 PC = cia;
7851 srcreg1 = translate_rreg (SD_, RM1);
7852 dstreg1 = translate_rreg (SD_, RN1);
7853 dstreg2 = translate_rreg (SD_, RN2);
7854
7855 State.regs[dstreg1] |= State.regs[srcreg1];
7856 State.regs[dstreg2] <<= IMM4;
7857}
7858
7859// 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
78608.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_add
7861"sat16_add"
7862*am33
7863{
7864 int srcreg1, srcreg2, dstreg1, dstreg2;
7865
7866 PC = cia;
7867 srcreg1 = translate_rreg (SD_, RM1);
7868 srcreg2 = translate_rreg (SD_, RM2);
7869 dstreg1 = translate_rreg (SD_, RN1);
7870 dstreg2 = translate_rreg (SD_, RN2);
7871
7872 if (State.regs[srcreg1] >= 0x7fff)
7873 State.regs[dstreg1] = 0x7fff;
7874 else if (State.regs[srcreg1] <= 0xffff8000)
7875 State.regs[dstreg1] = 0xffff8000;
7876 else
7877 State.regs[dstreg1] = State.regs[srcreg1];
7878
7879 State.regs[dstreg2] += State.regs[srcreg2];
7880}
7881
7882// 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
78838.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_add
7884"sat16_add"
7885*am33
7886{
7887 int srcreg1, dstreg1, dstreg2;
7888
7889 PC = cia;
7890 srcreg1 = translate_rreg (SD_, RM1);
7891 dstreg1 = translate_rreg (SD_, RN1);
7892 dstreg2 = translate_rreg (SD_, RN2);
7893
7894 if (State.regs[srcreg1] >= 0x7fff)
7895 State.regs[dstreg1] = 0x7fff;
7896 else if (State.regs[srcreg1] <= 0xffff8000)
7897 State.regs[dstreg1] = 0xffff8000;
7898 else
7899 State.regs[dstreg1] = State.regs[srcreg1];
7900
7901 State.regs[dstreg2] += EXTEND4 (IMM4);
7902}
7903
7904// 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
79058.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_sub
7906"sat16_sub"
7907*am33
7908{
7909 int srcreg1, srcreg2, dstreg1, dstreg2;
7910
7911 PC = cia;
7912 srcreg1 = translate_rreg (SD_, RM1);
7913 srcreg2 = translate_rreg (SD_, RM2);
7914 dstreg1 = translate_rreg (SD_, RN1);
7915 dstreg2 = translate_rreg (SD_, RN2);
7916
7917 if (State.regs[srcreg1] >= 0x7fff)
7918 State.regs[dstreg1] = 0x7fff;
7919 else if (State.regs[srcreg1] <= 0xffff8000)
7920 State.regs[dstreg1] = 0xffff8000;
7921 else
7922 State.regs[dstreg1] = State.regs[srcreg1];
7923
7924 State.regs[dstreg2] -= State.regs[srcreg2];
7925}
7926
7927// 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
79288.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_sub
7929"sat16_sub"
7930*am33
7931{
7932 int srcreg1, dstreg1, dstreg2;
7933
7934 PC = cia;
7935 srcreg1 = translate_rreg (SD_, RM1);
7936 dstreg1 = translate_rreg (SD_, RN1);
7937 dstreg2 = translate_rreg (SD_, RN2);
7938
7939 if (State.regs[srcreg1] >= 0x7fff)
7940 State.regs[dstreg1] = 0x7fff;
7941 else if (State.regs[srcreg1] <= 0xffff8000)
7942 State.regs[dstreg1] = 0xffff8000;
7943 else
7944 State.regs[dstreg1] = State.regs[srcreg1];
7945
7946 State.regs[dstreg2] -= EXTEND4 (IMM4);
7947}
7948
7949// 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
79508.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_cmp
7951"sat16_cmp"
7952*am33
7953{
7954 int srcreg1, srcreg2, dstreg1, dstreg2;
7955
7956 PC = cia;
7957 srcreg1 = translate_rreg (SD_, RM1);
7958 srcreg2 = translate_rreg (SD_, RM2);
7959 dstreg1 = translate_rreg (SD_, RN1);
7960 dstreg2 = translate_rreg (SD_, RN2);
7961
7962 if (State.regs[srcreg1] >= 0x7fff)
7963 State.regs[dstreg1] = 0x7fff;
7964 else if (State.regs[srcreg1] <= 0xffff8000)
7965 State.regs[dstreg1] = 0xffff8000;
7966 else
7967 State.regs[dstreg1] = State.regs[srcreg1];
7968
7969 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7970}
7971
7972// 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
79738.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_cmp
7974"sat16_cmp"
7975*am33
7976{
7977 int srcreg1, dstreg1, dstreg2;
7978
7979 PC = cia;
7980 srcreg1 = translate_rreg (SD_, RM1);
7981 dstreg1 = translate_rreg (SD_, RN1);
7982 dstreg2 = translate_rreg (SD_, RN2);
7983
7984 if (State.regs[srcreg1] >= 0x7fff)
7985 State.regs[dstreg1] = 0x7fff;
7986 else if (State.regs[srcreg1] <= 0xffff8000)
7987 State.regs[dstreg1] = 0xffff8000;
7988 else
7989 State.regs[dstreg1] = State.regs[srcreg1];
7990
7991 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7992}
7993
7994// 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
79958.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_mov
7996"sat16_mov"
7997*am33
7998{
7999 int srcreg1, srcreg2, dstreg1, dstreg2;
8000
8001 PC = cia;
8002 srcreg1 = translate_rreg (SD_, RM1);
8003 srcreg2 = translate_rreg (SD_, RM2);
8004 dstreg1 = translate_rreg (SD_, RN1);
8005 dstreg2 = translate_rreg (SD_, RN2);
8006
8007 if (State.regs[srcreg1] >= 0x7fff)
8008 State.regs[dstreg1] = 0x7fff;
8009 else if (State.regs[srcreg1] <= 0xffff8000)
8010 State.regs[dstreg1] = 0xffff8000;
8011 else
8012 State.regs[dstreg1] = State.regs[srcreg1];
8013
8014 State.regs[dstreg2] = State.regs[srcreg2];
8015}
8016
8017// 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
80188.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_mov
8019"sat16_mov"
8020*am33
8021{
8022 int srcreg1, dstreg1, dstreg2;
8023
8024 PC = cia;
8025 srcreg1 = translate_rreg (SD_, RM1);
8026 dstreg1 = translate_rreg (SD_, RN1);
8027 dstreg2 = translate_rreg (SD_, RN2);
8028
8029 if (State.regs[srcreg1] >= 0x7fff)
8030 State.regs[dstreg1] = 0x7fff;
8031 else if (State.regs[srcreg1] <= 0xffff8000)
8032 State.regs[dstreg1] = 0xffff8000;
8033 else
8034 State.regs[dstreg1] = State.regs[srcreg1];
8035
8036 State.regs[dstreg2] = EXTEND4 (IMM4);
8037}
8038
8039// 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
80408.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asr
8041"sat16_asr"
8042*am33
8043{
8044 int srcreg1, srcreg2, dstreg1, dstreg2;
8045 signed int temp;
8046
8047 PC = cia;
8048 srcreg1 = translate_rreg (SD_, RM1);
8049 srcreg2 = translate_rreg (SD_, RM2);
8050 dstreg1 = translate_rreg (SD_, RN1);
8051 dstreg2 = translate_rreg (SD_, RN2);
8052
8053 if (State.regs[srcreg1] >= 0x7fff)
8054 State.regs[dstreg1] = 0x7fff;
8055 else if (State.regs[srcreg1] <= 0xffff8000)
8056 State.regs[dstreg1] = 0xffff8000;
8057 else
8058 State.regs[dstreg1] = State.regs[srcreg1];
8059
8060 temp = State.regs[dstreg2];
8061 temp >>= State.regs[srcreg2];
8062 State.regs[dstreg2] = temp;
8063}
8064
8065// 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
80668.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asr
8067"sat16_asr"
8068*am33
8069{
8070 int srcreg1, dstreg1, dstreg2;
8071 signed int temp;
8072
8073 PC = cia;
8074 srcreg1 = translate_rreg (SD_, RM1);
8075 dstreg1 = translate_rreg (SD_, RN1);
8076 dstreg2 = translate_rreg (SD_, RN2);
8077
8078 if (State.regs[srcreg1] >= 0x7fff)
8079 State.regs[dstreg1] = 0x7fff;
8080 else if (State.regs[srcreg1] <= 0xffff8000)
8081 State.regs[dstreg1] = 0xffff8000;
8082 else
8083 State.regs[dstreg1] = State.regs[srcreg1];
8084
8085 temp = State.regs[dstreg2];
8086 temp >>= IMM4;
8087 State.regs[dstreg2] = temp;
8088}
8089
8090// 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
80918.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_lsr
8092"sat16_lsr"
8093*am33
8094{
8095 int srcreg1, srcreg2, dstreg1, dstreg2;
8096
8097 PC = cia;
8098 srcreg1 = translate_rreg (SD_, RM1);
8099 srcreg2 = translate_rreg (SD_, RM2);
8100 dstreg1 = translate_rreg (SD_, RN1);
8101 dstreg2 = translate_rreg (SD_, RN2);
8102
8103 if (State.regs[srcreg1] >= 0x7fff)
8104 State.regs[dstreg1] = 0x7fff;
8105 else if (State.regs[srcreg1] <= 0xffff8000)
8106 State.regs[dstreg1] = 0xffff8000;
8107 else
8108 State.regs[dstreg1] = State.regs[srcreg1];
8109
8110 State.regs[dstreg2] >>= State.regs[srcreg2];
8111}
8112
8113// 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
81148.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_lsr
8115"sat16_lsr"
8116*am33
8117{
8118 int srcreg1, dstreg1, dstreg2;
8119 signed int temp;
8120
8121 PC = cia;
8122 srcreg1 = translate_rreg (SD_, RM1);
8123 dstreg1 = translate_rreg (SD_, RN1);
8124 dstreg2 = translate_rreg (SD_, RN2);
8125
8126 if (State.regs[srcreg1] >= 0x7fff)
8127 State.regs[dstreg1] = 0x7fff;
8128 else if (State.regs[srcreg1] <= 0xffff8000)
8129 State.regs[dstreg1] = 0xffff8000;
8130 else
8131 State.regs[dstreg1] = State.regs[srcreg1];
8132
8133 State.regs[dstreg2] >>= IMM4;
8134}
8135
8136
8137// 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
81388.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asl
8139"sat16_asl"
8140*am33
8141{
8142 int srcreg1, srcreg2, dstreg1, dstreg2;
8143
8144 PC = cia;
8145 srcreg1 = translate_rreg (SD_, RM1);
8146 srcreg2 = translate_rreg (SD_, RM2);
8147 dstreg1 = translate_rreg (SD_, RN1);
8148 dstreg2 = translate_rreg (SD_, RN2);
8149
8150 if (State.regs[srcreg1] >= 0x7fff)
8151 State.regs[dstreg1] = 0x7fff;
8152 else if (State.regs[srcreg1] <= 0xffff8000)
8153 State.regs[dstreg1] = 0xffff8000;
8154 else
8155 State.regs[dstreg1] = State.regs[srcreg1];
8156
8157 State.regs[dstreg2] <<= State.regs[srcreg2];
8158}
8159
8160// 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
81618.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asl
8162"sat16_asl"
8163*am33
8164{
8165 int srcreg1, dstreg1, dstreg2;
8166 signed int temp;
8167
8168 PC = cia;
8169 srcreg1 = translate_rreg (SD_, RM1);
8170 dstreg1 = translate_rreg (SD_, RN1);
8171 dstreg2 = translate_rreg (SD_, RN2);
8172
8173 if (State.regs[srcreg1] >= 0x7fff)
8174 State.regs[dstreg1] = 0x7fff;
8175 else if (State.regs[srcreg1] <= 0xffff8000)
8176 State.regs[dstreg1] = 0xffff8000;
8177 else
8178 State.regs[dstreg1] = State.regs[srcreg1];
8179
8180 State.regs[dstreg2] <<= IMM4;
8181}
8182
6ae1456e
JL		 8183// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
81848.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x0:D2:::mov_llt
8185"mov_llt"
8186*am33
8187{
8188 int srcreg, dstreg;
8189
8190 PC = cia;
8191 srcreg = translate_rreg (SD_, RM);
8192 dstreg = translate_rreg (SD_, RN);
8193
8194 State.regs[dstreg] = load_word (State.regs[srcreg]);
8195 State.regs[srcreg] += EXTEND4 (IMM4);
8196
8197 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
8198 {
8199 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8200 nia = PC;
8201 }
8202}
8203
8204// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
82058.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x1:D2:::mov_lgt
8206"mov_lgt"
8207*am33
8208{
8209 int srcreg, dstreg;
8210
8211 PC = cia;
8212 srcreg = translate_rreg (SD_, RM);
8213 dstreg = translate_rreg (SD_, RN);
8214
8215 State.regs[dstreg] = load_word (State.regs[srcreg]);
8216 State.regs[srcreg] += EXTEND4 (IMM4);
8217
8218 if (!((PSW & PSW_Z)
8219 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
8220 {
8221 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8222 nia = PC;
8223 }
8224}
8225
8226// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
82278.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x2:D2:::mov_lge
8228"mov_lge"
8229*am33
8230{
8231 int srcreg, dstreg;
8232
8233 PC = cia;
8234 srcreg = translate_rreg (SD_, RM);
8235 dstreg = translate_rreg (SD_, RN);
8236
8237 State.regs[dstreg] = load_word (State.regs[srcreg]);
8238 State.regs[srcreg] += EXTEND4 (IMM4);
8239
8240 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8241 {
8242 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8243 nia = PC;
8244 }
8245}
8246
8247// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
82488.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x3:D2:::mov_lle
8249"mov_lle"
8250*am33
8251{
8252 int srcreg, dstreg;
8253
8254 PC = cia;
8255 srcreg = translate_rreg (SD_, RM);
8256 dstreg = translate_rreg (SD_, RN);
8257
8258 State.regs[dstreg] = load_word (State.regs[srcreg]);
8259 State.regs[srcreg] += EXTEND4 (IMM4);
8260
8261 if ((PSW & PSW_Z)
8262 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8263 {
8264 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8265 nia = PC;
8266 }
8267}
8268
8269// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
82708.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x4:D2:::mov_lcs
8271"mov_lcs"
8272*am33
8273{
8274 int srcreg, dstreg;
8275
8276 PC = cia;
8277 srcreg = translate_rreg (SD_, RM);
8278 dstreg = translate_rreg (SD_, RN);
8279
8280 State.regs[dstreg] = load_word (State.regs[srcreg]);
8281 State.regs[srcreg] += EXTEND4 (IMM4);
8282
8283 if (PSW & PSW_C)
8284 {
8285 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8286 nia = PC;
8287 }
8288}
8289
8290// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
82918.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x5:D2:::mov_lhi
8292"mov_lhi"
8293*am33
8294{
8295 int srcreg, dstreg;
8296
8297 PC = cia;
8298 srcreg = translate_rreg (SD_, RM);
8299 dstreg = translate_rreg (SD_, RN);
8300
8301 State.regs[dstreg] = load_word (State.regs[srcreg]);
8302 State.regs[srcreg] += EXTEND4 (IMM4);
8303
8304 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8305 {
8306 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8307 nia = PC;
8308 }
8309}
8310
8311// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
83128.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x6:D2:::mov_lcc
8313"mov_lcc"
8314*am33
8315{
8316 int srcreg, dstreg;
8317
8318 PC = cia;
8319 srcreg = translate_rreg (SD_, RM);
8320 dstreg = translate_rreg (SD_, RN);
8321
8322 State.regs[dstreg] = load_word (State.regs[srcreg]);
8323 State.regs[srcreg] += EXTEND4 (IMM4);
8324
8325 if (!(PSW & PSW_C))
8326 {
8327 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8328 nia = PC;
8329 }
8330}
8331
8332// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
83338.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x7:D2:::mov_lls
8334"mov_lls"
8335*am33
8336{
8337 int srcreg, dstreg;
8338
8339 PC = cia;
8340 srcreg = translate_rreg (SD_, RM);
8341 dstreg = translate_rreg (SD_, RN);
8342
8343 State.regs[dstreg] = load_word (State.regs[srcreg]);
8344 State.regs[srcreg] += EXTEND4 (IMM4);
8345
8346 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8347 {
8348 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8349 nia = PC;
8350 }
8351}
8352
8353// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
83548.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x8:D2:::mov_leq
8355"mov_leq"
8356*am33
8357{
8358 int srcreg, dstreg;
8359
8360 PC = cia;
8361 srcreg = translate_rreg (SD_, RM);
8362 dstreg = translate_rreg (SD_, RN);
8363
8364 State.regs[dstreg] = load_word (State.regs[srcreg]);
8365 State.regs[srcreg] += EXTEND4 (IMM4);
8366
8367 if (PSW & PSW_Z)
8368 {
8369 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8370 nia = PC;
8371 }
8372}
8373
8374// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
83758.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x9:D2:::mov_lne
8376"mov_lne"
8377*am33
8378{
8379 int srcreg, dstreg;
8380
8381 PC = cia;
8382 srcreg = translate_rreg (SD_, RM);
8383 dstreg = translate_rreg (SD_, RN);
8384
8385 State.regs[dstreg] = load_word (State.regs[srcreg]);
8386 State.regs[srcreg] += EXTEND4 (IMM4);
8387
8388 if (!(PSW & PSW_Z))
8389 {
8390 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8391 nia = PC;
8392 }
8393}
8394
8395// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
83968.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0xa:D2:::mov_lra
8397"mov_lra"
8398*am33
8399{
8400 int srcreg, dstreg;
8401
8402 PC = cia;
8403 srcreg = translate_rreg (SD_, RM);
8404 dstreg = translate_rreg (SD_, RN);
8405
8406 State.regs[dstreg] = load_word (State.regs[srcreg]);
8407 State.regs[srcreg] += EXTEND4 (IMM4);
8408
8409 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8410 nia = PC;
8411}
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