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Commit | Line | Data |
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c906108c | 1 | #include "sim-main.h" |
61a0c964 | 2 | #include "sim-syscall.h" |
c906108c SS |
3 | #include "targ-vals.h" |
4 | ||
c906108c | 5 | #include <time.h> |
c906108c SS |
6 | #ifdef HAVE_UNISTD_H |
7 | #include <unistd.h> | |
8 | #endif | |
c906108c | 9 | #include <string.h> |
c906108c SS |
10 | #include <sys/stat.h> |
11 | #include <sys/times.h> | |
12 | #include <sys/time.h> | |
13 | ||
14 | ||
15 | ||
16 | #define REG0(X) ((X) & 0x3) | |
17 | #define REG1(X) (((X) & 0xc) >> 2) | |
18 | #define REG0_4(X) (((X) & 0x30) >> 4) | |
19 | #define REG0_8(X) (((X) & 0x300) >> 8) | |
20 | #define REG1_8(X) (((X) & 0xc00) >> 10) | |
21 | #define REG0_16(X) (((X) & 0x30000) >> 16) | |
22 | #define REG1_16(X) (((X) & 0xc0000) >> 18) | |
23 | ||
24 | ||
25 | INLINE_SIM_MAIN (void) | |
24a39d88 | 26 | genericAdd(unsigned32 source, unsigned32 destReg) |
c906108c SS |
27 | { |
28 | int z, c, n, v; | |
24a39d88 | 29 | unsigned32 dest, sum; |
c906108c SS |
30 | |
31 | dest = State.regs[destReg]; | |
32 | sum = source + dest; | |
33 | State.regs[destReg] = sum; | |
34 | ||
35 | z = (sum == 0); | |
36 | n = (sum & 0x80000000); | |
37 | c = (sum < source) || (sum < dest); | |
38 | v = ((dest & 0x80000000) == (source & 0x80000000) | |
39 | && (dest & 0x80000000) != (sum & 0x80000000)); | |
40 | ||
41 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
42 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
43 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
44 | } | |
45 | ||
46 | ||
47 | ||
48 | ||
49 | INLINE_SIM_MAIN (void) | |
24a39d88 | 50 | genericSub(unsigned32 source, unsigned32 destReg) |
c906108c SS |
51 | { |
52 | int z, c, n, v; | |
24a39d88 | 53 | unsigned32 dest, difference; |
c906108c SS |
54 | |
55 | dest = State.regs[destReg]; | |
56 | difference = dest - source; | |
57 | State.regs[destReg] = difference; | |
58 | ||
59 | z = (difference == 0); | |
60 | n = (difference & 0x80000000); | |
61 | c = (source > dest); | |
62 | v = ((dest & 0x80000000) != (source & 0x80000000) | |
63 | && (dest & 0x80000000) != (difference & 0x80000000)); | |
64 | ||
65 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
66 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
67 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
68 | } | |
69 | ||
70 | INLINE_SIM_MAIN (void) | |
24a39d88 | 71 | genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd) |
c906108c SS |
72 | { |
73 | int z, c, n, v; | |
24a39d88 | 74 | unsigned32 value; |
c906108c SS |
75 | |
76 | value = rightOpnd - leftOpnd; | |
77 | ||
78 | z = (value == 0); | |
79 | n = (value & 0x80000000); | |
80 | c = (leftOpnd > rightOpnd); | |
81 | v = ((rightOpnd & 0x80000000) != (leftOpnd & 0x80000000) | |
82 | && (rightOpnd & 0x80000000) != (value & 0x80000000)); | |
83 | ||
84 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
85 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
86 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
87 | } | |
88 | ||
89 | ||
90 | INLINE_SIM_MAIN (void) | |
24a39d88 | 91 | genericOr(unsigned32 source, unsigned32 destReg) |
c906108c SS |
92 | { |
93 | int n, z; | |
94 | ||
95 | State.regs[destReg] |= source; | |
96 | z = (State.regs[destReg] == 0); | |
97 | n = (State.regs[destReg] & 0x80000000) != 0; | |
98 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
99 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
100 | } | |
101 | ||
102 | ||
103 | INLINE_SIM_MAIN (void) | |
24a39d88 | 104 | genericXor(unsigned32 source, unsigned32 destReg) |
c906108c SS |
105 | { |
106 | int n, z; | |
107 | ||
108 | State.regs[destReg] ^= source; | |
109 | z = (State.regs[destReg] == 0); | |
110 | n = (State.regs[destReg] & 0x80000000) != 0; | |
111 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
112 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
113 | } | |
114 | ||
115 | ||
116 | INLINE_SIM_MAIN (void) | |
24a39d88 | 117 | genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd) |
c906108c | 118 | { |
24a39d88 | 119 | unsigned32 temp; |
c906108c SS |
120 | int z, n; |
121 | ||
122 | temp = rightOpnd; | |
123 | temp &= leftOpnd; | |
124 | n = (temp & 0x80000000) != 0; | |
125 | z = (temp == 0); | |
126 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
127 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
128 | } | |
129 | ||
c906108c SS |
130 | /* syscall */ |
131 | INLINE_SIM_MAIN (void) | |
489503ee | 132 | do_syscall (void) |
c906108c | 133 | { |
7d5c6c43 MF |
134 | /* Registers passed to trap 0. */ |
135 | ||
136 | /* Function number. */ | |
137 | reg_t func = State.regs[0]; | |
138 | /* Parameters. */ | |
139 | reg_t parm1 = State.regs[1]; | |
140 | reg_t parm2 = load_word (State.regs[REG_SP] + 12); | |
141 | reg_t parm3 = load_word (State.regs[REG_SP] + 16); | |
142 | reg_t parm4 = load_word (State.regs[REG_SP] + 20); | |
c906108c SS |
143 | |
144 | /* We use this for simulated system calls; we may need to change | |
145 | it to a reserved instruction if we conflict with uses at | |
146 | Matsushita. */ | |
147 | int save_errno = errno; | |
148 | errno = 0; | |
149 | ||
7d5c6c43 | 150 | if (func == TARGET_SYS_exit) |
c906108c | 151 | { |
7d5c6c43 | 152 | /* EXIT - caller can look in parm1 to work out the reason */ |
96eaf29e | 153 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, |
7d5c6c43 | 154 | (parm1 == 0xdead ? SIM_SIGABRT : sim_exited), parm1); |
c906108c SS |
155 | } |
156 | else | |
157 | { | |
7d5c6c43 MF |
158 | long result, result2; |
159 | int errcode; | |
c906108c | 160 | |
7d5c6c43 MF |
161 | sim_syscall_multi (STATE_CPU (simulator, 0), func, parm1, parm2, |
162 | parm3, parm4, &result, &result2, &errcode); | |
163 | ||
164 | /* Registers set by trap 0. */ | |
165 | State.regs[0] = errcode; | |
166 | State.regs[1] = result; | |
167 | } | |
c906108c SS |
168 | |
169 | errno = save_errno; | |
170 | } |