[thirdparty/binutils-gdb.git] / sim / or1k / Makefile.in

# Makefile template for configure for the or1k simulator
# Copyright (C) 2017-2021 Free Software Foundation, Inc.
#
# This file is part of GDB, the GNU debugger.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program.  If not, see <http://www.gnu.org/licenses/>.

## COMMON_PRE_CONFIG_FRAG

OR1K_OBJS = \
	or1k.o \
	arch.o \
	cpu.o \
	decode.o \
	model.o \
	sem.o \
	mloop.o \
	sim-if.o \
	traps.o

SIM_OBJS = \
	$(SIM_NEW_COMMON_OBJS) \
	cgen-utils.o \
	cgen-trace.o \
	cgen-scache.o \
	cgen-run.o \
	cgen-fpu.o \
	cgen-accfp.o

SIM_OBJS += $(OR1K_OBJS)

# Extra headers included by sim-main.h.
SIM_EXTRA_DEPS = \
	$(CGEN_INCLUDE_DEPS) \
	or1k-sim.h \
	$(srcdir)/../../opcodes/or1k-desc.h \
	arch.h \
	cpuall.h \
	decode.h

SIM_EXTRA_CFLAGS =

SIM_EXTRA_LIBS = -lm

SIM_EXTRA_CLEAN = or1k-clean

# Code doesn't build cleanly yet.
SIM_WERROR_CFLAGS =

## COMMON_POST_CONFIG_FRAG

arch = or1k

# or1k32bf

OR1K32BF_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpu.h \
	decode.h \
	eng.h

mloop.c eng.h: stamp-mloop ; @true
stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
	$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
		-mono -fast -pbb -switch sem-switch.c \
		-cpu or1k32bf -infile $(srcdir)/mloop.in
	$(SILENCE) $(SHELL) $(srcroot)/move-if-change eng.hin eng.h
	$(SILENCE) $(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
	$(SILENCE) touch $@
or1k.o: or1k.c $(OR1K32BF_INCLUDE_DEPS)
	$(COMPILE) $<
	$(POSTCOMPILE)

sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h eng.h
	$(COMPILE) $<
	$(POSTCOMPILE)

traps.o: traps.c $(SIM_MAIN_DEPS) eng.h
	$(COMPILE) $<
	$(POSTCOMPILE)

or1k-clean:
	rm -f mloop.c eng.h stamp-mloop

stamps: stamp-arch stamp-cpu stamp-mloop

# NOTE: Generated source files are specified as full paths,
# e.g. $(srcdir)/arch.c, because make may decide the files live
# in objdir otherwise.

OR1K_CGEN_DEPS = \
	$(CPU_DIR)/or1k.cpu \
	$(CPU_DIR)/or1k.opc \
	$(CPU_DIR)/or1kcommon.cpu \
	$(CPU_DIR)/or1korbis.cpu \
	$(CPU_DIR)/or1korfpx.cpu \
	Makefile

stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(OR1K_CGEN_DEPS)
	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) \
	  mach=or32,or32nd \
	  archfile=$(CPU_DIR)/or1k.cpu \
	  FLAGS="with-scache"
	$(SILENCE) touch $@
$(srcdir)/arch.h $(srcdir)/arch.c $(srcdir)/cpuall.h: $(CGEN_MAINT) stamp-arch
	@true

stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(OR1K_CGEN_DEPS)
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	  cpu=or1k32bf \
	  mach=or32,or32nd \
	  archfile=$(CPU_DIR)/or1k.cpu \
	  FLAGS="with-scache" \
	  EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
	$(SILENCE) touch $@
$(srcdir)/cpu.h $(srcdir)/cpu.c $(srcdir)/model.c $(srcdir)/sem.c $(srcdir)/sem-switch.c $(srcdir)/decode.c $(srcdir)/decode.h: $(CGEN_MAINT) stamp-cpu
	@true
Commit	Line	Data
fa8b7c21	1	# Makefile template for configure for the or1k simulator
3666a048	2	# Copyright (C) 2017-2021 Free Software Foundation, Inc.
fa8b7c21 SH	3	#
	4	# This file is part of GDB, the GNU debugger.
	5	#
	6	# This program is free software; you can redistribute it and/or modify
	7	# it under the terms of the GNU General Public License as published by
	8	# the Free Software Foundation; either version 3 of the License, or
	9	# (at your option) any later version.
	10	#
	11	# This program is distributed in the hope that it will be useful,
	12	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	# GNU General Public License for more details.
	15	#
	16	# You should have received a copy of the GNU General Public License
	17	# along with this program. If not, see <http://www.gnu.org/licenses/>.
	18
	19	## COMMON_PRE_CONFIG_FRAG
	20
	21	OR1K_OBJS = \
	22	or1k.o \
	23	arch.o \
	24	cpu.o \
	25	decode.o \
	26	model.o \
	27	sem.o \
	28	mloop.o \
	29	sim-if.o \
	30	traps.o
	31
	32	SIM_OBJS = \
	33	$(SIM_NEW_COMMON_OBJS) \
fa8b7c21 SH	34	cgen-utils.o \
	35	cgen-trace.o \
	36	cgen-scache.o \
	37	cgen-run.o \
	38	cgen-fpu.o \
5e9e2f41	39	cgen-accfp.o
fa8b7c21 SH	40
	41	SIM_OBJS += $(OR1K_OBJS)
	42
	43	# Extra headers included by sim-main.h.
	44	SIM_EXTRA_DEPS = \
	45	$(CGEN_INCLUDE_DEPS) \
	46	or1k-sim.h \
	47	$(srcdir)/../../opcodes/or1k-desc.h \
	48	arch.h \
	49	cpuall.h \
	50	decode.h
	51
	52	SIM_EXTRA_CFLAGS =
	53
	54	SIM_EXTRA_LIBS = -lm
	55
fa8b7c21 SH	56	SIM_EXTRA_CLEAN = or1k-clean
fa8b7c21 SH	57
982c3a65 MF	58	# Code doesn't build cleanly yet.
	59	SIM_WERROR_CFLAGS =
	60
fa8b7c21 SH	61	## COMMON_POST_CONFIG_FRAG
	62
	63	arch = or1k
	64
	65	# or1k32bf
	66
	67	OR1K32BF_INCLUDE_DEPS = \
	68	$(CGEN_MAIN_CPU_DEPS) \
	69	cpu.h \
	70	decode.h \
	71	eng.h
	72
	73	mloop.c eng.h: stamp-mloop ; @true
	74	stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
	75	$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
	76	-mono -fast -pbb -switch sem-switch.c \
	77	-cpu or1k32bf -infile $(srcdir)/mloop.in
4f2b181e MF	78	$(SILENCE) $(SHELL) $(srcroot)/move-if-change eng.hin eng.h
4f2b181e MF	79	$(SILENCE) $(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
b6143d31	80	$(SILENCE) touch $@
fa8b7c21 SH	81	or1k.o: or1k.c $(OR1K32BF_INCLUDE_DEPS)
	82	$(COMPILE) $<
	83	$(POSTCOMPILE)
fa8b7c21 SH	84
	85	sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h eng.h
	86	$(COMPILE) $<
	87	$(POSTCOMPILE)
	88
	89	traps.o: traps.c $(SIM_MAIN_DEPS) eng.h
	90	$(COMPILE) $<
	91	$(POSTCOMPILE)
	92
	93	or1k-clean:
	94	rm -f mloop.c eng.h stamp-mloop
	95
fa8b7c21 SH	96	stamps: stamp-arch stamp-cpu stamp-mloop
	97
	98	# NOTE: Generated source files are specified as full paths,
	99	# e.g. $(srcdir)/arch.c, because make may decide the files live
	100	# in objdir otherwise.
	101
	102	OR1K_CGEN_DEPS = \
	103	$(CPU_DIR)/or1k.cpu \
	104	$(CPU_DIR)/or1k.opc \
	105	$(CPU_DIR)/or1kcommon.cpu \
	106	$(CPU_DIR)/or1korbis.cpu \
	107	$(CPU_DIR)/or1korfpx.cpu \
	108	Makefile
	109
	110	stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(OR1K_CGEN_DEPS)
	111	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) \
	112	mach=or32,or32nd \
	113	archfile=$(CPU_DIR)/or1k.cpu \
	114	FLAGS="with-scache"
b6143d31	115	$(SILENCE) touch $@
fa8b7c21 SH	116	$(srcdir)/arch.h $(srcdir)/arch.c $(srcdir)/cpuall.h: $(CGEN_MAINT) stamp-arch
	117	@true
	118
	119	stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(OR1K_CGEN_DEPS)
	120	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	121	cpu=or1k32bf \
	122	mach=or32,or32nd \
	123	archfile=$(CPU_DIR)/or1k.cpu \
	124	FLAGS="with-scache" \
	125	EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
b6143d31	126	$(SILENCE) touch $@
fa8b7c21 SH	127	$(srcdir)/cpu.h $(srcdir)/cpu.c $(srcdir)/model.c $(srcdir)/sem.c $(srcdir)/sem-switch.c $(srcdir)/decode.c $(srcdir)/decode.h: $(CGEN_MAINT) stamp-cpu
fa8b7c21 SH	128	@true