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[thirdparty/binutils-gdb.git] / sim / sh64 / decode-media.h
CommitLineData
cbb38b47
BE		 1/* Decode header for sh64_media.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
8acc9f48 5Copyright 1996-2013 Free Software Foundation, Inc.
cbb38b47 6
c7e628df 7This file is part of the GNU simulators.
cbb38b47 8
fda1c30b
DE		 9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
cbb38b47 13
fda1c30b
DE		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
cbb38b47 18
fda1c30b 19 You should have received a copy of the GNU General Public License along
51b318de 20 with this program; if not, see <http://www.gnu.org/licenses/>.
cbb38b47
BE		 21
22*/
23
24#ifndef SH64_MEDIA_DECODE_H
25#define SH64_MEDIA_DECODE_H
26
27extern const IDESC *sh64_media_decode (SIM_CPU *, IADDR,
197fa1aa 28 CGEN_INSN_WORD, CGEN_INSN_WORD,
cbb38b47
BE		 29 ARGBUF *);
30extern void sh64_media_init_idesc_table (SIM_CPU *);
31extern void sh64_media_sem_init_idesc_table (SIM_CPU *);
32extern void sh64_media_semf_init_idesc_table (SIM_CPU *);
33
34/* Enum declaration for instructions in cpu family sh64. */
35typedef enum sh64_media_insn_type {
36 SH64_MEDIA_INSN_X_INVALID, SH64_MEDIA_INSN_X_AFTER, SH64_MEDIA_INSN_X_BEFORE, SH64_MEDIA_INSN_X_CTI_CHAIN
37 , SH64_MEDIA_INSN_X_CHAIN, SH64_MEDIA_INSN_X_BEGIN, SH64_MEDIA_INSN_ADD, SH64_MEDIA_INSN_ADDL
38 , SH64_MEDIA_INSN_ADDI, SH64_MEDIA_INSN_ADDIL, SH64_MEDIA_INSN_ADDZL, SH64_MEDIA_INSN_ALLOCO
39 , SH64_MEDIA_INSN_AND, SH64_MEDIA_INSN_ANDC, SH64_MEDIA_INSN_ANDI, SH64_MEDIA_INSN_BEQ
40 , SH64_MEDIA_INSN_BEQI, SH64_MEDIA_INSN_BGE, SH64_MEDIA_INSN_BGEU, SH64_MEDIA_INSN_BGT
41 , SH64_MEDIA_INSN_BGTU, SH64_MEDIA_INSN_BLINK, SH64_MEDIA_INSN_BNE, SH64_MEDIA_INSN_BNEI
42 , SH64_MEDIA_INSN_BRK, SH64_MEDIA_INSN_BYTEREV, SH64_MEDIA_INSN_CMPEQ, SH64_MEDIA_INSN_CMPGT
43 , SH64_MEDIA_INSN_CMPGTU, SH64_MEDIA_INSN_CMVEQ, SH64_MEDIA_INSN_CMVNE, SH64_MEDIA_INSN_FABSD
44 , SH64_MEDIA_INSN_FABSS, SH64_MEDIA_INSN_FADDD, SH64_MEDIA_INSN_FADDS, SH64_MEDIA_INSN_FCMPEQD
45 , SH64_MEDIA_INSN_FCMPEQS, SH64_MEDIA_INSN_FCMPGED, SH64_MEDIA_INSN_FCMPGES, SH64_MEDIA_INSN_FCMPGTD
46 , SH64_MEDIA_INSN_FCMPGTS, SH64_MEDIA_INSN_FCMPUND, SH64_MEDIA_INSN_FCMPUNS, SH64_MEDIA_INSN_FCNVDS
47 , SH64_MEDIA_INSN_FCNVSD, SH64_MEDIA_INSN_FDIVD, SH64_MEDIA_INSN_FDIVS, SH64_MEDIA_INSN_FGETSCR
48 , SH64_MEDIA_INSN_FIPRS, SH64_MEDIA_INSN_FLDD, SH64_MEDIA_INSN_FLDP, SH64_MEDIA_INSN_FLDS
49 , SH64_MEDIA_INSN_FLDXD, SH64_MEDIA_INSN_FLDXP, SH64_MEDIA_INSN_FLDXS, SH64_MEDIA_INSN_FLOATLD
50 , SH64_MEDIA_INSN_FLOATLS, SH64_MEDIA_INSN_FLOATQD, SH64_MEDIA_INSN_FLOATQS, SH64_MEDIA_INSN_FMACS
51 , SH64_MEDIA_INSN_FMOVD, SH64_MEDIA_INSN_FMOVDQ, SH64_MEDIA_INSN_FMOVLS, SH64_MEDIA_INSN_FMOVQD
52 , SH64_MEDIA_INSN_FMOVS, SH64_MEDIA_INSN_FMOVSL, SH64_MEDIA_INSN_FMULD, SH64_MEDIA_INSN_FMULS
53 , SH64_MEDIA_INSN_FNEGD, SH64_MEDIA_INSN_FNEGS, SH64_MEDIA_INSN_FPUTSCR, SH64_MEDIA_INSN_FSQRTD
54 , SH64_MEDIA_INSN_FSQRTS, SH64_MEDIA_INSN_FSTD, SH64_MEDIA_INSN_FSTP, SH64_MEDIA_INSN_FSTS
55 , SH64_MEDIA_INSN_FSTXD, SH64_MEDIA_INSN_FSTXP, SH64_MEDIA_INSN_FSTXS, SH64_MEDIA_INSN_FSUBD
56 , SH64_MEDIA_INSN_FSUBS, SH64_MEDIA_INSN_FTRCDL, SH64_MEDIA_INSN_FTRCSL, SH64_MEDIA_INSN_FTRCDQ
57 , SH64_MEDIA_INSN_FTRCSQ, SH64_MEDIA_INSN_FTRVS, SH64_MEDIA_INSN_GETCFG, SH64_MEDIA_INSN_GETCON
58 , SH64_MEDIA_INSN_GETTR, SH64_MEDIA_INSN_ICBI, SH64_MEDIA_INSN_LDB, SH64_MEDIA_INSN_LDL
59 , SH64_MEDIA_INSN_LDQ, SH64_MEDIA_INSN_LDUB, SH64_MEDIA_INSN_LDUW, SH64_MEDIA_INSN_LDW
60 , SH64_MEDIA_INSN_LDHIL, SH64_MEDIA_INSN_LDHIQ, SH64_MEDIA_INSN_LDLOL, SH64_MEDIA_INSN_LDLOQ
61 , SH64_MEDIA_INSN_LDXB, SH64_MEDIA_INSN_LDXL, SH64_MEDIA_INSN_LDXQ, SH64_MEDIA_INSN_LDXUB
62 , SH64_MEDIA_INSN_LDXUW, SH64_MEDIA_INSN_LDXW, SH64_MEDIA_INSN_MABSL, SH64_MEDIA_INSN_MABSW
63 , SH64_MEDIA_INSN_MADDL, SH64_MEDIA_INSN_MADDW, SH64_MEDIA_INSN_MADDSL, SH64_MEDIA_INSN_MADDSUB
64 , SH64_MEDIA_INSN_MADDSW, SH64_MEDIA_INSN_MCMPEQB, SH64_MEDIA_INSN_MCMPEQL, SH64_MEDIA_INSN_MCMPEQW
65 , SH64_MEDIA_INSN_MCMPGTL, SH64_MEDIA_INSN_MCMPGTUB, SH64_MEDIA_INSN_MCMPGTW, SH64_MEDIA_INSN_MCMV
66 , SH64_MEDIA_INSN_MCNVSLW, SH64_MEDIA_INSN_MCNVSWB, SH64_MEDIA_INSN_MCNVSWUB, SH64_MEDIA_INSN_MEXTR1
67 , SH64_MEDIA_INSN_MEXTR2, SH64_MEDIA_INSN_MEXTR3, SH64_MEDIA_INSN_MEXTR4, SH64_MEDIA_INSN_MEXTR5
68 , SH64_MEDIA_INSN_MEXTR6, SH64_MEDIA_INSN_MEXTR7, SH64_MEDIA_INSN_MMACFXWL, SH64_MEDIA_INSN_MMACNFX_WL
69 , SH64_MEDIA_INSN_MMULL, SH64_MEDIA_INSN_MMULW, SH64_MEDIA_INSN_MMULFXL, SH64_MEDIA_INSN_MMULFXW
70 , SH64_MEDIA_INSN_MMULFXRPW, SH64_MEDIA_INSN_MMULHIWL, SH64_MEDIA_INSN_MMULLOWL, SH64_MEDIA_INSN_MMULSUMWQ
71 , SH64_MEDIA_INSN_MOVI, SH64_MEDIA_INSN_MPERMW, SH64_MEDIA_INSN_MSADUBQ, SH64_MEDIA_INSN_MSHALDSL
72 , SH64_MEDIA_INSN_MSHALDSW, SH64_MEDIA_INSN_MSHARDL, SH64_MEDIA_INSN_MSHARDW, SH64_MEDIA_INSN_MSHARDSQ
73 , SH64_MEDIA_INSN_MSHFHIB, SH64_MEDIA_INSN_MSHFHIL, SH64_MEDIA_INSN_MSHFHIW, SH64_MEDIA_INSN_MSHFLOB
74 , SH64_MEDIA_INSN_MSHFLOL, SH64_MEDIA_INSN_MSHFLOW, SH64_MEDIA_INSN_MSHLLDL, SH64_MEDIA_INSN_MSHLLDW
75 , SH64_MEDIA_INSN_MSHLRDL, SH64_MEDIA_INSN_MSHLRDW, SH64_MEDIA_INSN_MSUBL, SH64_MEDIA_INSN_MSUBW
76 , SH64_MEDIA_INSN_MSUBSL, SH64_MEDIA_INSN_MSUBSUB, SH64_MEDIA_INSN_MSUBSW, SH64_MEDIA_INSN_MULSL
77 , SH64_MEDIA_INSN_MULUL, SH64_MEDIA_INSN_NOP, SH64_MEDIA_INSN_NSB, SH64_MEDIA_INSN_OCBI
78 , SH64_MEDIA_INSN_OCBP, SH64_MEDIA_INSN_OCBWB, SH64_MEDIA_INSN_OR, SH64_MEDIA_INSN_ORI
79 , SH64_MEDIA_INSN_PREFI, SH64_MEDIA_INSN_PTA, SH64_MEDIA_INSN_PTABS, SH64_MEDIA_INSN_PTB
80 , SH64_MEDIA_INSN_PTREL, SH64_MEDIA_INSN_PUTCFG, SH64_MEDIA_INSN_PUTCON, SH64_MEDIA_INSN_RTE
81 , SH64_MEDIA_INSN_SHARD, SH64_MEDIA_INSN_SHARDL, SH64_MEDIA_INSN_SHARI, SH64_MEDIA_INSN_SHARIL
82 , SH64_MEDIA_INSN_SHLLD, SH64_MEDIA_INSN_SHLLDL, SH64_MEDIA_INSN_SHLLI, SH64_MEDIA_INSN_SHLLIL
83 , SH64_MEDIA_INSN_SHLRD, SH64_MEDIA_INSN_SHLRDL, SH64_MEDIA_INSN_SHLRI, SH64_MEDIA_INSN_SHLRIL
84 , SH64_MEDIA_INSN_SHORI, SH64_MEDIA_INSN_SLEEP, SH64_MEDIA_INSN_STB, SH64_MEDIA_INSN_STL
85 , SH64_MEDIA_INSN_STQ, SH64_MEDIA_INSN_STW, SH64_MEDIA_INSN_STHIL, SH64_MEDIA_INSN_STHIQ
86 , SH64_MEDIA_INSN_STLOL, SH64_MEDIA_INSN_STLOQ, SH64_MEDIA_INSN_STXB, SH64_MEDIA_INSN_STXL
87 , SH64_MEDIA_INSN_STXQ, SH64_MEDIA_INSN_STXW, SH64_MEDIA_INSN_SUB, SH64_MEDIA_INSN_SUBL
88 , SH64_MEDIA_INSN_SWAPQ, SH64_MEDIA_INSN_SYNCI, SH64_MEDIA_INSN_SYNCO, SH64_MEDIA_INSN_TRAPA
c7e628df 89 , SH64_MEDIA_INSN_XOR, SH64_MEDIA_INSN_XORI, SH64_MEDIA_INSN__MAX
cbb38b47
BE		 90} SH64_MEDIA_INSN_TYPE;
91
92/* Enum declaration for semantic formats in cpu family sh64. */
93typedef enum sh64_media_sfmt_type {
94 SH64_MEDIA_SFMT_EMPTY, SH64_MEDIA_SFMT_ADD, SH64_MEDIA_SFMT_ADDI, SH64_MEDIA_SFMT_ALLOCO
c5351010
DE		 95 , SH64_MEDIA_SFMT_BEQ, SH64_MEDIA_SFMT_BEQI, SH64_MEDIA_SFMT_BLINK, SH64_MEDIA_SFMT_BNEI
96 , SH64_MEDIA_SFMT_BRK, SH64_MEDIA_SFMT_BYTEREV, SH64_MEDIA_SFMT_CMVEQ, SH64_MEDIA_SFMT_FABSD
97 , SH64_MEDIA_SFMT_FABSS, SH64_MEDIA_SFMT_FADDD, SH64_MEDIA_SFMT_FADDS, SH64_MEDIA_SFMT_FCMPEQD
98 , SH64_MEDIA_SFMT_FCMPEQS, SH64_MEDIA_SFMT_FCNVDS, SH64_MEDIA_SFMT_FCNVSD, SH64_MEDIA_SFMT_FGETSCR
99 , SH64_MEDIA_SFMT_FIPRS, SH64_MEDIA_SFMT_FLDD, SH64_MEDIA_SFMT_FLDP, SH64_MEDIA_SFMT_FLDS
100 , SH64_MEDIA_SFMT_FLDXD, SH64_MEDIA_SFMT_FLDXP, SH64_MEDIA_SFMT_FLDXS, SH64_MEDIA_SFMT_FMACS
101 , SH64_MEDIA_SFMT_FMOVDQ, SH64_MEDIA_SFMT_FMOVLS, SH64_MEDIA_SFMT_FMOVQD, SH64_MEDIA_SFMT_FMOVSL
102 , SH64_MEDIA_SFMT_FPUTSCR, SH64_MEDIA_SFMT_FSTD, SH64_MEDIA_SFMT_FSTS, SH64_MEDIA_SFMT_FSTXD
103 , SH64_MEDIA_SFMT_FSTXS, SH64_MEDIA_SFMT_FSUBD, SH64_MEDIA_SFMT_FTRCDQ, SH64_MEDIA_SFMT_FTRVS
104 , SH64_MEDIA_SFMT_GETCFG, SH64_MEDIA_SFMT_GETCON, SH64_MEDIA_SFMT_GETTR, SH64_MEDIA_SFMT_LDB
105 , SH64_MEDIA_SFMT_LDL, SH64_MEDIA_SFMT_LDQ, SH64_MEDIA_SFMT_LDUW, SH64_MEDIA_SFMT_LDHIL
106 , SH64_MEDIA_SFMT_LDHIQ, SH64_MEDIA_SFMT_LDLOL, SH64_MEDIA_SFMT_LDLOQ, SH64_MEDIA_SFMT_LDXB
107 , SH64_MEDIA_SFMT_LDXL, SH64_MEDIA_SFMT_LDXQ, SH64_MEDIA_SFMT_LDXUB, SH64_MEDIA_SFMT_LDXUW
108 , SH64_MEDIA_SFMT_LDXW, SH64_MEDIA_SFMT_MCMV, SH64_MEDIA_SFMT_MMACNFX_WL, SH64_MEDIA_SFMT_MOVI
109 , SH64_MEDIA_SFMT_NOP, SH64_MEDIA_SFMT_ORI, SH64_MEDIA_SFMT_PREFI, SH64_MEDIA_SFMT_PTA
110 , SH64_MEDIA_SFMT_PTABS, SH64_MEDIA_SFMT_PTREL, SH64_MEDIA_SFMT_PUTCFG, SH64_MEDIA_SFMT_PUTCON
111 , SH64_MEDIA_SFMT_SHARI, SH64_MEDIA_SFMT_SHORI, SH64_MEDIA_SFMT_STB, SH64_MEDIA_SFMT_STL
112 , SH64_MEDIA_SFMT_STQ, SH64_MEDIA_SFMT_STW, SH64_MEDIA_SFMT_STHIL, SH64_MEDIA_SFMT_STHIQ
113 , SH64_MEDIA_SFMT_STLOL, SH64_MEDIA_SFMT_STLOQ, SH64_MEDIA_SFMT_STXB, SH64_MEDIA_SFMT_STXL
114 , SH64_MEDIA_SFMT_STXQ, SH64_MEDIA_SFMT_STXW, SH64_MEDIA_SFMT_SWAPQ, SH64_MEDIA_SFMT_TRAPA
115 , SH64_MEDIA_SFMT_XORI
cbb38b47
BE		 116} SH64_MEDIA_SFMT_TYPE;
117
118/* Function unit handlers (user written). */
119
c7e628df
DB		 120extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
121extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
122extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
123extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
124extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
125extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
126extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
127extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
128extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
129extern int sh64_model_sh5_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
130extern int sh64_model_sh5_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
131extern int sh64_model_sh5_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
132extern int sh64_model_sh5_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
133extern int sh64_model_sh5_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
134extern int sh64_model_sh5_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
135extern int sh64_model_sh5_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
136extern int sh64_model_sh5_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
137extern int sh64_model_sh5_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
138extern int sh64_model_sh5_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
139extern int sh64_model_sh5_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
140extern int sh64_model_sh5_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
141extern int sh64_model_sh5_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
142extern int sh64_model_sh5_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
143extern int sh64_model_sh5_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
144extern int sh64_model_sh5_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
145extern int sh64_model_sh5_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
146extern int sh64_model_sh5_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
147extern int sh64_model_sh5_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
148extern int sh64_model_sh5_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
149extern int sh64_model_sh5_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
150extern int sh64_model_sh5_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
151extern int sh64_model_sh5_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
152extern int sh64_model_sh5_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
153extern int sh64_model_sh5_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
154extern int sh64_model_sh5_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
155extern int sh64_model_sh5_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
156extern int sh64_model_sh5_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
157extern int sh64_model_sh5_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
158extern int sh64_model_sh5_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
159extern int sh64_model_sh5_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
160extern int sh64_model_sh5_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
161extern int sh64_model_sh5_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
162extern int sh64_model_sh5_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
163extern int sh64_model_sh5_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
164extern int sh64_model_sh5_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
165extern int sh64_model_sh5_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
166extern int sh64_model_sh5_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
167extern int sh64_model_sh5_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
168extern int sh64_model_sh5_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
169extern int sh64_model_sh5_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
170extern int sh64_model_sh5_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
171extern int sh64_model_sh5_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
172extern int sh64_model_sh5_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
173extern int sh64_model_sh5_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
174extern int sh64_model_sh5_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
175extern int sh64_model_sh5_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
176extern int sh64_model_sh5_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
177extern int sh64_model_sh5_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
178extern int sh64_model_sh5_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
179extern int sh64_model_sh5_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
180extern int sh64_model_sh5_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
cbb38b47 181extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
c7e628df
DB		 182extern int sh64_model_sh5_media_u_putcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
183extern int sh64_model_sh5_media_u_getcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
184extern int sh64_model_sh5_media_u_pt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
185extern int sh64_model_sh5_media_u_ftrvs (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
186extern int sh64_model_sh5_media_u_fsqrtd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
187extern int sh64_model_sh5_media_u_fdivd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
188extern int sh64_model_sh5_media_u_cond_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
189extern int sh64_model_sh5_media_u_blink (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
190extern int sh64_model_sh5_media_u_use_tr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
191extern int sh64_model_sh5_media_u_use_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
192extern int sh64_model_sh5_media_u_use_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
193extern int sh64_model_sh5_media_u_use_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
194extern int sh64_model_sh5_media_u_load_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
195extern int sh64_model_sh5_media_u_load_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
196extern int sh64_model_sh5_media_u_load_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
197extern int sh64_model_sh5_media_u_set_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
198extern int sh64_model_sh5_media_u_set_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
199extern int sh64_model_sh5_media_u_set_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
200extern int sh64_model_sh5_media_u_set_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
201extern int sh64_model_sh5_media_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
202extern int sh64_model_sh5_media_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
203extern int sh64_model_sh5_media_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
204extern int sh64_model_sh5_media_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
205extern int sh64_model_sh5_media_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
206extern int sh64_model_sh5_media_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
207extern int sh64_model_sh5_media_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
208extern int sh64_model_sh5_media_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
209extern int sh64_model_sh5_media_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
210extern int sh64_model_sh5_media_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
211extern int sh64_model_sh5_media_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
212extern int sh64_model_sh5_media_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
213extern int sh64_model_sh5_media_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
214extern int sh64_model_sh5_media_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
215extern int sh64_model_sh5_media_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
216extern int sh64_model_sh5_media_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
217extern int sh64_model_sh5_media_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
218extern int sh64_model_sh5_media_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
219extern int sh64_model_sh5_media_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
220extern int sh64_model_sh5_media_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
221extern int sh64_model_sh5_media_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
222extern int sh64_model_sh5_media_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
223extern int sh64_model_sh5_media_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
224extern int sh64_model_sh5_media_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
225extern int sh64_model_sh5_media_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
226extern int sh64_model_sh5_media_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
227extern int sh64_model_sh5_media_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
228extern int sh64_model_sh5_media_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
229extern int sh64_model_sh5_media_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
230extern int sh64_model_sh5_media_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
231extern int sh64_model_sh5_media_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
232extern int sh64_model_sh5_media_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
233extern int sh64_model_sh5_media_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
234extern int sh64_model_sh5_media_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
235extern int sh64_model_sh5_media_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
236extern int sh64_model_sh5_media_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
237extern int sh64_model_sh5_media_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
238extern int sh64_model_sh5_media_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
239extern int sh64_model_sh5_media_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
240extern int sh64_model_sh5_media_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
241extern int sh64_model_sh5_media_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
242extern int sh64_model_sh5_media_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
243extern int sh64_model_sh5_media_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
244extern int sh64_model_sh5_media_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
245extern int sh64_model_sh5_media_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
246extern int sh64_model_sh5_media_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
247extern int sh64_model_sh5_media_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
248extern int sh64_model_sh5_media_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
249extern int sh64_model_sh5_media_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
250extern int sh64_model_sh5_media_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
251extern int sh64_model_sh5_media_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
252extern int sh64_model_sh5_media_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
253extern int sh64_model_sh5_media_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
254extern int sh64_model_sh5_media_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
255extern int sh64_model_sh5_media_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
256extern int sh64_model_sh5_media_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
257extern int sh64_model_sh5_media_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
258extern int sh64_model_sh5_media_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
259extern int sh64_model_sh5_media_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
260extern int sh64_model_sh5_media_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
261extern int sh64_model_sh5_media_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
262extern int sh64_model_sh5_media_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
cbb38b47
BE		 263
264/* Profiling before/after handlers (user written) */
265
266extern void sh64_model_insn_before (SIM_CPU *, int /*first_p*/);
267extern void sh64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
268
269#endif /* SH64_MEDIA_DECODE_H */
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