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cbb38b47 BE |
1 | /* SH64 target configuration file. -*- C -*- */ |
2 | ||
cbb38b47 BE |
3 | /* See sim-hload.c. We properly handle LMA. -- TODO: check this */ |
4 | #define SIM_HANDLES_LMA 1 | |
5 | ||
6 | /* For MSPR support. FIXME: revisit. */ | |
7 | #define WITH_DEVICES 0 | |
8 | ||
cbb38b47 BE |
9 | #if 0 |
10 | /* Enable watchpoints. */ | |
11 | #define WITH_WATCHPOINTS 1 | |
12 | #endif | |
13 | ||
14 | /* ??? Temporary hack until model support unified. */ | |
15 | #define SIM_HAVE_MODEL | |
16 | ||
17 | /* Define this to enable the intrinsic breakpoint mechanism. */ | |
18 | /* FIXME: may be able to remove SIM_HAVE_BREAKPOINTS since it essentially | |
19 | duplicates ifdef SIM_BREAKPOINT (right?) */ | |
20 | #if 1 | |
21 | #define SIM_HAVE_BREAKPOINTS | |
22 | #define SIM_BREAKPOINT { 0, 0, 0, 0xD } | |
23 | #define SIM_BREAKPOINT_SIZE 4 | |
24 | #endif | |
25 | ||
26 | /* This is a global setting. Different cpu families can't mix-n-match -scache | |
27 | and -pbb. However some cpu families may use -simple while others use | |
28 | one of -scache/-pbb. ???? */ | |
29 | #define WITH_SCACHE_PBB 1 |