[thirdparty/binutils-gdb.git] / sim / sparc / Makefile.in

# Makefile template for Configure for the sparc simulator
# Copyright (C) 1999 Cygnus Solutions.

## COMMON_PRE_CONFIG_FRAG

SPARC32_OBJS = sparc32.o trap32.o dev32.o cpu32.o decode32.o model32.o mloop32.o sem32.o
SPARC64_OBJS = sparc64.o trap64.o dev64.o cpu64.o decode64.o model64.o mloop64.o sem64.o

# Set to one of SPARC32_OBJS/SPARC64_OBJS.
CPU_OBJS = @cpu_objs@

SIM_OBJS = \
	$(SIM_NEW_COMMON_OBJS) \
	sim-cpu.o \
	sim-hload.o \
	sim-hrw.o \
	sim-model.o \
	sim-reg.o \
	cgen-utils.o cgen-trace.o cgen-scache.o \
	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
	sim-if.o sparc.o arch.o sparc-desc.o \
	$(CPU_OBJS)

# Extra headers included by sim-main.h.
# This plus sim_main_headers is used by Make-common.in for files in common.
SIM_EXTRA_DEPS = \
	$(CGEN_INCLUDE_DEPS) \
	arch.h cpuall.h sparc-desc.h
# sparc-sim.h kept out for now (too much unnecessary recompilation)

SIM_EXTRA_CFLAGS =

SIM_RUN_OBJS = nrun.o
SIM_EXTRA_CLEAN = sparc-clean

# This selects the sparc newlib/libgloss syscall definitions.
NL_TARGET = -DNL_TARGET_sparc

## COMMON_POST_CONFIG_FRAG

arch = sparc

sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h \
	dev32.h dev64.h
sparc.o: sparc.c $(SIM_MAIN_DEPS) \
	$(srcdir)/../common/cgen-mem.h \
	$(srcdir)/../common/cgen-ops.h
arch.o: arch.c $(SIM_MAIN_DEPS)

# sparc32 objs

SPARC32_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpu32.h decode32.h eng32.h \
	regs32.h trap32.h

sparc32.o: sparc32.c $(SPARC32_INCLUDE_DEPS)
trap32.o: trap32.c $(SPARC32_INCLUDE_DEPS)
dev32.o: dev32.c $(SPARC32_INCLUDE_DEPS) dev32.h

# FIXME: Use of `mono' is wip.
# FIXME: Add -fast when switching from -simple to -pbb.
# FIXME: Add -switch sem32-switch.c at same time.
mloop32.c eng32.h: stamp-mloop32
stamp-mloop32: $(srcdir)/../common/genmloop.sh mloop32.in Makefile
	$(SHELL) $(srccom)/genmloop.sh \
		-mono -simple \
		-cpu sparc32 -infile $(srcdir)/mloop32.in
	$(SHELL) $(srcroot)/move-if-change eng.hin eng32.h
	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop32.c
	touch stamp-mloop32
mloop32.o: mloop32.c sem32-switch.c $(SPARC32_INCLUDE_DEPS)

cpu32.o: cpu32.c $(SPARC32_INCLUDE_DEPS)
decode32.o: decode32.c $(SPARC32_INCLUDE_DEPS)
model32.o: model32.c $(SPARC32_INCLUDE_DEPS)
sem32.o: sem32.c $(SPARC32_INCLUDE_DEPS)

# sparc64 objs

SPARC64_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpu64.h decode64.h eng64.h \
	regs64.h trap64.h

sparc64.o: sparc64.c $(SPARC64_INCLUDE_DEPS)
trap64.o: trap64.c $(SPARC64_INCLUDE_DEPS)
dev64.o: dev64.c $(SPARC32_INCLUDE_DEPS) dev64.h

# FIXME: Use of `mono' is wip.
mloop64.c eng64.h: stamp-mloop64
stamp-mloop64: $(srcdir)/../common/genmloop.sh mloop64.in Makefile
	$(SHELL) $(srccom)/genmloop.sh \
		-mono -fast -pbb -switch sem64-switch.c \
		-cpu sparc64 -infile $(srcdir)/mloop64.in
	$(SHELL) $(srcroot)/move-if-change eng.hin eng64.h
	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop64.c
	touch stamp-mloop64
mloop64.o: mloop64.c sem64-switch.c $(SPARC64_INCLUDE_DEPS)

cpu64.o: cpu64.c $(SPARC64_INCLUDE_DEPS)
decode64.o: decode64.c $(SPARC64_INCLUDE_DEPS)
model64.o: model64.c $(SPARC64_INCLUDE_DEPS)

sparc-clean:
	rm -f mloop32.c eng32.h stamp-mloop32
	rm -f mloop64.c eng64.h stamp-mloop64
	rm -f stamp-arch stamp-cpu32 stamp-cpu64 stamp-desc
	rm -f tmp-*

# cgen support

stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) \
		$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu \
		$(srccgen)/sparc32.cpu $(srccgen)/sparc64.cpu
	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) \
		mach=sparc-v8,sparclite,sparc-v9 \
		FLAGS="copyright=cygnus package=cygsim"
	touch stamp-arch
arch.h arch.c cpuall.h: $(CGEN_MAIN) stamp-arch
	@true

# Add with-scache to FLAGS when switching to -pbb.
stamp-cpu32: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \
		$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc32.cpu
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
		cpu=sparc32 mach=sparc-v8,sparclite SUFFIX=32 \
		FLAGS="with-profile=fn copyright=cygnus package=cygsim" \
		EXTRAFILES="$(CGEN_CPU_SEM)"
	touch stamp-cpu32
cpu32.h decode32.h decode32.c model32.c sem32.c sem32-switch.c: $(CGEN_MAINT) stamp-cpu32
	@true

# Add with-scache to FLAGS when switching to -pbb.
stamp-cpu64: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \
		$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc64.cpu
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
		cpu=sparc64 mach=sparc-v9 SUFFIX=64 \
		FLAGS="with-profile=fn copyright=cygnus package=cygsim" \
		EXTRAFILES="$(CGEN_CPU_SEM)"
	touch stamp-cpu64
cpu64.h decode64.h decode64.c model64.c sem64.c sem64-switch.c: $(CGEN_MAINT) stamp-cpu64
	@true

stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) \
		$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc32.cpu $(srccgen)/sparc64.cpu
	$(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \
		cpu=sparc mach=all \
		FLAGS="copyright=cygnus package=cygsim"
	touch stamp-desc
sparc-desc.c sparc-desc.h sparc-opc: $(CGEN_MAINT) stamp-desc
	@true
Commit	Line	Data
cd6245ce DE	1	# Makefile template for Configure for the sparc simulator
	2	# Copyright (C) 1999 Cygnus Solutions.
	3
	4	## COMMON_PRE_CONFIG_FRAG
	5
	6	SPARC32_OBJS = sparc32.o trap32.o dev32.o cpu32.o decode32.o model32.o mloop32.o sem32.o
c14d22a7 DE	7	SPARC64_OBJS = sparc64.o trap64.o dev64.o cpu64.o decode64.o model64.o mloop64.o sem64.o
	8
	9	# Set to one of SPARC32_OBJS/SPARC64_OBJS.
	10	CPU_OBJS = @cpu_objs@
cd6245ce DE	11
	12	SIM_OBJS = \
	13	$(SIM_NEW_COMMON_OBJS) \
	14	sim-cpu.o \
	15	sim-hload.o \
	16	sim-hrw.o \
	17	sim-model.o \
	18	sim-reg.o \
	19	cgen-utils.o cgen-trace.o cgen-scache.o \
	20	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
c14d22a7 DE	21	sim-if.o sparc.o arch.o sparc-desc.o \
c14d22a7 DE	22	$(CPU_OBJS)
cd6245ce DE	23
	24	# Extra headers included by sim-main.h.
	25	# This plus sim_main_headers is used by Make-common.in for files in common.
	26	SIM_EXTRA_DEPS = \
	27	$(CGEN_INCLUDE_DEPS) \
c14d22a7	28	arch.h cpuall.h sparc-desc.h
cd6245ce DE	29	# sparc-sim.h kept out for now (too much unnecessary recompilation)
	30
	31	SIM_EXTRA_CFLAGS =
	32
	33	SIM_RUN_OBJS = nrun.o
	34	SIM_EXTRA_CLEAN = sparc-clean
	35
	36	# This selects the sparc newlib/libgloss syscall definitions.
	37	NL_TARGET = -DNL_TARGET_sparc
	38
	39	## COMMON_POST_CONFIG_FRAG
	40
	41	arch = sparc
	42
c14d22a7 DE	43	sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h \
c14d22a7 DE	44	dev32.h dev64.h
cd6245ce DE	45	sparc.o: sparc.c $(SIM_MAIN_DEPS) \
	46	$(srcdir)/../common/cgen-mem.h \
	47	$(srcdir)/../common/cgen-ops.h
	48	arch.o: arch.c $(SIM_MAIN_DEPS)
	49
	50	# sparc32 objs
	51
	52	SPARC32_INCLUDE_DEPS = \
	53	$(CGEN_MAIN_CPU_DEPS) \
	54	cpu32.h decode32.h eng32.h \
	55	regs32.h trap32.h
	56
	57	sparc32.o: sparc32.c $(SPARC32_INCLUDE_DEPS)
	58	trap32.o: trap32.c $(SPARC32_INCLUDE_DEPS)
	59	dev32.o: dev32.c $(SPARC32_INCLUDE_DEPS) dev32.h
	60
	61	# FIXME: Use of `mono' is wip.
	62	# FIXME: Add -fast when switching from -simple to -pbb.
	63	# FIXME: Add -switch sem32-switch.c at same time.
	64	mloop32.c eng32.h: stamp-mloop32
	65	stamp-mloop32: $(srcdir)/../common/genmloop.sh mloop32.in Makefile
	66	$(SHELL) $(srccom)/genmloop.sh \
	67	-mono -simple \
	68	-cpu sparc32 -infile $(srcdir)/mloop32.in
	69	$(SHELL) $(srcroot)/move-if-change eng.hin eng32.h
	70	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop32.c
	71	touch stamp-mloop32
	72	mloop32.o: mloop32.c sem32-switch.c $(SPARC32_INCLUDE_DEPS)
	73
	74	cpu32.o: cpu32.c $(SPARC32_INCLUDE_DEPS)
	75	decode32.o: decode32.c $(SPARC32_INCLUDE_DEPS)
	76	model32.o: model32.c $(SPARC32_INCLUDE_DEPS)
	77	sem32.o: sem32.c $(SPARC32_INCLUDE_DEPS)
	78
	79	# sparc64 objs
	80
	81	SPARC64_INCLUDE_DEPS = \
	82	$(CGEN_MAIN_CPU_DEPS) \
	83	cpu64.h decode64.h eng64.h \
	84	regs64.h trap64.h
	85
	86	sparc64.o: sparc64.c $(SPARC64_INCLUDE_DEPS)
	87	trap64.o: trap64.c $(SPARC64_INCLUDE_DEPS)
c14d22a7	88	dev64.o: dev64.c $(SPARC32_INCLUDE_DEPS) dev64.h
cd6245ce DE	89
	90	# FIXME: Use of `mono' is wip.
	91	mloop64.c eng64.h: stamp-mloop64
	92	stamp-mloop64: $(srcdir)/../common/genmloop.sh mloop64.in Makefile
	93	$(SHELL) $(srccom)/genmloop.sh \
	94	-mono -fast -pbb -switch sem64-switch.c \
	95	-cpu sparc64 -infile $(srcdir)/mloop64.in
	96	$(SHELL) $(srcroot)/move-if-change eng.hin eng64.h
	97	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop64.c
	98	touch stamp-mloop64
	99	mloop64.o: mloop64.c sem64-switch.c $(SPARC64_INCLUDE_DEPS)
	100
	101	cpu64.o: cpu64.c $(SPARC64_INCLUDE_DEPS)
	102	decode64.o: decode64.c $(SPARC64_INCLUDE_DEPS)
	103	model64.o: model64.c $(SPARC64_INCLUDE_DEPS)
	104
	105	sparc-clean:
c14d22a7 DE	106	rm -f mloop32.c eng32.h stamp-mloop32
	107	rm -f mloop64.c eng64.h stamp-mloop64
	108	rm -f stamp-arch stamp-cpu32 stamp-cpu64 stamp-desc
cd6245ce DE	109	rm -f tmp-*
	110
	111	# cgen support
	112
c14d22a7	113	stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) \
cd6245ce DE	114	$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu \
cd6245ce DE	115	$(srccgen)/sparc32.cpu $(srccgen)/sparc64.cpu
c14d22a7 DE	116	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) \
	117	mach=sparc-v8,sparclite,sparc-v9 \
	118	FLAGS="copyright=cygnus package=cygsim"
cd6245ce DE	119	touch stamp-arch
	120	arch.h arch.c cpuall.h: $(CGEN_MAIN) stamp-arch
	121	@true
	122
	123	# Add with-scache to FLAGS when switching to -pbb.
c14d22a7	124	stamp-cpu32: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \
cd6245ce DE	125	$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc32.cpu
	126	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	127	cpu=sparc32 mach=sparc-v8,sparclite SUFFIX=32 \
c14d22a7	128	FLAGS="with-profile=fn copyright=cygnus package=cygsim" \
cd6245ce DE	129	EXTRAFILES="$(CGEN_CPU_SEM)"
	130	touch stamp-cpu32
	131	cpu32.h decode32.h decode32.c model32.c sem32.c sem32-switch.c: $(CGEN_MAINT) stamp-cpu32
	132	@true
	133
	134	# Add with-scache to FLAGS when switching to -pbb.
c14d22a7	135	stamp-cpu64: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \
cd6245ce DE	136	$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc64.cpu
cd6245ce DE	137	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
c14d22a7 DE	138	cpu=sparc64 mach=sparc-v9 SUFFIX=64 \
c14d22a7 DE	139	FLAGS="with-profile=fn copyright=cygnus package=cygsim" \
cd6245ce DE	140	EXTRAFILES="$(CGEN_CPU_SEM)"
	141	touch stamp-cpu64
	142	cpu64.h decode64.h decode64.c model64.c sem64.c sem64-switch.c: $(CGEN_MAINT) stamp-cpu64
	143	@true
c14d22a7 DE	144
	145	stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) \
	146	$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc32.cpu $(srccgen)/sparc64.cpu
	147	$(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \
	148	cpu=sparc mach=all \
	149	FLAGS="copyright=cygnus package=cygsim"
	150	touch stamp-desc
	151	sparc-desc.c sparc-desc.h sparc-opc: $(CGEN_MAINT) stamp-desc
	152	@true