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* config/sh/tm-sh.h (BELIEVE_PCC_PROMOTION): Define, so that
[thirdparty/binutils-gdb.git] / sim / sparc / arch.h
CommitLineData
c14d22a7
DE		 1/* Simulator header for sparc.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright (C) 1999 Cygnus Solutions, Inc.
6
7This file is part of the Cygnus Simulators.
8
9
10*/
11
12#ifndef SPARC_ARCH_H
13#define SPARC_ARCH_H
14
15#define TARGET_BIG_ENDIAN 1
16
17/* Cover fns for register access. */
18USI a_sparc_h_pc_get (SIM_CPU *);
19void a_sparc_h_pc_set (SIM_CPU *, USI);
20SI a_sparc_h_npc_get (SIM_CPU *);
21void a_sparc_h_npc_set (SIM_CPU *, SI);
22SI a_sparc_h_gr_get (SIM_CPU *, UINT);
23void a_sparc_h_gr_set (SIM_CPU *, UINT, SI);
24BI a_sparc_h_icc_c_get (SIM_CPU *);
25void a_sparc_h_icc_c_set (SIM_CPU *, BI);
26BI a_sparc_h_icc_n_get (SIM_CPU *);
27void a_sparc_h_icc_n_set (SIM_CPU *, BI);
28BI a_sparc_h_icc_v_get (SIM_CPU *);
29void a_sparc_h_icc_v_set (SIM_CPU *, BI);
30BI a_sparc_h_icc_z_get (SIM_CPU *);
31void a_sparc_h_icc_z_set (SIM_CPU *, BI);
32BI a_sparc_h_xcc_c_get (SIM_CPU *);
33void a_sparc_h_xcc_c_set (SIM_CPU *, BI);
34BI a_sparc_h_xcc_n_get (SIM_CPU *);
35void a_sparc_h_xcc_n_set (SIM_CPU *, BI);
36BI a_sparc_h_xcc_v_get (SIM_CPU *);
37void a_sparc_h_xcc_v_set (SIM_CPU *, BI);
38BI a_sparc_h_xcc_z_get (SIM_CPU *);
39void a_sparc_h_xcc_z_set (SIM_CPU *, BI);
40SI a_sparc_h_y_get (SIM_CPU *);
41void a_sparc_h_y_set (SIM_CPU *, SI);
42SI a_sparc_h_asr_get (SIM_CPU *, UINT);
43void a_sparc_h_asr_set (SIM_CPU *, UINT, SI);
44BI a_sparc_h_annul_p_get (SIM_CPU *);
45void a_sparc_h_annul_p_set (SIM_CPU *, BI);
46SF a_sparc_h_fr_get (SIM_CPU *, UINT);
47void a_sparc_h_fr_set (SIM_CPU *, UINT, SF);
48USI a_sparc_h_psr_get (SIM_CPU *);
49void a_sparc_h_psr_set (SIM_CPU *, USI);
50BI a_sparc_h_s_get (SIM_CPU *);
51void a_sparc_h_s_set (SIM_CPU *, BI);
52BI a_sparc_h_ps_get (SIM_CPU *);
53void a_sparc_h_ps_set (SIM_CPU *, BI);
54UQI a_sparc_h_pil_get (SIM_CPU *);
55void a_sparc_h_pil_set (SIM_CPU *, UQI);
56BI a_sparc_h_et_get (SIM_CPU *);
57void a_sparc_h_et_set (SIM_CPU *, BI);
58SI a_sparc_h_tbr_get (SIM_CPU *);
59void a_sparc_h_tbr_set (SIM_CPU *, SI);
60UQI a_sparc_h_cwp_get (SIM_CPU *);
61void a_sparc_h_cwp_set (SIM_CPU *, UQI);
62USI a_sparc_h_wim_get (SIM_CPU *);
63void a_sparc_h_wim_set (SIM_CPU *, USI);
64QI a_sparc_h_ag_get (SIM_CPU *);
65void a_sparc_h_ag_set (SIM_CPU *, QI);
66BI a_sparc_h_ec_get (SIM_CPU *);
67void a_sparc_h_ec_set (SIM_CPU *, BI);
68BI a_sparc_h_ef_get (SIM_CPU *);
69void a_sparc_h_ef_set (SIM_CPU *, BI);
70USI a_sparc_h_fsr_get (SIM_CPU *);
71void a_sparc_h_fsr_set (SIM_CPU *, USI);
72UDI a_sparc_h_ver_get (SIM_CPU *);
73void a_sparc_h_ver_set (SIM_CPU *, UDI);
74UDI a_sparc_h_pstate_get (SIM_CPU *);
75void a_sparc_h_pstate_set (SIM_CPU *, UDI);
76UDI a_sparc_h_tba_get (SIM_CPU *);
77void a_sparc_h_tba_set (SIM_CPU *, UDI);
78UDI a_sparc_h_tt_get (SIM_CPU *);
79void a_sparc_h_tt_set (SIM_CPU *, UDI);
80UQI a_sparc_h_asi_get (SIM_CPU *);
81void a_sparc_h_asi_set (SIM_CPU *, UQI);
82UQI a_sparc_h_tl_get (SIM_CPU *);
83void a_sparc_h_tl_set (SIM_CPU *, UQI);
84UDI a_sparc_h_tpc_get (SIM_CPU *);
85void a_sparc_h_tpc_set (SIM_CPU *, UDI);
86UDI a_sparc_h_tnpc_get (SIM_CPU *);
87void a_sparc_h_tnpc_set (SIM_CPU *, UDI);
88UDI a_sparc_h_tstate_get (SIM_CPU *);
89void a_sparc_h_tstate_set (SIM_CPU *, UDI);
90UDI a_sparc_h_tick_get (SIM_CPU *);
91void a_sparc_h_tick_set (SIM_CPU *, UDI);
92UDI a_sparc_h_cansave_get (SIM_CPU *);
93void a_sparc_h_cansave_set (SIM_CPU *, UDI);
94UDI a_sparc_h_canrestore_get (SIM_CPU *);
95void a_sparc_h_canrestore_set (SIM_CPU *, UDI);
96UDI a_sparc_h_otherwin_get (SIM_CPU *);
97void a_sparc_h_otherwin_set (SIM_CPU *, UDI);
98UDI a_sparc_h_cleanwin_get (SIM_CPU *);
99void a_sparc_h_cleanwin_set (SIM_CPU *, UDI);
100UDI a_sparc_h_wstate_get (SIM_CPU *);
101void a_sparc_h_wstate_set (SIM_CPU *, UDI);
102UQI a_sparc_h_fcc0_get (SIM_CPU *);
103void a_sparc_h_fcc0_set (SIM_CPU *, UQI);
104UQI a_sparc_h_fcc1_get (SIM_CPU *);
105void a_sparc_h_fcc1_set (SIM_CPU *, UQI);
106UQI a_sparc_h_fcc2_get (SIM_CPU *);
107void a_sparc_h_fcc2_set (SIM_CPU *, UQI);
108UQI a_sparc_h_fcc3_get (SIM_CPU *);
109void a_sparc_h_fcc3_set (SIM_CPU *, UQI);
110UQI a_sparc_h_fsr_rd_get (SIM_CPU *);
111void a_sparc_h_fsr_rd_set (SIM_CPU *, UQI);
112UQI a_sparc_h_fsr_tem_get (SIM_CPU *);
113void a_sparc_h_fsr_tem_set (SIM_CPU *, UQI);
114BI a_sparc_h_fsr_ns_get (SIM_CPU *);
115void a_sparc_h_fsr_ns_set (SIM_CPU *, BI);
116UQI a_sparc_h_fsr_ver_get (SIM_CPU *);
117void a_sparc_h_fsr_ver_set (SIM_CPU *, UQI);
118UQI a_sparc_h_fsr_ftt_get (SIM_CPU *);
119void a_sparc_h_fsr_ftt_set (SIM_CPU *, UQI);
120BI a_sparc_h_fsr_qne_get (SIM_CPU *);
121void a_sparc_h_fsr_qne_set (SIM_CPU *, BI);
122UQI a_sparc_h_fsr_aexc_get (SIM_CPU *);
123void a_sparc_h_fsr_aexc_set (SIM_CPU *, UQI);
124UQI a_sparc_h_fsr_cexc_get (SIM_CPU *);
125void a_sparc_h_fsr_cexc_set (SIM_CPU *, UQI);
126BI a_sparc_h_fpsr_fef_get (SIM_CPU *);
127void a_sparc_h_fpsr_fef_set (SIM_CPU *, BI);
128BI a_sparc_h_fpsr_du_get (SIM_CPU *);
129void a_sparc_h_fpsr_du_set (SIM_CPU *, BI);
130BI a_sparc_h_fpsr_dl_get (SIM_CPU *);
131void a_sparc_h_fpsr_dl_set (SIM_CPU *, BI);
132UQI a_sparc_h_fpsr_get (SIM_CPU *);
133void a_sparc_h_fpsr_set (SIM_CPU *, UQI);
134
135/* Enum declaration for model types. */
136typedef enum model_type {
137 MODEL_SPARC32_DEF, MODEL_SPARC64_DEF, MODEL_MAX
138} MODEL_TYPE;
139
140#define MAX_MODELS ((int) MODEL_MAX)
141
142/* Enum declaration for unit types. */
143typedef enum unit_type {
144 UNIT_NONE, UNIT_SPARC32_DEF_U_EXEC, UNIT_SPARC64_DEF_U_EXEC, UNIT_MAX
145} UNIT_TYPE;
146
147#define MAX_UNITS (1)
148
149#endif /* SPARC_ARCH_H */
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