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* config/sh/tm-sh.h (BELIEVE_PCC_PROMOTION): Define, so that
[thirdparty/binutils-gdb.git] / sim / sparc / cpu64.h
CommitLineData
8d3b7234
DE		 1/* CPU family header for sparc64.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright (C) 1999 Cygnus Solutions, Inc.
6
7This file is part of the Cygnus Simulators.
8
9
10*/
11
12#ifndef CPU_SPARC64_H
13#define CPU_SPARC64_H
14
15/* Maximum number of instructions that are fetched at a time.
16 This is for LIW type instructions sets (e.g. m32r). */
17#define MAX_LIW_INSNS 1
18
19/* Maximum number of instructions that can be executed in parallel. */
20#define MAX_PARALLEL_INSNS 1
21
22/* CPU state information. */
23typedef struct {
24 /* Hardware elements. */
25 struct {
26 /* program counter */
27 USI h_pc;
28#define GET_H_PC() CPU (h_pc)
29#define SET_H_PC(x) (CPU (h_pc) = (x))
30 /* next pc */
31 SI h_npc;
32#define GET_H_NPC() CPU (h_npc)
33#define SET_H_NPC(x) (CPU (h_npc) = (x))
34/* GET_H_GR macro user-written */
35/* SET_H_GR macro user-written */
36 /* icc carry bit */
37 BI h_icc_c;
38#define GET_H_ICC_C() CPU (h_icc_c)
39#define SET_H_ICC_C(x) (CPU (h_icc_c) = (x))
40 /* icc negative bit */
41 BI h_icc_n;
42#define GET_H_ICC_N() CPU (h_icc_n)
43#define SET_H_ICC_N(x) (CPU (h_icc_n) = (x))
44 /* icc overflow bit */
45 BI h_icc_v;
46#define GET_H_ICC_V() CPU (h_icc_v)
47#define SET_H_ICC_V(x) (CPU (h_icc_v) = (x))
48 /* icc zero bit */
49 BI h_icc_z;
50#define GET_H_ICC_Z() CPU (h_icc_z)
51#define SET_H_ICC_Z(x) (CPU (h_icc_z) = (x))
52 /* xcc carry bit */
53 BI h_xcc_c;
54#define GET_H_XCC_C() CPU (h_xcc_c)
55#define SET_H_XCC_C(x) (CPU (h_xcc_c) = (x))
56 /* xcc negative bit */
57 BI h_xcc_n;
58#define GET_H_XCC_N() CPU (h_xcc_n)
59#define SET_H_XCC_N(x) (CPU (h_xcc_n) = (x))
60 /* xcc overflow bit */
61 BI h_xcc_v;
62#define GET_H_XCC_V() CPU (h_xcc_v)
63#define SET_H_XCC_V(x) (CPU (h_xcc_v) = (x))
64 /* xcc zero bit */
65 BI h_xcc_z;
66#define GET_H_XCC_Z() CPU (h_xcc_z)
67#define SET_H_XCC_Z(x) (CPU (h_xcc_z) = (x))
68/* GET_H_Y macro user-written */
69/* SET_H_Y macro user-written */
70 /* ancilliary state registers */
71 SI h_asr[32];
72#define GET_H_ASR(a1) CPU (h_asr)[a1]
73#define SET_H_ASR(a1, x) (CPU (h_asr)[a1] = (x))
74 /* annul next insn? - assists execution */
75 BI h_annul_p;
76#define GET_H_ANNUL_P() CPU (h_annul_p)
77#define SET_H_ANNUL_P(x) (CPU (h_annul_p) = (x))
78 /* floating point regs */
79 SF h_fr[32];
80#define GET_H_FR(a1) CPU (h_fr)[a1]
81#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
82 /* version */
83 UDI h_ver;
84#define GET_H_VER() CPU (h_ver)
85#define SET_H_VER(x) (CPU (h_ver) = (x))
86 /* processor state */
87 UDI h_pstate;
88#define GET_H_PSTATE() CPU (h_pstate)
89#define SET_H_PSTATE(x) (CPU (h_pstate) = (x))
90 /* trap base address */
91 UDI h_tba;
92#define GET_H_TBA() CPU (h_tba)
93#define SET_H_TBA(x) (CPU (h_tba) = (x))
94 /* trap type */
95 UDI h_tt;
96#define GET_H_TT() CPU (h_tt)
97#define SET_H_TT(x) (CPU (h_tt) = (x))
98 /* trap pc */
99 UDI h_tpc;
100#define GET_H_TPC() CPU (h_tpc)
101#define SET_H_TPC(x) (CPU (h_tpc) = (x))
102 /* trap npc */
103 UDI h_tnpc;
104#define GET_H_TNPC() CPU (h_tnpc)
105#define SET_H_TNPC(x) (CPU (h_tnpc) = (x))
106 /* trap state */
107 UDI h_tstate;
108#define GET_H_TSTATE() CPU (h_tstate)
109#define SET_H_TSTATE(x) (CPU (h_tstate) = (x))
110 /* trap level */
111 UQI h_tl;
112#define GET_H_TL() CPU (h_tl)
113#define SET_H_TL(x) (CPU (h_tl) = (x))
114 /* address space identifier */
115 UQI h_asi;
116#define GET_H_ASI() CPU (h_asi)
117#define SET_H_ASI(x) (CPU (h_asi) = (x))
118 /* tick counter */
119 UDI h_tick;
120#define GET_H_TICK() CPU (h_tick)
121#define SET_H_TICK(x) (CPU (h_tick) = (x))
122 /* savable window registers */
123 UDI h_cansave;
124#define GET_H_CANSAVE() CPU (h_cansave)
125#define SET_H_CANSAVE(x) (CPU (h_cansave) = (x))
126 /* restorable window registers */
127 UDI h_canrestore;
128#define GET_H_CANRESTORE() CPU (h_canrestore)
129#define SET_H_CANRESTORE(x) (CPU (h_canrestore) = (x))
130 /* other window registers */
131 UDI h_otherwin;
132#define GET_H_OTHERWIN() CPU (h_otherwin)
133#define SET_H_OTHERWIN(x) (CPU (h_otherwin) = (x))
134 /* clean window registers */
135 UDI h_cleanwin;
136#define GET_H_CLEANWIN() CPU (h_cleanwin)
137#define SET_H_CLEANWIN(x) (CPU (h_cleanwin) = (x))
138 /* window state */
139 UDI h_wstate;
140#define GET_H_WSTATE() CPU (h_wstate)
141#define SET_H_WSTATE(x) (CPU (h_wstate) = (x))
142 /* */
143 UQI h_fcc0;
144#define GET_H_FCC0() CPU (h_fcc0)
145#define SET_H_FCC0(x) (CPU (h_fcc0) = (x))
146 /* */
147 UQI h_fcc1;
148#define GET_H_FCC1() CPU (h_fcc1)
149#define SET_H_FCC1(x) (CPU (h_fcc1) = (x))
150 /* */
151 UQI h_fcc2;
152#define GET_H_FCC2() CPU (h_fcc2)
153#define SET_H_FCC2(x) (CPU (h_fcc2) = (x))
154 /* */
155 UQI h_fcc3;
156#define GET_H_FCC3() CPU (h_fcc3)
157#define SET_H_FCC3(x) (CPU (h_fcc3) = (x))
158 /* fsr rounding direction */
159 UQI h_fsr_rd;
160#define GET_H_FSR_RD() CPU (h_fsr_rd)
161#define SET_H_FSR_RD(x) (CPU (h_fsr_rd) = (x))
162 /* fsr trap enable mask */
163 UQI h_fsr_tem;
164#define GET_H_FSR_TEM() CPU (h_fsr_tem)
165#define SET_H_FSR_TEM(x) (CPU (h_fsr_tem) = (x))
166 /* fsr nonstandard fp */
167 BI h_fsr_ns;
168#define GET_H_FSR_NS() CPU (h_fsr_ns)
169#define SET_H_FSR_NS(x) (CPU (h_fsr_ns) = (x))
170 /* fsr version */
171 UQI h_fsr_ver;
172#define GET_H_FSR_VER() CPU (h_fsr_ver)
173#define SET_H_FSR_VER(x) (CPU (h_fsr_ver) = (x))
174 /* fsr fp trap type */
175 UQI h_fsr_ftt;
176#define GET_H_FSR_FTT() CPU (h_fsr_ftt)
177#define SET_H_FSR_FTT(x) (CPU (h_fsr_ftt) = (x))
178 /* fsr queue not empty */
179 BI h_fsr_qne;
180#define GET_H_FSR_QNE() CPU (h_fsr_qne)
181#define SET_H_FSR_QNE(x) (CPU (h_fsr_qne) = (x))
182 /* fsr accrued exception */
183 UQI h_fsr_aexc;
184#define GET_H_FSR_AEXC() CPU (h_fsr_aexc)
185#define SET_H_FSR_AEXC(x) (CPU (h_fsr_aexc) = (x))
186 /* fsr current exception */
187 UQI h_fsr_cexc;
188#define GET_H_FSR_CEXC() CPU (h_fsr_cexc)
189#define SET_H_FSR_CEXC(x) (CPU (h_fsr_cexc) = (x))
190 /* fpsr enable fp */
191 BI h_fpsr_fef;
192#define GET_H_FPSR_FEF() CPU (h_fpsr_fef)
193#define SET_H_FPSR_FEF(x) (CPU (h_fpsr_fef) = (x))
194 /* fpsr dirty upper */
195 BI h_fpsr_du;
196#define GET_H_FPSR_DU() CPU (h_fpsr_du)
197#define SET_H_FPSR_DU(x) (CPU (h_fpsr_du) = (x))
198 /* fpsr dirty lower */
199 BI h_fpsr_dl;
200#define GET_H_FPSR_DL() CPU (h_fpsr_dl)
201#define SET_H_FPSR_DL(x) (CPU (h_fpsr_dl) = (x))
202/* GET_H_FPSR macro user-written */
203/* SET_H_FPSR macro user-written */
204 } hardware;
205#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
206} SPARC64_CPU_DATA;
207
208/* Cover fns for register access. */
209USI sparc64_h_pc_get (SIM_CPU *);
210void sparc64_h_pc_set (SIM_CPU *, USI);
211SI sparc64_h_npc_get (SIM_CPU *);
212void sparc64_h_npc_set (SIM_CPU *, SI);
213SI sparc64_h_gr_get (SIM_CPU *, UINT);
214void sparc64_h_gr_set (SIM_CPU *, UINT, SI);
215BI sparc64_h_icc_c_get (SIM_CPU *);
216void sparc64_h_icc_c_set (SIM_CPU *, BI);
217BI sparc64_h_icc_n_get (SIM_CPU *);
218void sparc64_h_icc_n_set (SIM_CPU *, BI);
219BI sparc64_h_icc_v_get (SIM_CPU *);
220void sparc64_h_icc_v_set (SIM_CPU *, BI);
221BI sparc64_h_icc_z_get (SIM_CPU *);
222void sparc64_h_icc_z_set (SIM_CPU *, BI);
223BI sparc64_h_xcc_c_get (SIM_CPU *);
224void sparc64_h_xcc_c_set (SIM_CPU *, BI);
225BI sparc64_h_xcc_n_get (SIM_CPU *);
226void sparc64_h_xcc_n_set (SIM_CPU *, BI);
227BI sparc64_h_xcc_v_get (SIM_CPU *);
228void sparc64_h_xcc_v_set (SIM_CPU *, BI);
229BI sparc64_h_xcc_z_get (SIM_CPU *);
230void sparc64_h_xcc_z_set (SIM_CPU *, BI);
231SI sparc64_h_y_get (SIM_CPU *);
232void sparc64_h_y_set (SIM_CPU *, SI);
233SI sparc64_h_asr_get (SIM_CPU *, UINT);
234void sparc64_h_asr_set (SIM_CPU *, UINT, SI);
235BI sparc64_h_annul_p_get (SIM_CPU *);
236void sparc64_h_annul_p_set (SIM_CPU *, BI);
237SF sparc64_h_fr_get (SIM_CPU *, UINT);
238void sparc64_h_fr_set (SIM_CPU *, UINT, SF);
239UDI sparc64_h_ver_get (SIM_CPU *);
240void sparc64_h_ver_set (SIM_CPU *, UDI);
241UDI sparc64_h_pstate_get (SIM_CPU *);
242void sparc64_h_pstate_set (SIM_CPU *, UDI);
243UDI sparc64_h_tba_get (SIM_CPU *);
244void sparc64_h_tba_set (SIM_CPU *, UDI);
245UDI sparc64_h_tt_get (SIM_CPU *);
246void sparc64_h_tt_set (SIM_CPU *, UDI);
247UDI sparc64_h_tpc_get (SIM_CPU *);
248void sparc64_h_tpc_set (SIM_CPU *, UDI);
249UDI sparc64_h_tnpc_get (SIM_CPU *);
250void sparc64_h_tnpc_set (SIM_CPU *, UDI);
251UDI sparc64_h_tstate_get (SIM_CPU *);
252void sparc64_h_tstate_set (SIM_CPU *, UDI);
253UQI sparc64_h_tl_get (SIM_CPU *);
254void sparc64_h_tl_set (SIM_CPU *, UQI);
255UQI sparc64_h_asi_get (SIM_CPU *);
256void sparc64_h_asi_set (SIM_CPU *, UQI);
257UDI sparc64_h_tick_get (SIM_CPU *);
258void sparc64_h_tick_set (SIM_CPU *, UDI);
259UDI sparc64_h_cansave_get (SIM_CPU *);
260void sparc64_h_cansave_set (SIM_CPU *, UDI);
261UDI sparc64_h_canrestore_get (SIM_CPU *);
262void sparc64_h_canrestore_set (SIM_CPU *, UDI);
263UDI sparc64_h_otherwin_get (SIM_CPU *);
264void sparc64_h_otherwin_set (SIM_CPU *, UDI);
265UDI sparc64_h_cleanwin_get (SIM_CPU *);
266void sparc64_h_cleanwin_set (SIM_CPU *, UDI);
267UDI sparc64_h_wstate_get (SIM_CPU *);
268void sparc64_h_wstate_set (SIM_CPU *, UDI);
269UQI sparc64_h_fcc0_get (SIM_CPU *);
270void sparc64_h_fcc0_set (SIM_CPU *, UQI);
271UQI sparc64_h_fcc1_get (SIM_CPU *);
272void sparc64_h_fcc1_set (SIM_CPU *, UQI);
273UQI sparc64_h_fcc2_get (SIM_CPU *);
274void sparc64_h_fcc2_set (SIM_CPU *, UQI);
275UQI sparc64_h_fcc3_get (SIM_CPU *);
276void sparc64_h_fcc3_set (SIM_CPU *, UQI);
277UQI sparc64_h_fsr_rd_get (SIM_CPU *);
278void sparc64_h_fsr_rd_set (SIM_CPU *, UQI);
279UQI sparc64_h_fsr_tem_get (SIM_CPU *);
280void sparc64_h_fsr_tem_set (SIM_CPU *, UQI);
281BI sparc64_h_fsr_ns_get (SIM_CPU *);
282void sparc64_h_fsr_ns_set (SIM_CPU *, BI);
283UQI sparc64_h_fsr_ver_get (SIM_CPU *);
284void sparc64_h_fsr_ver_set (SIM_CPU *, UQI);
285UQI sparc64_h_fsr_ftt_get (SIM_CPU *);
286void sparc64_h_fsr_ftt_set (SIM_CPU *, UQI);
287BI sparc64_h_fsr_qne_get (SIM_CPU *);
288void sparc64_h_fsr_qne_set (SIM_CPU *, BI);
289UQI sparc64_h_fsr_aexc_get (SIM_CPU *);
290void sparc64_h_fsr_aexc_set (SIM_CPU *, UQI);
291UQI sparc64_h_fsr_cexc_get (SIM_CPU *);
292void sparc64_h_fsr_cexc_set (SIM_CPU *, UQI);
293BI sparc64_h_fpsr_fef_get (SIM_CPU *);
294void sparc64_h_fpsr_fef_set (SIM_CPU *, BI);
295BI sparc64_h_fpsr_du_get (SIM_CPU *);
296void sparc64_h_fpsr_du_set (SIM_CPU *, BI);
297BI sparc64_h_fpsr_dl_get (SIM_CPU *);
298void sparc64_h_fpsr_dl_set (SIM_CPU *, BI);
299UQI sparc64_h_fpsr_get (SIM_CPU *);
300void sparc64_h_fpsr_set (SIM_CPU *, UQI);
301
302/* These must be hand-written. */
303extern CPUREG_FETCH_FN sparc64_fetch_register;
304extern CPUREG_STORE_FN sparc64_store_register;
305
306typedef struct {
307 int empty;
308} MODEL_SPARC64_DEF_DATA;
309
310/* The ARGBUF struct. */
311struct argbuf {
312 /* These are the baseclass definitions. */
313 IADDR addr;
314 const IDESC *idesc;
315 char trace_p;
316 char profile_p;
317 /* cpu specific data follows */
318 CGEN_INSN_INT insn;
319 int written;
320};
321
322/* A cached insn.
323
324 ??? SCACHE used to contain more than just argbuf. We could delete the
325 type entirely and always just use ARGBUF, but for future concerns and as
326 a level of abstraction it is left in. */
327
328struct scache {
329 struct argbuf argbuf;
330};
331
332/* Macros to simplify extraction, reading and semantic code.
333 These define and assign the local vars that contain the insn's fields. */
334
335#define EXTRACT_IFMT_EMPTY_VARS \
336 /* Instruction fields. */ \
337 unsigned int length;
338#define EXTRACT_IFMT_EMPTY_CODE \
339 length = 0; \
340
341#define EXTRACT_IFMT_BEQZ_VARS \
342 /* Instruction fields. */ \
343 INT f_disp16; \
344 UINT f_disp16_hi; \
345 UINT f_disp16_lo; \
346 UINT f_rs1; \
347 UINT f_p; \
348 UINT f_op2; \
349 UINT f_fmt2_rcond; \
350 INT f_bpr_res28_1; \
351 UINT f_a; \
352 UINT f_op; \
353 unsigned int length;
354#define EXTRACT_IFMT_BEQZ_CODE \
355 length = 4; \
356 f_disp16_hi = EXTRACT_UINT (insn, 32, 10, 2); \
357 f_disp16_lo = EXTRACT_UINT (insn, 32, 18, 14); \
358do {\
359 f_disp16 = ((((f_disp16_hi) << (14))) | (f_disp16_low));\
360} while (0);\
361 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
362 f_p = EXTRACT_UINT (insn, 32, 19, 1); \
363 f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
364 f_fmt2_rcond = EXTRACT_UINT (insn, 32, 27, 3); \
365 f_bpr_res28_1 = EXTRACT_INT (insn, 32, 28, 1); \
366 f_a = EXTRACT_UINT (insn, 32, 29, 1); \
367 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
368
369#define EXTRACT_IFMT_BPCC_BA_VARS \
370 /* Instruction fields. */ \
371 INT f_disp19; \
372 UINT f_p; \
373 UINT f_fmt2_cc0; \
374 UINT f_fmt2_cc1; \
375 UINT f_op2; \
376 UINT f_fmt2_cond; \
377 UINT f_a; \
378 UINT f_op; \
379 unsigned int length;
380#define EXTRACT_IFMT_BPCC_BA_CODE \
381 length = 4; \
382 f_disp19 = EXTRACT_INT (insn, 32, 13, 19); \
383 f_p = EXTRACT_UINT (insn, 32, 19, 1); \
384 f_fmt2_cc0 = EXTRACT_UINT (insn, 32, 20, 1); \
385 f_fmt2_cc1 = EXTRACT_UINT (insn, 32, 21, 1); \
386 f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
387 f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
388 f_a = EXTRACT_UINT (insn, 32, 29, 1); \
389 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
390
391#define EXTRACT_IFMT_DONE_VARS \
392 /* Instruction fields. */ \
393 INT f_res_18_19; \
394 UINT f_op3; \
395 UINT f_fcn; \
396 UINT f_op; \
397 unsigned int length;
398#define EXTRACT_IFMT_DONE_CODE \
399 length = 4; \
400 f_res_18_19 = EXTRACT_INT (insn, 32, 18, 19); \
401 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
402 f_fcn = EXTRACT_UINT (insn, 32, 29, 5); \
403 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
404
405#define EXTRACT_IFMT_FLUSH_VARS \
406 /* Instruction fields. */ \
407 UINT f_rs2; \
408 INT f_res_asi; \
409 UINT f_i; \
410 UINT f_rs1; \
411 UINT f_op3; \
412 UINT f_rd; \
413 UINT f_op; \
414 unsigned int length;
415#define EXTRACT_IFMT_FLUSH_CODE \
416 length = 4; \
417 f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
418 f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
419 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
420 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
421 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
422 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
423 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
424
425#define EXTRACT_IFMT_FLUSH_IMM_VARS \
426 /* Instruction fields. */ \
427 INT f_simm13; \
428 UINT f_i; \
429 UINT f_rs1; \
430 UINT f_op3; \
431 UINT f_rd; \
432 UINT f_op; \
433 unsigned int length;
434#define EXTRACT_IFMT_FLUSH_IMM_CODE \
435 length = 4; \
436 f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
437 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
438 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
439 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
440 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
441 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
442
443#define EXTRACT_IFMT_FLUSHW_VARS \
444 /* Instruction fields. */ \
445 INT f_simm13; \
446 UINT f_i; \
447 UINT f_rs1; \
448 UINT f_op3; \
449 UINT f_rd; \
450 UINT f_op; \
451 unsigned int length;
452#define EXTRACT_IFMT_FLUSHW_CODE \
453 length = 4; \
454 f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
455 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
456 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
457 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
458 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
459 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
460
461#define EXTRACT_IFMT_IMPDEP1_VARS \
462 /* Instruction fields. */ \
463 INT f_impdep19; \
464 UINT f_op3; \
465 INT f_impdep5; \
466 UINT f_op; \
467 unsigned int length;
468#define EXTRACT_IFMT_IMPDEP1_CODE \
469 length = 4; \
470 f_impdep19 = EXTRACT_INT (insn, 32, 18, 19); \
471 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
472 f_impdep5 = EXTRACT_INT (insn, 32, 29, 5); \
473 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
474
475#define EXTRACT_IFMT_MEMBAR_VARS \
476 /* Instruction fields. */ \
477 UINT f_membarmask; \
478 INT f_membar_res12_6; \
479 UINT f_i; \
480 UINT f_rs1; \
481 UINT f_op3; \
482 UINT f_rd; \
483 UINT f_op; \
484 unsigned int length;
485#define EXTRACT_IFMT_MEMBAR_CODE \
486 length = 4; \
487 f_membarmask = EXTRACT_UINT (insn, 32, 6, 7); \
488 f_membar_res12_6 = EXTRACT_INT (insn, 32, 12, 6); \
489 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
490 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
491 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
492 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
493 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
494
495#define EXTRACT_IFMT_MOVA_ICC_ICC_VARS \
496 /* Instruction fields. */ \
497 UINT f_rs2; \
498 INT f_fmt4_res10_6; \
499 UINT f_fmt4_cc1_0; \
500 UINT f_i; \
501 UINT f_fmt4_cc2; \
502 UINT f_op3; \
503 UINT f_fmt2_cond; \
504 UINT f_rd; \
505 UINT f_op; \
506 unsigned int length;
507#define EXTRACT_IFMT_MOVA_ICC_ICC_CODE \
508 length = 4; \
509 f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
510 f_fmt4_res10_6 = EXTRACT_INT (insn, 32, 10, 6); \
511 f_fmt4_cc1_0 = EXTRACT_UINT (insn, 32, 12, 2); \
512 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
513 f_fmt4_cc2 = EXTRACT_UINT (insn, 32, 18, 1); \
514 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
515 f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
516 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
517 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
518
519#define EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS \
520 /* Instruction fields. */ \
521 INT f_simm11; \
522 UINT f_fmt4_cc1_0; \
523 UINT f_i; \
524 UINT f_fmt4_cc2; \
525 UINT f_op3; \
526 UINT f_fmt2_cond; \
527 UINT f_rd; \
528 UINT f_op; \
529 unsigned int length;
530#define EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE \
531 length = 4; \
532 f_simm11 = EXTRACT_INT (insn, 32, 10, 11); \
533 f_fmt4_cc1_0 = EXTRACT_UINT (insn, 32, 12, 2); \
534 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
535 f_fmt4_cc2 = EXTRACT_UINT (insn, 32, 18, 1); \
536 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
537 f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
538 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
539 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
540
541#define EXTRACT_IFMT_LDSB_REG_REG_VARS \
542 /* Instruction fields. */ \
543 UINT f_rs2; \
544 INT f_res_asi; \
545 UINT f_i; \
546 UINT f_rs1; \
547 UINT f_op3; \
548 UINT f_rd; \
549 UINT f_op; \
550 unsigned int length;
551#define EXTRACT_IFMT_LDSB_REG_REG_CODE \
552 length = 4; \
553 f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
554 f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
555 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
556 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
557 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
558 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
559 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
560
561#define EXTRACT_IFMT_LDSB_REG_IMM_VARS \
562 /* Instruction fields. */ \
563 INT f_simm13; \
564 UINT f_i; \
565 UINT f_rs1; \
566 UINT f_op3; \
567 UINT f_rd; \
568 UINT f_op; \
569 unsigned int length;
570#define EXTRACT_IFMT_LDSB_REG_IMM_CODE \
571 length = 4; \
572 f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
573 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
574 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
575 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
576 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
577 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
578
579#define EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS \
580 /* Instruction fields. */ \
581 UINT f_rs2; \
582 UINT f_asi; \
583 UINT f_i; \
584 UINT f_rs1; \
585 UINT f_op3; \
586 UINT f_rd; \
587 UINT f_op; \
588 unsigned int length;
589#define EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE \
590 length = 4; \
591 f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
592 f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
593 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
594 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
595 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
596 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
597 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
598
599#define EXTRACT_IFMT_LDD_REG_REG_VARS \
600 /* Instruction fields. */ \
601 UINT f_rs2; \
602 INT f_res_asi; \
603 UINT f_i; \
604 UINT f_rs1; \
605 UINT f_op3; \
606 UINT f_rd; \
607 UINT f_op; \
608 unsigned int length;
609#define EXTRACT_IFMT_LDD_REG_REG_CODE \
610 length = 4; \
611 f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
612 f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
613 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
614 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
615 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
616 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
617 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
618
619#define EXTRACT_IFMT_LDD_REG_IMM_VARS \
620 /* Instruction fields. */ \
621 INT f_simm13; \
622 UINT f_i; \
623 UINT f_rs1; \
624 UINT f_op3; \
625 UINT f_rd; \
626 UINT f_op; \
627 unsigned int length;
628#define EXTRACT_IFMT_LDD_REG_IMM_CODE \
629 length = 4; \
630 f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
631 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
632 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
633 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
634 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
635 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
636
637#define EXTRACT_IFMT_LDD_REG_REG_ASI_VARS \
638 /* Instruction fields. */ \
639 UINT f_rs2; \
640 UINT f_asi; \
641 UINT f_i; \
642 UINT f_rs1; \
643 UINT f_op3; \
644 UINT f_rd; \
645 UINT f_op; \
646 unsigned int length;
647#define EXTRACT_IFMT_LDD_REG_REG_ASI_CODE \
648 length = 4; \
649 f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
650 f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
651 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
652 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
653 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
654 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
655 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
656
657#define EXTRACT_IFMT_FP_LD_REG_REG_VARS \
658 /* Instruction fields. */ \
659 UINT f_rs2; \
660 INT f_res_asi; \
661 UINT f_i; \
662 UINT f_rs1; \
663 UINT f_op3; \
664 UINT f_rd; \
665 UINT f_op; \
666 unsigned int length;
667#define EXTRACT_IFMT_FP_LD_REG_REG_CODE \
668 length = 4; \
669 f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
670 f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
671 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
672 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
673 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
674 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
675 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
676
677#define EXTRACT_IFMT_FP_LD_REG_IMM_VARS \
678 /* Instruction fields. */ \
679 INT f_simm13; \
680 UINT f_i; \
681 UINT f_rs1; \
682 UINT f_op3; \
683 UINT f_rd; \
684 UINT f_op; \
685 unsigned int length;
686#define EXTRACT_IFMT_FP_LD_REG_IMM_CODE \
687 length = 4; \
688 f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
689 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
690 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
691 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
692 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
693 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
694
695#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS \
696 /* Instruction fields. */ \
697 UINT f_rs2; \
698 UINT f_asi; \
699 UINT f_i; \
700 UINT f_rs1; \
701 UINT f_op3; \
702 UINT f_rd; \
703 UINT f_op; \
704 unsigned int length;
705#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE \
706 length = 4; \
707 f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
708 f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
709 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
710 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
711 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
712 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
713 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
714
715#define EXTRACT_IFMT_SETHI_VARS \
716 /* Instruction fields. */ \
717 INT f_hi22; \
718 UINT f_op2; \
719 UINT f_rd; \
720 UINT f_op; \
721 unsigned int length;
722#define EXTRACT_IFMT_SETHI_CODE \
723 length = 4; \
724 f_hi22 = EXTRACT_INT (insn, 32, 21, 22); \
725 f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
726 f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
727 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
728
729#define EXTRACT_IFMT_UNIMP_VARS \
730 /* Instruction fields. */ \
731 INT f_imm22; \
732 UINT f_op2; \
733 UINT f_rd_res; \
734 UINT f_op; \
735 unsigned int length;
736#define EXTRACT_IFMT_UNIMP_CODE \
737 length = 4; \
738 f_imm22 = EXTRACT_INT (insn, 32, 21, 22); \
739 f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
740 f_rd_res = EXTRACT_UINT (insn, 32, 29, 5); \
741 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
742
743#define EXTRACT_IFMT_CALL_VARS \
744 /* Instruction fields. */ \
745 SI f_disp30; \
746 UINT f_op; \
747 unsigned int length;
748#define EXTRACT_IFMT_CALL_CODE \
749 length = 4; \
750 f_disp30 = ((((EXTRACT_INT (insn, 32, 29, 30)) << (2))) + (pc)); \
751 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
752
753#define EXTRACT_IFMT_BA_VARS \
754 /* Instruction fields. */ \
755 SI f_disp22; \
756 UINT f_op2; \
757 UINT f_fmt2_cond; \
758 UINT f_a; \
759 UINT f_op; \
760 unsigned int length;
761#define EXTRACT_IFMT_BA_CODE \
762 length = 4; \
763 f_disp22 = ((((EXTRACT_INT (insn, 32, 21, 22)) << (2))) + (pc)); \
764 f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
765 f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
766 f_a = EXTRACT_UINT (insn, 32, 29, 1); \
767 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
768
769#define EXTRACT_IFMT_TA_VARS \
770 /* Instruction fields. */ \
771 UINT f_rs2; \
772 INT f_res_asi; \
773 UINT f_i; \
774 UINT f_rs1; \
775 UINT f_op3; \
776 UINT f_fmt2_cond; \
777 UINT f_a; \
778 UINT f_op; \
779 unsigned int length;
780#define EXTRACT_IFMT_TA_CODE \
781 length = 4; \
782 f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
783 f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
784 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
785 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
786 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
787 f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
788 f_a = EXTRACT_UINT (insn, 32, 29, 1); \
789 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
790
791#define EXTRACT_IFMT_TA_IMM_VARS \
792 /* Instruction fields. */ \
793 INT f_simm13; \
794 UINT f_i; \
795 UINT f_rs1; \
796 UINT f_op3; \
797 UINT f_fmt2_cond; \
798 UINT f_a; \
799 UINT f_op; \
800 unsigned int length;
801#define EXTRACT_IFMT_TA_IMM_CODE \
802 length = 4; \
803 f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
804 f_i = EXTRACT_UINT (insn, 32, 13, 1); \
805 f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
806 f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
807 f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
808 f_a = EXTRACT_UINT (insn, 32, 29, 1); \
809 f_op = EXTRACT_UINT (insn, 32, 31, 2); \
810
811/* Collection of various things for the trace handler to use. */
812
813typedef struct trace_record {
814 IADDR pc;
815 /* FIXME:wip */
816} TRACE_RECORD;
817
818#endif /* CPU_SPARC64_H */
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