projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| cd6245ce DE |
1 | /* sparc32 register definitions |
| 2 | Copyright (C) 1999 Cygnus Solutions. */ | |
| 3 | ||
| 4 | #ifndef REG32_H | |
| 5 | #define REG32_H | |
| 6 | ||
| 7 | /* PSR bits */ | |
| 8 | ||
| 9 | #define PSR_IMPL 0xf0000000 | |
| 10 | #define PSR_VER 0x0f000000 | |
| 11 | #define PSR_CC 0x00f00000 | |
| 12 | #define PSR_N 0x00800000 | |
| 13 | #define PSR_Z 0x00400000 | |
| 14 | #define PSR_V 0x00200000 | |
| 15 | #define PSR_C 0x00100000 | |
| 16 | #define PSR_EC 0x00002000 | |
| 17 | #define PSR_EF 0x00001000 | |
| 18 | #define PSR_PIL 0x00000f00 | |
| 19 | #define PSR_S 0x00000080 | |
| 20 | #define PSR_PS 0x00000040 | |
| 21 | #define PSR_ET 0x00000020 | |
| 22 | #define PSR_CWP 0x0000001f | |
| 23 | ||
| 24 | /* The PSR is a hodge-podge of various things. | |
| 25 | ??? The final organization of this is wip. */ | |
| 26 | ||
| 27 | extern USI sparc32_get_h_psr_handler (SIM_CPU *); | |
| 28 | extern void sparc32_set_h_psr_handler (SIM_CPU *, USI); | |
| 29 | #define GET_H_PSR() sparc32_get_h_psr_handler (current_cpu) | |
| 30 | #define SET_H_PSR(val) sparc32_set_h_psr_handler (current_cpu, (val)) | |
| 31 | ||
| 32 | /* The y reg is a virtual reg as it's actually one of the asr regs. | |
| 33 | ??? To be replaced in time with get/set specs. */ | |
| 34 | #if 0 | |
| 35 | #define sparc32_h_y_get(cpu) (CPU_CGEN_HW (cpu)->h_asr[0]) | |
| 36 | #define sparc32_h_y_set(cpu,val) (CPU_CGEN_HW (cpu)->h_asr[0] = (val)) | |
| 37 | #endif | |
| 38 | #define GET_H_Y() (CPU (h_asr) [0]) | |
| 39 | #define SET_H_Y(newval) do { CPU (h_asr) [0] = (newval); } while (0) | |
| 40 | ||
| 41 | /* The Trap Base Register. */ | |
| 42 | #define GET_H_TBR() CPU (h_tbr) | |
| 43 | #define SET_H_TBR(newval) \ | |
| 44 | do { \ | |
| 45 | CPU (h_tbr) = (CPU (h_tbr) & 0xff0) | ((newval) & 0xfffff000); \ | |
| 46 | } while (0) | |
| 47 | \f | |
| 48 | /* sparc32 register window stuff. */ | |
| 49 | ||
| 50 | /* Handle gets/sets of h-cwp. | |
| 51 | This handles swapping out the current set of window registers | |
| 52 | and swapping in the new. How the "swapping" is done depends on the | |
| 53 | register window implementation of the day. */ | |
| 54 | void sparc32_set_h_cwp_handler (SIM_CPU *, int); | |
| 55 | #define GET_H_CWP() CPU (h_cwp) | |
| 56 | #define SET_H_CWP(newval) sparc32_set_h_cwp_handler (current_cpu, (newval)) | |
| 57 | ||
| 58 | /* WIM accessors. */ | |
| 59 | /* ??? Yes, mask computation assumes nwindows < 32. */ | |
| 60 | #define GET_H_WIM() (CPU (h_wim) & ((1 << GET_NWINDOWS ()) - 1)) | |
| 61 | #define SET_H_WIM(newval) (CPU (h_wim) = (newval)) | |
| 62 | ||
| 63 | /* Return non-zero if window WIN is valid in WIM. */ | |
| 64 | #define WINDOW_VALID_P(win, wim) (((wim) & (1 << (win))) == 0) | |
| 65 | ||
| 66 | void sparc32_alloc_regwins (SIM_CPU *, int); | |
| 67 | void sparc32_free_regwins (SIM_CPU *); | |
| 68 | void sparc32_swapout_regwin (SIM_CPU *, int); | |
| 69 | void sparc32_swapin_regwin (SIM_CPU *, int); | |
| 70 | ||
| 71 | void sparc32_load_regwin (SIM_CPU *, IADDR pc_, int win_); | |
| 72 | void sparc32_flush_regwin (SIM_CPU *, IADDR pc_, int win_, int no_errors_p_); | |
| 73 | void sparc32_flush_regwins (SIM_CPU *, IADDR pc_, int no_errors_p_); | |
| 74 | ||
| 75 | void sparc32_save_regwin (SIM_CPU *); | |
| 76 | void sparc32_restore_regwin (SIM_CPU *); | |
| 77 | \f | |
| 78 | /* Integer register access macros. | |
| 79 | Provides an interface between the cpu description and the register window | |
| 80 | implementation of the day. To be solidified in time. */ | |
| 81 | #define GET_H_GR(r) (current_cpu->current_regs[r]) | |
| 82 | ||
| 83 | /* ??? The r != 0 test may not be necessary as sufficient numbers of dni | |
| 84 | entries can prevent this from occuring (I think). Even then though doing | |
| 85 | this makes things more robust, and a lot of dni's would be needed. | |
| 86 | ??? The other way to handle %g0 is to always reset it for each insn | |
| 87 | [perhaps optimized to only do so when necessary]. */ | |
| 88 | #define SET_H_GR(r, val) \ | |
| 89 | ((r) != 0 ? (current_cpu->current_regs[r] = (val)) : 0) | |
| 90 | ||
| 91 | #endif /* REG32_H */ |