projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| cd6245ce DE |
1 | /* Sparc target configuration file. -*- C -*- */ |
| 2 | ||
| 3 | #ifndef SPARC_TCONFIG_H | |
| 4 | #define SPARC_TCONFIG_H | |
| 5 | ||
| 6 | /* See sim-hload.c. We properly handle LMA. */ | |
| 7 | ||
| 8 | #define SIM_HANDLES_LMA 1 | |
| 9 | ||
| 10 | /* Device support. FIXME: revisit. */ | |
| 11 | #define WITH_DEVICES 1 | |
| 12 | ||
| 13 | /* This is a global setting. Different cpu families can't mix-n-match -scache | |
| 14 | and -pbb. However some cpu families may use -simple while others use | |
| 15 | one of -scache/-pbb. */ | |
| 16 | #define WITH_SCACHE_PBB 0 | |
| 17 | ||
| 18 | /* Simple-engine branch support. | |
| 19 | Delay slots, annuling, and traps are (currently) handled by using the | |
| 20 | simple engine and doing all the work in SEM_{,N}BRANCH_FINI. */ | |
| 21 | ||
| 22 | #define TARGET_SEM_BRANCH_FINI(vpc, bool_attrs, taken_p) \ | |
| 23 | do { \ | |
| 24 | IADDR npc = GET_H_NPC (); \ | |
| 25 | if (CGEN_BOOL_ATTR ((bool_attrs), CGEN_INSN_DELAY_SLOT) && taken_p) \ | |
| 26 | { \ | |
| 27 | SET_H_PC (npc); \ | |
| 28 | SET_H_NPC (vpc); \ | |
| 29 | } \ | |
| 30 | else if (CGEN_BOOL_ATTR ((bool_attrs), CGEN_INSN_TRAP) && taken_p) \ | |
| 31 | { \ | |
| 32 | SET_H_PC (vpc); \ | |
| 33 | SET_H_NPC ((vpc) + 4); \ | |
| 34 | } \ | |
| 35 | else \ | |
| 36 | { \ | |
| 37 | SET_H_PC (npc); \ | |
| 38 | SET_H_NPC (npc + 4); \ | |
| 39 | } \ | |
| 40 | } while (0) | |
| 41 | ||
| 42 | #define TARGET_SEM_NBRANCH_FINI(vpc, bool_attrs) \ | |
| 43 | do { \ | |
| 44 | IADDR npc = GET_H_NPC (); \ | |
| 45 | SET_H_PC (npc); \ | |
| 46 | SET_H_NPC (npc + 4); \ | |
| 47 | } while (0) | |
| 48 | ||
| 49 | #endif /* SPARC_TCONFIG_H */ |