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import gdb-1999-09-21
[thirdparty/binutils-gdb.git] / sim / testsuite / ChangeLog
CommitLineData
c2c6d25f
JM		 11999-09-15 Doug Evans <devans@casey.cygnus.com>
2
3 * sim/arm/b.cgs: New testcase.
4 * sim/arm/bic.cgs: New testcase.
5 * sim/arm/bl.cgs: New testcase.
6
d4f3574e
SS		 7Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
8
9 * configure: Regenerated to track ../common/aclocal.m4 changes.
10
104c1213
JM		 111999-08-30 Doug Evans <devans@casey.cygnus.com>
12
104c1213
JM		 13 * lib/sim-defs.exp (run_sim_test): Rename all_machs arg to
14 requested_machs, now is list of machs to run tests for.
15 Delete locals AS,ASFLAGS,LD,LDFLAGS. Use target_assemble
16 and target_link instead.
17
7a292a7a
SS		 181999-04-21 Doug Evans <devans@casey.cygnus.com>
19
20 * sim/m32r/nop.cgs: Add missing nop insn.
21
22Mon Mar 22 13:28:56 1999 Dave Brolley <brolley@cygnus.com>
23
24 * sim/fr30/stb.cgs: Correct for unaligned access.
25 * sim/fr30/sth.cgs: Correct for unaligned access.
26 * sim/fr30/ldub.cgs: Fix typo: lduh->ldub. Correct
27 for unaligned access.
28 * sim/fr30/and.cgs: Test unaligned access.
29
c906108c
SS		 30Fri Feb 5 12:41:11 1999 Doug Evans <devans@canuck.cygnus.com>
31
32 * lib/sim-defs.exp (sim_run): Print simulator arguments log message.
33
341999-01-05 Doug Evans <devans@casey.cygnus.com>
35
36 * lib/sim-defs.exp (run_sim_test): New arg all_machs.
37 * sim/fr30/allinsn.exp: Update.
38 * sim/fr30/misc.exp: Update.
39 * sim/m32r/allinsn.exp: Update.
40 * sim/m32r/misc.exp: Update.
41
42Fri Dec 18 17:19:34 1998 Dave Brolley <brolley@cygnus.com>
43
44 * sim/fr30/ldres.cgs: New testcase.
45 * sim/fr30/copld.cgs: New testcase.
46 * sim/fr30/copst.cgs: New testcase.
47 * sim/fr30/copsv.cgs: New testcase.
48 * sim/fr30/nop.cgs: New testcase.
49 * sim/fr30/andccr.cgs: New testcase.
50 * sim/fr30/orccr.cgs: New testcase.
51 * sim/fr30/addsp.cgs: New testcase.
52 * sim/fr30/stilm.cgs: New testcase.
53 * sim/fr30/extsb.cgs: New testcase.
54 * sim/fr30/extub.cgs: New testcase.
55 * sim/fr30/extsh.cgs: New testcase.
56 * sim/fr30/extuh.cgs: New testcase.
57 * sim/fr30/enter.cgs: New testcase.
58 * sim/fr30/leave.cgs: New testcase.
59 * sim/fr30/xchb.cgs: New testcase.
60 * sim/fr30/dmovb.cgs: New testcase.
61 * sim/fr30/dmov.cgs: New testcase.
62 * sim/fr30/dmovh.cgs: New testcase.
63
64Thu Dec 17 17:18:43 1998 Dave Brolley <brolley@cygnus.com>
65
66 * sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros.
67 * sim/fr30/ret.cgs: Add tests fir ret:d.
68 * sim/fr30/inte.cgs: New testcase.
69 * sim/fr30/reti.cgs: New testcase.
70 * sim/fr30/bra.cgs: New testcase.
71 * sim/fr30/bno.cgs: New testcase.
72 * sim/fr30/beq.cgs: New testcase.
73 * sim/fr30/bne.cgs: New testcase.
74 * sim/fr30/bc.cgs: New testcase.
75 * sim/fr30/bnc.cgs: New testcase.
76 * sim/fr30/bn.cgs: New testcase.
77 * sim/fr30/bp.cgs: New testcase.
78 * sim/fr30/bv.cgs: New testcase.
79 * sim/fr30/bnv.cgs: New testcase.
80 * sim/fr30/blt.cgs: New testcase.
81 * sim/fr30/bge.cgs: New testcase.
82 * sim/fr30/ble.cgs: New testcase.
83 * sim/fr30/bgt.cgs: New testcase.
84 * sim/fr30/bls.cgs: New testcase.
85 * sim/fr30/bhi.cgs: New testcase.
86
87Tue Dec 15 17:47:13 1998 Dave Brolley <brolley@cygnus.com>
88
89 * sim/fr30/div.cgs (int): Add signed division scenario.
90 * sim/fr30/int.cgs (int): Complete testcase.
91 * sim/fr30/testutils.inc (_start): Initialize tbr.
92 (test_s_user,test_s_system,set_i,test_i): New macros.
93
941998-12-14 Doug Evans <devans@casey.cygnus.com>
95
96 * lib/sim-defs.exp (run_sim_test): New option xerror, for expected
97 errors. Translate \n sequences in expected output to newline char.
98 (slurp_options): Make parentheses optional.
99 (sim_run): Look for board_info sim,options.
100 * sim/fr30/hello.ms: Add trailing \n to expected output.
101 * sim/m32r/hello.ms: Ditto.
102 * sim/m32r/hw-trap.ms: Ditto.
103
104 * sim/m32r/trap.cgs: Properly align trap2_handler.
105
106 * sim/m32r/uread16.ms: New testcase.
107 * sim/m32r/uread32.ms: New testcase.
108 * sim/m32r/uwrite16.ms: New testcase.
109 * sim/m32r/uwrite32.ms: New testcase.
110
1111998-12-14 Dave Brolley <brolley@cygnus.com>
112
113 * sim/fr30/call.cgs: Test ret here as well.
114 * sim/fr30/ld.cgs: Remove bogus comment.
115 * sim/fr30/testutils.inc (save_rp,restore_rp): New macros.
116 * sim/fr30/div.ms: New testcase.
117 * sim/fr30/st.cgs: New testcase.
118 * sim/fr30/sth.cgs: New testcase.
119 * sim/fr30/stb.cgs: New testcase.
120 * sim/fr30/mov.cgs: New testcase.
121 * sim/fr30/jmp.cgs: New testcase.
122 * sim/fr30/ret.cgs: New testcase.
123 * sim/fr30/int.cgs: New testcase.
124
125Thu Dec 10 18:46:25 1998 Dave Brolley <brolley@cygnus.com>
126
127 * sim/fr30/div0s.cgs: New testcase.
128 * sim/fr30/div0u.cgs: New testcase.
129 * sim/fr30/div1.cgs: New testcase.
130 * sim/fr30/div2.cgs: New testcase.
131 * sim/fr30/div3.cgs: New testcase.
132 * sim/fr30/div4s.cgs: New testcase.
133 * sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros.
134
135Tue Dec 8 13:16:53 1998 Dave Brolley <brolley@cygnus.com>
136
137 * sim/fr30/testutils.inc (set_s_user): Correct Mask.
138 (set_s_system): Correct Mask.
139 * sim/fr30/ld.cgs (ld): Move previously failing test back
140 into place.
141 * sim/fr30/ldm0.cgs: New testcase.
142 * sim/fr30/ldm1.cgs: New testcase.
143 * sim/fr30/stm0.cgs: New testcase.
144 * sim/fr30/stm1.cgs: New testcase.
145
146Thu Dec 3 14:20:03 1998 Dave Brolley <brolley@cygnus.com>
147
148 * sim/fr30/ld.cgs: Implement more loads.
149 * sim/fr30/call.cgs: New testcase.
150 * sim/fr30/testutils.inc (testr_h_dr): New macro.
151 (set_s_user,set_s_system): New macros.
152
153 * sim/fr30: New Directory.
154
155Wed Nov 18 10:50:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
156
157 * common/bits-gen.c (main): Add BYTE_ORDER so that it matches
158 recent sim/common/sim-basics.h changes.
159 * common/Makefile.in: Update.
160
161Fri Oct 30 00:37:31 1998 Felix Lee <flee@cygnus.com>
162
163 * lib/sim-defs.exp (sim_run): download target program to remote
164 host, if necessary. for unix-driven win32 testing.
165
166Tue Sep 15 14:56:22 1998 Doug Evans <devans@canuck.cygnus.com>
167
168 * sim/m32r/testutils.inc (test_h_gr): Use mvaddr_h_gr.
169 * sim/m32r/rte.cgs: Test bbpc,bbpsw.
170 * sim/m32r/trap.cgs: Test bbpc,bbpsw.
171
7a292a7a
SS		 172Fri Jul 31 17:49:13 1998 Felix Lee <flee@cygnus.com>
173
174 * lib/sim-defs.exp (sim_run): remote_spawn, use writeto instead of
175 writeonly.
176
c906108c
SS		 177Fri Jul 24 09:40:34 1998 Doug Evans <devans@canuck.cygnus.com>
178
179 * Makefile.in (clean,mostlyclean): Change leading spaces to a tab.
180
181Wed Jul 1 15:57:54 1998 Doug Evans <devans@seba.cygnus.com>
182
183 * sim/m32r/hw-trap.ms: New testcase.
184
7a292a7a
SS		 185Tue Jun 16 15:44:01 1998 Jillian Ye <jillian@cygnus.com>
186
187 * lib/sim-defs.exp: Print out timeout setting info when "-v" is used.
188
189Thu Jun 11 15:24:53 1998 Doug Evans <devans@canuck.cygnus.com>
190
191 * lib/sim-defs.exp (sim_run): Argument env_vals renamed to options,
192 which is now a list of options controlling the behaviour of sim_run.
193
c906108c
SS		 194Wed Jun 10 10:53:20 1998 Doug Evans <devans@seba.cygnus.com>
195
196 * sim/m32r/addx.cgs: Add another test.
197 * sim/m32r/jmp.cgs: Add another test.
198
199Mon Jun 8 16:08:27 1998 Doug Evans <devans@canuck.cygnus.com>
200
201 * sim/m32r/trap.cgs: Test trap 2.
202
203Mon Jun 1 18:54:22 1998 Frank Ch. Eigler <fche@cygnus.com>
204
205 * lib/sim-defs.exp (sim_run): Add possible environment variable
206 list to simulator run.
207
208Thu May 28 14:59:46 1998 Jillian Ye <jillian@cygnus.com>
209
210 * Makefile.in: Take RUNTEST out of FLAG_TO_PASS
211 so that make check can be invoked recursively.
212
213Thu May 14 11:48:35 1998 Doug Evans <devans@canuck.cygnus.com>
214
215 * config/default.exp (CC,SIM): Delete.
216
217 * lib/sim-defs.exp (sim_run): Fix handling of output redirection.
218 New arg prog_opts. All callers updated.
219
220Fri May 8 18:10:28 1998 Jillian Ye <jillian@cygnus.com>
221
222 * Makefile.in: Made "check" the target of two
223 dependencies (test1, test2) so that test2 get a chance to
224 run even when test1 failed if "make -k check" is used.
225
226Fri May 8 14:41:28 1998 Doug Evans <devans@canuck.cygnus.com>
227
228 * lib/sim-defs.exp (sim_version): Simplify.
229 (sim_run): Implement.
230 (run_sim_test): Use sim_run.
231 (sim_compile): New proc.
232
233Mon May 4 17:59:11 1998 Frank Ch. Eigler <fche@cygnus.com>
234
235 * config/default.exp: Added C compiler settings.
236
237Wed Apr 22 12:26:28 1998 Doug Evans <devans@canuck.cygnus.com>
238
239 * Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS.
240
241Tue Apr 21 10:49:03 1998 Doug Evans <devans@canuck.cygnus.com>
242
243 * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails,
244 try all machs.
245
246 * sim/m32r/addx.cgs: Test (-1)+(-1)+1.
247
248Fri Apr 17 16:00:52 1998 Doug Evans <devans@canuck.cygnus.com>
249
250 * sim/m32r/mv[ft]achi.cgs: Fix expected result
251 (sign extension of top 8 bits).
252
253Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com>
254
255 * Makefile.in (RUNTEST): Fix path to runtest.
256
257
258Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com>
259
260 * sim/m32r/unlock.cgs: Fixed test.
261 * sim/m32r/mvfc.cgs: Fixed test.
262 * sim/m32r/remu.cgs: Fixed test.
263
264 * sim/m32r/bnc24.cgs: Test long BNC instruction.
265 * sim/m32r/bnc8.cgs: Test short BNC instruction.
266 * sim/m32r/ld-plus.cgs: Test LD instruction.
267 * sim/m32r/macwhi.cgs: Test MACWHI instruction.
268 * sim/m32r/macwlo.cgs: Test MACWLO instruction.
269 * sim/m32r/mulwhi.cgs: Test MULWHI instruction.
270 * sim/m32r/mulwlo.cgs: Test MULWLO instruction.
271 * sim/m32r/mvfachi.cgs: Test MVFACHI instruction.
272 * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction.
273 * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction.
274 * sim/m32r/addv.cgs: Test ADDV instruction.
275 * sim/m32r/addv3.cgs: Test ADDV3 instruction.
276 * sim/m32r/addx.cgs: Test ADDX instruction.
277 * sim/m32r/lock.cgs: Test LOCK instruction.
278 * sim/m32r/neg.cgs: Test NEG instruction.
279 * sim/m32r/not.cgs: Test NOT instruction.
280 * sim/m32r/unlock.cgs: Test UNLOCK instruction.
281Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
282
283 * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an
284 address into a general register.
285
286 * sim/m32r/or3.cgs: Test OR3 instruction.
287 * sim/m32r/rach.cgs: Test RACH instruction.
288 * sim/m32r/rem.cgs: Test REM instruction.
289 * sim/m32r/sub.cgs: Test SUB instruction.
290 * sim/m32r/mv.cgs: Test MV instruction.
291 * sim/m32r/mul.cgs: Test MUL instruction.
292 * sim/m32r/bl24.cgs: Test long BL instruction.
293 * sim/m32r/bl8.cgs: Test short BL instruction.
294 * sim/m32r/blez.cgs: Test BLEZ instruction.
295 * sim/m32r/bltz.cgs: Test BLTZ instruction.
296 * sim/m32r/bne.cgs: Test BNE instruction.
297 * sim/m32r/bnez.cgs: Test BNEZ instruction.
298 * sim/m32r/bra24.cgs: Test long BRA instruction.
299 * sim/m32r/bra8.cgs: Test short BRA instruction.
300 * sim/m32r/jl.cgs: Test JL instruction.
301 * sim/m32r/or.cgs: Test OR instruction.
302 * sim/m32r/jmp.cgs: Test JMP instruction.
303 * sim/m32r/and.cgs: Test AND instruction.
304 * sim/m32r/and3.cgs: Test AND3 instruction.
305 * sim/m32r/beq.cgs: Test BEQ instruction.
306 * sim/m32r/beqz.cgs: Test BEQZ instruction.
307 * sim/m32r/bgez.cgs: Test BGEZ instruction.
308 * sim/m32r/bgtz.cgs: Test BGTZ instruction.
309 * sim/m32r/cmp.cgs: Test CMP instruction.
310 * sim/m32r/cmpi.cgs: Test CMPI instruction.
311 * sim/m32r/cmpu.cgs: Test CMPU instruction.
312 * sim/m32r/cmpui.cgs: Test CMPUI instruction.
313 * sim/m32r/div.cgs: Test DIV instruction.
314 * sim/m32r/divu.cgs: Test DIVU instruction.
315 * sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
316 * sim/m32r/sll.cgs: Test SLL instruction.
317 * sim/m32r/sll3.cgs: Test SLL3 instruction.
318 * sim/m32r/slli.cgs: Test SLLI instruction.
319 * sim/m32r/sra.cgs: Test SRA instruction.
320 * sim/m32r/sra3.cgs: Test SRA3 instruction.
321 * sim/m32r/srai.cgs: Test SRAI instruction.
322 * sim/m32r/srl.cgs: Test SRL instruction.
323 * sim/m32r/srl3.cgs: Test SRL3 instruction.
324 * sim/m32r/srli.cgs: Test SRLI instruction.
325 * sim/m32r/xor3.cgs: Test XOR3 instruction.
326 * sim/m32r/xor.cgs: Test XOR instruction.
327Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
328
329 * config/default.exp: New file.
330 * lib/sim-defs.exp: New file.
331 * sim/m32r/*: m32r dejagnu simulator testsuite.
332
333 * Makefile.in (build_alias): Define.
334 (arch): Define.
335 (RUNTEST_FOR_TARGET): Delete.
336 (RUNTEST): Fix.
337 (check): Depend on site.exp. Run dejagnu.
338 (site.exp): New target.
339 * configure.in (arch): Define from target_cpu.
340 * configure: Regenerate.
341
342Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
343
344 * common/bits-gen.c (gen_bit): Pass in the full name of the macro.
345 (gen_mask): Ditto.
346
347 * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT.
348 (calc): Add support for 8 bit version of macros.
349 (main): Add tests for 8 bit versions of macros.
350 (check_sext): Check SEXT of zero clears bits.
351
352 * common/bits-gen.c (main): Generate tests for 8 bit versions of
353 macros.
354
355Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
356
357 * common/Make-common.in: New file, provide generic rules for
358 running checks.
359
360Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
361
362 * configure.in (configdirs): Test for the target directory instead
363 of matching on a target.
364
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