[thirdparty/binutils-gdb.git] / sim / v850 / interp.c

#include "sim-main.h"
#include "sim-options.h"
#include "v850_sim.h"
#include "sim-assert.h"
#include "itable.h"

#include <stdlib.h>
#include <string.h>

#include "bfd.h"

static const char * get_insn_name (sim_cpu *, int);

/* For compatibility.  */
SIM_DESC simulator;

/* V850 interrupt model.  */

enum interrupt_type
{
  int_reset,
  int_nmi,
  int_intov1,
  int_intp10,
  int_intp11,
  int_intp12,
  int_intp13,
  int_intcm4,
  num_int_types
};

const char *interrupt_names[] =
{
  "reset",
  "nmi",
  "intov1",
  "intp10",
  "intp11",
  "intp12",
  "intp13",
  "intcm4",
  NULL
};

static void
do_interrupt (SIM_DESC sd, void *data)
{
  const char **interrupt_name = (const char**)data;
  enum interrupt_type inttype;
  inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names);

  /* For a hardware reset, drop everything and jump to the start
     address */
  if (inttype == int_reset)
    {
      PC = 0;
      PSW = 0x20;
      ECR = 0;
      sim_engine_restart (sd, NULL, NULL, NULL_CIA);
    }

  /* Deliver an NMI when allowed */
  if (inttype == int_nmi)
    {
      if (PSW & PSW_NP)
	{
	  /* We're already working on an NMI, so this one must wait
	     around until the previous one is done.  The processor
	     ignores subsequent NMIs, so we don't need to count them.
	     Just keep re-scheduling a single NMI until it manages to
	     be delivered */
	  if (STATE_CPU (sd, 0)->pending_nmi != NULL)
	    sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi);
	  STATE_CPU (sd, 0)->pending_nmi =
	    sim_events_schedule (sd, 1, do_interrupt, data);
	  return;
	}
      else
	{
	  /* NMI can be delivered.  Do not deschedule pending_nmi as
             that, if still in the event queue, is a second NMI that
             needs to be delivered later. */
	  FEPC = PC;
	  FEPSW = PSW;
	  /* Set the FECC part of the ECR. */
	  ECR &= 0x0000ffff;
	  ECR |= 0x10;
	  PSW |= PSW_NP;
	  PSW &= ~PSW_EP;
	  PSW |= PSW_ID;
	  PC = 0x10;
	  sim_engine_restart (sd, NULL, NULL, NULL_CIA);
	}
    }

  /* deliver maskable interrupt when allowed */
  if (inttype > int_nmi && inttype < num_int_types)
    {
      if ((PSW & PSW_NP) || (PSW & PSW_ID))
	{
	  /* Can't deliver this interrupt, reschedule it for later */
	  sim_events_schedule (sd, 1, do_interrupt, data);
	  return;
	}
      else
	{
	  /* save context */
	  EIPC = PC;
	  EIPSW = PSW;
	  /* Disable further interrupts.  */
	  PSW |= PSW_ID;
	  /* Indicate that we're doing interrupt not exception processing.  */
	  PSW &= ~PSW_EP;
	  /* Clear the EICC part of the ECR, will set below. */
	  ECR &= 0xffff0000;
	  switch (inttype)
	    {
	    case int_intov1:
	      PC = 0x80;
	      ECR |= 0x80;
	      break;
	    case int_intp10:
	      PC = 0x90;
	      ECR |= 0x90;
	      break;
	    case int_intp11:
	      PC = 0xa0;
	      ECR |= 0xa0;
	      break;
	    case int_intp12:
	      PC = 0xb0;
	      ECR |= 0xb0;
	      break;
	    case int_intp13:
	      PC = 0xc0;
	      ECR |= 0xc0;
	      break;
	    case int_intcm4:
	      PC = 0xd0;
	      ECR |= 0xd0;
	      break;
	    default:
	      /* Should never be possible.  */
	      sim_engine_abort (sd, NULL, NULL_CIA,
				"do_interrupt - internal error - bad switch");
	      break;
	    }
	}
      sim_engine_restart (sd, NULL, NULL, NULL_CIA);
    }
  
  /* some other interrupt? */
  sim_engine_abort (sd, NULL, NULL_CIA,
		    "do_interrupt - internal error - interrupt %d unknown",
		    inttype);
}

/* Return name of an insn, used by insn profiling.  */

static const char *
get_insn_name (sim_cpu *cpu, int i)
{
  return itable[i].name;
}

/* These default values correspond to expected usage for the chip.  */

uint32 OP[4];

static sim_cia
v850_pc_get (sim_cpu *cpu)
{
  return PC;
}

static void
v850_pc_set (sim_cpu *cpu, sim_cia pc)
{
  PC = pc;
}

static int v850_reg_fetch (SIM_CPU *, int, unsigned char *, int);
static int v850_reg_store (SIM_CPU *, int, unsigned char *, int);

SIM_DESC
sim_open (SIM_OPEN_KIND    kind,
	  host_callback *  cb,
	  struct bfd *     abfd,
	  char * const *   argv)
{
  int i;
  SIM_DESC sd = sim_state_alloc (kind, cb);
  int mach;

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

  /* The cpu data is kept in a separately allocated chunk of memory.  */
  if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
    return 0;

  /* for compatibility */
  simulator = sd;

  /* FIXME: should be better way of setting up interrupts */
  STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt;
  STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names;

  /* Initialize the mechanism for doing insn profiling.  */
  CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name;
  CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries;

  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
    return 0;

  /* Allocate core managed memory */

  /* "Mirror" the ROM addresses below 1MB. */
  sim_do_commandf (sd, "memory region 0,0x100000,0x%lx", V850_ROM_SIZE);
  /* Chunk of ram adjacent to rom */
  sim_do_commandf (sd, "memory region 0x100000,0x%lx", V850_LOW_END-0x100000);
  /* peripheral I/O region - mirror 1K across 4k (0x1000) */
  sim_do_command (sd, "memory region 0xfff000,0x1000,1024");
  /* similarly if in the internal RAM region */
  sim_do_command (sd, "memory region 0xffe000,0x1000,1024");

  /* The parser will print an error message for us, so we silently return.  */
  if (sim_parse_args (sd, argv) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
	 file descriptor leaks, etc.  */
      sim_module_uninstall (sd);
      return 0;
    }

  /* check for/establish the a reference program image */
  if (sim_analyze_program (sd,
			   (STATE_PROG_ARGV (sd) != NULL
			    ? *STATE_PROG_ARGV (sd)
			    : NULL),
			   abfd) != SIM_RC_OK)
    {
      sim_module_uninstall (sd);
      return 0;
    }

  /* establish any remaining configuration options */
  if (sim_config (sd) != SIM_RC_OK)
    {
      sim_module_uninstall (sd);
      return 0;
    }

  if (sim_post_argv_init (sd) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
	 file descriptor leaks, etc.  */
      sim_module_uninstall (sd);
      return 0;
    }


  /* determine the machine type */
  if (STATE_ARCHITECTURE (sd) != NULL
      && (STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850
	  || STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850_rh850))
    mach = STATE_ARCHITECTURE (sd)->mach;
  else
    mach = bfd_mach_v850; /* default */

  /* set machine specific configuration */
  switch (mach)
    {
    case bfd_mach_v850:
    case bfd_mach_v850e:
    case bfd_mach_v850e1:
    case bfd_mach_v850e2:
    case bfd_mach_v850e2v3:
    case bfd_mach_v850e3v5:
      STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT
				     | PSW_CY | PSW_OV | PSW_S | PSW_Z);
      break;
    }

  /* CPU specific initialization.  */
  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
    {
      SIM_CPU *cpu = STATE_CPU (sd, i);

      CPU_REG_FETCH (cpu) = v850_reg_fetch;
      CPU_REG_STORE (cpu) = v850_reg_store;
      CPU_PC_FETCH (cpu) = v850_pc_get;
      CPU_PC_STORE (cpu) = v850_pc_set;
    }

  return sd;
}

SIM_RC
sim_create_inferior (SIM_DESC      sd,
		     struct bfd *  prog_bfd,
		     char * const *argv,
		     char * const *env)
{
  memset (&State, 0, sizeof (State));
  if (prog_bfd != NULL)
    PC = bfd_get_start_address (prog_bfd);
  return SIM_RC_OK;
}

static int
v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
  *(unsigned32*)memory = H2T_4 (State.regs[rn]);
  return -1;
}

static int
v850_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
  State.regs[rn] = T2H_4 (*(unsigned32 *) memory);
  return length;
}
Commit	Line	Data
c906108c SS	1	#include "sim-main.h"
	2	#include "sim-options.h"
	3	#include "v850_sim.h"
	4	#include "sim-assert.h"
	5	#include "itable.h"
	6
c906108c	7	#include <stdlib.h>
c906108c	8	#include <string.h>
c906108c SS	9
	10	#include "bfd.h"
	11
c906108c SS	12	static const char * get_insn_name (sim_cpu *, int);
c906108c SS	13
a3976a7c	14	/* For compatibility. */
c906108c SS	15	SIM_DESC simulator;
c906108c SS	16
a3976a7c	17	/* V850 interrupt model. */
c906108c SS	18
	19	enum interrupt_type
	20	{
	21	int_reset,
	22	int_nmi,
	23	int_intov1,
	24	int_intp10,
	25	int_intp11,
	26	int_intp12,
	27	int_intp13,
	28	int_intcm4,
	29	num_int_types
	30	};
	31
a3976a7c NC	32	const char *interrupt_names[] =
a3976a7c NC	33	{
c906108c SS	34	"reset",
	35	"nmi",
	36	"intov1",
	37	"intp10",
	38	"intp11",
	39	"intp12",
	40	"intp13",
	41	"intcm4",
	42	NULL
	43	};
	44
	45	static void
a3976a7c	46	do_interrupt (SIM_DESC sd, void *data)
c906108c	47	{
4e9586f0	48	const char interrupt_name = (const char)data;
c906108c SS	49	enum interrupt_type inttype;
	50	inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names);
	51
	52	/* For a hardware reset, drop everything and jump to the start
	53	address */
	54	if (inttype == int_reset)
	55	{
	56	PC = 0;
	57	PSW = 0x20;
	58	ECR = 0;
	59	sim_engine_restart (sd, NULL, NULL, NULL_CIA);
	60	}
	61
	62	/* Deliver an NMI when allowed */
	63	if (inttype == int_nmi)
	64	{
	65	if (PSW & PSW_NP)
	66	{
	67	/* We're already working on an NMI, so this one must wait
	68	around until the previous one is done. The processor
	69	ignores subsequent NMIs, so we don't need to count them.
	70	Just keep re-scheduling a single NMI until it manages to
	71	be delivered */
	72	if (STATE_CPU (sd, 0)->pending_nmi != NULL)
	73	sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi);
	74	STATE_CPU (sd, 0)->pending_nmi =
	75	sim_events_schedule (sd, 1, do_interrupt, data);
	76	return;
	77	}
	78	else
	79	{
	80	/* NMI can be delivered. Do not deschedule pending_nmi as
	81	that, if still in the event queue, is a second NMI that
	82	needs to be delivered later. */
	83	FEPC = PC;
	84	FEPSW = PSW;
	85	/* Set the FECC part of the ECR. */
	86	ECR &= 0x0000ffff;
	87	ECR \|= 0x10;
	88	PSW \|= PSW_NP;
	89	PSW &= ~PSW_EP;
	90	PSW \|= PSW_ID;
	91	PC = 0x10;
	92	sim_engine_restart (sd, NULL, NULL, NULL_CIA);
	93	}
	94	}
	95
	96	/* deliver maskable interrupt when allowed */
	97	if (inttype > int_nmi && inttype < num_int_types)
	98	{
	99	if ((PSW & PSW_NP) \|\| (PSW & PSW_ID))
	100	{
	101	/* Can't deliver this interrupt, reschedule it for later */
	102	sim_events_schedule (sd, 1, do_interrupt, data);
	103	return;
	104	}
	105	else
	106	{
	107	/* save context */
	108	EIPC = PC;
	109	EIPSW = PSW;
	110	/* Disable further interrupts. */
	111	PSW \|= PSW_ID;
	112	/* Indicate that we're doing interrupt not exception processing. */
113	PSW &= ~PSW_EP;
114	/* Clear the EICC part of the ECR, will set below. */
115	ECR &= 0xffff0000;
116	switch (inttype)
117	{
118	case int_intov1:
119	PC = 0x80;
120	ECR \|= 0x80;
121	break;
122	case int_intp10:
123	PC = 0x90;
124	ECR \|= 0x90;
125	break;
126	case int_intp11:
127	PC = 0xa0;
128	ECR \|= 0xa0;
129	break;
130	case int_intp12:
131	PC = 0xb0;
132	ECR \|= 0xb0;
133	break;
134	case int_intp13:
135	PC = 0xc0;
136	ECR \|= 0xc0;
137	break;
138	case int_intcm4:
139	PC = 0xd0;
140	ECR \|= 0xd0;
141	break;
142	default:
143	/* Should never be possible. */
144	sim_engine_abort (sd, NULL, NULL_CIA,
145	"do_interrupt - internal error - bad switch");
146	break;
147	}
148	}
149	sim_engine_restart (sd, NULL, NULL, NULL_CIA);
150	}
151
152	/* some other interrupt? */
153	sim_engine_abort (sd, NULL, NULL_CIA,
154	"do_interrupt - internal error - interrupt %d unknown",
155	inttype);
156	}
157
158	/* Return name of an insn, used by insn profiling. */
159
160	static const char *
161	get_insn_name (sim_cpu *cpu, int i)
162	{
163	return itable[i].name;
164	}
165
166	/* These default values correspond to expected usage for the chip. */
167
168	uint32 OP[4];
169
14c9ad2e MF	170	static sim_cia
	171	v850_pc_get (sim_cpu *cpu)
	172	{
	173	return PC;
	174	}
	175
	176	static void
	177	v850_pc_set (sim_cpu *cpu, sim_cia pc)
	178	{
	179	PC = pc;
	180	}
c906108c	181
e1211e55 MF	182	static int v850_reg_fetch (SIM_CPU , int, unsigned char , int);
	183	static int v850_reg_store (SIM_CPU , int, unsigned char , int);
	184
c906108c	185	SIM_DESC
a3976a7c NC	186	sim_open (SIM_OPEN_KIND kind,
	187	host_callback * cb,
	188	struct bfd * abfd,
2e3d4f4d	189	char * const * argv)
c906108c	190	{
14c9ad2e	191	int i;
c906108c SS	192	SIM_DESC sd = sim_state_alloc (kind, cb);
	193	int mach;
	194
	195	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	196
14c9ad2e	197	/* The cpu data is kept in a separately allocated chunk of memory. */
d5a71b11	198	if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
14c9ad2e MF	199	return 0;
14c9ad2e MF	200
c906108c SS	201	/* for compatibility */
	202	simulator = sd;
	203
	204	/* FIXME: should be better way of setting up interrupts */
c906108c SS	205	STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt;
	206	STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names;
	207
	208	/* Initialize the mechanism for doing insn profiling. */
	209	CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name;
	210	CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries;
	211
	212	if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
	213	return 0;
	214
	215	/* Allocate core managed memory */
	216
	217	/* "Mirror" the ROM addresses below 1MB. */
	218	sim_do_commandf (sd, "memory region 0,0x100000,0x%lx", V850_ROM_SIZE);
	219	/* Chunk of ram adjacent to rom */
	220	sim_do_commandf (sd, "memory region 0x100000,0x%lx", V850_LOW_END-0x100000);
	221	/* peripheral I/O region - mirror 1K across 4k (0x1000) */
	222	sim_do_command (sd, "memory region 0xfff000,0x1000,1024");
	223	/* similarly if in the internal RAM region */
	224	sim_do_command (sd, "memory region 0xffe000,0x1000,1024");
	225
77cf2ef5	226	/* The parser will print an error message for us, so we silently return. */
c906108c SS	227	if (sim_parse_args (sd, argv) != SIM_RC_OK)
	228	{
	229	/* Uninstall the modules to avoid memory leaks,
	230	file descriptor leaks, etc. */
	231	sim_module_uninstall (sd);
	232	return 0;
	233	}
	234
	235	/* check for/establish the a reference program image */
	236	if (sim_analyze_program (sd,
	237	(STATE_PROG_ARGV (sd) != NULL
	238	? *STATE_PROG_ARGV (sd)
	239	: NULL),
	240	abfd) != SIM_RC_OK)
	241	{
	242	sim_module_uninstall (sd);
	243	return 0;
	244	}
	245
	246	/* establish any remaining configuration options */
	247	if (sim_config (sd) != SIM_RC_OK)
	248	{
	249	sim_module_uninstall (sd);
	250	return 0;
	251	}
	252
	253	if (sim_post_argv_init (sd) != SIM_RC_OK)
	254	{
	255	/* Uninstall the modules to avoid memory leaks,
	256	file descriptor leaks, etc. */
	257	sim_module_uninstall (sd);
	258	return 0;
	259	}
	260
	261
	262	/* determine the machine type */
	263	if (STATE_ARCHITECTURE (sd) != NULL
85367826 NC	264	&& (STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850
85367826 NC	265	\|\| STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850_rh850))
c906108c SS	266	mach = STATE_ARCHITECTURE (sd)->mach;
	267	else
	268	mach = bfd_mach_v850; /* default */
	269
	270	/* set machine specific configuration */
	271	switch (mach)
	272	{
	273	case bfd_mach_v850:
	274	case bfd_mach_v850e:
c5ea1d53	275	case bfd_mach_v850e1:
85367826 NC	276	case bfd_mach_v850e2:
85367826 NC	277	case bfd_mach_v850e2v3:
67d7515b	278	case bfd_mach_v850e3v5:
c906108c SS	279	STATE_CPU (sd, 0)->psw_mask = (PSW_NP \| PSW_EP \| PSW_ID \| PSW_SAT
	280	\| PSW_CY \| PSW_OV \| PSW_S \| PSW_Z);
	281	break;
c906108c SS	282	}
c906108c SS	283
14c9ad2e MF	284	/* CPU specific initialization. */
	285	for (i = 0; i < MAX_NR_PROCESSORS; ++i)
	286	{
	287	SIM_CPU *cpu = STATE_CPU (sd, i);
	288
e1211e55 MF	289	CPU_REG_FETCH (cpu) = v850_reg_fetch;
e1211e55 MF	290	CPU_REG_STORE (cpu) = v850_reg_store;
14c9ad2e MF	291	CPU_PC_FETCH (cpu) = v850_pc_get;
	292	CPU_PC_STORE (cpu) = v850_pc_set;
	293	}
	294
c906108c SS	295	return sd;
	296	}
	297
c906108c	298	SIM_RC
a3976a7c NC	299	sim_create_inferior (SIM_DESC sd,
a3976a7c NC	300	struct bfd * prog_bfd,
2e3d4f4d MF	301	char * const *argv,
2e3d4f4d MF	302	char * const *env)
c906108c SS	303	{
	304	memset (&State, 0, sizeof (State));
	305	if (prog_bfd != NULL)
	306	PC = bfd_get_start_address (prog_bfd);
c906108c SS	307	return SIM_RC_OK;
	308	}
	309
e1211e55 MF	310	static int
e1211e55 MF	311	v850_reg_fetch (SIM_CPU cpu, int rn, unsigned char memory, int length)
c906108c SS	312	{
	313	(unsigned32)memory = H2T_4 (State.regs[rn]);
	314	return -1;
	315	}
e1211e55 MF	316
	317	static int
	318	v850_reg_store (SIM_CPU cpu, int rn, unsigned char memory, int length)
c906108c	319	{
a3976a7c	320	State.regs[rn] = T2H_4 ((unsigned32 ) memory);
dae477fe	321	return length;
c906108c	322	}